1 /* linux/arch/arm/plat-s3c24xx/pwm-clock.c
3 * Copyright (c) 2007 Simtec Electronics
4 * Copyright (c) 2007, 2008 Ben Dooks
5 * Ben Dooks <ben-linux@fluff.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/errno.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
21 #include <mach/hardware.h>
25 #include <plat/clock.h>
28 #include <plat/regs-timer.h>
30 /* Each of the timers 0 through 5 go through the following
31 * clock tree, with the inputs depending on the timers.
33 * pclk ---- [ prescaler 0 ] -+---> timer 0
36 * pclk ---- [ prescaler 1 ] -+---> timer 2
40 * Which are fed into the timers as so:
42 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
44 * tclk 0 ------------------------------/
46 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
48 * tclk 0 ------------------------------/
51 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
53 * tclk 1 ------------------------------/
55 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
57 * tclk 1 ------------------------------/
59 * prescaled 1 ---- [ div 2,4,8, 16 ] --\
61 * tclk 1 ------------------------------/
63 * Since the mux and the divider are tied together in the
64 * same register space, it is impossible to set the parent
65 * and the rate at the same time. To avoid this, we add an
66 * intermediate 'prescaled-and-divided' clock to select
67 * as the parent for the timer input clock called tdiv.
69 * prescaled clk --> pwm-tdiv ---\
71 * tclk -------------------------/
74 static struct clk clk_timer_scaler[];
76 static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
78 unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
80 if (clk == &clk_timer_scaler[1]) {
81 tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
82 tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
84 tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
87 return clk_get_rate(clk->parent) / (tcfg0 + 1);
90 static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
93 unsigned long parent_rate = clk_get_rate(clk->parent);
94 unsigned long divisor = parent_rate / rate;
101 return parent_rate / divisor;
104 static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
106 unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
108 unsigned long divisor;
111 divisor = clk_get_rate(clk->parent) / round;
114 local_irq_save(flags);
115 tcfg0 = __raw_readl(S3C2410_TCFG0);
117 if (clk == &clk_timer_scaler[1]) {
118 tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
119 tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
121 tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
125 __raw_writel(tcfg0, S3C2410_TCFG0);
126 local_irq_restore(flags);
131 static struct clk clk_timer_scaler[] = {
133 .name = "pwm-scaler0",
135 .get_rate = clk_pwm_scaler_get_rate,
136 .set_rate = clk_pwm_scaler_set_rate,
137 .round_rate = clk_pwm_scaler_round_rate,
140 .name = "pwm-scaler1",
142 .get_rate = clk_pwm_scaler_get_rate,
143 .set_rate = clk_pwm_scaler_set_rate,
144 .round_rate = clk_pwm_scaler_round_rate,
148 static struct clk clk_timer_tclk[] = {
159 struct pwm_tdiv_clk {
161 unsigned int divisor;
164 static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
166 return container_of(clk, struct pwm_tdiv_clk, clk);
169 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
171 return 1 << (1 + tcfg1);
174 static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
176 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
177 unsigned int divisor;
179 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
180 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
182 if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
183 divisor = to_tdiv(clk)->divisor;
185 divisor = tcfg_to_divisor(tcfg1);
187 return clk_get_rate(clk->parent) / divisor;
190 static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
193 unsigned long parent_rate;
194 unsigned long divisor;
196 parent_rate = clk_get_rate(clk->parent);
197 divisor = parent_rate / rate;
201 else if (divisor <= 4)
203 else if (divisor <= 8)
208 return parent_rate / divisor;
211 static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
215 switch (divclk->divisor) {
217 bits = S3C2410_TCFG1_MUX_DIV2;
220 bits = S3C2410_TCFG1_MUX_DIV4;
223 bits = S3C2410_TCFG1_MUX_DIV8;
227 bits = S3C2410_TCFG1_MUX_DIV16;
234 static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
236 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
237 unsigned long bits = clk_pwm_tdiv_bits(divclk);
239 unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
241 local_irq_save(flags);
243 tcfg1 = __raw_readl(S3C2410_TCFG1);
244 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
245 tcfg1 |= bits << shift;
246 __raw_writel(tcfg1, S3C2410_TCFG1);
248 local_irq_restore(flags);
251 static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
253 struct pwm_tdiv_clk *divclk = to_tdiv(clk);
254 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
255 unsigned long parent_rate = clk_get_rate(clk->parent);
256 unsigned long divisor;
258 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
259 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
261 rate = clk_round_rate(clk, rate);
262 divisor = parent_rate / rate;
267 divclk->divisor = divisor;
269 /* Update the current MUX settings if we are currently
270 * selected as the clock source for this clock. */
272 if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
273 clk_pwm_tdiv_update(divclk);
278 static struct pwm_tdiv_clk clk_timer_tdiv[] = {
282 .parent = &clk_timer_scaler[0],
283 .get_rate = clk_pwm_tdiv_get_rate,
284 .set_rate = clk_pwm_tdiv_set_rate,
285 .round_rate = clk_pwm_tdiv_round_rate,
291 .parent = &clk_timer_scaler[0],
292 .get_rate = clk_pwm_tdiv_get_rate,
293 .set_rate = clk_pwm_tdiv_set_rate,
294 .round_rate = clk_pwm_tdiv_round_rate,
300 .parent = &clk_timer_scaler[1],
301 .get_rate = clk_pwm_tdiv_get_rate,
302 .set_rate = clk_pwm_tdiv_set_rate,
303 .round_rate = clk_pwm_tdiv_round_rate,
309 .parent = &clk_timer_scaler[1],
310 .get_rate = clk_pwm_tdiv_get_rate,
311 .set_rate = clk_pwm_tdiv_set_rate,
312 .round_rate = clk_pwm_tdiv_round_rate,
318 .parent = &clk_timer_scaler[1],
319 .get_rate = clk_pwm_tdiv_get_rate,
320 .set_rate = clk_pwm_tdiv_set_rate,
321 .round_rate = clk_pwm_tdiv_round_rate,
326 static int __init clk_pwm_tdiv_register(unsigned int id)
328 struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
329 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
331 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
332 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
335 divclk->divisor = tcfg_to_divisor(tcfg1);
337 return s3c24xx_register_clock(&divclk->clk);
340 static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
342 return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
345 static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
347 return &clk_timer_tdiv[id].clk;
350 static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
352 unsigned int id = clk->id;
356 unsigned long shift = S3C2410_TCFG1_SHIFT(id);
358 if (parent == s3c24xx_pwmclk_tclk(id))
359 bits = S3C2410_TCFG1_MUX_TCLK << shift;
360 else if (parent == s3c24xx_pwmclk_tdiv(id))
361 bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
365 clk->parent = parent;
367 local_irq_save(flags);
369 tcfg1 = __raw_readl(S3C2410_TCFG1);
370 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
371 __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
373 local_irq_restore(flags);
378 static struct clk clk_tin[] = {
382 .set_parent = clk_pwm_tin_set_parent,
387 .set_parent = clk_pwm_tin_set_parent,
392 .set_parent = clk_pwm_tin_set_parent,
397 .set_parent = clk_pwm_tin_set_parent,
402 .set_parent = clk_pwm_tin_set_parent,
406 static __init int clk_pwm_tin_register(struct clk *pwm)
408 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
409 unsigned int id = pwm->id;
414 ret = s3c24xx_register_clock(pwm);
418 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
419 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
421 if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
422 parent = s3c24xx_pwmclk_tclk(id);
424 parent = s3c24xx_pwmclk_tdiv(id);
426 return clk_set_parent(pwm, parent);
429 static __init int s3c24xx_pwmclk_init(void)
431 struct clk *clk_timers;
435 clk_timers = clk_get(NULL, "timers");
436 if (IS_ERR(clk_timers)) {
437 printk(KERN_ERR "%s: no parent clock\n", __func__);
441 for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
442 clk_timer_scaler[clk].parent = clk_timers;
443 ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
445 printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
450 for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
451 ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
453 printk(KERN_ERR "error adding pww tclk%d\n", clk);
458 for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
459 ret = clk_pwm_tdiv_register(clk);
461 printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
466 for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
467 ret = clk_pwm_tin_register(&clk_tin[clk]);
469 printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
480 arch_initcall(s3c24xx_pwmclk_init);