2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
22 * Copyright 2001 MontaVista Software Inc.
23 * Author: MontaVista Software, Inc.
24 * ahennessy@mvista.com
26 * Copyright (C) 2000-2001 Toshiba Corporation
27 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/kdev_t.h>
33 #include <linux/types.h>
34 #include <linux/pci.h>
35 #include <linux/ide.h>
36 #include <linux/ioport.h>
37 #include <linux/delay.h>
39 #include <linux/platform_device.h>
40 #ifdef CONFIG_SERIAL_TXX9
41 #include <linux/tty.h>
42 #include <linux/serial.h>
43 #include <linux/serial_core.h>
46 #include <asm/addrspace.h>
47 #include <asm/txx9tmr.h>
48 #include <asm/reboot.h>
49 #include <asm/jmr3927/jmr3927.h>
50 #include <asm/mipsregs.h>
52 extern void puts(const char *cp);
54 /* don't enable - see errata */
55 static int jmr3927_ccfg_toeon;
57 static inline void do_reset(void)
59 #if 1 /* Resetting PCI bus */
60 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
61 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI, JMR3927_IOC_RESET_ADDR);
62 (void)jmr3927_ioc_reg_in(JMR3927_IOC_RESET_ADDR); /* flush WB */
64 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
66 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_CPU, JMR3927_IOC_RESET_ADDR);
69 static void jmr3927_machine_restart(char *command)
76 static void jmr3927_machine_halt(void)
78 puts("JMR-TX3927 halted.\n");
82 static void jmr3927_machine_power_off(void)
84 puts("JMR-TX3927 halted. Please turn off the power.\n");
88 void __init plat_time_init(void)
90 txx9_clockevent_init(TX3927_TMR_REG(0),
91 TXX9_IRQ_BASE + JMR3927_IRQ_IRC_TMR(0),
93 txx9_clocksource_init(TX3927_TMR_REG(1), JMR3927_IMCLK);
96 #define DO_WRITE_THROUGH
97 #define DO_ENABLE_CACHE
99 extern char * __init prom_getcmdline(void);
100 static void jmr3927_board_init(void);
101 extern struct resource pci_io_resource;
102 extern struct resource pci_mem_resource;
104 void __init plat_mem_setup(void)
108 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
110 _machine_restart = jmr3927_machine_restart;
111 _machine_halt = jmr3927_machine_halt;
112 pm_power_off = jmr3927_machine_power_off;
117 ioport_resource.start = pci_io_resource.start;
118 ioport_resource.end = pci_io_resource.end;
119 iomem_resource.start = 0;
120 iomem_resource.end = 0xffffffff;
122 /* Reboot on panic */
128 #ifdef DO_ENABLE_CACHE
129 int mips_ic_disable = 0, mips_dc_disable = 0;
131 int mips_ic_disable = 1, mips_dc_disable = 1;
133 #ifdef DO_WRITE_THROUGH
134 int mips_config_cwfon = 0;
135 int mips_config_wbon = 0;
137 int mips_config_cwfon = 1;
138 int mips_config_wbon = 1;
141 conf = read_c0_conf();
142 conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON);
143 conf |= mips_ic_disable ? 0 : TX39_CONF_ICE;
144 conf |= mips_dc_disable ? 0 : TX39_CONF_DCE;
145 conf |= mips_config_wbon ? TX39_CONF_WBON : 0;
146 conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0;
152 /* initialize board */
153 jmr3927_board_init();
155 argptr = prom_getcmdline();
157 if ((argptr = strstr(argptr, "toeon")) != NULL)
158 jmr3927_ccfg_toeon = 1;
159 argptr = prom_getcmdline();
160 if ((argptr = strstr(argptr, "ip=")) == NULL) {
161 argptr = prom_getcmdline();
162 strcat(argptr, " ip=bootp");
165 #ifdef CONFIG_SERIAL_TXX9
167 extern int early_serial_txx9_setup(struct uart_port *port);
169 struct uart_port req;
170 for(i = 0; i < 2; i++) {
171 memset(&req, 0, sizeof(req));
173 req.iotype = UPIO_MEM;
174 req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
175 req.mapbase = TX3927_SIO_REG(i);
177 JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1;
179 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
180 req.uartclk = JMR3927_IMCLK;
181 early_serial_txx9_setup(&req);
184 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
185 argptr = prom_getcmdline();
186 if ((argptr = strstr(argptr, "console=")) == NULL) {
187 argptr = prom_getcmdline();
188 strcat(argptr, " console=ttyS1,115200");
194 static void tx3927_setup(void);
196 static void __init jmr3927_board_init(void)
201 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
205 printk("JMR-TX3927 (Rev %d) --- IOC(Rev %d) DIPSW:%d,%d,%d,%d\n",
206 jmr3927_ioc_reg_in(JMR3927_IOC_BREV_ADDR) & JMR3927_REV_MASK,
207 jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_REV_MASK,
208 jmr3927_dipsw1(), jmr3927_dipsw2(),
209 jmr3927_dipsw3(), jmr3927_dipsw4());
212 static void __init tx3927_setup(void)
216 unsigned long mips_pci_io_base = JMR3927_PCIIO;
217 unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
218 unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
219 unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
220 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
221 unsigned long mips_pci_io_pciaddr = 0;
224 /* SDRAMC are configured by PROM */
227 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048;
228 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8;
229 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698;
230 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218;
233 /* enable Timeout BusError */
234 if (jmr3927_ccfg_toeon)
235 tx3927_ccfgptr->ccfg |= TX3927_CCFG_TOE;
237 /* clear BusErrorOnWrite flag */
238 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_BEOW;
239 /* Disable PCI snoop */
240 tx3927_ccfgptr->ccfg &= ~TX3927_CCFG_PSNP;
242 #ifdef DO_WRITE_THROUGH
243 /* Enable PCI SNOOP - with write through only */
244 tx3927_ccfgptr->ccfg |= TX3927_CCFG_PSNP;
248 tx3927_ccfgptr->pcfg &= ~TX3927_PCFG_SELALL;
249 tx3927_ccfgptr->pcfg |=
250 TX3927_PCFG_SELSIOC(0) | TX3927_PCFG_SELSIO_ALL |
251 (TX3927_PCFG_SELDMA_ALL & ~TX3927_PCFG_SELDMA(1));
253 printk("TX3927 -- CRIR:%08lx CCFG:%08lx PCFG:%08lx\n",
254 tx3927_ccfgptr->crir,
255 tx3927_ccfgptr->ccfg, tx3927_ccfgptr->pcfg);
258 for (i = 0; i < TX3927_NR_TMR; i++)
259 txx9_tmr_init(TX3927_TMR_REG(i));
262 tx3927_dmaptr->mcr = 0;
263 for (i = 0; i < ARRAY_SIZE(tx3927_dmaptr->ch); i++) {
265 tx3927_dmaptr->ch[i].ccr = TX3927_DMA_CCR_CHRST;
266 tx3927_dmaptr->ch[i].ccr = 0;
270 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN;
272 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
277 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
278 tx3927_pcicptr->did, tx3927_pcicptr->vid,
279 tx3927_pcicptr->rid);
280 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
281 printk("External\n");
284 printk("Internal\n");
287 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
289 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
290 JMR3927_IOC_RESET_ADDR);
292 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
295 /* Disable External PCI Config. Access */
296 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
298 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
299 TX3927_PCIC_LBC_TIBSE |
300 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
302 /* LB->PCI mappings */
303 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
304 tx3927_pcicptr->ilbioma = mips_pci_io_base;
305 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
306 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
307 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
308 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
309 /* PCI->LB mappings */
310 tx3927_pcicptr->iobas = 0xffffffff;
311 tx3927_pcicptr->ioba = 0;
312 tx3927_pcicptr->tlbioma = 0;
313 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
314 tx3927_pcicptr->mba = 0;
315 tx3927_pcicptr->tlbmma = 0;
316 /* Enable Direct mapping Address Space Decoder */
317 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
319 /* Clear All Local Bus Status */
320 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
321 /* Enable All Local Bus Interrupts */
322 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
323 /* Clear All PCI Status Error */
324 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
325 /* Enable All PCI Status Error Interrupts */
326 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
328 /* PCIC Int => IRC IRQ10 */
329 tx3927_pcicptr->il = TX3927_IR_PCI;
330 /* Target Control (per errata) */
331 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
333 /* Enable Bus Arbiter */
334 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
336 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
339 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
341 #endif /* CONFIG_PCI */
344 /* PIO[15:12] connected to LEDs */
345 tx3927_pioptr->dir = 0x0000f000;
346 tx3927_pioptr->maskcpu = 0;
347 tx3927_pioptr->maskext = 0;
351 conf = read_c0_conf();
352 if (!(conf & TX39_CONF_ICE))
353 printk("TX3927 I-Cache disabled.\n");
354 if (!(conf & TX39_CONF_DCE))
355 printk("TX3927 D-Cache disabled.\n");
356 else if (!(conf & TX39_CONF_WBON))
357 printk("TX3927 D-Cache WriteThrough.\n");
358 else if (!(conf & TX39_CONF_CWFON))
359 printk("TX3927 D-Cache WriteBack.\n");
361 printk("TX3927 D-Cache WriteBack (CWF) .\n");
365 /* This trick makes rtc-ds1742 driver usable as is. */
366 unsigned long __swizzle_addr_b(unsigned long port)
368 if ((port & 0xffff0000) != JMR3927_IOC_NVRAMB_ADDR)
370 port = (port & 0xffff0000) | (port & 0x7fff << 1);
377 EXPORT_SYMBOL(__swizzle_addr_b);
379 static int __init jmr3927_rtc_init(void)
381 static struct resource __initdata res = {
382 .start = JMR3927_IOC_NVRAMB_ADDR - IO_BASE,
383 .end = JMR3927_IOC_NVRAMB_ADDR - IO_BASE + 0x800 - 1,
384 .flags = IORESOURCE_MEM,
386 struct platform_device *dev;
387 dev = platform_device_register_simple("rtc-ds1742", -1, &res, 1);
388 return IS_ERR(dev) ? PTR_ERR(dev) : 0;
390 device_initcall(jmr3927_rtc_init);