[ARM] 4909/1: [AT91] Timer/Counter Block platform_devices
[linux-2.6] / arch / arm / mach-at91 / at91cap9_devices.c
1 /*
2  * arch/arm/mach-at91/at91cap9_devices.c
3  *
4  *  Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5  *  Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6  *  Copyright (C) 2007 Atmel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  */
14 #include <asm/mach/arch.h>
15 #include <asm/mach/map.h>
16
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/physmap.h>
20
21 #include <video/atmel_lcdc.h>
22
23 #include <asm/arch/board.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/at91cap9.h>
26 #include <asm/arch/at91cap9_matrix.h>
27 #include <asm/arch/at91sam9_smc.h>
28
29 #include "generic.h"
30
31
32 /* --------------------------------------------------------------------
33  *  USB Host
34  * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37 static u64 ohci_dmamask = DMA_BIT_MASK(32);
38 static struct at91_usbh_data usbh_data;
39
40 static struct resource usbh_resources[] = {
41         [0] = {
42                 .start  = AT91CAP9_UHP_BASE,
43                 .end    = AT91CAP9_UHP_BASE + SZ_1M - 1,
44                 .flags  = IORESOURCE_MEM,
45         },
46         [1] = {
47                 .start  = AT91CAP9_ID_UHP,
48                 .end    = AT91CAP9_ID_UHP,
49                 .flags  = IORESOURCE_IRQ,
50         },
51 };
52
53 static struct platform_device at91_usbh_device = {
54         .name           = "at91_ohci",
55         .id             = -1,
56         .dev            = {
57                                 .dma_mask               = &ohci_dmamask,
58                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
59                                 .platform_data          = &usbh_data,
60         },
61         .resource       = usbh_resources,
62         .num_resources  = ARRAY_SIZE(usbh_resources),
63 };
64
65 void __init at91_add_device_usbh(struct at91_usbh_data *data)
66 {
67         int i;
68
69         if (!data)
70                 return;
71
72         /* Enable VBus control for UHP ports */
73         for (i = 0; i < data->ports; i++) {
74                 if (data->vbus_pin[i])
75                         at91_set_gpio_output(data->vbus_pin[i], 0);
76         }
77
78         usbh_data = *data;
79         platform_device_register(&at91_usbh_device);
80 }
81 #else
82 void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83 #endif
84
85
86 /* --------------------------------------------------------------------
87  *  Ethernet
88  * -------------------------------------------------------------------- */
89
90 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
91 static u64 eth_dmamask = DMA_BIT_MASK(32);
92 static struct at91_eth_data eth_data;
93
94 static struct resource eth_resources[] = {
95         [0] = {
96                 .start  = AT91CAP9_BASE_EMAC,
97                 .end    = AT91CAP9_BASE_EMAC + SZ_16K - 1,
98                 .flags  = IORESOURCE_MEM,
99         },
100         [1] = {
101                 .start  = AT91CAP9_ID_EMAC,
102                 .end    = AT91CAP9_ID_EMAC,
103                 .flags  = IORESOURCE_IRQ,
104         },
105 };
106
107 static struct platform_device at91cap9_eth_device = {
108         .name           = "macb",
109         .id             = -1,
110         .dev            = {
111                                 .dma_mask               = &eth_dmamask,
112                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
113                                 .platform_data          = &eth_data,
114         },
115         .resource       = eth_resources,
116         .num_resources  = ARRAY_SIZE(eth_resources),
117 };
118
119 void __init at91_add_device_eth(struct at91_eth_data *data)
120 {
121         if (!data)
122                 return;
123
124         if (data->phy_irq_pin) {
125                 at91_set_gpio_input(data->phy_irq_pin, 0);
126                 at91_set_deglitch(data->phy_irq_pin, 1);
127         }
128
129         /* Pins used for MII and RMII */
130         at91_set_A_periph(AT91_PIN_PB21, 0);    /* ETXCK_EREFCK */
131         at91_set_A_periph(AT91_PIN_PB22, 0);    /* ERXDV */
132         at91_set_A_periph(AT91_PIN_PB25, 0);    /* ERX0 */
133         at91_set_A_periph(AT91_PIN_PB26, 0);    /* ERX1 */
134         at91_set_A_periph(AT91_PIN_PB27, 0);    /* ERXER */
135         at91_set_A_periph(AT91_PIN_PB28, 0);    /* ETXEN */
136         at91_set_A_periph(AT91_PIN_PB23, 0);    /* ETX0 */
137         at91_set_A_periph(AT91_PIN_PB24, 0);    /* ETX1 */
138         at91_set_A_periph(AT91_PIN_PB30, 0);    /* EMDIO */
139         at91_set_A_periph(AT91_PIN_PB29, 0);    /* EMDC */
140
141         if (!data->is_rmii) {
142                 at91_set_B_periph(AT91_PIN_PC25, 0);    /* ECRS */
143                 at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
144                 at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
145                 at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
146                 at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
147                 at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
148                 at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
149                 at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
150         }
151
152         eth_data = *data;
153         platform_device_register(&at91cap9_eth_device);
154 }
155 #else
156 void __init at91_add_device_eth(struct at91_eth_data *data) {}
157 #endif
158
159
160 /* --------------------------------------------------------------------
161  *  MMC / SD
162  * -------------------------------------------------------------------- */
163
164 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
165 static u64 mmc_dmamask = DMA_BIT_MASK(32);
166 static struct at91_mmc_data mmc0_data, mmc1_data;
167
168 static struct resource mmc0_resources[] = {
169         [0] = {
170                 .start  = AT91CAP9_BASE_MCI0,
171                 .end    = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
172                 .flags  = IORESOURCE_MEM,
173         },
174         [1] = {
175                 .start  = AT91CAP9_ID_MCI0,
176                 .end    = AT91CAP9_ID_MCI0,
177                 .flags  = IORESOURCE_IRQ,
178         },
179 };
180
181 static struct platform_device at91cap9_mmc0_device = {
182         .name           = "at91_mci",
183         .id             = 0,
184         .dev            = {
185                                 .dma_mask               = &mmc_dmamask,
186                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
187                                 .platform_data          = &mmc0_data,
188         },
189         .resource       = mmc0_resources,
190         .num_resources  = ARRAY_SIZE(mmc0_resources),
191 };
192
193 static struct resource mmc1_resources[] = {
194         [0] = {
195                 .start  = AT91CAP9_BASE_MCI1,
196                 .end    = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
197                 .flags  = IORESOURCE_MEM,
198         },
199         [1] = {
200                 .start  = AT91CAP9_ID_MCI1,
201                 .end    = AT91CAP9_ID_MCI1,
202                 .flags  = IORESOURCE_IRQ,
203         },
204 };
205
206 static struct platform_device at91cap9_mmc1_device = {
207         .name           = "at91_mci",
208         .id             = 1,
209         .dev            = {
210                                 .dma_mask               = &mmc_dmamask,
211                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
212                                 .platform_data          = &mmc1_data,
213         },
214         .resource       = mmc1_resources,
215         .num_resources  = ARRAY_SIZE(mmc1_resources),
216 };
217
218 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
219 {
220         if (!data)
221                 return;
222
223         /* input/irq */
224         if (data->det_pin) {
225                 at91_set_gpio_input(data->det_pin, 1);
226                 at91_set_deglitch(data->det_pin, 1);
227         }
228         if (data->wp_pin)
229                 at91_set_gpio_input(data->wp_pin, 1);
230         if (data->vcc_pin)
231                 at91_set_gpio_output(data->vcc_pin, 0);
232
233         if (mmc_id == 0) {              /* MCI0 */
234                 /* CLK */
235                 at91_set_A_periph(AT91_PIN_PA2, 0);
236
237                 /* CMD */
238                 at91_set_A_periph(AT91_PIN_PA1, 1);
239
240                 /* DAT0, maybe DAT1..DAT3 */
241                 at91_set_A_periph(AT91_PIN_PA0, 1);
242                 if (data->wire4) {
243                         at91_set_A_periph(AT91_PIN_PA3, 1);
244                         at91_set_A_periph(AT91_PIN_PA4, 1);
245                         at91_set_A_periph(AT91_PIN_PA5, 1);
246                 }
247
248                 mmc0_data = *data;
249                 at91_clock_associate("mci0_clk", &at91cap9_mmc1_device.dev, "mci_clk");
250                 platform_device_register(&at91cap9_mmc0_device);
251         } else {                        /* MCI1 */
252                 /* CLK */
253                 at91_set_A_periph(AT91_PIN_PA16, 0);
254
255                 /* CMD */
256                 at91_set_A_periph(AT91_PIN_PA17, 1);
257
258                 /* DAT0, maybe DAT1..DAT3 */
259                 at91_set_A_periph(AT91_PIN_PA18, 1);
260                 if (data->wire4) {
261                         at91_set_A_periph(AT91_PIN_PA19, 1);
262                         at91_set_A_periph(AT91_PIN_PA20, 1);
263                         at91_set_A_periph(AT91_PIN_PA21, 1);
264                 }
265
266                 mmc1_data = *data;
267                 at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
268                 platform_device_register(&at91cap9_mmc1_device);
269         }
270 }
271 #else
272 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
273 #endif
274
275
276 /* --------------------------------------------------------------------
277  *  NAND / SmartMedia
278  * -------------------------------------------------------------------- */
279
280 #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
281 static struct at91_nand_data nand_data;
282
283 #define NAND_BASE       AT91_CHIPSELECT_3
284
285 static struct resource nand_resources[] = {
286         [0] = {
287                 .start  = NAND_BASE,
288                 .end    = NAND_BASE + SZ_256M - 1,
289                 .flags  = IORESOURCE_MEM,
290         },
291         [1] = {
292                 .start  = AT91_BASE_SYS + AT91_ECC,
293                 .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
294                 .flags  = IORESOURCE_MEM,
295         }
296 };
297
298 static struct platform_device at91cap9_nand_device = {
299         .name           = "at91_nand",
300         .id             = -1,
301         .dev            = {
302                                 .platform_data  = &nand_data,
303         },
304         .resource       = nand_resources,
305         .num_resources  = ARRAY_SIZE(nand_resources),
306 };
307
308 void __init at91_add_device_nand(struct at91_nand_data *data)
309 {
310         unsigned long csa, mode;
311
312         if (!data)
313                 return;
314
315         csa = at91_sys_read(AT91_MATRIX_EBICSA);
316         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
317
318         /* set the bus interface characteristics */
319         at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1)
320                         | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
321
322         at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6)
323                         | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
324
325         at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
326
327         if (data->bus_width_16)
328                 mode = AT91_SMC_DBW_16;
329         else
330                 mode = AT91_SMC_DBW_8;
331         at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
332
333         /* enable pin */
334         if (data->enable_pin)
335                 at91_set_gpio_output(data->enable_pin, 1);
336
337         /* ready/busy pin */
338         if (data->rdy_pin)
339                 at91_set_gpio_input(data->rdy_pin, 1);
340
341         /* card detect pin */
342         if (data->det_pin)
343                 at91_set_gpio_input(data->det_pin, 1);
344
345         nand_data = *data;
346         platform_device_register(&at91cap9_nand_device);
347 }
348 #else
349 void __init at91_add_device_nand(struct at91_nand_data *data) {}
350 #endif
351
352 /* --------------------------------------------------------------------
353  *  TWI (i2c)
354  * -------------------------------------------------------------------- */
355
356 /*
357  * Prefer the GPIO code since the TWI controller isn't robust
358  * (gets overruns and underruns under load) and can only issue
359  * repeated STARTs in one scenario (the driver doesn't yet handle them).
360  */
361 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
362
363 static struct i2c_gpio_platform_data pdata = {
364         .sda_pin                = AT91_PIN_PB4,
365         .sda_is_open_drain      = 1,
366         .scl_pin                = AT91_PIN_PB5,
367         .scl_is_open_drain      = 1,
368         .udelay                 = 2,            /* ~100 kHz */
369 };
370
371 static struct platform_device at91cap9_twi_device = {
372         .name                   = "i2c-gpio",
373         .id                     = -1,
374         .dev.platform_data      = &pdata,
375 };
376
377 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
378 {
379         at91_set_GPIO_periph(AT91_PIN_PB4, 1);          /* TWD (SDA) */
380         at91_set_multi_drive(AT91_PIN_PB4, 1);
381
382         at91_set_GPIO_periph(AT91_PIN_PB5, 1);          /* TWCK (SCL) */
383         at91_set_multi_drive(AT91_PIN_PB5, 1);
384
385         i2c_register_board_info(0, devices, nr_devices);
386         platform_device_register(&at91cap9_twi_device);
387 }
388
389 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
390
391 static struct resource twi_resources[] = {
392         [0] = {
393                 .start  = AT91CAP9_BASE_TWI,
394                 .end    = AT91CAP9_BASE_TWI + SZ_16K - 1,
395                 .flags  = IORESOURCE_MEM,
396         },
397         [1] = {
398                 .start  = AT91CAP9_ID_TWI,
399                 .end    = AT91CAP9_ID_TWI,
400                 .flags  = IORESOURCE_IRQ,
401         },
402 };
403
404 static struct platform_device at91cap9_twi_device = {
405         .name           = "at91_i2c",
406         .id             = -1,
407         .resource       = twi_resources,
408         .num_resources  = ARRAY_SIZE(twi_resources),
409 };
410
411 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
412 {
413         /* pins used for TWI interface */
414         at91_set_B_periph(AT91_PIN_PB4, 0);             /* TWD */
415         at91_set_multi_drive(AT91_PIN_PB4, 1);
416
417         at91_set_B_periph(AT91_PIN_PB5, 0);             /* TWCK */
418         at91_set_multi_drive(AT91_PIN_PB5, 1);
419
420         i2c_register_board_info(0, devices, nr_devices);
421         platform_device_register(&at91cap9_twi_device);
422 }
423 #else
424 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
425 #endif
426
427 /* --------------------------------------------------------------------
428  *  SPI
429  * -------------------------------------------------------------------- */
430
431 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
432 static u64 spi_dmamask = DMA_BIT_MASK(32);
433
434 static struct resource spi0_resources[] = {
435         [0] = {
436                 .start  = AT91CAP9_BASE_SPI0,
437                 .end    = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
438                 .flags  = IORESOURCE_MEM,
439         },
440         [1] = {
441                 .start  = AT91CAP9_ID_SPI0,
442                 .end    = AT91CAP9_ID_SPI0,
443                 .flags  = IORESOURCE_IRQ,
444         },
445 };
446
447 static struct platform_device at91cap9_spi0_device = {
448         .name           = "atmel_spi",
449         .id             = 0,
450         .dev            = {
451                                 .dma_mask               = &spi_dmamask,
452                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
453         },
454         .resource       = spi0_resources,
455         .num_resources  = ARRAY_SIZE(spi0_resources),
456 };
457
458 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
459
460 static struct resource spi1_resources[] = {
461         [0] = {
462                 .start  = AT91CAP9_BASE_SPI1,
463                 .end    = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
464                 .flags  = IORESOURCE_MEM,
465         },
466         [1] = {
467                 .start  = AT91CAP9_ID_SPI1,
468                 .end    = AT91CAP9_ID_SPI1,
469                 .flags  = IORESOURCE_IRQ,
470         },
471 };
472
473 static struct platform_device at91cap9_spi1_device = {
474         .name           = "atmel_spi",
475         .id             = 1,
476         .dev            = {
477                                 .dma_mask               = &spi_dmamask,
478                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
479         },
480         .resource       = spi1_resources,
481         .num_resources  = ARRAY_SIZE(spi1_resources),
482 };
483
484 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
485
486 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
487 {
488         int i;
489         unsigned long cs_pin;
490         short enable_spi0 = 0;
491         short enable_spi1 = 0;
492
493         /* Choose SPI chip-selects */
494         for (i = 0; i < nr_devices; i++) {
495                 if (devices[i].controller_data)
496                         cs_pin = (unsigned long) devices[i].controller_data;
497                 else if (devices[i].bus_num == 0)
498                         cs_pin = spi0_standard_cs[devices[i].chip_select];
499                 else
500                         cs_pin = spi1_standard_cs[devices[i].chip_select];
501
502                 if (devices[i].bus_num == 0)
503                         enable_spi0 = 1;
504                 else
505                         enable_spi1 = 1;
506
507                 /* enable chip-select pin */
508                 at91_set_gpio_output(cs_pin, 1);
509
510                 /* pass chip-select pin to driver */
511                 devices[i].controller_data = (void *) cs_pin;
512         }
513
514         spi_register_board_info(devices, nr_devices);
515
516         /* Configure SPI bus(es) */
517         if (enable_spi0) {
518                 at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
519                 at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
520                 at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
521
522                 at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk");
523                 platform_device_register(&at91cap9_spi0_device);
524         }
525         if (enable_spi1) {
526                 at91_set_A_periph(AT91_PIN_PB12, 0);    /* SPI1_MISO */
527                 at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
528                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
529
530                 at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk");
531                 platform_device_register(&at91cap9_spi1_device);
532         }
533 }
534 #else
535 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
536 #endif
537
538
539 /* --------------------------------------------------------------------
540  *  Timer/Counter block
541  * -------------------------------------------------------------------- */
542
543 #ifdef CONFIG_ATMEL_TCLIB
544
545 static struct resource tcb_resources[] = {
546         [0] = {
547                 .start  = AT91CAP9_BASE_TCB0,
548                 .end    = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
549                 .flags  = IORESOURCE_MEM,
550         },
551         [1] = {
552                 .start  = AT91CAP9_ID_TCB,
553                 .end    = AT91CAP9_ID_TCB,
554                 .flags  = IORESOURCE_IRQ,
555         },
556 };
557
558 static struct platform_device at91cap9_tcb_device = {
559         .name           = "atmel_tcb",
560         .id             = 0,
561         .resource       = tcb_resources,
562         .num_resources  = ARRAY_SIZE(tcb_resources),
563 };
564
565 static void __init at91_add_device_tc(void)
566 {
567         /* this chip has one clock and irq for all three TC channels */
568         at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
569         platform_device_register(&at91cap9_tcb_device);
570 }
571 #else
572 static void __init at91_add_device_tc(void) { }
573 #endif
574
575
576 /* --------------------------------------------------------------------
577  *  RTT
578  * -------------------------------------------------------------------- */
579
580 static struct resource rtt_resources[] = {
581         {
582                 .start  = AT91_BASE_SYS + AT91_RTT,
583                 .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
584                 .flags  = IORESOURCE_MEM,
585         }
586 };
587
588 static struct platform_device at91cap9_rtt_device = {
589         .name           = "at91_rtt",
590         .id             = 0,
591         .resource       = rtt_resources,
592         .num_resources  = ARRAY_SIZE(rtt_resources),
593 };
594
595 static void __init at91_add_device_rtt(void)
596 {
597         platform_device_register(&at91cap9_rtt_device);
598 }
599
600
601 /* --------------------------------------------------------------------
602  *  Watchdog
603  * -------------------------------------------------------------------- */
604
605 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
606 static struct platform_device at91cap9_wdt_device = {
607         .name           = "at91_wdt",
608         .id             = -1,
609         .num_resources  = 0,
610 };
611
612 static void __init at91_add_device_watchdog(void)
613 {
614         platform_device_register(&at91cap9_wdt_device);
615 }
616 #else
617 static void __init at91_add_device_watchdog(void) {}
618 #endif
619
620
621 /* --------------------------------------------------------------------
622  *  AC97
623  * -------------------------------------------------------------------- */
624
625 #if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
626 static u64 ac97_dmamask = DMA_BIT_MASK(32);
627 static struct atmel_ac97_data ac97_data;
628
629 static struct resource ac97_resources[] = {
630         [0] = {
631                 .start  = AT91CAP9_BASE_AC97C,
632                 .end    = AT91CAP9_BASE_AC97C + SZ_16K - 1,
633                 .flags  = IORESOURCE_MEM,
634         },
635         [1] = {
636                 .start  = AT91CAP9_ID_AC97C,
637                 .end    = AT91CAP9_ID_AC97C,
638                 .flags  = IORESOURCE_IRQ,
639         },
640 };
641
642 static struct platform_device at91cap9_ac97_device = {
643         .name           = "ac97c",
644         .id             = 1,
645         .dev            = {
646                                 .dma_mask               = &ac97_dmamask,
647                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
648                                 .platform_data          = &ac97_data,
649         },
650         .resource       = ac97_resources,
651         .num_resources  = ARRAY_SIZE(ac97_resources),
652 };
653
654 void __init at91_add_device_ac97(struct atmel_ac97_data *data)
655 {
656         if (!data)
657                 return;
658
659         at91_set_A_periph(AT91_PIN_PA6, 0);     /* AC97FS */
660         at91_set_A_periph(AT91_PIN_PA7, 0);     /* AC97CK */
661         at91_set_A_periph(AT91_PIN_PA8, 0);     /* AC97TX */
662         at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
663
664         /* reset */
665         if (data->reset_pin)
666                 at91_set_gpio_output(data->reset_pin, 0);
667
668         ac97_data = *data;
669         platform_device_register(&at91cap9_ac97_device);
670 }
671 #else
672 void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
673 #endif
674
675
676 /* --------------------------------------------------------------------
677  *  LCD Controller
678  * -------------------------------------------------------------------- */
679
680 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
681 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
682 static struct atmel_lcdfb_info lcdc_data;
683
684 static struct resource lcdc_resources[] = {
685         [0] = {
686                 .start  = AT91CAP9_LCDC_BASE,
687                 .end    = AT91CAP9_LCDC_BASE + SZ_4K - 1,
688                 .flags  = IORESOURCE_MEM,
689         },
690         [1] = {
691                 .start  = AT91CAP9_ID_LCDC,
692                 .end    = AT91CAP9_ID_LCDC,
693                 .flags  = IORESOURCE_IRQ,
694         },
695 };
696
697 static struct platform_device at91_lcdc_device = {
698         .name           = "atmel_lcdfb",
699         .id             = 0,
700         .dev            = {
701                                 .dma_mask               = &lcdc_dmamask,
702                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
703                                 .platform_data          = &lcdc_data,
704         },
705         .resource       = lcdc_resources,
706         .num_resources  = ARRAY_SIZE(lcdc_resources),
707 };
708
709 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
710 {
711         if (!data)
712                 return;
713
714         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
715         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
716         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
717         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
718         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
719         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
720         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
721         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
722         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
723         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
724         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
725         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
726         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
727         at91_set_A_periph(AT91_PIN_PC17, 0);    /* LCDD13 */
728         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
729         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
730         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
731         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
732         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
733         at91_set_A_periph(AT91_PIN_PC25, 0);    /* LCDD21 */
734         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
735         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
736
737         lcdc_data = *data;
738         platform_device_register(&at91_lcdc_device);
739 }
740 #else
741 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
742 #endif
743
744
745 /* --------------------------------------------------------------------
746  *  SSC -- Synchronous Serial Controller
747  * -------------------------------------------------------------------- */
748
749 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
750 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
751
752 static struct resource ssc0_resources[] = {
753         [0] = {
754                 .start  = AT91CAP9_BASE_SSC0,
755                 .end    = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
756                 .flags  = IORESOURCE_MEM,
757         },
758         [1] = {
759                 .start  = AT91CAP9_ID_SSC0,
760                 .end    = AT91CAP9_ID_SSC0,
761                 .flags  = IORESOURCE_IRQ,
762         },
763 };
764
765 static struct platform_device at91cap9_ssc0_device = {
766         .name   = "ssc",
767         .id     = 0,
768         .dev    = {
769                 .dma_mask               = &ssc0_dmamask,
770                 .coherent_dma_mask      = DMA_BIT_MASK(32),
771         },
772         .resource       = ssc0_resources,
773         .num_resources  = ARRAY_SIZE(ssc0_resources),
774 };
775
776 static inline void configure_ssc0_pins(unsigned pins)
777 {
778         if (pins & ATMEL_SSC_TF)
779                 at91_set_A_periph(AT91_PIN_PB0, 1);
780         if (pins & ATMEL_SSC_TK)
781                 at91_set_A_periph(AT91_PIN_PB1, 1);
782         if (pins & ATMEL_SSC_TD)
783                 at91_set_A_periph(AT91_PIN_PB2, 1);
784         if (pins & ATMEL_SSC_RD)
785                 at91_set_A_periph(AT91_PIN_PB3, 1);
786         if (pins & ATMEL_SSC_RK)
787                 at91_set_A_periph(AT91_PIN_PB4, 1);
788         if (pins & ATMEL_SSC_RF)
789                 at91_set_A_periph(AT91_PIN_PB5, 1);
790 }
791
792 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
793
794 static struct resource ssc1_resources[] = {
795         [0] = {
796                 .start  = AT91CAP9_BASE_SSC1,
797                 .end    = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
798                 .flags  = IORESOURCE_MEM,
799         },
800         [1] = {
801                 .start  = AT91CAP9_ID_SSC1,
802                 .end    = AT91CAP9_ID_SSC1,
803                 .flags  = IORESOURCE_IRQ,
804         },
805 };
806
807 static struct platform_device at91cap9_ssc1_device = {
808         .name   = "ssc",
809         .id     = 1,
810         .dev    = {
811                 .dma_mask               = &ssc1_dmamask,
812                 .coherent_dma_mask      = DMA_BIT_MASK(32),
813         },
814         .resource       = ssc1_resources,
815         .num_resources  = ARRAY_SIZE(ssc1_resources),
816 };
817
818 static inline void configure_ssc1_pins(unsigned pins)
819 {
820         if (pins & ATMEL_SSC_TF)
821                 at91_set_A_periph(AT91_PIN_PB6, 1);
822         if (pins & ATMEL_SSC_TK)
823                 at91_set_A_periph(AT91_PIN_PB7, 1);
824         if (pins & ATMEL_SSC_TD)
825                 at91_set_A_periph(AT91_PIN_PB8, 1);
826         if (pins & ATMEL_SSC_RD)
827                 at91_set_A_periph(AT91_PIN_PB9, 1);
828         if (pins & ATMEL_SSC_RK)
829                 at91_set_A_periph(AT91_PIN_PB10, 1);
830         if (pins & ATMEL_SSC_RF)
831                 at91_set_A_periph(AT91_PIN_PB11, 1);
832 }
833
834 /*
835  * SSC controllers are accessed through library code, instead of any
836  * kind of all-singing/all-dancing driver.  For example one could be
837  * used by a particular I2S audio codec's driver, while another one
838  * on the same system might be used by a custom data capture driver.
839  */
840 void __init at91_add_device_ssc(unsigned id, unsigned pins)
841 {
842         struct platform_device *pdev;
843
844         /*
845          * NOTE: caller is responsible for passing information matching
846          * "pins" to whatever will be using each particular controller.
847          */
848         switch (id) {
849         case AT91CAP9_ID_SSC0:
850                 pdev = &at91cap9_ssc0_device;
851                 configure_ssc0_pins(pins);
852                 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
853                 break;
854         case AT91CAP9_ID_SSC1:
855                 pdev = &at91cap9_ssc1_device;
856                 configure_ssc1_pins(pins);
857                 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
858                 break;
859         default:
860                 return;
861         }
862
863         platform_device_register(pdev);
864 }
865
866 #else
867 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
868 #endif
869
870
871 /* --------------------------------------------------------------------
872  *  UART
873  * -------------------------------------------------------------------- */
874
875 #if defined(CONFIG_SERIAL_ATMEL)
876 static struct resource dbgu_resources[] = {
877         [0] = {
878                 .start  = AT91_VA_BASE_SYS + AT91_DBGU,
879                 .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
880                 .flags  = IORESOURCE_MEM,
881         },
882         [1] = {
883                 .start  = AT91_ID_SYS,
884                 .end    = AT91_ID_SYS,
885                 .flags  = IORESOURCE_IRQ,
886         },
887 };
888
889 static struct atmel_uart_data dbgu_data = {
890         .use_dma_tx     = 0,
891         .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
892         .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
893 };
894
895 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
896
897 static struct platform_device at91cap9_dbgu_device = {
898         .name           = "atmel_usart",
899         .id             = 0,
900         .dev            = {
901                                 .dma_mask               = &dbgu_dmamask,
902                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
903                                 .platform_data          = &dbgu_data,
904         },
905         .resource       = dbgu_resources,
906         .num_resources  = ARRAY_SIZE(dbgu_resources),
907 };
908
909 static inline void configure_dbgu_pins(void)
910 {
911         at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
912         at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
913 }
914
915 static struct resource uart0_resources[] = {
916         [0] = {
917                 .start  = AT91CAP9_BASE_US0,
918                 .end    = AT91CAP9_BASE_US0 + SZ_16K - 1,
919                 .flags  = IORESOURCE_MEM,
920         },
921         [1] = {
922                 .start  = AT91CAP9_ID_US0,
923                 .end    = AT91CAP9_ID_US0,
924                 .flags  = IORESOURCE_IRQ,
925         },
926 };
927
928 static struct atmel_uart_data uart0_data = {
929         .use_dma_tx     = 1,
930         .use_dma_rx     = 1,
931 };
932
933 static u64 uart0_dmamask = DMA_BIT_MASK(32);
934
935 static struct platform_device at91cap9_uart0_device = {
936         .name           = "atmel_usart",
937         .id             = 1,
938         .dev            = {
939                                 .dma_mask               = &uart0_dmamask,
940                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
941                                 .platform_data          = &uart0_data,
942         },
943         .resource       = uart0_resources,
944         .num_resources  = ARRAY_SIZE(uart0_resources),
945 };
946
947 static inline void configure_usart0_pins(unsigned pins)
948 {
949         at91_set_A_periph(AT91_PIN_PA22, 1);            /* TXD0 */
950         at91_set_A_periph(AT91_PIN_PA23, 0);            /* RXD0 */
951
952         if (pins & ATMEL_UART_RTS)
953                 at91_set_A_periph(AT91_PIN_PA24, 0);    /* RTS0 */
954         if (pins & ATMEL_UART_CTS)
955                 at91_set_A_periph(AT91_PIN_PA25, 0);    /* CTS0 */
956 }
957
958 static struct resource uart1_resources[] = {
959         [0] = {
960                 .start  = AT91CAP9_BASE_US1,
961                 .end    = AT91CAP9_BASE_US1 + SZ_16K - 1,
962                 .flags  = IORESOURCE_MEM,
963         },
964         [1] = {
965                 .start  = AT91CAP9_ID_US1,
966                 .end    = AT91CAP9_ID_US1,
967                 .flags  = IORESOURCE_IRQ,
968         },
969 };
970
971 static struct atmel_uart_data uart1_data = {
972         .use_dma_tx     = 1,
973         .use_dma_rx     = 1,
974 };
975
976 static u64 uart1_dmamask = DMA_BIT_MASK(32);
977
978 static struct platform_device at91cap9_uart1_device = {
979         .name           = "atmel_usart",
980         .id             = 2,
981         .dev            = {
982                                 .dma_mask               = &uart1_dmamask,
983                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
984                                 .platform_data          = &uart1_data,
985         },
986         .resource       = uart1_resources,
987         .num_resources  = ARRAY_SIZE(uart1_resources),
988 };
989
990 static inline void configure_usart1_pins(unsigned pins)
991 {
992         at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
993         at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
994
995         if (pins & ATMEL_UART_RTS)
996                 at91_set_B_periph(AT91_PIN_PD7, 0);     /* RTS1 */
997         if (pins & ATMEL_UART_CTS)
998                 at91_set_B_periph(AT91_PIN_PD8, 0);     /* CTS1 */
999 }
1000
1001 static struct resource uart2_resources[] = {
1002         [0] = {
1003                 .start  = AT91CAP9_BASE_US2,
1004                 .end    = AT91CAP9_BASE_US2 + SZ_16K - 1,
1005                 .flags  = IORESOURCE_MEM,
1006         },
1007         [1] = {
1008                 .start  = AT91CAP9_ID_US2,
1009                 .end    = AT91CAP9_ID_US2,
1010                 .flags  = IORESOURCE_IRQ,
1011         },
1012 };
1013
1014 static struct atmel_uart_data uart2_data = {
1015         .use_dma_tx     = 1,
1016         .use_dma_rx     = 1,
1017 };
1018
1019 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1020
1021 static struct platform_device at91cap9_uart2_device = {
1022         .name           = "atmel_usart",
1023         .id             = 3,
1024         .dev            = {
1025                                 .dma_mask               = &uart2_dmamask,
1026                                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1027                                 .platform_data          = &uart2_data,
1028         },
1029         .resource       = uart2_resources,
1030         .num_resources  = ARRAY_SIZE(uart2_resources),
1031 };
1032
1033 static inline void configure_usart2_pins(unsigned pins)
1034 {
1035         at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
1036         at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
1037
1038         if (pins & ATMEL_UART_RTS)
1039                 at91_set_B_periph(AT91_PIN_PD5, 0);     /* RTS2 */
1040         if (pins & ATMEL_UART_CTS)
1041                 at91_set_B_periph(AT91_PIN_PD6, 0);     /* CTS2 */
1042 }
1043
1044 static struct platform_device *at91_uarts[ATMEL_MAX_UART];      /* the UARTs to use */
1045 struct platform_device *atmel_default_console_device;   /* the serial console device */
1046
1047 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1048 {
1049         struct platform_device *pdev;
1050
1051         switch (id) {
1052                 case 0:         /* DBGU */
1053                         pdev = &at91cap9_dbgu_device;
1054                         configure_dbgu_pins();
1055                         at91_clock_associate("mck", &pdev->dev, "usart");
1056                         break;
1057                 case AT91CAP9_ID_US0:
1058                         pdev = &at91cap9_uart0_device;
1059                         configure_usart0_pins(pins);
1060                         at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1061                         break;
1062                 case AT91CAP9_ID_US1:
1063                         pdev = &at91cap9_uart1_device;
1064                         configure_usart1_pins(pins);
1065                         at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1066                         break;
1067                 case AT91CAP9_ID_US2:
1068                         pdev = &at91cap9_uart2_device;
1069                         configure_usart2_pins(pins);
1070                         at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1071                         break;
1072                 default:
1073                         return;
1074         }
1075         pdev->id = portnr;              /* update to mapped ID */
1076
1077         if (portnr < ATMEL_MAX_UART)
1078                 at91_uarts[portnr] = pdev;
1079 }
1080
1081 void __init at91_set_serial_console(unsigned portnr)
1082 {
1083         if (portnr < ATMEL_MAX_UART)
1084                 atmel_default_console_device = at91_uarts[portnr];
1085         if (!atmel_default_console_device)
1086                 printk(KERN_INFO "AT91: No default serial console defined.\n");
1087 }
1088
1089 void __init at91_add_device_serial(void)
1090 {
1091         int i;
1092
1093         for (i = 0; i < ATMEL_MAX_UART; i++) {
1094                 if (at91_uarts[i])
1095                         platform_device_register(at91_uarts[i]);
1096         }
1097 }
1098 #else
1099 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1100 void __init at91_set_serial_console(unsigned portnr) {}
1101 void __init at91_add_device_serial(void) {}
1102 #endif
1103
1104
1105 /* -------------------------------------------------------------------- */
1106 /*
1107  * These devices are always present and don't need any board-specific
1108  * setup.
1109  */
1110 static int __init at91_add_standard_devices(void)
1111 {
1112         at91_add_device_rtt();
1113         at91_add_device_watchdog();
1114         at91_add_device_tc();
1115         return 0;
1116 }
1117
1118 arch_initcall(at91_add_standard_devices);