4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006, 2007 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include <linux/delay.h>
28 /* Struct to hold initial RF register values (RF Banks) */
30 u8 rf_bank; /* check out ath5k_reg.h */
31 u16 rf_register; /* register address */
32 u32 rf_value[5]; /* register value for different modes (above) */
36 * Mode-specific RF Gain table (64bytes) for RF5111/5112
37 * (RF5110 only comes with AR5210 and only supports a/turbo a mode so initial
38 * RF Gain values are included in AR5K_AR5210_INI)
40 struct ath5k_ini_rfgain {
41 u16 rfg_register; /* RF Gain register address */
42 u32 rfg_value[2]; /* [freq (see below)] */
45 struct ath5k_gain_opt {
48 const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
51 /* RF5111 mode-specific init registers */
52 static const struct ath5k_ini_rf rfregs_5111[] = {
54 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
55 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
57 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
59 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
61 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
63 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
65 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
67 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
69 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
71 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
73 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
75 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
77 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
79 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
81 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
83 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
85 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
87 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
89 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
91 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
93 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
95 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
97 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
99 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
101 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
103 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
105 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
107 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
109 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
113 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
115 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
117 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
119 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
121 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
123 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
125 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
127 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
129 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
131 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
133 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
135 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
137 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
139 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
141 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
143 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
146 /* Initial RF Gain settings for RF5111 */
147 static const struct ath5k_ini_rfgain rfgain_5111[] = {
149 { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } },
150 { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } },
151 { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } },
152 { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } },
153 { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } },
154 { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } },
155 { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } },
156 { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } },
157 { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } },
158 { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } },
159 { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } },
160 { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } },
161 { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } },
162 { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } },
163 { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } },
164 { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } },
165 { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } },
166 { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } },
167 { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } },
168 { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } },
169 { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } },
170 { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } },
171 { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } },
172 { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } },
173 { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } },
174 { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } },
175 { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } },
176 { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } },
177 { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } },
178 { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } },
179 { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } },
180 { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } },
181 { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } },
182 { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } },
183 { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } },
184 { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } },
185 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } },
186 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } },
187 { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } },
188 { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } },
189 { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } },
190 { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } },
191 { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } },
192 { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } },
193 { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } },
194 { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } },
195 { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } },
196 { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } },
197 { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } },
198 { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } },
199 { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } },
200 { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } },
201 { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } },
202 { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } },
203 { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } },
204 { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } },
205 { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } },
206 { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } },
207 { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } },
208 { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } },
209 { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } },
210 { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } },
211 { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } },
212 { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } },
215 static const struct ath5k_gain_opt rfgain_opt_5111 = {
219 { { 4, 1, 1, 1 }, 6 },
220 { { 4, 0, 1, 1 }, 4 },
221 { { 3, 1, 1, 1 }, 3 },
222 { { 4, 0, 0, 1 }, 1 },
223 { { 4, 1, 1, 0 }, 0 },
224 { { 4, 0, 1, 0 }, -2 },
225 { { 3, 1, 1, 0 }, -3 },
226 { { 4, 0, 0, 0 }, -4 },
227 { { 2, 1, 1, 0 }, -6 }
231 /* RF5112 mode-specific init registers */
232 static const struct ath5k_ini_rf rfregs_5112[] = {
234 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
235 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
237 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
239 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
241 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
243 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
245 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
247 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
249 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
251 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
253 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
255 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
257 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
259 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
261 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
263 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
265 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
267 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
269 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
271 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
273 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
275 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
277 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
279 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
281 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
283 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
285 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
287 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
289 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
291 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
293 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
295 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
297 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
299 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
301 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
303 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
305 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
307 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
309 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
311 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
313 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
315 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
317 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
319 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
321 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
323 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
325 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
327 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
329 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
331 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
333 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
335 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
337 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
339 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
341 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
344 /* RF5112A mode-specific init registers */
345 static const struct ath5k_ini_rf rfregs_5112a[] = {
347 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
348 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
350 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
352 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
354 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
356 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
358 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
360 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
362 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
364 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
366 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
368 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
370 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
372 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
374 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
376 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
378 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
380 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
382 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
384 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
386 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
388 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
390 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
392 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
394 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
396 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
398 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
400 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
402 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
404 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
406 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
408 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
410 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
412 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
414 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
416 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
418 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
420 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
422 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
424 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
426 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
428 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
430 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
432 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
434 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
436 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
438 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
440 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
442 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
444 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
446 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
448 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
450 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
452 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
454 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
456 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
458 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
462 static const struct ath5k_ini_rf rfregs_2112a[] = {
463 { 1, AR5K_RF_BUFFER_CONTROL_4,
464 /* mode b mode g mode gTurbo */
465 { 0x00000020, 0x00000020, 0x00000020 } },
466 { 2, AR5K_RF_BUFFER_CONTROL_3,
467 { 0x03060408, 0x03060408, 0x03070408 } },
468 { 3, AR5K_RF_BUFFER_CONTROL_6,
469 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
471 { 0x0a000000, 0x0a000000, 0x0a000000 } },
473 { 0x00000000, 0x00000000, 0x00000000 } },
475 { 0x00800000, 0x00800000, 0x00800000 } },
477 { 0x002a0000, 0x002a0000, 0x002a0000 } },
479 { 0x00010000, 0x00010000, 0x00010000 } },
481 { 0x00000000, 0x00000000, 0x00000000 } },
483 { 0x00180000, 0x00180000, 0x00180000 } },
485 { 0x006e0000, 0x006e0000, 0x006e0000 } },
487 { 0x00c70000, 0x00c70000, 0x00c70000 } },
489 { 0x004b0000, 0x004b0000, 0x004b0000 } },
491 { 0x04480000, 0x04480000, 0x04480000 } },
493 { 0x002a0000, 0x002a0000, 0x002a0000 } },
495 { 0x00e40000, 0x00e40000, 0x00e40000 } },
497 { 0x00000000, 0x00000000, 0x00000000 } },
499 { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
501 { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
503 { 0x043f0000, 0x043f0000, 0x043f0000 } },
505 { 0x0c0c0000, 0x0c0c0000, 0x0c0c0000 } },
507 { 0x02190000, 0x02190000, 0x02190000 } },
509 { 0x00240000, 0x00240000, 0x00240000 } },
511 { 0x00b40000, 0x00b40000, 0x00b40000 } },
513 { 0x00990000, 0x00990000, 0x00990000 } },
515 { 0x00500000, 0x00500000, 0x00500000 } },
517 { 0x002a0000, 0x002a0000, 0x002a0000 } },
519 { 0x00120000, 0x00120000, 0x00120000 } },
521 { 0xc0320000, 0xc0320000, 0xc0320000 } },
523 { 0x01740000, 0x01740000, 0x01740000 } },
525 { 0x00110000, 0x00110000, 0x00110000 } },
527 { 0x86280000, 0x86280000, 0x86280000 } },
529 { 0x31840000, 0x31840000, 0x31840000 } },
531 { 0x00f20080, 0x00f20080, 0x00f20080 } },
533 { 0x00070019, 0x00070019, 0x00070019 } },
535 { 0x00000000, 0x00000000, 0x00000000 } },
537 { 0x00000000, 0x00000000, 0x00000000 } },
539 { 0x000000b2, 0x000000b2, 0x000000b2 } },
541 { 0x00b02184, 0x00b02184, 0x00b02184 } },
543 { 0x004125a4, 0x004125a4, 0x004125a4 } },
545 { 0x00119220, 0x00119220, 0x00119220 } },
547 { 0x001a4800, 0x001a4800, 0x001a4800 } },
548 { 6, AR5K_RF_BUFFER_CONTROL_5,
549 { 0x000b0230, 0x000b0230, 0x000b0230 } },
551 { 0x00000094, 0x00000094, 0x00000094 } },
553 { 0x00000091, 0x00000091, 0x00000091 } },
555 { 0x00000012, 0x00000012, 0x00000012 } },
557 { 0x00000080, 0x00000080, 0x00000080 } },
559 { 0x000000d9, 0x000000d9, 0x000000d9 } },
561 { 0x00000060, 0x00000060, 0x00000060 } },
563 { 0x000000f0, 0x000000f0, 0x000000f0 } },
565 { 0x000000a2, 0x000000a2, 0x000000a2 } },
567 { 0x00000052, 0x00000052, 0x00000052 } },
569 { 0x000000d4, 0x000000d4, 0x000000d4 } },
571 { 0x000014cc, 0x000014cc, 0x000014cc } },
573 { 0x0000048c, 0x0000048c, 0x0000048c } },
574 { 7, AR5K_RF_BUFFER_CONTROL_1,
575 { 0x00000003, 0x00000003, 0x00000003 } },
578 /* RF5413/5414 mode-specific init registers */
579 static const struct ath5k_ini_rf rfregs_5413[] = {
581 /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
582 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
584 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
586 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
588 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
590 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
592 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
594 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
596 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
598 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
600 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
602 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
604 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
606 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
608 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
610 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
612 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
614 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
616 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
618 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
620 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
622 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
624 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
626 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
628 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
630 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
632 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
634 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
636 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
638 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
640 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
642 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
644 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
646 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } },
648 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } },
650 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } },
652 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
654 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
656 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
658 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } },
660 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
662 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
664 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
666 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
669 /* RF2413/2414 mode-specific init registers */
670 static const struct ath5k_ini_rf rfregs_2413[] = {
671 { 1, AR5K_RF_BUFFER_CONTROL_4,
672 /* mode b mode g mode gTurbo */
673 { 0x00000020, 0x00000020, 0x00000020 } },
674 { 2, AR5K_RF_BUFFER_CONTROL_3,
675 { 0x02001408, 0x02001408, 0x02001408 } },
676 { 3, AR5K_RF_BUFFER_CONTROL_6,
677 { 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
679 { 0xf0000000, 0xf0000000, 0xf0000000 } },
681 { 0x00000000, 0x00000000, 0x00000000 } },
683 { 0x03000000, 0x03000000, 0x03000000 } },
685 { 0x00000000, 0x00000000, 0x00000000 } },
687 { 0x00000000, 0x00000000, 0x00000000 } },
689 { 0x00000000, 0x00000000, 0x00000000 } },
691 { 0x00000000, 0x00000000, 0x00000000 } },
693 { 0x00000000, 0x00000000, 0x00000000 } },
695 { 0x40400000, 0x40400000, 0x40400000 } },
697 { 0x65050000, 0x65050000, 0x65050000 } },
699 { 0x00000000, 0x00000000, 0x00000000 } },
701 { 0x00000000, 0x00000000, 0x00000000 } },
703 { 0x00420000, 0x00420000, 0x00420000 } },
705 { 0x00b50000, 0x00b50000, 0x00b50000 } },
707 { 0x00030000, 0x00030000, 0x00030000 } },
709 { 0x00f70000, 0x00f70000, 0x00f70000 } },
711 { 0x009d0000, 0x009d0000, 0x009d0000 } },
713 { 0x00220000, 0x00220000, 0x00220000 } },
715 { 0x04220000, 0x04220000, 0x04220000 } },
717 { 0x00230018, 0x00230018, 0x00230018 } },
719 { 0x00280050, 0x00280050, 0x00280050 } },
721 { 0x005000c3, 0x005000c3, 0x005000c3 } },
723 { 0x0004007f, 0x0004007f, 0x0004007f } },
725 { 0x00000458, 0x00000458, 0x00000458 } },
727 { 0x00000000, 0x00000000, 0x00000000 } },
729 { 0x0000c000, 0x0000c000, 0x0000c000 } },
730 { 6, AR5K_RF_BUFFER_CONTROL_5,
731 { 0x00400230, 0x00400230, 0x00400230 } },
733 { 0x00006400, 0x00006400, 0x00006400 } },
735 { 0x00000800, 0x00000800, 0x00000800 } },
736 { 7, AR5K_RF_BUFFER_CONTROL_2,
737 { 0x0000000e, 0x0000000e, 0x0000000e } },
740 /* RF2425 mode-specific init registers */
741 static const struct ath5k_ini_rf rfregs_2425[] = {
742 { 1, AR5K_RF_BUFFER_CONTROL_4,
743 /* mode g mode gTurbo */
744 { 0x00000020, 0x00000020 } },
745 { 2, AR5K_RF_BUFFER_CONTROL_3,
746 { 0x02001408, 0x02001408 } },
747 { 3, AR5K_RF_BUFFER_CONTROL_6,
748 { 0x00e020c0, 0x00e020c0 } },
750 { 0x10000000, 0x10000000 } },
752 { 0x00000000, 0x00000000 } },
754 { 0x00000000, 0x00000000 } },
756 { 0x00000000, 0x00000000 } },
758 { 0x00000000, 0x00000000 } },
760 { 0x00000000, 0x00000000 } },
762 { 0x00000000, 0x00000000 } },
764 { 0x00000000, 0x00000000 } },
766 { 0x00000000, 0x00000000 } },
768 { 0x00000000, 0x00000000 } },
770 { 0x00000000, 0x00000000 } },
772 { 0x002a0000, 0x002a0000 } },
774 { 0x00000000, 0x00000000 } },
776 { 0x00000000, 0x00000000 } },
778 { 0x00100000, 0x00100000 } },
780 { 0x00020000, 0x00020000 } },
782 { 0x00730000, 0x00730000 } },
784 { 0x00f80000, 0x00f80000 } },
786 { 0x00e70000, 0x00e70000 } },
788 { 0x00140000, 0x00140000 } },
790 { 0x00910040, 0x00910040 } },
792 { 0x0007001a, 0x0007001a } },
794 { 0x00410000, 0x00410000 } },
796 { 0x00810060, 0x00810060 } },
798 { 0x00020803, 0x00020803 } },
800 { 0x00000000, 0x00000000 } },
802 { 0x00000000, 0x00000000 } },
804 { 0x00001660, 0x00001660 } },
806 { 0x00001688, 0x00001688 } },
807 { 6, AR5K_RF_BUFFER_CONTROL_1,
808 { 0x00000001, 0x00000001 } },
810 { 0x00006400, 0x00006400 } },
812 { 0x00000800, 0x00000800 } },
813 { 7, AR5K_RF_BUFFER_CONTROL_2,
814 { 0x0000000e, 0x0000000e } },
817 /* Initial RF Gain settings for RF5112 */
818 static const struct ath5k_ini_rfgain rfgain_5112[] = {
820 { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } },
821 { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } },
822 { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } },
823 { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } },
824 { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } },
825 { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } },
826 { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } },
827 { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } },
828 { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } },
829 { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } },
830 { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } },
831 { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } },
832 { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } },
833 { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } },
834 { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } },
835 { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } },
836 { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } },
837 { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } },
838 { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } },
839 { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } },
840 { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } },
841 { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } },
842 { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } },
843 { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } },
844 { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } },
845 { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } },
846 { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } },
847 { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } },
848 { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } },
849 { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } },
850 { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } },
851 { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } },
852 { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } },
853 { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } },
854 { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } },
855 { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } },
856 { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } },
857 { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } },
858 { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } },
859 { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } },
860 { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } },
861 { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } },
862 { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } },
863 { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } },
864 { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } },
865 { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } },
866 { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } },
867 { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } },
868 { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } },
869 { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } },
870 { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } },
871 { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } },
872 { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } },
873 { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } },
874 { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } },
875 { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } },
876 { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } },
877 { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } },
878 { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } },
879 { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } },
880 { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } },
881 { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } },
882 { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } },
883 { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } },
886 /* Initial RF Gain settings for RF5413 */
887 static const struct ath5k_ini_rfgain rfgain_5413[] = {
889 { AR5K_RF_GAIN(0), { 0x00000000, 0x00000000 } },
890 { AR5K_RF_GAIN(1), { 0x00000040, 0x00000040 } },
891 { AR5K_RF_GAIN(2), { 0x00000080, 0x00000080 } },
892 { AR5K_RF_GAIN(3), { 0x000001a1, 0x00000161 } },
893 { AR5K_RF_GAIN(4), { 0x000001e1, 0x000001a1 } },
894 { AR5K_RF_GAIN(5), { 0x00000021, 0x000001e1 } },
895 { AR5K_RF_GAIN(6), { 0x00000061, 0x00000021 } },
896 { AR5K_RF_GAIN(7), { 0x00000188, 0x00000061 } },
897 { AR5K_RF_GAIN(8), { 0x000001c8, 0x00000188 } },
898 { AR5K_RF_GAIN(9), { 0x00000008, 0x000001c8 } },
899 { AR5K_RF_GAIN(10), { 0x00000048, 0x00000008 } },
900 { AR5K_RF_GAIN(11), { 0x00000088, 0x00000048 } },
901 { AR5K_RF_GAIN(12), { 0x000001a9, 0x00000088 } },
902 { AR5K_RF_GAIN(13), { 0x000001e9, 0x00000169 } },
903 { AR5K_RF_GAIN(14), { 0x00000029, 0x000001a9 } },
904 { AR5K_RF_GAIN(15), { 0x00000069, 0x000001e9 } },
905 { AR5K_RF_GAIN(16), { 0x000001d0, 0x00000029 } },
906 { AR5K_RF_GAIN(17), { 0x00000010, 0x00000069 } },
907 { AR5K_RF_GAIN(18), { 0x00000050, 0x00000190 } },
908 { AR5K_RF_GAIN(19), { 0x00000090, 0x000001d0 } },
909 { AR5K_RF_GAIN(20), { 0x000001b1, 0x00000010 } },
910 { AR5K_RF_GAIN(21), { 0x000001f1, 0x00000050 } },
911 { AR5K_RF_GAIN(22), { 0x00000031, 0x00000090 } },
912 { AR5K_RF_GAIN(23), { 0x00000071, 0x00000171 } },
913 { AR5K_RF_GAIN(24), { 0x000001b8, 0x000001b1 } },
914 { AR5K_RF_GAIN(25), { 0x000001f8, 0x000001f1 } },
915 { AR5K_RF_GAIN(26), { 0x00000038, 0x00000031 } },
916 { AR5K_RF_GAIN(27), { 0x00000078, 0x00000071 } },
917 { AR5K_RF_GAIN(28), { 0x00000199, 0x00000198 } },
918 { AR5K_RF_GAIN(29), { 0x000001d9, 0x000001d8 } },
919 { AR5K_RF_GAIN(30), { 0x00000019, 0x00000018 } },
920 { AR5K_RF_GAIN(31), { 0x00000059, 0x00000058 } },
921 { AR5K_RF_GAIN(32), { 0x00000099, 0x00000098 } },
922 { AR5K_RF_GAIN(33), { 0x000000d9, 0x00000179 } },
923 { AR5K_RF_GAIN(34), { 0x000000f9, 0x000001b9 } },
924 { AR5K_RF_GAIN(35), { 0x000000f9, 0x000001f9 } },
925 { AR5K_RF_GAIN(36), { 0x000000f9, 0x00000039 } },
926 { AR5K_RF_GAIN(37), { 0x000000f9, 0x00000079 } },
927 { AR5K_RF_GAIN(38), { 0x000000f9, 0x000000b9 } },
928 { AR5K_RF_GAIN(39), { 0x000000f9, 0x000000f9 } },
929 { AR5K_RF_GAIN(40), { 0x000000f9, 0x000000f9 } },
930 { AR5K_RF_GAIN(41), { 0x000000f9, 0x000000f9 } },
931 { AR5K_RF_GAIN(42), { 0x000000f9, 0x000000f9 } },
932 { AR5K_RF_GAIN(43), { 0x000000f9, 0x000000f9 } },
933 { AR5K_RF_GAIN(44), { 0x000000f9, 0x000000f9 } },
934 { AR5K_RF_GAIN(45), { 0x000000f9, 0x000000f9 } },
935 { AR5K_RF_GAIN(46), { 0x000000f9, 0x000000f9 } },
936 { AR5K_RF_GAIN(47), { 0x000000f9, 0x000000f9 } },
937 { AR5K_RF_GAIN(48), { 0x000000f9, 0x000000f9 } },
938 { AR5K_RF_GAIN(49), { 0x000000f9, 0x000000f9 } },
939 { AR5K_RF_GAIN(50), { 0x000000f9, 0x000000f9 } },
940 { AR5K_RF_GAIN(51), { 0x000000f9, 0x000000f9 } },
941 { AR5K_RF_GAIN(52), { 0x000000f9, 0x000000f9 } },
942 { AR5K_RF_GAIN(53), { 0x000000f9, 0x000000f9 } },
943 { AR5K_RF_GAIN(54), { 0x000000f9, 0x000000f9 } },
944 { AR5K_RF_GAIN(55), { 0x000000f9, 0x000000f9 } },
945 { AR5K_RF_GAIN(56), { 0x000000f9, 0x000000f9 } },
946 { AR5K_RF_GAIN(57), { 0x000000f9, 0x000000f9 } },
947 { AR5K_RF_GAIN(58), { 0x000000f9, 0x000000f9 } },
948 { AR5K_RF_GAIN(59), { 0x000000f9, 0x000000f9 } },
949 { AR5K_RF_GAIN(60), { 0x000000f9, 0x000000f9 } },
950 { AR5K_RF_GAIN(61), { 0x000000f9, 0x000000f9 } },
951 { AR5K_RF_GAIN(62), { 0x000000f9, 0x000000f9 } },
952 { AR5K_RF_GAIN(63), { 0x000000f9, 0x000000f9 } },
955 /* Initial RF Gain settings for RF2413 */
956 static const struct ath5k_ini_rfgain rfgain_2413[] = {
957 { AR5K_RF_GAIN(0), { 0x00000000 } },
958 { AR5K_RF_GAIN(1), { 0x00000040 } },
959 { AR5K_RF_GAIN(2), { 0x00000080 } },
960 { AR5K_RF_GAIN(3), { 0x00000181 } },
961 { AR5K_RF_GAIN(4), { 0x000001c1 } },
962 { AR5K_RF_GAIN(5), { 0x00000001 } },
963 { AR5K_RF_GAIN(6), { 0x00000041 } },
964 { AR5K_RF_GAIN(7), { 0x00000081 } },
965 { AR5K_RF_GAIN(8), { 0x00000168 } },
966 { AR5K_RF_GAIN(9), { 0x000001a8 } },
967 { AR5K_RF_GAIN(10), { 0x000001e8 } },
968 { AR5K_RF_GAIN(11), { 0x00000028 } },
969 { AR5K_RF_GAIN(12), { 0x00000068 } },
970 { AR5K_RF_GAIN(13), { 0x00000189 } },
971 { AR5K_RF_GAIN(14), { 0x000001c9 } },
972 { AR5K_RF_GAIN(15), { 0x00000009 } },
973 { AR5K_RF_GAIN(16), { 0x00000049 } },
974 { AR5K_RF_GAIN(17), { 0x00000089 } },
975 { AR5K_RF_GAIN(18), { 0x00000190 } },
976 { AR5K_RF_GAIN(19), { 0x000001d0 } },
977 { AR5K_RF_GAIN(20), { 0x00000010 } },
978 { AR5K_RF_GAIN(21), { 0x00000050 } },
979 { AR5K_RF_GAIN(22), { 0x00000090 } },
980 { AR5K_RF_GAIN(23), { 0x00000191 } },
981 { AR5K_RF_GAIN(24), { 0x000001d1 } },
982 { AR5K_RF_GAIN(25), { 0x00000011 } },
983 { AR5K_RF_GAIN(26), { 0x00000051 } },
984 { AR5K_RF_GAIN(27), { 0x00000091 } },
985 { AR5K_RF_GAIN(28), { 0x00000178 } },
986 { AR5K_RF_GAIN(29), { 0x000001b8 } },
987 { AR5K_RF_GAIN(30), { 0x000001f8 } },
988 { AR5K_RF_GAIN(31), { 0x00000038 } },
989 { AR5K_RF_GAIN(32), { 0x00000078 } },
990 { AR5K_RF_GAIN(33), { 0x00000199 } },
991 { AR5K_RF_GAIN(34), { 0x000001d9 } },
992 { AR5K_RF_GAIN(35), { 0x00000019 } },
993 { AR5K_RF_GAIN(36), { 0x00000059 } },
994 { AR5K_RF_GAIN(37), { 0x00000099 } },
995 { AR5K_RF_GAIN(38), { 0x000000d9 } },
996 { AR5K_RF_GAIN(39), { 0x000000f9 } },
997 { AR5K_RF_GAIN(40), { 0x000000f9 } },
998 { AR5K_RF_GAIN(41), { 0x000000f9 } },
999 { AR5K_RF_GAIN(42), { 0x000000f9 } },
1000 { AR5K_RF_GAIN(43), { 0x000000f9 } },
1001 { AR5K_RF_GAIN(44), { 0x000000f9 } },
1002 { AR5K_RF_GAIN(45), { 0x000000f9 } },
1003 { AR5K_RF_GAIN(46), { 0x000000f9 } },
1004 { AR5K_RF_GAIN(47), { 0x000000f9 } },
1005 { AR5K_RF_GAIN(48), { 0x000000f9 } },
1006 { AR5K_RF_GAIN(49), { 0x000000f9 } },
1007 { AR5K_RF_GAIN(50), { 0x000000f9 } },
1008 { AR5K_RF_GAIN(51), { 0x000000f9 } },
1009 { AR5K_RF_GAIN(52), { 0x000000f9 } },
1010 { AR5K_RF_GAIN(53), { 0x000000f9 } },
1011 { AR5K_RF_GAIN(54), { 0x000000f9 } },
1012 { AR5K_RF_GAIN(55), { 0x000000f9 } },
1013 { AR5K_RF_GAIN(56), { 0x000000f9 } },
1014 { AR5K_RF_GAIN(57), { 0x000000f9 } },
1015 { AR5K_RF_GAIN(58), { 0x000000f9 } },
1016 { AR5K_RF_GAIN(59), { 0x000000f9 } },
1017 { AR5K_RF_GAIN(60), { 0x000000f9 } },
1018 { AR5K_RF_GAIN(61), { 0x000000f9 } },
1019 { AR5K_RF_GAIN(62), { 0x000000f9 } },
1020 { AR5K_RF_GAIN(63), { 0x000000f9 } },
1023 /* Initial RF Gain settings for RF2425 */
1024 static const struct ath5k_ini_rfgain rfgain_2425[] = {
1025 { AR5K_RF_GAIN(0), { 0x00000000 } },
1026 { AR5K_RF_GAIN(1), { 0x00000040 } },
1027 { AR5K_RF_GAIN(2), { 0x00000080 } },
1028 { AR5K_RF_GAIN(3), { 0x00000181 } },
1029 { AR5K_RF_GAIN(4), { 0x000001c1 } },
1030 { AR5K_RF_GAIN(5), { 0x00000001 } },
1031 { AR5K_RF_GAIN(6), { 0x00000041 } },
1032 { AR5K_RF_GAIN(7), { 0x00000081 } },
1033 { AR5K_RF_GAIN(8), { 0x00000188 } },
1034 { AR5K_RF_GAIN(9), { 0x000001c8 } },
1035 { AR5K_RF_GAIN(10), { 0x00000008 } },
1036 { AR5K_RF_GAIN(11), { 0x00000048 } },
1037 { AR5K_RF_GAIN(12), { 0x00000088 } },
1038 { AR5K_RF_GAIN(13), { 0x00000189 } },
1039 { AR5K_RF_GAIN(14), { 0x000001c9 } },
1040 { AR5K_RF_GAIN(15), { 0x00000009 } },
1041 { AR5K_RF_GAIN(16), { 0x00000049 } },
1042 { AR5K_RF_GAIN(17), { 0x00000089 } },
1043 { AR5K_RF_GAIN(18), { 0x000001b0 } },
1044 { AR5K_RF_GAIN(19), { 0x000001f0 } },
1045 { AR5K_RF_GAIN(20), { 0x00000030 } },
1046 { AR5K_RF_GAIN(21), { 0x00000070 } },
1047 { AR5K_RF_GAIN(22), { 0x00000171 } },
1048 { AR5K_RF_GAIN(23), { 0x000001b1 } },
1049 { AR5K_RF_GAIN(24), { 0x000001f1 } },
1050 { AR5K_RF_GAIN(25), { 0x00000031 } },
1051 { AR5K_RF_GAIN(26), { 0x00000071 } },
1052 { AR5K_RF_GAIN(27), { 0x000001b8 } },
1053 { AR5K_RF_GAIN(28), { 0x000001f8 } },
1054 { AR5K_RF_GAIN(29), { 0x00000038 } },
1055 { AR5K_RF_GAIN(30), { 0x00000078 } },
1056 { AR5K_RF_GAIN(31), { 0x000000b8 } },
1057 { AR5K_RF_GAIN(32), { 0x000001b9 } },
1058 { AR5K_RF_GAIN(33), { 0x000001f9 } },
1059 { AR5K_RF_GAIN(34), { 0x00000039 } },
1060 { AR5K_RF_GAIN(35), { 0x00000079 } },
1061 { AR5K_RF_GAIN(36), { 0x000000b9 } },
1062 { AR5K_RF_GAIN(37), { 0x000000f9 } },
1063 { AR5K_RF_GAIN(38), { 0x000000f9 } },
1064 { AR5K_RF_GAIN(39), { 0x000000f9 } },
1065 { AR5K_RF_GAIN(40), { 0x000000f9 } },
1066 { AR5K_RF_GAIN(41), { 0x000000f9 } },
1067 { AR5K_RF_GAIN(42), { 0x000000f9 } },
1068 { AR5K_RF_GAIN(43), { 0x000000f9 } },
1069 { AR5K_RF_GAIN(44), { 0x000000f9 } },
1070 { AR5K_RF_GAIN(45), { 0x000000f9 } },
1071 { AR5K_RF_GAIN(46), { 0x000000f9 } },
1072 { AR5K_RF_GAIN(47), { 0x000000f9 } },
1073 { AR5K_RF_GAIN(48), { 0x000000f9 } },
1074 { AR5K_RF_GAIN(49), { 0x000000f9 } },
1075 { AR5K_RF_GAIN(50), { 0x000000f9 } },
1076 { AR5K_RF_GAIN(51), { 0x000000f9 } },
1077 { AR5K_RF_GAIN(52), { 0x000000f9 } },
1078 { AR5K_RF_GAIN(53), { 0x000000f9 } },
1079 { AR5K_RF_GAIN(54), { 0x000000f9 } },
1080 { AR5K_RF_GAIN(55), { 0x000000f9 } },
1081 { AR5K_RF_GAIN(56), { 0x000000f9 } },
1082 { AR5K_RF_GAIN(57), { 0x000000f9 } },
1083 { AR5K_RF_GAIN(58), { 0x000000f9 } },
1084 { AR5K_RF_GAIN(59), { 0x000000f9 } },
1085 { AR5K_RF_GAIN(60), { 0x000000f9 } },
1086 { AR5K_RF_GAIN(61), { 0x000000f9 } },
1087 { AR5K_RF_GAIN(62), { 0x000000f9 } },
1088 { AR5K_RF_GAIN(63), { 0x000000f9 } },
1091 static const struct ath5k_gain_opt rfgain_opt_5112 = {
1095 { { 3, 0, 0, 0, 0, 0, 0 }, 6 },
1096 { { 2, 0, 0, 0, 0, 0, 0 }, 0 },
1097 { { 1, 0, 0, 0, 0, 0, 0 }, -3 },
1098 { { 0, 0, 0, 0, 0, 0, 0 }, -6 },
1099 { { 0, 1, 1, 0, 0, 0, 0 }, -8 },
1100 { { 0, 1, 1, 0, 1, 1, 0 }, -10 },
1101 { { 0, 1, 0, 1, 1, 1, 0 }, -13 },
1102 { { 0, 1, 0, 1, 1, 0, 1 }, -16 },
1107 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
1109 static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
1110 u32 first, u32 col, bool set)
1112 u32 mask, entry, last, data, shift, position;
1119 /* should not happen */
1122 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
1123 ATH5K_PRINTF("invalid values at offset %u\n", offset);
1127 entry = ((first - 1) / 8) + offset;
1128 position = (first - 1) % 8;
1131 data = ath5k_hw_bitswap(reg, bits);
1133 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
1134 last = (position + left > 8) ? 8 : position + left;
1135 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
1139 rf[entry] |= ((data << position) << (col * 8)) & mask;
1140 data >>= (8 - position);
1142 data = (((rf[entry] & mask) >> (col * 8)) >> position)
1144 shift += last - position;
1147 left -= 8 - position;
1150 data = set ? 1 : ath5k_hw_bitswap(data, bits);
1155 static u32 ath5k_hw_rfregs_gainf_corr(struct ath5k_hw *ah)
1160 if (ah->ah_rf_banks == NULL)
1163 rf = ah->ah_rf_banks;
1164 ah->ah_gain.g_f_corr = 0;
1166 if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
1169 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
1170 mix = ah->ah_gain.g_step->gos_param[0];
1174 ah->ah_gain.g_f_corr = step * 2;
1177 ah->ah_gain.g_f_corr = (step - 5) * 2;
1180 ah->ah_gain.g_f_corr = step;
1183 ah->ah_gain.g_f_corr = 0;
1187 return ah->ah_gain.g_f_corr;
1190 static bool ath5k_hw_rfregs_gain_readback(struct ath5k_hw *ah)
1192 u32 step, mix, level[4];
1195 if (ah->ah_rf_banks == NULL)
1198 rf = ah->ah_rf_banks;
1200 if (ah->ah_radio == AR5K_RF5111) {
1201 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
1204 level[1] = (step == 0x3f) ? 0x32 : step + 4;
1205 level[2] = (step != 0x3f) ? 0x40 : level[0];
1206 level[3] = level[2] + 0x32;
1208 ah->ah_gain.g_high = level[3] -
1209 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
1210 ah->ah_gain.g_low = level[0] +
1211 (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
1213 mix = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
1215 level[0] = level[2] = 0;
1218 level[1] = level[3] = 83;
1220 level[1] = level[3] = 107;
1221 ah->ah_gain.g_high = 55;
1225 return (ah->ah_gain.g_current >= level[0] &&
1226 ah->ah_gain.g_current <= level[1]) ||
1227 (ah->ah_gain.g_current >= level[2] &&
1228 ah->ah_gain.g_current <= level[3]);
1231 static s32 ath5k_hw_rfregs_gain_adjust(struct ath5k_hw *ah)
1233 const struct ath5k_gain_opt *go;
1236 switch (ah->ah_radio) {
1238 go = &rfgain_opt_5111;
1241 go = &rfgain_opt_5112;
1247 ah->ah_gain.g_step = &go->go_step[ah->ah_gain.g_step_idx];
1249 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
1250 if (ah->ah_gain.g_step_idx == 0)
1252 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1253 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
1254 ah->ah_gain.g_step_idx > 0;
1255 ah->ah_gain.g_step =
1256 &go->go_step[ah->ah_gain.g_step_idx])
1257 ah->ah_gain.g_target -= 2 *
1258 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
1259 ah->ah_gain.g_step->gos_gain);
1265 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
1266 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
1268 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
1269 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
1270 ah->ah_gain.g_step_idx < go->go_steps_count-1;
1271 ah->ah_gain.g_step =
1272 &go->go_step[ah->ah_gain.g_step_idx])
1273 ah->ah_gain.g_target -= 2 *
1274 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
1275 ah->ah_gain.g_step->gos_gain);
1282 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1283 "ret %d, gain step %u, current gain %u, target gain %u\n",
1284 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
1285 ah->ah_gain.g_target);
1291 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
1293 static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
1294 struct ieee80211_channel *channel, unsigned int mode)
1296 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1298 const unsigned int rf_size = ARRAY_SIZE(rfregs_5111);
1300 int obdb = -1, bank = -1;
1303 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1305 rf = ah->ah_rf_banks;
1307 /* Copy values to modify them */
1308 for (i = 0; i < rf_size; i++) {
1309 if (rfregs_5111[i].rf_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
1310 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1314 if (bank != rfregs_5111[i].rf_bank) {
1315 bank = rfregs_5111[i].rf_bank;
1316 ah->ah_offset[bank] = i;
1319 rf[i] = rfregs_5111[i].rf_value[mode];
1323 if (channel->hw_value & CHANNEL_2GHZ) {
1324 if (channel->hw_value & CHANNEL_CCK)
1325 ee_mode = AR5K_EEPROM_MODE_11B;
1327 ee_mode = AR5K_EEPROM_MODE_11G;
1330 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1331 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
1334 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
1335 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
1341 /* For 11a, Turbo and XR */
1342 ee_mode = AR5K_EEPROM_MODE_11A;
1343 obdb = channel->center_freq >= 5725 ? 3 :
1344 (channel->center_freq >= 5500 ? 2 :
1345 (channel->center_freq >= 5260 ? 1 :
1346 (channel->center_freq > 4000 ? 0 : -1)));
1348 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1349 ee->ee_pwd_84, 1, 51, 3, true))
1352 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1353 ee->ee_pwd_90, 1, 45, 3, true))
1357 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1358 !ee->ee_xpd[ee_mode], 1, 95, 0, true))
1361 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1362 ee->ee_x_gain[ee_mode], 4, 96, 0, true))
1365 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1366 ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
1369 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
1370 ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
1374 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1375 ee->ee_i_gain[ee_mode], 6, 29, 0, true))
1378 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1379 ee->ee_xpd[ee_mode], 1, 4, 0, true))
1382 /* Write RF values */
1383 for (i = 0; i < rf_size; i++) {
1385 ath5k_hw_reg_write(ah, rf[i], rfregs_5111[i].rf_register);
1392 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
1394 static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
1395 struct ieee80211_channel *channel, unsigned int mode)
1397 const struct ath5k_ini_rf *rf_ini;
1398 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1400 unsigned int rf_size, i;
1401 int obdb = -1, bank = -1;
1404 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1406 rf = ah->ah_rf_banks;
1408 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_2112A
1409 && !test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
1410 rf_ini = rfregs_2112a;
1411 rf_size = ARRAY_SIZE(rfregs_5112a);
1413 ATH5K_ERR(ah->ah_sc,"invalid channel mode: %i\n",mode);
1416 mode = mode - 2; /*no a/turboa modes for 2112*/
1417 } else if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
1418 rf_ini = rfregs_5112a;
1419 rf_size = ARRAY_SIZE(rfregs_5112a);
1421 rf_ini = rfregs_5112;
1422 rf_size = ARRAY_SIZE(rfregs_5112);
1425 /* Copy values to modify them */
1426 for (i = 0; i < rf_size; i++) {
1427 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1428 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1432 if (bank != rf_ini[i].rf_bank) {
1433 bank = rf_ini[i].rf_bank;
1434 ah->ah_offset[bank] = i;
1437 rf[i] = rf_ini[i].rf_value[mode];
1441 if (channel->hw_value & CHANNEL_2GHZ) {
1442 if (channel->hw_value & CHANNEL_OFDM)
1443 ee_mode = AR5K_EEPROM_MODE_11G;
1445 ee_mode = AR5K_EEPROM_MODE_11B;
1448 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1449 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
1452 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1453 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
1456 /* For 11a, Turbo and XR */
1457 ee_mode = AR5K_EEPROM_MODE_11A;
1458 obdb = channel->center_freq >= 5725 ? 3 :
1459 (channel->center_freq >= 5500 ? 2 :
1460 (channel->center_freq >= 5260 ? 1 :
1461 (channel->center_freq > 4000 ? 0 : -1)));
1466 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1467 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
1470 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1471 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
1475 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1476 ee->ee_x_gain[ee_mode], 2, 270, 0, true);
1477 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1478 ee->ee_x_gain[ee_mode], 2, 257, 0, true);
1480 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
1481 ee->ee_xpd[ee_mode], 1, 302, 0, true))
1485 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
1486 ee->ee_i_gain[ee_mode], 6, 14, 0, true))
1489 /* Write RF values */
1490 for (i = 0; i < rf_size; i++)
1491 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1497 * Initialize RF5413/5414 and future chips
1498 * (until we come up with a better solution)
1500 static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
1501 struct ieee80211_channel *channel, unsigned int mode)
1503 const struct ath5k_ini_rf *rf_ini;
1505 unsigned int rf_size, i;
1508 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
1510 rf = ah->ah_rf_banks;
1512 switch (ah->ah_radio) {
1514 rf_ini = rfregs_5413;
1515 rf_size = ARRAY_SIZE(rfregs_5413);
1518 rf_ini = rfregs_2413;
1519 rf_size = ARRAY_SIZE(rfregs_2413);
1522 ATH5K_ERR(ah->ah_sc,
1523 "invalid channel mode: %i\n", mode);
1530 rf_ini = rfregs_2425;
1531 rf_size = ARRAY_SIZE(rfregs_2425);
1534 ATH5K_ERR(ah->ah_sc,
1535 "invalid channel mode: %i\n", mode);
1550 /* Copy values to modify them */
1551 for (i = 0; i < rf_size; i++) {
1552 if (rf_ini[i].rf_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
1553 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
1557 if (bank != rf_ini[i].rf_bank) {
1558 bank = rf_ini[i].rf_bank;
1559 ah->ah_offset[bank] = i;
1562 rf[i] = rf_ini[i].rf_value[mode];
1566 * After compairing dumps from different cards
1567 * we get the same RF_BUFFER settings (diff returns
1568 * 0 lines). It seems that RF_BUFFER settings are static
1569 * and are written unmodified (no EEPROM stuff
1570 * is used because calibration data would be
1571 * different between different cards and would result
1572 * different RF_BUFFER settings)
1575 /* Write RF values */
1576 for (i = 0; i < rf_size; i++)
1577 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rf_register);
1585 int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1588 int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
1591 switch (ah->ah_radio) {
1593 ah->ah_rf_banks_size = sizeof(rfregs_5111);
1594 func = ath5k_hw_rf5111_rfregs;
1597 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
1598 ah->ah_rf_banks_size = sizeof(rfregs_5112a);
1600 ah->ah_rf_banks_size = sizeof(rfregs_5112);
1601 func = ath5k_hw_rf5112_rfregs;
1604 ah->ah_rf_banks_size = sizeof(rfregs_5413);
1605 func = ath5k_hw_rf5413_rfregs;
1608 ah->ah_rf_banks_size = sizeof(rfregs_2413);
1609 func = ath5k_hw_rf5413_rfregs;
1612 ah->ah_rf_banks_size = sizeof(rfregs_2425);
1613 func = ath5k_hw_rf5413_rfregs;
1619 if (ah->ah_rf_banks == NULL) {
1620 /* XXX do extra checks? */
1621 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
1622 if (ah->ah_rf_banks == NULL) {
1623 ATH5K_ERR(ah->ah_sc, "out of memory\n");
1628 ret = func(ah, channel, mode);
1630 ah->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
1635 int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq)
1637 const struct ath5k_ini_rfgain *ath5k_rfg;
1638 unsigned int i, size;
1640 switch (ah->ah_radio) {
1642 ath5k_rfg = rfgain_5111;
1643 size = ARRAY_SIZE(rfgain_5111);
1646 ath5k_rfg = rfgain_5112;
1647 size = ARRAY_SIZE(rfgain_5112);
1650 ath5k_rfg = rfgain_5413;
1651 size = ARRAY_SIZE(rfgain_5413);
1654 ath5k_rfg = rfgain_2413;
1655 size = ARRAY_SIZE(rfgain_2413);
1656 freq = 0; /* only 2Ghz */
1659 ath5k_rfg = rfgain_2425;
1660 size = ARRAY_SIZE(rfgain_2425);
1661 freq = 0; /* only 2Ghz */
1668 case AR5K_INI_RFGAIN_2GHZ:
1669 case AR5K_INI_RFGAIN_5GHZ:
1675 for (i = 0; i < size; i++) {
1677 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
1678 (u32)ath5k_rfg[i].rfg_register);
1684 enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah)
1688 ATH5K_TRACE(ah->ah_sc);
1690 if (ah->ah_rf_banks == NULL || !ah->ah_gain.g_active ||
1691 ah->ah_version <= AR5K_AR5211)
1692 return AR5K_RFGAIN_INACTIVE;
1694 if (ah->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
1697 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
1699 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
1700 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
1701 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
1703 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
1704 ah->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
1706 if (ah->ah_radio >= AR5K_RF5112) {
1707 ath5k_hw_rfregs_gainf_corr(ah);
1708 ah->ah_gain.g_current =
1709 ah->ah_gain.g_current>=ah->ah_gain.g_f_corr ?
1710 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
1714 if (ath5k_hw_rfregs_gain_readback(ah) &&
1715 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
1716 ath5k_hw_rfregs_gain_adjust(ah))
1717 ah->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
1721 return ah->ah_rf_gain;
1724 int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah)
1726 /* Initialize the gain optimization values */
1727 switch (ah->ah_radio) {
1729 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
1730 ah->ah_gain.g_step =
1731 &rfgain_opt_5111.go_step[ah->ah_gain.g_step_idx];
1732 ah->ah_gain.g_low = 20;
1733 ah->ah_gain.g_high = 35;
1734 ah->ah_gain.g_active = 1;
1737 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
1738 ah->ah_gain.g_step =
1739 &rfgain_opt_5112.go_step[ah->ah_gain.g_step_idx];
1740 ah->ah_gain.g_low = 20;
1741 ah->ah_gain.g_high = 85;
1742 ah->ah_gain.g_active = 1;
1751 /**************************\
1752 PHY/RF channel functions
1753 \**************************/
1756 * Check if a channel is supported
1758 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
1760 /* Check if the channel is in our supported range */
1761 if (flags & CHANNEL_2GHZ) {
1762 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
1763 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
1765 } else if (flags & CHANNEL_5GHZ)
1766 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
1767 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
1774 * Convertion needed for RF5110
1776 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1781 * Convert IEEE channel/MHz to an internal channel value used
1782 * by the AR5210 chipset. This has not been verified with
1783 * newer chipsets like the AR5212A who have a completely
1784 * different RF/PHY part.
1786 athchan = (ath5k_hw_bitswap(
1787 (ieee80211_frequency_to_channel(
1788 channel->center_freq) - 24) / 2, 5)
1789 << 1) | (1 << 6) | 0x1;
1794 * Set channel on RF5110
1796 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1797 struct ieee80211_channel *channel)
1802 * Set the channel and wait
1804 data = ath5k_hw_rf5110_chan2athchan(channel);
1805 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1806 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1813 * Convertion needed for 5111
1815 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1816 struct ath5k_athchan_2ghz *athchan)
1820 /* Cast this value to catch negative channel numbers (>= -19) */
1821 channel = (int)ieee;
1824 * Map 2GHz IEEE channel to 5GHz Atheros channel
1826 if (channel <= 13) {
1827 athchan->a2_athchan = 115 + channel;
1828 athchan->a2_flags = 0x46;
1829 } else if (channel == 14) {
1830 athchan->a2_athchan = 124;
1831 athchan->a2_flags = 0x44;
1832 } else if (channel >= 15 && channel <= 26) {
1833 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1834 athchan->a2_flags = 0x46;
1842 * Set channel on 5111
1844 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1845 struct ieee80211_channel *channel)
1847 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1848 unsigned int ath5k_channel =
1849 ieee80211_frequency_to_channel(channel->center_freq);
1850 u32 data0, data1, clock;
1854 * Set the channel on the RF5111 radio
1858 if (channel->hw_value & CHANNEL_2GHZ) {
1859 /* Map 2GHz channel to 5GHz Atheros channel ID */
1860 ret = ath5k_hw_rf5111_chan2athchan(
1861 ieee80211_frequency_to_channel(channel->center_freq),
1862 &ath5k_channel_2ghz);
1866 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1867 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1871 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1873 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1874 (clock << 1) | (1 << 10) | 1;
1877 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1878 << 2) | (clock << 1) | (1 << 10) | 1;
1881 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1883 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1884 AR5K_RF_BUFFER_CONTROL_3);
1890 * Set channel on 5112 and newer
1892 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1893 struct ieee80211_channel *channel)
1895 u32 data, data0, data1, data2;
1898 data = data0 = data1 = data2 = 0;
1899 c = channel->center_freq;
1902 if (!((c - 2224) % 5)) {
1903 data0 = ((2 * (c - 704)) - 3040) / 10;
1905 } else if (!((c - 2192) % 5)) {
1906 data0 = ((2 * (c - 672)) - 3040) / 10;
1911 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1912 } else if ((c - (c % 5)) != 2 || c > 5435) {
1913 if (!(c % 20) && c >= 5120) {
1914 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1915 data2 = ath5k_hw_bitswap(3, 2);
1916 } else if (!(c % 10)) {
1917 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1918 data2 = ath5k_hw_bitswap(2, 2);
1919 } else if (!(c % 5)) {
1920 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1921 data2 = ath5k_hw_bitswap(1, 2);
1925 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1926 data2 = ath5k_hw_bitswap(0, 2);
1929 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1931 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1932 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1938 * Set the channel on the RF2425
1940 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1941 struct ieee80211_channel *channel)
1943 u32 data, data0, data2;
1946 data = data0 = data2 = 0;
1947 c = channel->center_freq;
1950 data0 = ath5k_hw_bitswap((c - 2272), 8);
1953 } else if ((c - (c % 5)) != 2 || c > 5435) {
1954 if (!(c % 20) && c < 5120)
1955 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1957 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1959 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1962 data2 = ath5k_hw_bitswap(1, 2);
1964 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1965 data2 = ath5k_hw_bitswap(0, 2);
1968 data = (data0 << 4) | data2 << 2 | 0x1001;
1970 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1971 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1977 * Set a channel on the radio chip
1979 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1983 * Check bounds supported by the PHY (we don't care about regultory
1984 * restrictions at this point). Note: hw_value already has the band
1985 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1986 * of the band by that */
1987 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1988 ATH5K_ERR(ah->ah_sc,
1989 "channel frequency (%u MHz) out of supported "
1991 channel->center_freq);
1996 * Set the channel and wait
1998 switch (ah->ah_radio) {
2000 ret = ath5k_hw_rf5110_channel(ah, channel);
2003 ret = ath5k_hw_rf5111_channel(ah, channel);
2006 ret = ath5k_hw_rf2425_channel(ah, channel);
2009 ret = ath5k_hw_rf5112_channel(ah, channel);
2016 /* Set JAPAN setting for channel 14 */
2017 if (channel->center_freq == 2484) {
2018 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
2019 AR5K_PHY_CCKTXCTL_JAPAN);
2021 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
2022 AR5K_PHY_CCKTXCTL_WORLD);
2025 ah->ah_current_channel.center_freq = channel->center_freq;
2026 ah->ah_current_channel.hw_value = channel->hw_value;
2027 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
2037 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
2039 * @ah: struct ath5k_hw pointer we are operating on
2040 * @freq: the channel frequency, just used for error logging
2042 * This function performs a noise floor calibration of the PHY and waits for
2043 * it to complete. Then the noise floor value is compared to some maximum
2044 * noise floor we consider valid.
2046 * Note that this is different from what the madwifi HAL does: it reads the
2047 * noise floor and afterwards initiates the calibration. Since the noise floor
2048 * calibration can take some time to finish, depending on the current channel
2049 * use, that avoids the occasional timeout warnings we are seeing now.
2051 * See the following link for an Atheros patent on noise floor calibration:
2052 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
2053 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
2055 * XXX: Since during noise floor calibration antennas are detached according to
2056 * the patent, we should stop tx queues here.
2059 ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
2066 * Enable noise floor calibration
2068 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
2069 AR5K_PHY_AGCCTL_NF);
2071 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2072 AR5K_PHY_AGCCTL_NF, 0, false);
2074 ATH5K_ERR(ah->ah_sc,
2075 "noise floor calibration timeout (%uMHz)\n", freq);
2079 /* Wait until the noise floor is calibrated and read the value */
2080 for (i = 20; i > 0; i--) {
2082 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
2083 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
2084 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
2085 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
2087 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
2092 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
2093 "noise floor %d\n", noise_floor);
2095 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
2096 ATH5K_ERR(ah->ah_sc,
2097 "noise floor calibration failed (%uMHz)\n", freq);
2101 ah->ah_noise_floor = noise_floor;
2107 * Perform a PHY calibration on RF5110
2108 * -Fix BPSK/QAM Constellation (I/Q correction)
2109 * -Calculate Noise Floor
2111 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
2112 struct ieee80211_channel *channel)
2114 u32 phy_sig, phy_agc, phy_sat, beacon;
2118 * Disable beacons and RX/TX queues, wait
2120 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
2121 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2122 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
2123 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
2128 * Set the channel (with AGC turned off)
2130 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2132 ret = ath5k_hw_channel(ah, channel);
2135 * Activate PHY and wait
2137 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
2140 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2146 * Calibrate the radio chip
2149 /* Remember normal state */
2150 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
2151 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
2152 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
2154 /* Update radio registers */
2155 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
2156 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
2158 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
2159 AR5K_PHY_AGCCOARSE_LO)) |
2160 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
2161 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
2163 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
2164 AR5K_PHY_ADCSAT_THR)) |
2165 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
2166 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
2170 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2172 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
2173 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
2178 * Enable calibration and wait until completion
2180 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
2182 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
2183 AR5K_PHY_AGCCTL_CAL, 0, false);
2185 /* Reset to normal state */
2186 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
2187 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
2188 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
2191 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
2192 channel->center_freq);
2196 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2201 * Re-enable RX/TX and beacons
2203 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
2204 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
2205 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
2211 * Perform a PHY calibration on RF5111/5112 and newer chips
2213 static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
2214 struct ieee80211_channel *channel)
2217 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
2219 ATH5K_TRACE(ah->ah_sc);
2221 if (!ah->ah_calibration ||
2222 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
2225 /* Calibration has finished, get the results and re-run */
2226 for (i = 0; i <= 10; i++) {
2227 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
2228 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
2229 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
2232 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
2233 q_coffd = q_pwr >> 7;
2236 if (i_coffd == 0 || q_coffd == 0)
2239 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
2241 /* Boundary check */
2247 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
2249 /* Boundary check */
2255 /* Commit new I/Q value */
2256 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
2257 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
2259 /* Re-enable calibration -if we don't we'll commit
2260 * the same values again and again */
2261 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
2262 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
2263 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
2267 /* TODO: Separate noise floor calibration from I/Q calibration
2268 * since noise floor calibration interrupts rx path while I/Q
2269 * calibration doesn't. We don't need to run noise floor calibration
2270 * as often as I/Q calibration.*/
2271 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
2273 /* Request RF gain */
2274 if (channel->hw_value & CHANNEL_5GHZ) {
2275 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
2276 AR5K_PHY_PAPD_PROBE_TXPOWER) |
2277 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
2278 ah->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
2285 * Perform a PHY calibration
2287 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
2288 struct ieee80211_channel *channel)
2292 if (ah->ah_radio == AR5K_RF5110)
2293 ret = ath5k_hw_rf5110_calibrate(ah, channel);
2295 ret = ath5k_hw_rf511x_calibrate(ah, channel);
2300 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
2302 ATH5K_TRACE(ah->ah_sc);
2304 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
2309 /********************\
2311 \********************/
2314 * Get the PHY Chip revision
2316 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
2322 ATH5K_TRACE(ah->ah_sc);
2325 * Set the radio chip access register
2329 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
2332 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2340 /* ...wait until PHY is ready and read the selected radio revision */
2341 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
2343 for (i = 0; i < 8; i++)
2344 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
2346 if (ah->ah_version == AR5K_AR5210) {
2347 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
2348 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
2350 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
2351 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
2352 ((srev & 0x0f) << 4), 8);
2355 /* Reset to the 5GHz mode */
2356 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
2361 void /*TODO:Boundary check*/
2362 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
2364 ATH5K_TRACE(ah->ah_sc);
2366 if (ah->ah_version != AR5K_AR5210)
2367 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
2370 unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
2372 ATH5K_TRACE(ah->ah_sc);
2374 if (ah->ah_version != AR5K_AR5210)
2375 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
2377 return false; /*XXX: What do we return for 5210 ?*/
2385 * Initialize the tx power table (not fully implemented)
2387 static void ath5k_txpower_table(struct ath5k_hw *ah,
2388 struct ieee80211_channel *channel, s16 max_power)
2390 unsigned int i, min, max, n;
2391 u16 txpower, *rates;
2393 rates = ah->ah_txpower.txp_rates;
2395 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
2396 if (max_power > txpower)
2397 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
2398 AR5K_TUNE_MAX_TXPOWER : max_power;
2400 for (i = 0; i < AR5K_MAX_RATES; i++)
2403 /* XXX setup target powers by rate */
2405 ah->ah_txpower.txp_min = rates[7];
2406 ah->ah_txpower.txp_max = rates[0];
2407 ah->ah_txpower.txp_ofdm = rates[0];
2409 /* Calculate the power table */
2410 n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
2411 min = AR5K_EEPROM_PCDAC_START;
2412 max = AR5K_EEPROM_PCDAC_STOP;
2413 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
2414 ah->ah_txpower.txp_pcdac[i] =
2416 min + ((i * (max - min)) / n);
2423 * Set transmition power
2425 int /*O.K. - txpower_table is unimplemented so this doesn't work*/
2426 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2427 unsigned int txpower)
2429 bool tpc = ah->ah_txpower.txp_tpc;
2432 ATH5K_TRACE(ah->ah_sc);
2433 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2434 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2439 * RF2413 for some reason can't
2440 * transmit anything if we call
2441 * this funtion, so we skip it
2442 * until we fix txpower.
2444 * XXX: Assume same for RF2425
2447 if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425))
2450 /* Reset TX power values */
2451 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2452 ah->ah_txpower.txp_tpc = tpc;
2454 /* Initialize TX power table */
2455 ath5k_txpower_table(ah, channel, txpower);
2458 * Write TX power values
2460 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2461 ath5k_hw_reg_write(ah,
2462 ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
2463 (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff),
2464 AR5K_PHY_PCDAC_TXPOWER(i));
2467 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2468 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2469 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2471 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2472 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2473 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2475 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2476 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2477 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2479 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2480 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2481 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2483 if (ah->ah_txpower.txp_tpc)
2484 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2485 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2487 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
2488 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
2493 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
2496 struct ieee80211_channel *channel = &ah->ah_current_channel;
2498 ATH5K_TRACE(ah->ah_sc);
2499 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
2500 "changing txpower to %d\n", power);
2502 return ath5k_hw_txpower(ah, channel, power);
projects / linux-2.6 / blob