Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6] / include / linux / mfd / asic3.h
1 /*
2  * include/linux/mfd/asic3.h
3  *
4  * Compaq ASIC3 headers.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * Copyright 2001 Compaq Computer Corporation.
11  * Copyright 2007-2008 OpenedHand Ltd.
12  */
13
14 #ifndef __ASIC3_H__
15 #define __ASIC3_H__
16
17 #include <linux/types.h>
18
19 struct asic3_platform_data {
20         u16 *gpio_config;
21         unsigned int gpio_config_num;
22
23         unsigned int irq_base;
24
25         unsigned int gpio_base;
26 };
27
28 #define ASIC3_NUM_GPIO_BANKS    4
29 #define ASIC3_GPIOS_PER_BANK    16
30 #define ASIC3_NUM_GPIOS         64
31 #define ASIC3_NR_IRQS           ASIC3_NUM_GPIOS + 6
32
33 #define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio))
34
35 #define ASIC3_GPIO_BANK_A       0
36 #define ASIC3_GPIO_BANK_B       1
37 #define ASIC3_GPIO_BANK_C       2
38 #define ASIC3_GPIO_BANK_D       3
39
40 #define ASIC3_GPIO(bank, gpio) \
41         ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
42 #define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
43 /* All offsets below are specified with this address bus shift */
44 #define ASIC3_DEFAULT_ADDR_SHIFT 2
45
46 #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg)
47 #define ASIC3_GPIO_OFFSET(base, reg) \
48         (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg)
49
50 #define ASIC3_GPIO_A_BASE      0x0000
51 #define ASIC3_GPIO_B_BASE      0x0100
52 #define ASIC3_GPIO_C_BASE      0x0200
53 #define ASIC3_GPIO_D_BASE      0x0300
54
55 #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4)
56 #define ASIC3_GPIO_TO_BIT(gpio)  ((gpio) - \
57                                   (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4)))
58 #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio))
59 #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100))
60 #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100))
61
62 #define ASIC3_GPIO_MASK          0x00    /* R/W 0:don't mask */
63 #define ASIC3_GPIO_DIRECTION     0x04    /* R/W 0:input */
64 #define ASIC3_GPIO_OUT           0x08    /* R/W 0:output low */
65 #define ASIC3_GPIO_TRIGGER_TYPE  0x0c    /* R/W 0:level */
66 #define ASIC3_GPIO_EDGE_TRIGGER  0x10    /* R/W 0:falling */
67 #define ASIC3_GPIO_LEVEL_TRIGGER 0x14    /* R/W 0:low level detect */
68 #define ASIC3_GPIO_SLEEP_MASK    0x18    /* R/W 0:don't mask in sleep mode */
69 #define ASIC3_GPIO_SLEEP_OUT     0x1c    /* R/W level 0:low in sleep mode */
70 #define ASIC3_GPIO_BAT_FAULT_OUT 0x20    /* R/W level 0:low in batt_fault */
71 #define ASIC3_GPIO_INT_STATUS    0x24    /* R/W 0:none, 1:detect */
72 #define ASIC3_GPIO_ALT_FUNCTION  0x28    /* R/W 1:LED register control */
73 #define ASIC3_GPIO_SLEEP_CONF    0x2c    /*
74                                           * R/W bit 1: autosleep
75                                           * 0: disable gposlpout in normal mode,
76                                           * enable gposlpout in sleep mode.
77                                           */
78 #define ASIC3_GPIO_STATUS        0x30    /* R   Pin status */
79
80 /*
81  * ASIC3 GPIO config
82  *
83  * Bits 0..6   gpio number
84  * Bits 7..13  Alternate function
85  * Bit  14     Direction
86  * Bit  15     Initial value
87  *
88  */
89 #define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f)
90 #define ASIC3_CONFIG_GPIO_ALT(config)  (((config) & (0x7f << 7)) >> 7)
91 #define ASIC3_CONFIG_GPIO_DIR(config)  ((config & (1 << 14)) >> 14)
92 #define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15)
93 #define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \
94         | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \
95         | (((init) & 0x1) << 15))
96 #define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \
97         ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init))
98 #define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \
99         ASIC3_CONFIG_GPIO((gpio), 0, 1, (init))
100
101 /*
102  * Alternate functions
103  */
104 #define ASIC3_GPIOA11_PWM0              ASIC3_CONFIG_GPIO(11, 1, 1, 0)
105 #define ASIC3_GPIOA12_PWM1              ASIC3_CONFIG_GPIO(12, 1, 1, 0)
106 #define ASIC3_GPIOA15_CONTROL_CX        ASIC3_CONFIG_GPIO(15, 1, 1, 0)
107 #define ASIC3_GPIOC0_LED0               ASIC3_CONFIG_GPIO(32, 1, 1, 0)
108 #define ASIC3_GPIOC1_LED1               ASIC3_CONFIG_GPIO(33, 1, 1, 0)
109 #define ASIC3_GPIOC2_LED2               ASIC3_CONFIG_GPIO(34, 1, 1, 0)
110 #define ASIC3_GPIOC3_SPI_RXD            ASIC3_CONFIG_GPIO(35, 1, 0, 0)
111 #define ASIC3_GPIOC4_CF_nCD             ASIC3_CONFIG_GPIO(36, 1, 0, 0)
112 #define ASIC3_GPIOC4_SPI_TXD            ASIC3_CONFIG_GPIO(36, 1, 1, 0)
113 #define ASIC3_GPIOC5_SPI_CLK            ASIC3_CONFIG_GPIO(37, 1, 1, 0)
114 #define ASIC3_GPIOC5_nCIOW              ASIC3_CONFIG_GPIO(37, 1, 1, 0)
115 #define ASIC3_GPIOC6_nCIOR              ASIC3_CONFIG_GPIO(38, 1, 1, 0)
116 #define ASIC3_GPIOC7_nPCE_1             ASIC3_CONFIG_GPIO(39, 1, 0, 0)
117 #define ASIC3_GPIOC8_nPCE_2             ASIC3_CONFIG_GPIO(40, 1, 0, 0)
118 #define ASIC3_GPIOC9_nPOE               ASIC3_CONFIG_GPIO(41, 1, 0, 0)
119 #define ASIC3_GPIOC10_nPWE              ASIC3_CONFIG_GPIO(42, 1, 0, 0)
120 #define ASIC3_GPIOC11_PSKTSEL           ASIC3_CONFIG_GPIO(43, 1, 0, 0)
121 #define ASIC3_GPIOC12_nPREG             ASIC3_CONFIG_GPIO(44, 1, 0, 0)
122 #define ASIC3_GPIOC13_nPWAIT            ASIC3_CONFIG_GPIO(45, 1, 1, 0)
123 #define ASIC3_GPIOC14_nPIOIS16          ASIC3_CONFIG_GPIO(46, 1, 1, 0)
124 #define ASIC3_GPIOC15_nPIOR             ASIC3_CONFIG_GPIO(47, 1, 0, 0)
125 #define ASIC3_GPIOD11_nCIOIS16          ASIC3_CONFIG_GPIO(59, 1, 0, 0)
126 #define ASIC3_GPIOD12_nCWAIT            ASIC3_CONFIG_GPIO(60, 1, 0, 0)
127 #define ASIC3_GPIOD15_nPIOW             ASIC3_CONFIG_GPIO(63, 1, 0, 0)
128
129
130 #define ASIC3_SPI_Base                0x0400
131 #define ASIC3_SPI_Control               0x0000
132 #define ASIC3_SPI_TxData                0x0004
133 #define ASIC3_SPI_RxData                0x0008
134 #define ASIC3_SPI_Int                   0x000c
135 #define ASIC3_SPI_Status                0x0010
136
137 #define SPI_CONTROL_SPR(clk)      ((clk) & 0x0f)  /* Clock rate */
138
139 #define ASIC3_PWM_0_Base                0x0500
140 #define ASIC3_PWM_1_Base                0x0600
141 #define ASIC3_PWM_TimeBase              0x0000
142 #define ASIC3_PWM_PeriodTime            0x0004
143 #define ASIC3_PWM_DutyTime              0x0008
144
145 #define PWM_TIMEBASE_VALUE(x)    ((x)&0xf)   /* Low 4 bits sets time base */
146 #define PWM_TIMEBASE_ENABLE     (1 << 4)   /* Enable clock */
147
148 #define ASIC3_LED_0_Base                0x0700
149 #define ASIC3_LED_1_Base                0x0800
150 #define ASIC3_LED_2_Base                      0x0900
151 #define ASIC3_LED_TimeBase              0x0000    /* R/W  7 bits */
152 #define ASIC3_LED_PeriodTime            0x0004    /* R/W 12 bits */
153 #define ASIC3_LED_DutyTime              0x0008    /* R/W 12 bits */
154 #define ASIC3_LED_AutoStopCount         0x000c    /* R/W 16 bits */
155
156 /* LED TimeBase bits - match ASIC2 */
157 #define LED_TBS         0x0f /* Low 4 bits sets time base, max = 13 */
158                              /* Note: max = 5 on hx4700 */
159                              /* 0: maximum time base */
160                              /* 1: maximum time base / 2 */
161                              /* n: maximum time base / 2^n */
162
163 #define LED_EN          (1 << 4) /* LED ON/OFF 0:off, 1:on */
164 #define LED_AUTOSTOP    (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
165 #define LED_ALWAYS      (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
166
167 #define ASIC3_CLOCK_BASE           0x0A00
168 #define ASIC3_CLOCK_CDEX           0x00
169 #define ASIC3_CLOCK_SEL            0x04
170
171 #define CLOCK_CDEX_SOURCE       (1 << 0)  /* 2 bits */
172 #define CLOCK_CDEX_SOURCE0      (1 << 0)
173 #define CLOCK_CDEX_SOURCE1      (1 << 1)
174 #define CLOCK_CDEX_SPI          (1 << 2)
175 #define CLOCK_CDEX_OWM          (1 << 3)
176 #define CLOCK_CDEX_PWM0         (1 << 4)
177 #define CLOCK_CDEX_PWM1         (1 << 5)
178 #define CLOCK_CDEX_LED0         (1 << 6)
179 #define CLOCK_CDEX_LED1         (1 << 7)
180 #define CLOCK_CDEX_LED2         (1 << 8)
181
182 /* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
183 #define CLOCK_CDEX_SD_HOST      (1 << 9)   /* R/W: SD host clock source */
184 #define CLOCK_CDEX_SD_BUS       (1 << 10)  /* R/W: SD bus clock source ctrl */
185 #define CLOCK_CDEX_SMBUS        (1 << 11)
186 #define CLOCK_CDEX_CONTROL_CX   (1 << 12)
187
188 #define CLOCK_CDEX_EX0          (1 << 13)  /* R/W: 32.768 kHz crystal */
189 #define CLOCK_CDEX_EX1          (1 << 14)  /* R/W: 24.576 MHz crystal */
190
191 #define CLOCK_SEL_SD_HCLK_SEL   (1 << 0)   /* R/W: SDIO host clock select */
192 #define CLOCK_SEL_SD_BCLK_SEL   (1 << 1)   /* R/W: SDIO bus clock select */
193
194 /* R/W: INT clock source control (32.768 kHz) */
195 #define CLOCK_SEL_CX            (1 << 2)
196
197
198 #define ASIC3_INTR_BASE         0x0B00
199
200 #define ASIC3_INTR_INT_MASK       0x00  /* Interrupt mask control */
201 #define ASIC3_INTR_P_INT_STAT     0x04  /* Peripheral interrupt status */
202 #define ASIC3_INTR_INT_CPS        0x08  /* Interrupt timer clock pre-scale */
203 #define ASIC3_INTR_INT_TBS        0x0c  /* Interrupt timer set */
204
205 #define ASIC3_INTMASK_GINTMASK    (1 << 0)  /* Global INTs mask 1:enable */
206 #define ASIC3_INTMASK_GINTEL      (1 << 1)  /* 1: rising edge, 0: hi level */
207 #define ASIC3_INTMASK_MASK0       (1 << 2)
208 #define ASIC3_INTMASK_MASK1       (1 << 3)
209 #define ASIC3_INTMASK_MASK2       (1 << 4)
210 #define ASIC3_INTMASK_MASK3       (1 << 5)
211 #define ASIC3_INTMASK_MASK4       (1 << 6)
212 #define ASIC3_INTMASK_MASK5       (1 << 7)
213
214 #define ASIC3_INTR_PERIPHERAL_A   (1 << 0)
215 #define ASIC3_INTR_PERIPHERAL_B   (1 << 1)
216 #define ASIC3_INTR_PERIPHERAL_C   (1 << 2)
217 #define ASIC3_INTR_PERIPHERAL_D   (1 << 3)
218 #define ASIC3_INTR_LED0           (1 << 4)
219 #define ASIC3_INTR_LED1           (1 << 5)
220 #define ASIC3_INTR_LED2           (1 << 6)
221 #define ASIC3_INTR_SPI            (1 << 7)
222 #define ASIC3_INTR_SMBUS          (1 << 8)
223 #define ASIC3_INTR_OWM            (1 << 9)
224
225 #define ASIC3_INTR_CPS(x)         ((x)&0x0f)    /* 4 bits, max 14 */
226 #define ASIC3_INTR_CPS_SET        (1 << 4)    /* Time base enable */
227
228
229 /* Basic control of the SD ASIC */
230 #define ASIC3_SDHWCTRL_Base     0x0E00
231 #define ASIC3_SDHWCTRL_SDConf    0x00
232
233 #define ASIC3_SDHWCTRL_SUSPEND    (1 << 0)  /* 1=suspend all SD operations */
234 #define ASIC3_SDHWCTRL_CLKSEL     (1 << 1)  /* 1=SDICK, 0=HCLK */
235 #define ASIC3_SDHWCTRL_PCLR       (1 << 2)  /* All registers of SDIO cleared */
236 #define ASIC3_SDHWCTRL_LEVCD      (1 << 3)  /* SD card detection: 0:low */
237
238 /* SD card write protection: 0=high */
239 #define ASIC3_SDHWCTRL_LEVWP      (1 << 4)
240 #define ASIC3_SDHWCTRL_SDLED      (1 << 5)  /* SD card LED signal 0=disable */
241
242 /* SD card power supply ctrl 1=enable */
243 #define ASIC3_SDHWCTRL_SDPWR      (1 << 6)
244
245 #define ASIC3_EXTCF_Base                0x1100
246
247 #define ASIC3_EXTCF_Select         0x00
248 #define ASIC3_EXTCF_Reset          0x04
249
250 #define ASIC3_EXTCF_SMOD0                (1 << 0)  /* slot number of mode 0 */
251 #define ASIC3_EXTCF_SMOD1                (1 << 1)  /* slot number of mode 1 */
252 #define ASIC3_EXTCF_SMOD2                (1 << 2)  /* slot number of mode 2 */
253 #define ASIC3_EXTCF_OWM_EN               (1 << 4)  /* enable onewire module */
254 #define ASIC3_EXTCF_OWM_SMB              (1 << 5)  /* OWM bus selection */
255 #define ASIC3_EXTCF_OWM_RESET            (1 << 6)  /* ?? used by OWM and CF */
256 #define ASIC3_EXTCF_CF0_SLEEP_MODE       (1 << 7)  /* CF0 sleep state */
257 #define ASIC3_EXTCF_CF1_SLEEP_MODE       (1 << 8)  /* CF1 sleep state */
258 #define ASIC3_EXTCF_CF0_PWAIT_EN         (1 << 10) /* CF0 PWAIT_n control */
259 #define ASIC3_EXTCF_CF1_PWAIT_EN         (1 << 11) /* CF1 PWAIT_n control */
260 #define ASIC3_EXTCF_CF0_BUF_EN           (1 << 12) /* CF0 buffer control */
261 #define ASIC3_EXTCF_CF1_BUF_EN           (1 << 13) /* CF1 buffer control */
262 #define ASIC3_EXTCF_SD_MEM_ENABLE        (1 << 14)
263 #define ASIC3_EXTCF_CF_SLEEP             (1 << 15) /* CF sleep mode control */
264
265 /*********************************************
266  *  The Onewire interface (DS1WM) is handled
267  *  by the ds1wm driver.
268  *
269  *********************************************/
270
271 #define ASIC3_OWM_BASE          0xC00
272
273 /*****************************************************************************
274  *  The SD configuration registers are at a completely different location
275  *  in memory.  They are divided into three sets of registers:
276  *
277  *  SD_CONFIG         Core configuration register
278  *  SD_CTRL           Control registers for SD operations
279  *  SDIO_CTRL         Control registers for SDIO operations
280  *
281  *****************************************************************************/
282 #define ASIC3_SD_CONFIG_Base            0x0400 /* Assumes 32 bit addressing */
283
284 #define ASIC3_SD_CONFIG_Command           0x08   /* R/W: Command */
285
286 /* [0:8] SD Control Register Base Address */
287 #define ASIC3_SD_CONFIG_Addr0             0x20
288
289 /* [9:31] SD Control Register Base Address */
290 #define ASIC3_SD_CONFIG_Addr1             0x24
291
292 /* R/O: interrupt assigned to pin */
293 #define ASIC3_SD_CONFIG_IntPin            0x78
294
295 /*
296  * Set to 0x1f to clock SD controller, 0 otherwise.
297  * At 0x82 - Gated Clock Ctrl
298  */
299 #define ASIC3_SD_CONFIG_ClkStop           0x80
300
301 /* Control clock of SD controller */
302 #define ASIC3_SD_CONFIG_ClockMode         0x84
303 #define ASIC3_SD_CONFIG_SDHC_PinStatus    0x88   /* R/0: SD pins status */
304 #define ASIC3_SD_CONFIG_SDHC_Power1       0x90   /* Power1 - manual pwr ctrl */
305
306 /* auto power up after card inserted */
307 #define ASIC3_SD_CONFIG_SDHC_Power2       0x92
308
309 /* auto power down when card removed */
310 #define ASIC3_SD_CONFIG_SDHC_Power3       0x94
311 #define ASIC3_SD_CONFIG_SDHC_CardDetect   0x98
312 #define ASIC3_SD_CONFIG_SDHC_Slot         0xA0   /* R/O: support slot number */
313 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk1  0x1E0  /* Not used */
314 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk2  0x1E2  /* Not used*/
315
316 /* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
317 #define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable  0x1E8
318 #define ASIC3_SD_CONFIG_SDHC_GPIO_Status  0x1EC  /* GPIO Status Reg. */
319
320 /* Bit 1: double buffer/single buffer */
321 #define ASIC3_SD_CONFIG_SDHC_ExtGateClk3  0x1F0
322
323 /* Memory access enable (set to 1 to access SD Controller) */
324 #define SD_CONFIG_COMMAND_MAE                (1<<1)
325
326 #define SD_CONFIG_CLK_ENABLE_ALL             0x1f
327
328 #define SD_CONFIG_POWER1_PC_33V              0x0200    /* Set for 3.3 volts */
329 #define SD_CONFIG_POWER1_PC_OFF              0x0000    /* Turn off power */
330
331  /* two bits - number of cycles for card detection */
332 #define SD_CONFIG_CARDDETECTMODE_CLK           ((x) & 0x3)
333
334
335 #define ASIC3_SD_CTRL_Base            0x1000
336
337 #define ASIC3_SD_CTRL_Cmd                  0x00
338 #define ASIC3_SD_CTRL_Arg0                 0x08
339 #define ASIC3_SD_CTRL_Arg1                 0x0C
340 #define ASIC3_SD_CTRL_StopInternal         0x10
341 #define ASIC3_SD_CTRL_TransferSectorCount  0x14
342 #define ASIC3_SD_CTRL_Response0            0x18
343 #define ASIC3_SD_CTRL_Response1            0x1C
344 #define ASIC3_SD_CTRL_Response2            0x20
345 #define ASIC3_SD_CTRL_Response3            0x24
346 #define ASIC3_SD_CTRL_Response4            0x28
347 #define ASIC3_SD_CTRL_Response5            0x2C
348 #define ASIC3_SD_CTRL_Response6            0x30
349 #define ASIC3_SD_CTRL_Response7            0x34
350 #define ASIC3_SD_CTRL_CardStatus           0x38
351 #define ASIC3_SD_CTRL_BufferCtrl           0x3C
352 #define ASIC3_SD_CTRL_IntMaskCard          0x40
353 #define ASIC3_SD_CTRL_IntMaskBuffer        0x44
354 #define ASIC3_SD_CTRL_CardClockCtrl        0x48
355 #define ASIC3_SD_CTRL_MemCardXferDataLen   0x4C
356 #define ASIC3_SD_CTRL_MemCardOptionSetup   0x50
357 #define ASIC3_SD_CTRL_ErrorStatus0         0x58
358 #define ASIC3_SD_CTRL_ErrorStatus1         0x5C
359 #define ASIC3_SD_CTRL_DataPort             0x60
360 #define ASIC3_SD_CTRL_TransactionCtrl      0x68
361 #define ASIC3_SD_CTRL_SoftwareReset        0x1C0
362
363 #define SD_CTRL_SOFTWARE_RESET_CLEAR            (1<<0)
364
365 #define SD_CTRL_TRANSACTIONCONTROL_SET          (1<<8)
366
367 #define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD    (1<<15)
368 #define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK   (1<<8)
369 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512    (1<<7)
370 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256    (1<<6)
371 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128    (1<<5)
372 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64     (1<<4)
373 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32     (1<<3)
374 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16     (1<<2)
375 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8      (1<<1)
376 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4      (1<<0)
377 #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2      (0<<0)
378
379 #define MEM_CARD_OPTION_REQUIRED                   0x000e
380 #define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x)   (((x) & 0x0f) << 4)
381 #define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT      (1<<14)
382 #define MEM_CARD_OPTION_DATA_XFR_WIDTH_1           (1<<15)
383 #define MEM_CARD_OPTION_DATA_XFR_WIDTH_4           0
384
385 #define SD_CTRL_COMMAND_INDEX(x)                   ((x) & 0x3f)
386 #define SD_CTRL_COMMAND_TYPE_CMD                   (0 << 6)
387 #define SD_CTRL_COMMAND_TYPE_ACMD                  (1 << 6)
388 #define SD_CTRL_COMMAND_TYPE_AUTHENTICATION        (2 << 6)
389 #define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL       (0 << 8)
390 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1       (4 << 8)
391 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B      (5 << 8)
392 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2       (6 << 8)
393 #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3       (7 << 8)
394 #define SD_CTRL_COMMAND_DATA_PRESENT               (1 << 11)
395 #define SD_CTRL_COMMAND_TRANSFER_READ              (1 << 12)
396 #define SD_CTRL_COMMAND_TRANSFER_WRITE             (0 << 12)
397 #define SD_CTRL_COMMAND_MULTI_BLOCK                (1 << 13)
398 #define SD_CTRL_COMMAND_SECURITY_CMD               (1 << 14)
399
400 #define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12         (1 << 0)
401 #define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12     (1 << 8)
402
403 #define SD_CTRL_CARDSTATUS_RESPONSE_END            (1 << 0)
404 #define SD_CTRL_CARDSTATUS_RW_END                  (1 << 2)
405 #define SD_CTRL_CARDSTATUS_CARD_REMOVED_0          (1 << 3)
406 #define SD_CTRL_CARDSTATUS_CARD_INSERTED_0         (1 << 4)
407 #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0  (1 << 5)
408 #define SD_CTRL_CARDSTATUS_WRITE_PROTECT           (1 << 7)
409 #define SD_CTRL_CARDSTATUS_CARD_REMOVED_3          (1 << 8)
410 #define SD_CTRL_CARDSTATUS_CARD_INSERTED_3         (1 << 9)
411 #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3  (1 << 10)
412
413 #define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR       (1 << 0)
414 #define SD_CTRL_BUFFERSTATUS_CRC_ERROR             (1 << 1)
415 #define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR    (1 << 2)
416 #define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT          (1 << 3)
417 #define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW       (1 << 4)
418 #define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW      (1 << 5)
419 #define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT           (1 << 6)
420 #define SD_CTRL_BUFFERSTATUS_UNK7                  (1 << 7)
421 #define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE    (1 << 8)
422 #define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE   (1 << 9)
423 #define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION      (1 << 13)
424 #define SD_CTRL_BUFFERSTATUS_CMD_BUSY              (1 << 14)
425 #define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS        (1 << 15)
426
427 #define SD_CTRL_INTMASKCARD_RESPONSE_END           (1 << 0)
428 #define SD_CTRL_INTMASKCARD_RW_END                 (1 << 2)
429 #define SD_CTRL_INTMASKCARD_CARD_REMOVED_0         (1 << 3)
430 #define SD_CTRL_INTMASKCARD_CARD_INSERTED_0        (1 << 4)
431 #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
432 #define SD_CTRL_INTMASKCARD_UNK6                   (1 << 6)
433 #define SD_CTRL_INTMASKCARD_WRITE_PROTECT          (1 << 7)
434 #define SD_CTRL_INTMASKCARD_CARD_REMOVED_3         (1 << 8)
435 #define SD_CTRL_INTMASKCARD_CARD_INSERTED_3        (1 << 9)
436 #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
437
438 #define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR      (1 << 0)
439 #define SD_CTRL_INTMASKBUFFER_CRC_ERROR            (1 << 1)
440 #define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR   (1 << 2)
441 #define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT         (1 << 3)
442 #define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW      (1 << 4)
443 #define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW     (1 << 5)
444 #define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT          (1 << 6)
445 #define SD_CTRL_INTMASKBUFFER_UNK7                 (1 << 7)
446 #define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE   (1 << 8)
447 #define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE  (1 << 9)
448 #define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION     (1 << 13)
449 #define SD_CTRL_INTMASKBUFFER_CMD_BUSY             (1 << 14)
450 #define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS       (1 << 15)
451
452 #define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR                   (1 << 0)
453 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
454 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12     (1 << 3)
455 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA          (1 << 4)
456 #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS   (1 << 5)
457 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12     (1 << 8)
458 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12         (1 << 9)
459 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA              (1 << 10)
460 #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD              (1 << 11)
461
462 #define SD_CTRL_DETAIL1_NO_CMD_RESPONSE                      (1 << 0)
463 #define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA                    (1 << 4)
464 #define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS                   (1 << 5)
465 #define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY                     (1 << 6)
466
467 #define ASIC3_SDIO_CTRL_Base          0x1200
468
469 #define ASIC3_SDIO_CTRL_Cmd                  0x00
470 #define ASIC3_SDIO_CTRL_CardPortSel          0x04
471 #define ASIC3_SDIO_CTRL_Arg0                 0x08
472 #define ASIC3_SDIO_CTRL_Arg1                 0x0C
473 #define ASIC3_SDIO_CTRL_TransferBlockCount   0x14
474 #define ASIC3_SDIO_CTRL_Response0            0x18
475 #define ASIC3_SDIO_CTRL_Response1            0x1C
476 #define ASIC3_SDIO_CTRL_Response2            0x20
477 #define ASIC3_SDIO_CTRL_Response3            0x24
478 #define ASIC3_SDIO_CTRL_Response4            0x28
479 #define ASIC3_SDIO_CTRL_Response5            0x2C
480 #define ASIC3_SDIO_CTRL_Response6            0x30
481 #define ASIC3_SDIO_CTRL_Response7            0x34
482 #define ASIC3_SDIO_CTRL_CardStatus           0x38
483 #define ASIC3_SDIO_CTRL_BufferCtrl           0x3C
484 #define ASIC3_SDIO_CTRL_IntMaskCard          0x40
485 #define ASIC3_SDIO_CTRL_IntMaskBuffer        0x44
486 #define ASIC3_SDIO_CTRL_CardXferDataLen      0x4C
487 #define ASIC3_SDIO_CTRL_CardOptionSetup      0x50
488 #define ASIC3_SDIO_CTRL_ErrorStatus0         0x54
489 #define ASIC3_SDIO_CTRL_ErrorStatus1         0x58
490 #define ASIC3_SDIO_CTRL_DataPort             0x60
491 #define ASIC3_SDIO_CTRL_TransactionCtrl      0x68
492 #define ASIC3_SDIO_CTRL_CardIntCtrl          0x6C
493 #define ASIC3_SDIO_CTRL_ClocknWaitCtrl       0x70
494 #define ASIC3_SDIO_CTRL_HostInformation      0x74
495 #define ASIC3_SDIO_CTRL_ErrorCtrl            0x78
496 #define ASIC3_SDIO_CTRL_LEDCtrl              0x7C
497 #define ASIC3_SDIO_CTRL_SoftwareReset        0x1C0
498
499 #define ASIC3_MAP_SIZE_32BIT    0x2000
500 #define ASIC3_MAP_SIZE_16BIT    0x1000
501
502 #endif /* __ASIC3_H__ */