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   1 /*
   2  * File:        mca.c
   3  * Purpose:     Generic MCA handling layer
   4  *
   5  * Copyright (C) 2003 Hewlett-Packard Co
   6  *      David Mosberger-Tang <davidm@hpl.hp.com>
   7  *
   8  * Copyright (C) 2002 Dell Inc.
   9  * Copyright (C) Matt Domsch <Matt_Domsch@dell.com>
  10  *
  11  * Copyright (C) 2002 Intel
  12  * Copyright (C) Jenna Hall <jenna.s.hall@intel.com>
  13  *
  14  * Copyright (C) 2001 Intel
  15  * Copyright (C) Fred Lewis <frederick.v.lewis@intel.com>
  16  *
  17  * Copyright (C) 2000 Intel
  18  * Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
  19  *
  20  * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
  21  * Copyright (C) Vijay Chander <vijay@engr.sgi.com>
  22  *
  23  * Copyright (C) 2006 FUJITSU LIMITED
  24  * Copyright (C) Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
  25  *
  26  * 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com>
  27  *            Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
  28  *            added min save state dump, added INIT handler.
  29  *
  30  * 2001-01-03 Fred Lewis <frederick.v.lewis@intel.com>
  31  *            Added setup of CMCI and CPEI IRQs, logging of corrected platform
  32  *            errors, completed code for logging of corrected & uncorrected
  33  *            machine check errors, and updated for conformance with Nov. 2000
  34  *            revision of the SAL 3.0 spec.
  35  *
  36  * 2002-01-04 Jenna Hall <jenna.s.hall@intel.com>
  37  *            Aligned MCA stack to 16 bytes, added platform vs. CPU error flag,
  38  *            set SAL default return values, changed error record structure to
  39  *            linked list, added init call to sal_get_state_info_size().
  40  *
  41  * 2002-03-25 Matt Domsch <Matt_Domsch@dell.com>
  42  *            GUID cleanups.
  43  *
  44  * 2003-04-15 David Mosberger-Tang <davidm@hpl.hp.com>
  45  *            Added INIT backtrace support.
  46  *
  47  * 2003-12-08 Keith Owens <kaos@sgi.com>
  48  *            smp_call_function() must not be called from interrupt context
  49  *            (can deadlock on tasklist_lock).
  50  *            Use keventd to call smp_call_function().
  51  *
  52  * 2004-02-01 Keith Owens <kaos@sgi.com>
  53  *            Avoid deadlock when using printk() for MCA and INIT records.
  54  *            Delete all record printing code, moved to salinfo_decode in user
  55  *            space.  Mark variables and functions static where possible.
  56  *            Delete dead variables and functions.  Reorder to remove the need
  57  *            for forward declarations and to consolidate related code.
  58  *
  59  * 2005-08-12 Keith Owens <kaos@sgi.com>
  60  *            Convert MCA/INIT handlers to use per event stacks and SAL/OS
  61  *            state.
  62  *
  63  * 2005-10-07 Keith Owens <kaos@sgi.com>
  64  *            Add notify_die() hooks.
  65  *
  66  * 2006-09-15 Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
  67  *            Add printing support for MCA/INIT.
  68  *
  69  * 2007-04-27 Russ Anderson <rja@sgi.com>
  70  *            Support multiple cpus going through OS_MCA in the same event.
  71  */
  72 #include <linux/jiffies.h>
  73 #include <linux/types.h>
  74 #include <linux/init.h>
  75 #include <linux/sched.h>
  76 #include <linux/interrupt.h>
  77 #include <linux/irq.h>
  78 #include <linux/bootmem.h>
  79 #include <linux/acpi.h>
  80 #include <linux/timer.h>
  81 #include <linux/module.h>
  82 #include <linux/kernel.h>
  83 #include <linux/smp.h>
  84 #include <linux/workqueue.h>
  85 #include <linux/cpumask.h>
  86 #include <linux/kdebug.h>
  87 #include <linux/cpu.h>
  88
  89 #include <asm/delay.h>
  90 #include <asm/machvec.h>
  91 #include <asm/meminit.h>
  92 #include <asm/page.h>
  93 #include <asm/ptrace.h>
  94 #include <asm/system.h>
  95 #include <asm/sal.h>
  96 #include <asm/mca.h>
  97 #include <asm/kexec.h>
  98
  99 #include <asm/irq.h>
 100 #include <asm/hw_irq.h>
 101 #include <asm/tlb.h>
 102
 103 #include "mca_drv.h"
 104 #include "entry.h"
 105
 106 #if defined(IA64_MCA_DEBUG_INFO)
 107 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
 108 #else
 109 # define IA64_MCA_DEBUG(fmt...)
 110 #endif
 111
 112 /* Used by mca_asm.S */
 113 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
 114 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
 115 DEFINE_PER_CPU(u64, ia64_mca_pal_pte);      /* PTE to map PAL code */
 116 DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
 117 DEFINE_PER_CPU(u64, ia64_mca_tr_reload);   /* Flag for TR reload */
 118
 119 unsigned long __per_cpu_mca[NR_CPUS];
 120
 121 /* In mca_asm.S */
 122 extern void                     ia64_os_init_dispatch_monarch (void);
 123 extern void                     ia64_os_init_dispatch_slave (void);
 124
 125 static int monarch_cpu = -1;
 126
 127 static ia64_mc_info_t           ia64_mc_info;
 128
 129 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
 130 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
 131 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
 132 #define CPE_HISTORY_LENGTH    5
 133 #define CMC_HISTORY_LENGTH    5
 134
 135 #ifdef CONFIG_ACPI
 136 static struct timer_list cpe_poll_timer;
 137 #endif
 138 static struct timer_list cmc_poll_timer;
 139 /*
 140  * This variable tells whether we are currently in polling mode.
 141  * Start with this in the wrong state so we won't play w/ timers
 142  * before the system is ready.
 143  */
 144 static int cmc_polling_enabled = 1;
 145
 146 /*
 147  * Clearing this variable prevents CPE polling from getting activated
 148  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
 149  * but encounters problems retrieving CPE logs.  This should only be
 150  * necessary for debugging.
 151  */
 152 static int cpe_poll_enabled = 1;
 153
 154 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
 155
 156 static int mca_init __initdata;
 157
 158 /*
 159  * limited & delayed printing support for MCA/INIT handler
 160  */
 161
 162 #define mprintk(fmt...) ia64_mca_printk(fmt)
 163
 164 #define MLOGBUF_SIZE (512+256*NR_CPUS)
 165 #define MLOGBUF_MSGMAX 256
 166 static char mlogbuf[MLOGBUF_SIZE];
 167 static DEFINE_SPINLOCK(mlogbuf_wlock);  /* mca context only */
 168 static DEFINE_SPINLOCK(mlogbuf_rlock);  /* normal context only */
 169 static unsigned long mlogbuf_start;
 170 static unsigned long mlogbuf_end;
 171 static unsigned int mlogbuf_finished = 0;
 172 static unsigned long mlogbuf_timestamp = 0;
 173
 174 static int loglevel_save = -1;
 175 #define BREAK_LOGLEVEL(__console_loglevel)              \
 176         oops_in_progress = 1;                           \
 177         if (loglevel_save < 0)                          \
 178                 loglevel_save = __console_loglevel;     \
 179         __console_loglevel = 15;
 180
 181 #define RESTORE_LOGLEVEL(__console_loglevel)            \
 182         if (loglevel_save >= 0) {                       \
 183                 __console_loglevel = loglevel_save;     \
 184                 loglevel_save = -1;                     \
 185         }                                               \
 186         mlogbuf_finished = 0;                           \
 187         oops_in_progress = 0;
 188
 189 /*
 190  * Push messages into buffer, print them later if not urgent.
 191  */
 192 void ia64_mca_printk(const char *fmt, ...)
 193 {
 194         va_list args;
 195         int printed_len;
 196         char temp_buf[MLOGBUF_MSGMAX];
 197         char *p;
 198
 199         va_start(args, fmt);
 200         printed_len = vscnprintf(temp_buf, sizeof(temp_buf), fmt, args);
 201         va_end(args);
 202
 203         /* Copy the output into mlogbuf */
 204         if (oops_in_progress) {
 205                 /* mlogbuf was abandoned, use printk directly instead. */
 206                 printk(temp_buf);
 207         } else {
 208                 spin_lock(&mlogbuf_wlock);
 209                 for (p = temp_buf; *p; p++) {
 210                         unsigned long next = (mlogbuf_end + 1) % MLOGBUF_SIZE;
 211                         if (next != mlogbuf_start) {
 212                                 mlogbuf[mlogbuf_end] = *p;
 213                                 mlogbuf_end = next;
 214                         } else {
 215                                 /* buffer full */
 216                                 break;
 217                         }
 218                 }
 219                 mlogbuf[mlogbuf_end] = '\0';
 220                 spin_unlock(&mlogbuf_wlock);
 221         }
 222 }
 223 EXPORT_SYMBOL(ia64_mca_printk);
 224
 225 /*
 226  * Print buffered messages.
 227  *  NOTE: call this after returning normal context. (ex. from salinfod)
 228  */
 229 void ia64_mlogbuf_dump(void)
 230 {
 231         char temp_buf[MLOGBUF_MSGMAX];
 232         char *p;
 233         unsigned long index;
 234         unsigned long flags;
 235         unsigned int printed_len;
 236
 237         /* Get output from mlogbuf */
 238         while (mlogbuf_start != mlogbuf_end) {
 239                 temp_buf[0] = '\0';
 240                 p = temp_buf;
 241                 printed_len = 0;
 242
 243                 spin_lock_irqsave(&mlogbuf_rlock, flags);
 244
 245                 index = mlogbuf_start;
 246                 while (index != mlogbuf_end) {
 247                         *p = mlogbuf[index];
 248                         index = (index + 1) % MLOGBUF_SIZE;
 249                         if (!*p)
 250                                 break;
 251                         p++;
 252                         if (++printed_len >= MLOGBUF_MSGMAX - 1)
 253                                 break;
 254                 }
 255                 *p = '\0';
 256                 if (temp_buf[0])
 257                         printk(temp_buf);
 258                 mlogbuf_start = index;
 259
 260                 mlogbuf_timestamp = 0;
 261                 spin_unlock_irqrestore(&mlogbuf_rlock, flags);
 262         }
 263 }
 264 EXPORT_SYMBOL(ia64_mlogbuf_dump);
 265
 266 /*
 267  * Call this if system is going to down or if immediate flushing messages to
 268  * console is required. (ex. recovery was failed, crash dump is going to be
 269  * invoked, long-wait rendezvous etc.)
 270  *  NOTE: this should be called from monarch.
 271  */
 272 static void ia64_mlogbuf_finish(int wait)
 273 {
 274         BREAK_LOGLEVEL(console_loglevel);
 275
 276         spin_lock_init(&mlogbuf_rlock);
 277         ia64_mlogbuf_dump();
 278         printk(KERN_EMERG "mlogbuf_finish: printing switched to urgent mode, "
 279                 "MCA/INIT might be dodgy or fail.\n");
 280
 281         if (!wait)
 282                 return;
 283
 284         /* wait for console */
 285         printk("Delaying for 5 seconds...\n");
 286         udelay(5*1000000);
 287
 288         mlogbuf_finished = 1;
 289 }
 290
 291 /*
 292  * Print buffered messages from INIT context.
 293  */
 294 static void ia64_mlogbuf_dump_from_init(void)
 295 {
 296         if (mlogbuf_finished)
 297                 return;
 298
 299         if (mlogbuf_timestamp &&
 300                         time_before(jiffies, mlogbuf_timestamp + 30 * HZ)) {
 301                 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT "
 302                         " and the system seems to be messed up.\n");
 303                 ia64_mlogbuf_finish(0);
 304                 return;
 305         }
 306
 307         if (!spin_trylock(&mlogbuf_rlock)) {
 308                 printk(KERN_ERR "INIT: mlogbuf_dump is interrupted by INIT. "
 309                         "Generated messages other than stack dump will be "
 310                         "buffered to mlogbuf and will be printed later.\n");
 311                 printk(KERN_ERR "INIT: If messages would not printed after "
 312                         "this INIT, wait 30sec and assert INIT again.\n");
 313                 if (!mlogbuf_timestamp)
 314                         mlogbuf_timestamp = jiffies;
 315                 return;
 316         }
 317         spin_unlock(&mlogbuf_rlock);
 318         ia64_mlogbuf_dump();
 319 }
 320
 321 static void inline
 322 ia64_mca_spin(const char *func)
 323 {
 324         if (monarch_cpu == smp_processor_id())
 325                 ia64_mlogbuf_finish(0);
 326         mprintk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
 327         while (1)
 328                 cpu_relax();
 329 }
 330 /*
 331  * IA64_MCA log support
 332  */
 333 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
 334 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
 335
 336 typedef struct ia64_state_log_s
 337 {
 338         spinlock_t      isl_lock;
 339         int             isl_index;
 340         unsigned long   isl_count;
 341         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 342 } ia64_state_log_t;
 343
 344 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 345
 346 #define IA64_LOG_ALLOCATE(it, size) \
 347         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
 348                 (ia64_err_rec_t *)alloc_bootmem(size); \
 349         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
 350                 (ia64_err_rec_t *)alloc_bootmem(size);}
 351 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 352 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 353 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
 354 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
 355 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
 356 #define IA64_LOG_INDEX_INC(it) \
 357     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
 358     ia64_state_log[it].isl_count++;}
 359 #define IA64_LOG_INDEX_DEC(it) \
 360     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 361 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
 362 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 363 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
 364
 365 /*
 366  * ia64_log_init
 367  *      Reset the OS ia64 log buffer
 368  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 369  * Outputs      :       None
 370  */
 371 static void __init
 372 ia64_log_init(int sal_info_type)
 373 {
 374         u64     max_size = 0;
 375
 376         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
 377         IA64_LOG_LOCK_INIT(sal_info_type);
 378
 379         // SAL will tell us the maximum size of any error record of this type
 380         max_size = ia64_sal_get_state_info_size(sal_info_type);
 381         if (!max_size)
 382                 /* alloc_bootmem() doesn't like zero-sized allocations! */
 383                 return;
 384
 385         // set up OS data structures to hold error info
 386         IA64_LOG_ALLOCATE(sal_info_type, max_size);
 387         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
 388         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 389 }
 390
 391 /*
 392  * ia64_log_get
 393  *
 394  *      Get the current MCA log from SAL and copy it into the OS log buffer.
 395  *
 396  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
 397  *              irq_safe    whether you can use printk at this point
 398  *  Outputs :   size        (total record length)
 399  *              *buffer     (ptr to error record)
 400  *
 401  */
 402 static u64
 403 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
 404 {
 405         sal_log_record_header_t     *log_buffer;
 406         u64                         total_len = 0;
 407         unsigned long               s;
 408
 409         IA64_LOG_LOCK(sal_info_type);
 410
 411         /* Get the process state information */
 412         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
 413
 414         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
 415
 416         if (total_len) {
 417                 IA64_LOG_INDEX_INC(sal_info_type);
 418                 IA64_LOG_UNLOCK(sal_info_type);
 419                 if (irq_safe) {
 420                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. Record length = %ld\n",
 421                                        __func__, sal_info_type, total_len);
 422                 }
 423                 *buffer = (u8 *) log_buffer;
 424                 return total_len;
 425         } else {
 426                 IA64_LOG_UNLOCK(sal_info_type);
 427                 return 0;
 428         }
 429 }
 430
 431 /*
 432  *  ia64_mca_log_sal_error_record
 433  *
 434  *  This function retrieves a specified error record type from SAL
 435  *  and wakes up any processes waiting for error records.
 436  *
 437  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
 438  *              FIXME: remove MCA and irq_safe.
 439  */
 440 static void
 441 ia64_mca_log_sal_error_record(int sal_info_type)
 442 {
 443         u8 *buffer;
 444         sal_log_record_header_t *rh;
 445         u64 size;
 446         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
 447 #ifdef IA64_MCA_DEBUG_INFO
 448         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
 449 #endif
 450
 451         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
 452         if (!size)
 453                 return;
 454
 455         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
 456
 457         if (irq_safe)
 458                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
 459                         smp_processor_id(),
 460                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
 461
 462         /* Clear logs from corrected errors in case there's no user-level logger */
 463         rh = (sal_log_record_header_t *)buffer;
 464         if (rh->severity == sal_log_severity_corrected)
 465                 ia64_sal_clear_state_info(sal_info_type);
 466 }
 467
 468 /*
 469  * search_mca_table
 470  *  See if the MCA surfaced in an instruction range
 471  *  that has been tagged as recoverable.
 472  *
 473  *  Inputs
 474  *      first   First address range to check
 475  *      last    Last address range to check
 476  *      ip      Instruction pointer, address we are looking for
 477  *
 478  * Return value:
 479  *      1 on Success (in the table)/ 0 on Failure (not in the  table)
 480  */
 481 int
 482 search_mca_table (const struct mca_table_entry *first,
 483                 const struct mca_table_entry *last,
 484                 unsigned long ip)
 485 {
 486         const struct mca_table_entry *curr;
 487         u64 curr_start, curr_end;
 488
 489         curr = first;
 490         while (curr <= last) {
 491                 curr_start = (u64) &curr->start_addr + curr->start_addr;
 492                 curr_end = (u64) &curr->end_addr + curr->end_addr;
 493
 494                 if ((ip >= curr_start) && (ip <= curr_end)) {
 495                         return 1;
 496                 }
 497                 curr++;
 498         }
 499         return 0;
 500 }
 501
 502 /* Given an address, look for it in the mca tables. */
 503 int mca_recover_range(unsigned long addr)
 504 {
 505         extern struct mca_table_entry __start___mca_table[];
 506         extern struct mca_table_entry __stop___mca_table[];
 507
 508         return search_mca_table(__start___mca_table, __stop___mca_table-1, addr);
 509 }
 510 EXPORT_SYMBOL_GPL(mca_recover_range);
 511
 512 #ifdef CONFIG_ACPI
 513
 514 int cpe_vector = -1;
 515 int ia64_cpe_irq = -1;
 516
 517 static irqreturn_t
 518 ia64_mca_cpe_int_handler (int cpe_irq, void *arg)
 519 {
 520         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
 521         static int              index;
 522         static DEFINE_SPINLOCK(cpe_history_lock);
 523
 524         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
 525                        __func__, cpe_irq, smp_processor_id());
 526
 527         /* SAL spec states this should run w/ interrupts enabled */
 528         local_irq_enable();
 529
 530         spin_lock(&cpe_history_lock);
 531         if (!cpe_poll_enabled && cpe_vector >= 0) {
 532
 533                 int i, count = 1; /* we know 1 happened now */
 534                 unsigned long now = jiffies;
 535
 536                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
 537                         if (now - cpe_history[i] <= HZ)
 538                                 count++;
 539                 }
 540
 541                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
 542                 if (count >= CPE_HISTORY_LENGTH) {
 543
 544                         cpe_poll_enabled = 1;
 545                         spin_unlock(&cpe_history_lock);
 546                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
 547
 548                         /*
 549                          * Corrected errors will still be corrected, but
 550                          * make sure there's a log somewhere that indicates
 551                          * something is generating more than we can handle.
 552                          */
 553                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
 554
 555                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
 556
 557                         /* lock already released, get out now */
 558                         goto out;
 559                 } else {
 560                         cpe_history[index++] = now;
 561                         if (index == CPE_HISTORY_LENGTH)
 562                                 index = 0;
 563                 }
 564         }
 565         spin_unlock(&cpe_history_lock);
 566 out:
 567         /* Get the CPE error record and log it */
 568         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
 569
 570         return IRQ_HANDLED;
 571 }
 572
 573 #endif /* CONFIG_ACPI */
 574
 575 #ifdef CONFIG_ACPI
 576 /*
 577  * ia64_mca_register_cpev
 578  *
 579  *  Register the corrected platform error vector with SAL.
 580  *
 581  *  Inputs
 582  *      cpev        Corrected Platform Error Vector number
 583  *
 584  *  Outputs
 585  *      None
 586  */
 587 void
 588 ia64_mca_register_cpev (int cpev)
 589 {
 590         /* Register the CPE interrupt vector with SAL */
 591         struct ia64_sal_retval isrv;
 592
 593         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
 594         if (isrv.status) {
 595                 printk(KERN_ERR "Failed to register Corrected Platform "
 596                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
 597                 return;
 598         }
 599
 600         IA64_MCA_DEBUG("%s: corrected platform error "
 601                        "vector %#x registered\n", __func__, cpev);
 602 }
 603 #endif /* CONFIG_ACPI */
 604
 605 /*
 606  * ia64_mca_cmc_vector_setup
 607  *
 608  *  Setup the corrected machine check vector register in the processor.
 609  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
 610  *  This function is invoked on a per-processor basis.
 611  *
 612  * Inputs
 613  *      None
 614  *
 615  * Outputs
 616  *      None
 617  */
 618 void __cpuinit
 619 ia64_mca_cmc_vector_setup (void)
 620 {
 621         cmcv_reg_t      cmcv;
 622
 623         cmcv.cmcv_regval        = 0;
 624         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
 625         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
 626         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 627
 628         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x registered.\n",
 629                        __func__, smp_processor_id(), IA64_CMC_VECTOR);
 630
 631         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
 632                        __func__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
 633 }
 634
 635 /*
 636  * ia64_mca_cmc_vector_disable
 637  *
 638  *  Mask the corrected machine check vector register in the processor.
 639  *  This function is invoked on a per-processor basis.
 640  *
 641  * Inputs
 642  *      dummy(unused)
 643  *
 644  * Outputs
 645  *      None
 646  */
 647 static void
 648 ia64_mca_cmc_vector_disable (void *dummy)
 649 {
 650         cmcv_reg_t      cmcv;
 651
 652         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 653
 654         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
 655         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 656
 657         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x disabled.\n",
 658                        __func__, smp_processor_id(), cmcv.cmcv_vector);
 659 }
 660
 661 /*
 662  * ia64_mca_cmc_vector_enable
 663  *
 664  *  Unmask the corrected machine check vector register in the processor.
 665  *  This function is invoked on a per-processor basis.
 666  *
 667  * Inputs
 668  *      dummy(unused)
 669  *
 670  * Outputs
 671  *      None
 672  */
 673 static void
 674 ia64_mca_cmc_vector_enable (void *dummy)
 675 {
 676         cmcv_reg_t      cmcv;
 677
 678         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
 679
 680         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
 681         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
 682
 683         IA64_MCA_DEBUG("%s: CPU %d corrected machine check vector %#x enabled.\n",
 684                        __func__, smp_processor_id(), cmcv.cmcv_vector);
 685 }
 686
 687 /*
 688  * ia64_mca_cmc_vector_disable_keventd
 689  *
 690  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 691  * disable the cmc interrupt vector.
 692  */
 693 static void
 694 ia64_mca_cmc_vector_disable_keventd(struct work_struct *unused)
 695 {
 696         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
 697 }
 698
 699 /*
 700  * ia64_mca_cmc_vector_enable_keventd
 701  *
 702  * Called via keventd (smp_call_function() is not safe in interrupt context) to
 703  * enable the cmc interrupt vector.
 704  */
 705 static void
 706 ia64_mca_cmc_vector_enable_keventd(struct work_struct *unused)
 707 {
 708         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
 709 }
 710
 711 /*
 712  * ia64_mca_wakeup
 713  *
 714  *      Send an inter-cpu interrupt to wake-up a particular cpu.
 715  *
 716  *  Inputs  :   cpuid
 717  *  Outputs :   None
 718  */
 719 static void
 720 ia64_mca_wakeup(int cpu)
 721 {
 722         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
 723 }
 724
 725 /*
 726  * ia64_mca_wakeup_all
 727  *
 728  *      Wakeup all the slave cpus which have rendez'ed previously.
 729  *
 730  *  Inputs  :   None
 731  *  Outputs :   None
 732  */
 733 static void
 734 ia64_mca_wakeup_all(void)
 735 {
 736         int cpu;
 737
 738         /* Clear the Rendez checkin flag for all cpus */
 739         for_each_online_cpu(cpu) {
 740                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 741                         ia64_mca_wakeup(cpu);
 742         }
 743
 744 }
 745
 746 /*
 747  * ia64_mca_rendez_interrupt_handler
 748  *
 749  *      This is handler used to put slave processors into spinloop
 750  *      while the monarch processor does the mca handling and later
 751  *      wake each slave up once the monarch is done.  The state
 752  *      IA64_MCA_RENDEZ_CHECKIN_DONE indicates the cpu is rendez'ed
 753  *      in SAL.  The state IA64_MCA_RENDEZ_CHECKIN_NOTDONE indicates
 754  *      the cpu has come out of OS rendezvous.
 755  *
 756  *  Inputs  :   None
 757  *  Outputs :   None
 758  */
 759 static irqreturn_t
 760 ia64_mca_rendez_int_handler(int rendez_irq, void *arg)
 761 {
 762         unsigned long flags;
 763         int cpu = smp_processor_id();
 764         struct ia64_mca_notify_die nd =
 765                 { .sos = NULL, .monarch_cpu = &monarch_cpu };
 766
 767         /* Mask all interrupts */
 768         local_irq_save(flags);
 769         if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", get_irq_regs(),
 770                        (long)&nd, 0, 0) == NOTIFY_STOP)
 771                 ia64_mca_spin(__func__);
 772
 773         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
 774         /* Register with the SAL monarch that the slave has
 775          * reached SAL
 776          */
 777         ia64_sal_mc_rendez();
 778
 779         if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", get_irq_regs(),
 780                        (long)&nd, 0, 0) == NOTIFY_STOP)
 781                 ia64_mca_spin(__func__);
 782
 783         /* Wait for the monarch cpu to exit. */
 784         while (monarch_cpu != -1)
 785                cpu_relax();     /* spin until monarch leaves */
 786
 787         if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", get_irq_regs(),
 788                        (long)&nd, 0, 0) == NOTIFY_STOP)
 789                 ia64_mca_spin(__func__);
 790
 791         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
 792         /* Enable all interrupts */
 793         local_irq_restore(flags);
 794         return IRQ_HANDLED;
 795 }
 796
 797 /*
 798  * ia64_mca_wakeup_int_handler
 799  *
 800  *      The interrupt handler for processing the inter-cpu interrupt to the
 801  *      slave cpu which was spinning in the rendez loop.
 802  *      Since this spinning is done by turning off the interrupts and
 803  *      polling on the wakeup-interrupt bit in the IRR, there is
 804  *      nothing useful to be done in the handler.
 805  *
 806  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
 807  *      arg             (Interrupt handler specific argument)
 808  *  Outputs :   None
 809  *
 810  */
 811 static irqreturn_t
 812 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg)
 813 {
 814         return IRQ_HANDLED;
 815 }
 816
 817 /* Function pointer for extra MCA recovery */
 818 int (*ia64_mca_ucmc_extension)
 819         (void*,struct ia64_sal_os_state*)
 820         = NULL;
 821
 822 int
 823 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
 824 {
 825         if (ia64_mca_ucmc_extension)
 826                 return 1;
 827
 828         ia64_mca_ucmc_extension = fn;
 829         return 0;
 830 }
 831
 832 void
 833 ia64_unreg_MCA_extension(void)
 834 {
 835         if (ia64_mca_ucmc_extension)
 836                 ia64_mca_ucmc_extension = NULL;
 837 }
 838
 839 EXPORT_SYMBOL(ia64_reg_MCA_extension);
 840 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
 841
 842
 843 static inline void
 844 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
 845 {
 846         u64 fslot, tslot, nat;
 847         *tr = *fr;
 848         fslot = ((unsigned long)fr >> 3) & 63;
 849         tslot = ((unsigned long)tr >> 3) & 63;
 850         *tnat &= ~(1UL << tslot);
 851         nat = (fnat >> fslot) & 1;
 852         *tnat |= (nat << tslot);
 853 }
 854
 855 /* Change the comm field on the MCA/INT task to include the pid that
 856  * was interrupted, it makes for easier debugging.  If that pid was 0
 857  * (swapper or nested MCA/INIT) then use the start of the previous comm
 858  * field suffixed with its cpu.
 859  */
 860
 861 static void
 862 ia64_mca_modify_comm(const struct task_struct *previous_current)
 863 {
 864         char *p, comm[sizeof(current->comm)];
 865         if (previous_current->pid)
 866                 snprintf(comm, sizeof(comm), "%s %d",
 867                         current->comm, previous_current->pid);
 868         else {
 869                 int l;
 870                 if ((p = strchr(previous_current->comm, ' ')))
 871                         l = p - previous_current->comm;
 872                 else
 873                         l = strlen(previous_current->comm);
 874                 snprintf(comm, sizeof(comm), "%s %*s %d",
 875                         current->comm, l, previous_current->comm,
 876                         task_thread_info(previous_current)->cpu);
 877         }
 878         memcpy(current->comm, comm, sizeof(current->comm));
 879 }
 880
 881 /* On entry to this routine, we are running on the per cpu stack, see
 882  * mca_asm.h.  The original stack has not been touched by this event.  Some of
 883  * the original stack's registers will be in the RBS on this stack.  This stack
 884  * also contains a partial pt_regs and switch_stack, the rest of the data is in
 885  * PAL minstate.
 886  *
 887  * The first thing to do is modify the original stack to look like a blocked
 888  * task so we can run backtrace on the original task.  Also mark the per cpu
 889  * stack as current to ensure that we use the correct task state, it also means
 890  * that we can do backtrace on the MCA/INIT handler code itself.
 891  */
 892
 893 static struct task_struct *
 894 ia64_mca_modify_original_stack(struct pt_regs *regs,
 895                 const struct switch_stack *sw,
 896                 struct ia64_sal_os_state *sos,
 897                 const char *type)
 898 {
 899         char *p;
 900         ia64_va va;
 901         extern char ia64_leave_kernel[];        /* Need asm address, not function descriptor */
 902         const pal_min_state_area_t *ms = sos->pal_min_state;
 903         struct task_struct *previous_current;
 904         struct pt_regs *old_regs;
 905         struct switch_stack *old_sw;
 906         unsigned size = sizeof(struct pt_regs) +
 907                         sizeof(struct switch_stack) + 16;
 908         u64 *old_bspstore, *old_bsp;
 909         u64 *new_bspstore, *new_bsp;
 910         u64 old_unat, old_rnat, new_rnat, nat;
 911         u64 slots, loadrs = regs->loadrs;
 912         u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
 913         u64 ar_bspstore = regs->ar_bspstore;
 914         u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
 915         const u64 *bank;
 916         const char *msg;
 917         int cpu = smp_processor_id();
 918
 919         previous_current = curr_task(cpu);
 920         set_curr_task(cpu, current);
 921         if ((p = strchr(current->comm, ' ')))
 922                 *p = '\0';
 923
 924         /* Best effort attempt to cope with MCA/INIT delivered while in
 925          * physical mode.
 926          */
 927         regs->cr_ipsr = ms->pmsa_ipsr;
 928         if (ia64_psr(regs)->dt == 0) {
 929                 va.l = r12;
 930                 if (va.f.reg == 0) {
 931                         va.f.reg = 7;
 932                         r12 = va.l;
 933                 }
 934                 va.l = r13;
 935                 if (va.f.reg == 0) {
 936                         va.f.reg = 7;
 937                         r13 = va.l;
 938                 }
 939         }
 940         if (ia64_psr(regs)->rt == 0) {
 941                 va.l = ar_bspstore;
 942                 if (va.f.reg == 0) {
 943                         va.f.reg = 7;
 944                         ar_bspstore = va.l;
 945                 }
 946                 va.l = ar_bsp;
 947                 if (va.f.reg == 0) {
 948                         va.f.reg = 7;
 949                         ar_bsp = va.l;
 950                 }
 951         }
 952
 953         /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
 954          * have been copied to the old stack, the old stack may fail the
 955          * validation tests below.  So ia64_old_stack() must restore the dirty
 956          * registers from the new stack.  The old and new bspstore probably
 957          * have different alignments, so loadrs calculated on the old bsp
 958          * cannot be used to restore from the new bsp.  Calculate a suitable
 959          * loadrs for the new stack and save it in the new pt_regs, where
 960          * ia64_old_stack() can get it.
 961          */
 962         old_bspstore = (u64 *)ar_bspstore;
 963         old_bsp = (u64 *)ar_bsp;
 964         slots = ia64_rse_num_regs(old_bspstore, old_bsp);
 965         new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
 966         new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
 967         regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
 968
 969         /* Verify the previous stack state before we change it */
 970         if (user_mode(regs)) {
 971                 msg = "occurred in user space";
 972                 /* previous_current is guaranteed to be valid when the task was
 973                  * in user space, so ...
 974                  */
 975                 ia64_mca_modify_comm(previous_current);
 976                 goto no_mod;
 977         }
 978
 979         if (r13 != sos->prev_IA64_KR_CURRENT) {
 980                 msg = "inconsistent previous current and r13";
 981                 goto no_mod;
 982         }
 983
 984         if (!mca_recover_range(ms->pmsa_iip)) {
 985                 if ((r12 - r13) >= KERNEL_STACK_SIZE) {
 986                         msg = "inconsistent r12 and r13";
 987                         goto no_mod;
 988                 }
 989                 if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
 990                         msg = "inconsistent ar.bspstore and r13";
 991                         goto no_mod;
 992                 }
 993                 va.p = old_bspstore;
 994                 if (va.f.reg < 5) {
 995                         msg = "old_bspstore is in the wrong region";
 996                         goto no_mod;
 997                 }
 998                 if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
 999                         msg = "inconsistent ar.bsp and r13";
1000                         goto no_mod;
1001                 }
1002                 size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
1003                 if (ar_bspstore + size > r12) {
1004                         msg = "no room for blocked state";
1005                         goto no_mod;
1006                 }
1007         }
1008
1009         ia64_mca_modify_comm(previous_current);
1010
1011         /* Make the original task look blocked.  First stack a struct pt_regs,
1012          * describing the state at the time of interrupt.  mca_asm.S built a
1013          * partial pt_regs, copy it and fill in the blanks using minstate.
1014          */
1015         p = (char *)r12 - sizeof(*regs);
1016         old_regs = (struct pt_regs *)p;
1017         memcpy(old_regs, regs, sizeof(*regs));
1018         /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
1019          * pmsa_{xip,xpsr,xfs}
1020          */
1021         if (ia64_psr(regs)->ic) {
1022                 old_regs->cr_iip = ms->pmsa_iip;
1023                 old_regs->cr_ipsr = ms->pmsa_ipsr;
1024                 old_regs->cr_ifs = ms->pmsa_ifs;
1025         } else {
1026                 old_regs->cr_iip = ms->pmsa_xip;
1027                 old_regs->cr_ipsr = ms->pmsa_xpsr;
1028                 old_regs->cr_ifs = ms->pmsa_xfs;
1029         }
1030         old_regs->pr = ms->pmsa_pr;
1031         old_regs->b0 = ms->pmsa_br0;
1032         old_regs->loadrs = loadrs;
1033         old_regs->ar_rsc = ms->pmsa_rsc;
1034         old_unat = old_regs->ar_unat;
1035         copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
1036         copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
1037         copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
1038         copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
1039         copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
1040         copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
1041         copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
1042         copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
1043         copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
1044         copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
1045         copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
1046         if (ia64_psr(old_regs)->bn)
1047                 bank = ms->pmsa_bank1_gr;
1048         else
1049                 bank = ms->pmsa_bank0_gr;
1050         copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
1051         copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
1052         copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
1053         copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
1054         copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
1055         copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
1056         copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
1057         copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
1058         copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
1059         copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
1060         copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
1061         copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
1062         copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
1063         copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
1064         copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
1065         copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
1066
1067         /* Next stack a struct switch_stack.  mca_asm.S built a partial
1068          * switch_stack, copy it and fill in the blanks using pt_regs and
1069          * minstate.
1070          *
1071          * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
1072          * ar.pfs is set to 0.
1073          *
1074          * unwind.c::unw_unwind() does special processing for interrupt frames.
1075          * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
1076          * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
1077          * that this is documented, of course.  Set PRED_NON_SYSCALL in the
1078          * switch_stack on the original stack so it will unwind correctly when
1079          * unwind.c reads pt_regs.
1080          *
1081          * thread.ksp is updated to point to the synthesized switch_stack.
1082          */
1083         p -= sizeof(struct switch_stack);
1084         old_sw = (struct switch_stack *)p;
1085         memcpy(old_sw, sw, sizeof(*sw));
1086         old_sw->caller_unat = old_unat;
1087         old_sw->ar_fpsr = old_regs->ar_fpsr;
1088         copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
1089         copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
1090         copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
1091         copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
1092         old_sw->b0 = (u64)ia64_leave_kernel;
1093         old_sw->b1 = ms->pmsa_br1;
1094         old_sw->ar_pfs = 0;
1095         old_sw->ar_unat = old_unat;
1096         old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
1097         previous_current->thread.ksp = (u64)p - 16;
1098
1099         /* Finally copy the original stack's registers back to its RBS.
1100          * Registers from ar.bspstore through ar.bsp at the time of the event
1101          * are in the current RBS, copy them back to the original stack.  The
1102          * copy must be done register by register because the original bspstore
1103          * and the current one have different alignments, so the saved RNAT
1104          * data occurs at different places.
1105          *
1106          * mca_asm does cover, so the old_bsp already includes all registers at
1107          * the time of MCA/INIT.  It also does flushrs, so all registers before
1108          * this function have been written to backing store on the MCA/INIT
1109          * stack.
1110          */
1111         new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
1112         old_rnat = regs->ar_rnat;
1113         while (slots--) {
1114                 if (ia64_rse_is_rnat_slot(new_bspstore)) {
1115                         new_rnat = ia64_get_rnat(new_bspstore++);
1116                 }
1117                 if (ia64_rse_is_rnat_slot(old_bspstore)) {
1118                         *old_bspstore++ = old_rnat;
1119                         old_rnat = 0;
1120                 }
1121                 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
1122                 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
1123                 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
1124                 *old_bspstore++ = *new_bspstore++;
1125         }
1126         old_sw->ar_bspstore = (unsigned long)old_bspstore;
1127         old_sw->ar_rnat = old_rnat;
1128
1129         sos->prev_task = previous_current;
1130         return previous_current;
1131
1132 no_mod:
1133         printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
1134                         smp_processor_id(), type, msg);
1135         return previous_current;
1136 }
1137
1138 /* The monarch/slave interaction is based on monarch_cpu and requires that all
1139  * slaves have entered rendezvous before the monarch leaves.  If any cpu has
1140  * not entered rendezvous yet then wait a bit.  The assumption is that any
1141  * slave that has not rendezvoused after a reasonable time is never going to do
1142  * so.  In this context, slave includes cpus that respond to the MCA rendezvous
1143  * interrupt, as well as cpus that receive the INIT slave event.
1144  */
1145
1146 static void
1147 ia64_wait_for_slaves(int monarch, const char *type)
1148 {
1149         int c, i , wait;
1150
1151         /*
1152          * wait 5 seconds total for slaves (arbitrary)
1153          */
1154         for (i = 0; i < 5000; i++) {
1155                 wait = 0;
1156                 for_each_online_cpu(c) {
1157                         if (c == monarch)
1158                                 continue;
1159                         if (ia64_mc_info.imi_rendez_checkin[c]
1160                                         == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
1161                                 udelay(1000);           /* short wait */
1162                                 wait = 1;
1163                                 break;
1164                         }
1165                 }
1166                 if (!wait)
1167                         goto all_in;
1168         }
1169
1170         /*
1171          * Maybe slave(s) dead. Print buffered messages immediately.
1172          */
1173         ia64_mlogbuf_finish(0);
1174         mprintk(KERN_INFO "OS %s slave did not rendezvous on cpu", type);
1175         for_each_online_cpu(c) {
1176                 if (c == monarch)
1177                         continue;
1178                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
1179                         mprintk(" %d", c);
1180         }
1181         mprintk("\n");
1182         return;
1183
1184 all_in:
1185         mprintk(KERN_INFO "All OS %s slaves have reached rendezvous\n", type);
1186         return;
1187 }
1188
1189 /*  mca_insert_tr
1190  *
1191  *  Switch rid when TR reload and needed!
1192  *  iord: 1: itr, 2: itr;
1193  *
1194 */
1195 static void mca_insert_tr(u64 iord)
1196 {
1197
1198         int i;
1199         u64 old_rr;
1200         struct ia64_tr_entry *p;
1201         unsigned long psr;
1202         int cpu = smp_processor_id();
1203
1204         psr = ia64_clear_ic();
1205         for (i = IA64_TR_ALLOC_BASE; i < IA64_TR_ALLOC_MAX; i++) {
1206                 p = &__per_cpu_idtrs[cpu][iord-1][i];
1207                 if (p->pte & 0x1) {
1208                         old_rr = ia64_get_rr(p->ifa);
1209                         if (old_rr != p->rr) {
1210                                 ia64_set_rr(p->ifa, p->rr);
1211                                 ia64_srlz_d();
1212                         }
1213                         ia64_ptr(iord, p->ifa, p->itir >> 2);
1214                         ia64_srlz_i();
1215                         if (iord & 0x1) {
1216                                 ia64_itr(0x1, i, p->ifa, p->pte, p->itir >> 2);
1217                                 ia64_srlz_i();
1218                         }
1219                         if (iord & 0x2) {
1220                                 ia64_itr(0x2, i, p->ifa, p->pte, p->itir >> 2);
1221                                 ia64_srlz_i();
1222                         }
1223                         if (old_rr != p->rr) {
1224                                 ia64_set_rr(p->ifa, old_rr);
1225                                 ia64_srlz_d();
1226                         }
1227                 }
1228         }
1229         ia64_set_psr(psr);
1230 }
1231
1232 /*
1233  * ia64_mca_handler
1234  *
1235  *      This is uncorrectable machine check handler called from OS_MCA
1236  *      dispatch code which is in turn called from SAL_CHECK().
1237  *      This is the place where the core of OS MCA handling is done.
1238  *      Right now the logs are extracted and displayed in a well-defined
1239  *      format. This handler code is supposed to be run only on the
1240  *      monarch processor. Once the monarch is done with MCA handling
1241  *      further MCA logging is enabled by clearing logs.
1242  *      Monarch also has the duty of sending wakeup-IPIs to pull the
1243  *      slave processors out of rendezvous spinloop.
1244  *
1245  *      If multiple processors call into OS_MCA, the first will become
1246  *      the monarch.  Subsequent cpus will be recorded in the mca_cpu
1247  *      bitmask.  After the first monarch has processed its MCA, it
1248  *      will wake up the next cpu in the mca_cpu bitmask and then go
1249  *      into the rendezvous loop.  When all processors have serviced
1250  *      their MCA, the last monarch frees up the rest of the processors.
1251  */
1252 void
1253 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
1254                  struct ia64_sal_os_state *sos)
1255 {
1256         int recover, cpu = smp_processor_id();
1257         struct task_struct *previous_current;
1258         struct ia64_mca_notify_die nd =
1259                 { .sos = sos, .monarch_cpu = &monarch_cpu };
1260         static atomic_t mca_count;
1261         static cpumask_t mca_cpu;
1262
1263         if (atomic_add_return(1, &mca_count) == 1) {
1264                 monarch_cpu = cpu;
1265                 sos->monarch = 1;
1266         } else {
1267                 cpu_set(cpu, mca_cpu);
1268                 sos->monarch = 0;
1269         }
1270         mprintk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d "
1271                 "monarch=%ld\n", sos->proc_state_param, cpu, sos->monarch);
1272
1273         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
1274
1275         if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, (long)&nd, 0, 0)
1276                         == NOTIFY_STOP)
1277                 ia64_mca_spin(__func__);
1278
1279         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_CONCURRENT_MCA;
1280         if (sos->monarch) {
1281                 ia64_wait_for_slaves(cpu, "MCA");
1282
1283                 /* Wakeup all the processors which are spinning in the
1284                  * rendezvous loop.  They will leave SAL, then spin in the OS
1285                  * with interrupts disabled until this monarch cpu leaves the
1286                  * MCA handler.  That gets control back to the OS so we can
1287                  * backtrace the other cpus, backtrace when spinning in SAL
1288                  * does not work.
1289                  */
1290                 ia64_mca_wakeup_all();
1291                 if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, (long)&nd, 0, 0)
1292                                 == NOTIFY_STOP)
1293                         ia64_mca_spin(__func__);
1294         } else {
1295                 while (cpu_isset(cpu, mca_cpu))
1296                         cpu_relax();    /* spin until monarch wakes us */
1297         }
1298
1299         /* Get the MCA error record and log it */
1300         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1301
1302         /* MCA error recovery */
1303         recover = (ia64_mca_ucmc_extension
1304                 && ia64_mca_ucmc_extension(
1305                         IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1306                         sos));
1307
1308         if (recover) {
1309                 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1310                 rh->severity = sal_log_severity_corrected;
1311                 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1312                 sos->os_status = IA64_MCA_CORRECTED;
1313         } else {
1314                 /* Dump buffered message to console */
1315                 ia64_mlogbuf_finish(1);
1316         }
1317
1318         if (__get_cpu_var(ia64_mca_tr_reload)) {
1319                 mca_insert_tr(0x1); /*Reload dynamic itrs*/
1320                 mca_insert_tr(0x2); /*Reload dynamic itrs*/
1321         }
1322
1323         if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, (long)&nd, 0, recover)
1324                         == NOTIFY_STOP)
1325                 ia64_mca_spin(__func__);
1326
1327         if (atomic_dec_return(&mca_count) > 0) {
1328                 int i;
1329
1330                 /* wake up the next monarch cpu,
1331                  * and put this cpu in the rendez loop.
1332                  */
1333                 for_each_online_cpu(i) {
1334                         if (cpu_isset(i, mca_cpu)) {
1335                                 monarch_cpu = i;
1336                                 cpu_clear(i, mca_cpu);  /* wake next cpu */
1337                                 while (monarch_cpu != -1)
1338                                         cpu_relax();    /* spin until last cpu leaves */
1339                                 set_curr_task(cpu, previous_current);
1340                                 ia64_mc_info.imi_rendez_checkin[cpu]
1341                                                 = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1342                                 return;
1343                         }
1344                 }
1345         }
1346         set_curr_task(cpu, previous_current);
1347         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1348         monarch_cpu = -1;       /* This frees the slaves and previous monarchs */
1349 }
1350
1351 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd);
1352 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd);
1353
1354 /*
1355  * ia64_mca_cmc_int_handler
1356  *
1357  *  This is corrected machine check interrupt handler.
1358  *      Right now the logs are extracted and displayed in a well-defined
1359  *      format.
1360  *
1361  * Inputs
1362  *      interrupt number
1363  *      client data arg ptr
1364  *
1365  * Outputs
1366  *      None
1367  */
1368 static irqreturn_t
1369 ia64_mca_cmc_int_handler(int cmc_irq, void *arg)
1370 {
1371         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
1372         static int              index;
1373         static DEFINE_SPINLOCK(cmc_history_lock);
1374
1375         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1376                        __func__, cmc_irq, smp_processor_id());
1377
1378         /* SAL spec states this should run w/ interrupts enabled */
1379         local_irq_enable();
1380
1381         spin_lock(&cmc_history_lock);
1382         if (!cmc_polling_enabled) {
1383                 int i, count = 1; /* we know 1 happened now */
1384                 unsigned long now = jiffies;
1385
1386                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1387                         if (now - cmc_history[i] <= HZ)
1388                                 count++;
1389                 }
1390
1391                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1392                 if (count >= CMC_HISTORY_LENGTH) {
1393
1394                         cmc_polling_enabled = 1;
1395                         spin_unlock(&cmc_history_lock);
1396                         /* If we're being hit with CMC interrupts, we won't
1397                          * ever execute the schedule_work() below.  Need to
1398                          * disable CMC interrupts on this processor now.
1399                          */
1400                         ia64_mca_cmc_vector_disable(NULL);
1401                         schedule_work(&cmc_disable_work);
1402
1403                         /*
1404                          * Corrected errors will still be corrected, but
1405                          * make sure there's a log somewhere that indicates
1406                          * something is generating more than we can handle.
1407                          */
1408                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1409
1410                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1411
1412                         /* lock already released, get out now */
1413                         goto out;
1414                 } else {
1415                         cmc_history[index++] = now;
1416                         if (index == CMC_HISTORY_LENGTH)
1417                                 index = 0;
1418                 }
1419         }
1420         spin_unlock(&cmc_history_lock);
1421 out:
1422         /* Get the CMC error record and log it */
1423         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1424
1425         return IRQ_HANDLED;
1426 }
1427
1428 /*
1429  *  ia64_mca_cmc_int_caller
1430  *
1431  *      Triggered by sw interrupt from CMC polling routine.  Calls
1432  *      real interrupt handler and either triggers a sw interrupt
1433  *      on the next cpu or does cleanup at the end.
1434  *
1435  * Inputs
1436  *      interrupt number
1437  *      client data arg ptr
1438  * Outputs
1439  *      handled
1440  */
1441 static irqreturn_t
1442 ia64_mca_cmc_int_caller(int cmc_irq, void *arg)
1443 {
1444         static int start_count = -1;
1445         unsigned int cpuid;
1446
1447         cpuid = smp_processor_id();
1448
1449         /* If first cpu, update count */
1450         if (start_count == -1)
1451                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1452
1453         ia64_mca_cmc_int_handler(cmc_irq, arg);
1454
1455         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1456
1457         if (cpuid < NR_CPUS) {
1458                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1459         } else {
1460                 /* If no log record, switch out of polling mode */
1461                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1462
1463                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1464                         schedule_work(&cmc_enable_work);
1465                         cmc_polling_enabled = 0;
1466
1467                 } else {
1468
1469                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1470                 }
1471
1472                 start_count = -1;
1473         }
1474
1475         return IRQ_HANDLED;
1476 }
1477
1478 /*
1479  *  ia64_mca_cmc_poll
1480  *
1481  *      Poll for Corrected Machine Checks (CMCs)
1482  *
1483  * Inputs   :   dummy(unused)
1484  * Outputs  :   None
1485  *
1486  */
1487 static void
1488 ia64_mca_cmc_poll (unsigned long dummy)
1489 {
1490         /* Trigger a CMC interrupt cascade  */
1491         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1492 }
1493
1494 /*
1495  *  ia64_mca_cpe_int_caller
1496  *
1497  *      Triggered by sw interrupt from CPE polling routine.  Calls
1498  *      real interrupt handler and either triggers a sw interrupt
1499  *      on the next cpu or does cleanup at the end.
1500  *
1501  * Inputs
1502  *      interrupt number
1503  *      client data arg ptr
1504  * Outputs
1505  *      handled
1506  */
1507 #ifdef CONFIG_ACPI
1508
1509 static irqreturn_t
1510 ia64_mca_cpe_int_caller(int cpe_irq, void *arg)
1511 {
1512         static int start_count = -1;
1513         static int poll_time = MIN_CPE_POLL_INTERVAL;
1514         unsigned int cpuid;
1515
1516         cpuid = smp_processor_id();
1517
1518         /* If first cpu, update count */
1519         if (start_count == -1)
1520                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1521
1522         ia64_mca_cpe_int_handler(cpe_irq, arg);
1523
1524         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1525
1526         if (cpuid < NR_CPUS) {
1527                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1528         } else {
1529                 /*
1530                  * If a log was recorded, increase our polling frequency,
1531                  * otherwise, backoff or return to interrupt mode.
1532                  */
1533                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1534                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1535                 } else if (cpe_vector < 0) {
1536                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1537                 } else {
1538                         poll_time = MIN_CPE_POLL_INTERVAL;
1539
1540                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1541                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1542                         cpe_poll_enabled = 0;
1543                 }
1544
1545                 if (cpe_poll_enabled)
1546                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1547                 start_count = -1;
1548         }
1549
1550         return IRQ_HANDLED;
1551 }
1552
1553 /*
1554  *  ia64_mca_cpe_poll
1555  *
1556  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1557  *      on first cpu, from there it will trickle through all the cpus.
1558  *
1559  * Inputs   :   dummy(unused)
1560  * Outputs  :   None
1561  *
1562  */
1563 static void
1564 ia64_mca_cpe_poll (unsigned long dummy)
1565 {
1566         /* Trigger a CPE interrupt cascade  */
1567         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1568 }
1569
1570 #endif /* CONFIG_ACPI */
1571
1572 static int
1573 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1574 {
1575         int c;
1576         struct task_struct *g, *t;
1577         if (val != DIE_INIT_MONARCH_PROCESS)
1578                 return NOTIFY_DONE;
1579 #ifdef CONFIG_KEXEC
1580         if (atomic_read(&kdump_in_progress))
1581                 return NOTIFY_DONE;
1582 #endif
1583
1584         /*
1585          * FIXME: mlogbuf will brim over with INIT stack dumps.
1586          * To enable show_stack from INIT, we use oops_in_progress which should
1587          * be used in real oops. This would cause something wrong after INIT.
1588          */
1589         BREAK_LOGLEVEL(console_loglevel);
1590         ia64_mlogbuf_dump_from_init();
1591
1592         printk(KERN_ERR "Processes interrupted by INIT -");
1593         for_each_online_cpu(c) {
1594                 struct ia64_sal_os_state *s;
1595                 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1596                 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1597                 g = s->prev_task;
1598                 if (g) {
1599                         if (g->pid)
1600                                 printk(" %d", g->pid);
1601                         else
1602                                 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1603                 }
1604         }
1605         printk("\n\n");
1606         if (read_trylock(&tasklist_lock)) {
1607                 do_each_thread (g, t) {
1608                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1609                         show_stack(t, NULL);
1610                 } while_each_thread (g, t);
1611                 read_unlock(&tasklist_lock);
1612         }
1613         /* FIXME: This will not restore zapped printk locks. */
1614         RESTORE_LOGLEVEL(console_loglevel);
1615         return NOTIFY_DONE;
1616 }
1617
1618 /*
1619  * C portion of the OS INIT handler
1620  *
1621  * Called from ia64_os_init_dispatch
1622  *
1623  * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1624  * this event.  This code is used for both monarch and slave INIT events, see
1625  * sos->monarch.
1626  *
1627  * All INIT events switch to the INIT stack and change the previous process to
1628  * blocked status.  If one of the INIT events is the monarch then we are
1629  * probably processing the nmi button/command.  Use the monarch cpu to dump all
1630  * the processes.  The slave INIT events all spin until the monarch cpu
1631  * returns.  We can also get INIT slave events for MCA, in which case the MCA
1632  * process is the monarch.
1633  */
1634
1635 void
1636 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1637                   struct ia64_sal_os_state *sos)
1638 {
1639         static atomic_t slaves;
1640         static atomic_t monarchs;
1641         struct task_struct *previous_current;
1642         int cpu = smp_processor_id();
1643         struct ia64_mca_notify_die nd =
1644                 { .sos = sos, .monarch_cpu = &monarch_cpu };
1645
1646         (void) notify_die(DIE_INIT_ENTER, "INIT", regs, (long)&nd, 0, 0);
1647
1648         mprintk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1649                 sos->proc_state_param, cpu, sos->monarch);
1650         salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1651
1652         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1653         sos->os_status = IA64_INIT_RESUME;
1654
1655         /* FIXME: Workaround for broken proms that drive all INIT events as
1656          * slaves.  The last slave that enters is promoted to be a monarch.
1657          * Remove this code in September 2006, that gives platforms a year to
1658          * fix their proms and get their customers updated.
1659          */
1660         if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1661                 mprintk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1662                         __func__, cpu);
1663                 atomic_dec(&slaves);
1664                 sos->monarch = 1;
1665         }
1666
1667         /* FIXME: Workaround for broken proms that drive all INIT events as
1668          * monarchs.  Second and subsequent monarchs are demoted to slaves.
1669          * Remove this code in September 2006, that gives platforms a year to
1670          * fix their proms and get their customers updated.
1671          */
1672         if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1673                 mprintk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1674                                __func__, cpu);
1675                 atomic_dec(&monarchs);
1676                 sos->monarch = 0;
1677         }
1678
1679         if (!sos->monarch) {
1680                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1681                 while (monarch_cpu == -1)
1682                        cpu_relax();     /* spin until monarch enters */
1683                 if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, (long)&nd, 0, 0)
1684                                 == NOTIFY_STOP)
1685                         ia64_mca_spin(__func__);
1686                 if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, (long)&nd, 0, 0)
1687                                 == NOTIFY_STOP)
1688                         ia64_mca_spin(__func__);
1689                 while (monarch_cpu != -1)
1690                        cpu_relax();     /* spin until monarch leaves */
1691                 if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, (long)&nd, 0, 0)
1692                                 == NOTIFY_STOP)
1693                         ia64_mca_spin(__func__);
1694                 mprintk("Slave on cpu %d returning to normal service.\n", cpu);
1695                 set_curr_task(cpu, previous_current);
1696                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1697                 atomic_dec(&slaves);
1698                 return;
1699         }
1700
1701         monarch_cpu = cpu;
1702         if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, (long)&nd, 0, 0)
1703                         == NOTIFY_STOP)
1704                 ia64_mca_spin(__func__);
1705
1706         /*
1707          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1708          * generated via the BMC's command-line interface, but since the console is on the
1709          * same serial line, the user will need some time to switch out of the BMC before
1710          * the dump begins.
1711          */
1712         mprintk("Delaying for 5 seconds...\n");
1713         udelay(5*1000000);
1714         ia64_wait_for_slaves(cpu, "INIT");
1715         /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1716          * to default_monarch_init_process() above and just print all the
1717          * tasks.
1718          */
1719         if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, (long)&nd, 0, 0)
1720                         == NOTIFY_STOP)
1721                 ia64_mca_spin(__func__);
1722         if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, (long)&nd, 0, 0)
1723                         == NOTIFY_STOP)
1724                 ia64_mca_spin(__func__);
1725         mprintk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1726         atomic_dec(&monarchs);
1727         set_curr_task(cpu, previous_current);
1728         monarch_cpu = -1;
1729         return;
1730 }
1731
1732 static int __init
1733 ia64_mca_disable_cpe_polling(char *str)
1734 {
1735         cpe_poll_enabled = 0;
1736         return 1;
1737 }
1738
1739 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1740
1741 static struct irqaction cmci_irqaction = {
1742         .handler =      ia64_mca_cmc_int_handler,
1743         .flags =        IRQF_DISABLED,
1744         .name =         "cmc_hndlr"
1745 };
1746
1747 static struct irqaction cmcp_irqaction = {
1748         .handler =      ia64_mca_cmc_int_caller,
1749         .flags =        IRQF_DISABLED,
1750         .name =         "cmc_poll"
1751 };
1752
1753 static struct irqaction mca_rdzv_irqaction = {
1754         .handler =      ia64_mca_rendez_int_handler,
1755         .flags =        IRQF_DISABLED,
1756         .name =         "mca_rdzv"
1757 };
1758
1759 static struct irqaction mca_wkup_irqaction = {
1760         .handler =      ia64_mca_wakeup_int_handler,
1761         .flags =        IRQF_DISABLED,
1762         .name =         "mca_wkup"
1763 };
1764
1765 #ifdef CONFIG_ACPI
1766 static struct irqaction mca_cpe_irqaction = {
1767         .handler =      ia64_mca_cpe_int_handler,
1768         .flags =        IRQF_DISABLED,
1769         .name =         "cpe_hndlr"
1770 };
1771
1772 static struct irqaction mca_cpep_irqaction = {
1773         .handler =      ia64_mca_cpe_int_caller,
1774         .flags =        IRQF_DISABLED,
1775         .name =         "cpe_poll"
1776 };
1777 #endif /* CONFIG_ACPI */
1778
1779 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1780  * these stacks can never sleep, they cannot return from the kernel to user
1781  * space, they do not appear in a normal ps listing.  So there is no need to
1782  * format most of the fields.
1783  */
1784
1785 static void __cpuinit
1786 format_mca_init_stack(void *mca_data, unsigned long offset,
1787                 const char *type, int cpu)
1788 {
1789         struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1790         struct thread_info *ti;
1791         memset(p, 0, KERNEL_STACK_SIZE);
1792         ti = task_thread_info(p);
1793         ti->flags = _TIF_MCA_INIT;
1794         ti->preempt_count = 1;
1795         ti->task = p;
1796         ti->cpu = cpu;
1797         p->stack = ti;
1798         p->state = TASK_UNINTERRUPTIBLE;
1799         cpu_set(cpu, p->cpus_allowed);
1800         INIT_LIST_HEAD(&p->tasks);
1801         p->parent = p->real_parent = p->group_leader = p;
1802         INIT_LIST_HEAD(&p->children);
1803         INIT_LIST_HEAD(&p->sibling);
1804         strncpy(p->comm, type, sizeof(p->comm)-1);
1805 }
1806
1807 /* Caller prevents this from being called after init */
1808 static void * __init_refok mca_bootmem(void)
1809 {
1810         return __alloc_bootmem(sizeof(struct ia64_mca_cpu),
1811                             KERNEL_STACK_SIZE, 0);
1812 }
1813
1814 /* Do per-CPU MCA-related initialization.  */
1815 void __cpuinit
1816 ia64_mca_cpu_init(void *cpu_data)
1817 {
1818         void *pal_vaddr;
1819         void *data;
1820         long sz = sizeof(struct ia64_mca_cpu);
1821         int cpu = smp_processor_id();
1822         static int first_time = 1;
1823
1824         /*
1825          * Structure will already be allocated if cpu has been online,
1826          * then offlined.
1827          */
1828         if (__per_cpu_mca[cpu]) {
1829                 data = __va(__per_cpu_mca[cpu]);
1830         } else {
1831                 if (first_time) {
1832                         data = mca_bootmem();
1833                         first_time = 0;
1834                 } else
1835                         data = page_address(alloc_pages_node(numa_node_id(),
1836                                         GFP_KERNEL, get_order(sz)));
1837                 if (!data)
1838                         panic("Could not allocate MCA memory for cpu %d\n",
1839                                         cpu);
1840         }
1841         format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack),
1842                 "MCA", cpu);
1843         format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack),
1844                 "INIT", cpu);
1845         __get_cpu_var(ia64_mca_data) = __per_cpu_mca[cpu] = __pa(data);
1846
1847         /*
1848          * Stash away a copy of the PTE needed to map the per-CPU page.
1849          * We may need it during MCA recovery.
1850          */
1851         __get_cpu_var(ia64_mca_per_cpu_pte) =
1852                 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1853
1854         /*
1855          * Also, stash away a copy of the PAL address and the PTE
1856          * needed to map it.
1857          */
1858         pal_vaddr = efi_get_pal_addr();
1859         if (!pal_vaddr)
1860                 return;
1861         __get_cpu_var(ia64_mca_pal_base) =
1862                 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1863         __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1864                                                               PAGE_KERNEL));
1865 }
1866
1867 static void __cpuinit ia64_mca_cmc_vector_adjust(void *dummy)
1868 {
1869         unsigned long flags;
1870
1871         local_irq_save(flags);
1872         if (!cmc_polling_enabled)
1873                 ia64_mca_cmc_vector_enable(NULL);
1874         local_irq_restore(flags);
1875 }
1876
1877 static int __cpuinit mca_cpu_callback(struct notifier_block *nfb,
1878                                       unsigned long action,
1879                                       void *hcpu)
1880 {
1881         int hotcpu = (unsigned long) hcpu;
1882
1883         switch (action) {
1884         case CPU_ONLINE:
1885         case CPU_ONLINE_FROZEN:
1886                 smp_call_function_single(hotcpu, ia64_mca_cmc_vector_adjust,
1887                                          NULL, 1, 0);
1888                 break;
1889         }
1890         return NOTIFY_OK;
1891 }
1892
1893 static struct notifier_block mca_cpu_notifier __cpuinitdata = {
1894         .notifier_call = mca_cpu_callback
1895 };
1896
1897 /*
1898  * ia64_mca_init
1899  *
1900  *  Do all the system level mca specific initialization.
1901  *
1902  *      1. Register spinloop and wakeup request interrupt vectors
1903  *
1904  *      2. Register OS_MCA handler entry point
1905  *
1906  *      3. Register OS_INIT handler entry point
1907  *
1908  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1909  *
1910  *  Note that this initialization is done very early before some kernel
1911  *  services are available.
1912  *
1913  *  Inputs  :   None
1914  *
1915  *  Outputs :   None
1916  */
1917 void __init
1918 ia64_mca_init(void)
1919 {
1920         ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1921         ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1922         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1923         int i;
1924         s64 rc;
1925         struct ia64_sal_retval isrv;
1926         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1927         static struct notifier_block default_init_monarch_nb = {
1928                 .notifier_call = default_monarch_init_process,
1929                 .priority = 0/* we need to notified last */
1930         };
1931
1932         IA64_MCA_DEBUG("%s: begin\n", __func__);
1933
1934         /* Clear the Rendez checkin flag for all cpus */
1935         for(i = 0 ; i < NR_CPUS; i++)
1936                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1937
1938         /*
1939          * Register the rendezvous spinloop and wakeup mechanism with SAL
1940          */
1941
1942         /* Register the rendezvous interrupt vector with SAL */
1943         while (1) {
1944                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1945                                               SAL_MC_PARAM_MECHANISM_INT,
1946                                               IA64_MCA_RENDEZ_VECTOR,
1947                                               timeout,
1948                                               SAL_MC_PARAM_RZ_ALWAYS);
1949                 rc = isrv.status;
1950                 if (rc == 0)
1951                         break;
1952                 if (rc == -2) {
1953                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1954                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1955                         timeout = isrv.v0;
1956                         (void) notify_die(DIE_MCA_NEW_TIMEOUT, "MCA", NULL, timeout, 0, 0);
1957                         continue;
1958                 }
1959                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1960                        "with SAL (status %ld)\n", rc);
1961                 return;
1962         }
1963
1964         /* Register the wakeup interrupt vector with SAL */
1965         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1966                                       SAL_MC_PARAM_MECHANISM_INT,
1967                                       IA64_MCA_WAKEUP_VECTOR,
1968                                       0, 0);
1969         rc = isrv.status;
1970         if (rc) {
1971                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1972                        "(status %ld)\n", rc);
1973                 return;
1974         }
1975
1976         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __func__);
1977
1978         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1979         /*
1980          * XXX - disable SAL checksum by setting size to 0; should be
1981          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1982          */
1983         ia64_mc_info.imi_mca_handler_size       = 0;
1984
1985         /* Register the os mca handler with SAL */
1986         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1987                                        ia64_mc_info.imi_mca_handler,
1988                                        ia64_tpa(mca_hldlr_ptr->gp),
1989                                        ia64_mc_info.imi_mca_handler_size,
1990                                        0, 0, 0)))
1991         {
1992                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1993                        "(status %ld)\n", rc);
1994                 return;
1995         }
1996
1997         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __func__,
1998                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1999
2000         /*
2001          * XXX - disable SAL checksum by setting size to 0, should be
2002          * size of the actual init handler in mca_asm.S.
2003          */
2004         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(init_hldlr_ptr_monarch->fp);
2005         ia64_mc_info.imi_monarch_init_handler_size      = 0;
2006         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(init_hldlr_ptr_slave->fp);
2007         ia64_mc_info.imi_slave_init_handler_size        = 0;
2008
2009         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __func__,
2010                        ia64_mc_info.imi_monarch_init_handler);
2011
2012         /* Register the os init handler with SAL */
2013         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
2014                                        ia64_mc_info.imi_monarch_init_handler,
2015                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2016                                        ia64_mc_info.imi_monarch_init_handler_size,
2017                                        ia64_mc_info.imi_slave_init_handler,
2018                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
2019                                        ia64_mc_info.imi_slave_init_handler_size)))
2020         {
2021                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
2022                        "(status %ld)\n", rc);
2023                 return;
2024         }
2025         if (register_die_notifier(&default_init_monarch_nb)) {
2026                 printk(KERN_ERR "Failed to register default monarch INIT process\n");
2027                 return;
2028         }
2029
2030         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __func__);
2031
2032         /*
2033          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
2034          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
2035          */
2036         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
2037         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
2038         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
2039
2040         /* Setup the MCA rendezvous interrupt vector */
2041         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
2042
2043         /* Setup the MCA wakeup interrupt vector */
2044         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
2045
2046 #ifdef CONFIG_ACPI
2047         /* Setup the CPEI/P handler */
2048         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
2049 #endif
2050
2051         /* Initialize the areas set aside by the OS to buffer the
2052          * platform/processor error states for MCA/INIT/CMC
2053          * handling.
2054          */
2055         ia64_log_init(SAL_INFO_TYPE_MCA);
2056         ia64_log_init(SAL_INFO_TYPE_INIT);
2057         ia64_log_init(SAL_INFO_TYPE_CMC);
2058         ia64_log_init(SAL_INFO_TYPE_CPE);
2059
2060         mca_init = 1;
2061         printk(KERN_INFO "MCA related initialization done\n");
2062 }
2063
2064 /*
2065  * ia64_mca_late_init
2066  *
2067  *      Opportunity to setup things that require initialization later
2068  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
2069  *      platform doesn't support an interrupt driven mechanism.
2070  *
2071  *  Inputs  :   None
2072  *  Outputs :   Status
2073  */
2074 static int __init
2075 ia64_mca_late_init(void)
2076 {
2077         if (!mca_init)
2078                 return 0;
2079
2080         register_hotcpu_notifier(&mca_cpu_notifier);
2081
2082         /* Setup the CMCI/P vector and handler */
2083         init_timer(&cmc_poll_timer);
2084         cmc_poll_timer.function = ia64_mca_cmc_poll;
2085
2086         /* Unmask/enable the vector */
2087         cmc_polling_enabled = 0;
2088         schedule_work(&cmc_enable_work);
2089
2090         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __func__);
2091
2092 #ifdef CONFIG_ACPI
2093         /* Setup the CPEI/P vector and handler */
2094         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
2095         init_timer(&cpe_poll_timer);
2096         cpe_poll_timer.function = ia64_mca_cpe_poll;
2097
2098         {
2099                 irq_desc_t *desc;
2100                 unsigned int irq;
2101
2102                 if (cpe_vector >= 0) {
2103                         /* If platform supports CPEI, enable the irq. */
2104                         irq = local_vector_to_irq(cpe_vector);
2105                         if (irq > 0) {
2106                                 cpe_poll_enabled = 0;
2107                                 desc = irq_desc + irq;
2108                                 desc->status |= IRQ_PER_CPU;
2109                                 setup_irq(irq, &mca_cpe_irqaction);
2110                                 ia64_cpe_irq = irq;
2111                                 ia64_mca_register_cpev(cpe_vector);
2112                                 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n",
2113                                         __func__);
2114                                 return 0;
2115                         }
2116                         printk(KERN_ERR "%s: Failed to find irq for CPE "
2117                                         "interrupt handler, vector %d\n",
2118                                         __func__, cpe_vector);
2119                 }
2120                 /* If platform doesn't support CPEI, get the timer going. */
2121                 if (cpe_poll_enabled) {
2122                         ia64_mca_cpe_poll(0UL);
2123                         IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __func__);
2124                 }
2125         }
2126 #endif
2127
2128         return 0;
2129 }
2130
2131 device_initcall(ia64_mca_late_init);