git.oblomov.eu Git - linux-2.6/blob - drivers/net/ipg.c

   1 /*
   2  * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
   3  *
   4  * Copyright (C) 2003, 2007  IC Plus Corp
   5  *
   6  * Original Author:
   7  *
   8  *   Craig Rich
   9  *   Sundance Technology, Inc.
  10  *   www.sundanceti.com
  11  *   craig_rich@sundanceti.com
  12  *
  13  * Current Maintainer:
  14  *
  15  *   Sorbica Shieh.
  16  *   http://www.icplus.com.tw
  17  *   sorbica@icplus.com.tw
  18  *
  19  *   Jesse Huang
  20  *   http://www.icplus.com.tw
  21  *   jesse@icplus.com.tw
  22  */
  23 #include <linux/crc32.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mii.h>
  26 #include <linux/mutex.h>
  27
  28 #include <asm/div64.h>
  29
  30 #define IPG_RX_RING_BYTES       (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
  31 #define IPG_TX_RING_BYTES       (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
  32 #define IPG_RESET_MASK \
  33         (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
  34          IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
  35          IPG_AC_AUTO_INIT)
  36
  37 #define ipg_w32(val32, reg)     iowrite32((val32), ioaddr + (reg))
  38 #define ipg_w16(val16, reg)     iowrite16((val16), ioaddr + (reg))
  39 #define ipg_w8(val8, reg)       iowrite8((val8), ioaddr + (reg))
  40
  41 #define ipg_r32(reg)            ioread32(ioaddr + (reg))
  42 #define ipg_r16(reg)            ioread16(ioaddr + (reg))
  43 #define ipg_r8(reg)             ioread8(ioaddr + (reg))
  44
  45 enum {
  46         netdev_io_size = 128
  47 };
  48
  49 #include "ipg.h"
  50 #define DRV_NAME        "ipg"
  51
  52 MODULE_AUTHOR("IC Plus Corp. 2003");
  53 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
  54 MODULE_LICENSE("GPL");
  55
  56 /*
  57  * Defaults
  58  */
  59 #define IPG_MAX_RXFRAME_SIZE    0x0600
  60 #define IPG_RXFRAG_SIZE         0x0600
  61 #define IPG_RXSUPPORT_SIZE      0x0600
  62 #define IPG_IS_JUMBO            false
  63
  64 /*
  65  * Variable record -- index by leading revision/length
  66  * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
  67  */
  68 static unsigned short DefaultPhyParam[] = {
  69         /* 11/12/03 IP1000A v1-3 rev=0x40 */
  70         /*--------------------------------------------------------------------------
  71         (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
  72                                  27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
  73                                  31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7,  9, 0x0700,
  74           --------------------------------------------------------------------------*/
  75         /* 12/17/03 IP1000A v1-4 rev=0x40 */
  76         (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
  77             0x0000,
  78         30, 0x005e, 9, 0x0700,
  79         /* 01/09/04 IP1000A v1-5 rev=0x41 */
  80         (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
  81             0x0000,
  82         30, 0x005e, 9, 0x0700,
  83         0x0000
  84 };
  85
  86 static const char *ipg_brand_name[] = {
  87         "IC PLUS IP1000 1000/100/10 based NIC",
  88         "Sundance Technology ST2021 based NIC",
  89         "Tamarack Microelectronics TC9020/9021 based NIC",
  90         "Tamarack Microelectronics TC9020/9021 based NIC",
  91         "D-Link NIC",
  92         "D-Link NIC IP1000A"
  93 };
  94
  95 static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
  96         { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
  97         { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
  98         { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
  99         { PCI_VDEVICE(DLINK,    0x9021), 3 },
 100         { PCI_VDEVICE(DLINK,    0x4000), 4 },
 101         { PCI_VDEVICE(DLINK,    0x4020), 5 },
 102         { 0, }
 103 };
 104
 105 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
 106
 107 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
 108 {
 109         struct ipg_nic_private *sp = netdev_priv(dev);
 110         return sp->ioaddr;
 111 }
 112
 113 #ifdef IPG_DEBUG
 114 static void ipg_dump_rfdlist(struct net_device *dev)
 115 {
 116         struct ipg_nic_private *sp = netdev_priv(dev);
 117         void __iomem *ioaddr = sp->ioaddr;
 118         unsigned int i;
 119         u32 offset;
 120
 121         IPG_DEBUG_MSG("_dump_rfdlist\n");
 122
 123         printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
 124         printk(KERN_INFO "rx_dirty   = %2.2x\n", sp->rx_dirty);
 125         printk(KERN_INFO "RFDList start address = %16.16lx\n",
 126                (unsigned long) sp->rxd_map);
 127         printk(KERN_INFO "RFDListPtr register   = %8.8x%8.8x\n",
 128                ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
 129
 130         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 131                 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
 132                 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
 133                        offset, (unsigned long) sp->rxd[i].next_desc);
 134                 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
 135                 printk(KERN_INFO "%2.2x %4.4x RFS        = %16.16lx\n", i,
 136                        offset, (unsigned long) sp->rxd[i].rfs);
 137                 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
 138                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
 139                        offset, (unsigned long) sp->rxd[i].frag_info);
 140         }
 141 }
 142
 143 static void ipg_dump_tfdlist(struct net_device *dev)
 144 {
 145         struct ipg_nic_private *sp = netdev_priv(dev);
 146         void __iomem *ioaddr = sp->ioaddr;
 147         unsigned int i;
 148         u32 offset;
 149
 150         IPG_DEBUG_MSG("_dump_tfdlist\n");
 151
 152         printk(KERN_INFO "tx_current         = %2.2x\n", sp->tx_current);
 153         printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
 154         printk(KERN_INFO "TFDList start address = %16.16lx\n",
 155                (unsigned long) sp->txd_map);
 156         printk(KERN_INFO "TFDListPtr register   = %8.8x%8.8x\n",
 157                ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
 158
 159         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 160                 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
 161                 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
 162                        offset, (unsigned long) sp->txd[i].next_desc);
 163
 164                 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
 165                 printk(KERN_INFO "%2.2x %4.4x TFC        = %16.16lx\n", i,
 166                        offset, (unsigned long) sp->txd[i].tfc);
 167                 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
 168                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
 169                        offset, (unsigned long) sp->txd[i].frag_info);
 170         }
 171 }
 172 #endif
 173
 174 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
 175 {
 176         ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
 177         ndelay(IPG_PC_PHYCTRLWAIT_NS);
 178 }
 179
 180 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
 181 {
 182         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
 183         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
 184 }
 185
 186 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
 187 {
 188         phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
 189
 190         ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
 191 }
 192
 193 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
 194 {
 195         ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
 196                 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
 197 }
 198
 199 static u16 read_phy_bit(void __iomem *ioaddr, u8 phyctrlpolarity)
 200 {
 201         u16 bit_data;
 202
 203         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
 204
 205         bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
 206
 207         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
 208
 209         return bit_data;
 210 }
 211
 212 /*
 213  * Read a register from the Physical Layer device located
 214  * on the IPG NIC, using the IPG PHYCTRL register.
 215  */
 216 static int mdio_read(struct net_device *dev, int phy_id, int phy_reg)
 217 {
 218         void __iomem *ioaddr = ipg_ioaddr(dev);
 219         /*
 220          * The GMII mangement frame structure for a read is as follows:
 221          *
 222          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 223          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 224          *
 225          * <32 1s> = 32 consecutive logic 1 values
 226          * A = bit of Physical Layer device address (MSB first)
 227          * R = bit of register address (MSB first)
 228          * z = High impedance state
 229          * D = bit of read data (MSB first)
 230          *
 231          * Transmission order is 'Preamble' field first, bits transmitted
 232          * left to right (first to last).
 233          */
 234         struct {
 235                 u32 field;
 236                 unsigned int len;
 237         } p[] = {
 238                 { GMII_PREAMBLE,        32 },   /* Preamble */
 239                 { GMII_ST,              2  },   /* ST */
 240                 { GMII_READ,            2  },   /* OP */
 241                 { phy_id,               5  },   /* PHYAD */
 242                 { phy_reg,              5  },   /* REGAD */
 243                 { 0x0000,               2  },   /* TA */
 244                 { 0x0000,               16 },   /* DATA */
 245                 { 0x0000,               1  }    /* IDLE */
 246         };
 247         unsigned int i, j;
 248         u8 polarity, data;
 249
 250         polarity  = ipg_r8(PHY_CTRL);
 251         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 252
 253         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 254         for (j = 0; j < 5; j++) {
 255                 for (i = 0; i < p[j].len; i++) {
 256                         /* For each variable length field, the MSB must be
 257                          * transmitted first. Rotate through the field bits,
 258                          * starting with the MSB, and move each bit into the
 259                          * the 1st (2^1) bit position (this is the bit position
 260                          * corresponding to the MgmtData bit of the PhyCtrl
 261                          * register for the IPG).
 262                          *
 263                          * Example: ST = 01;
 264                          *
 265                          *          First write a '0' to bit 1 of the PhyCtrl
 266                          *          register, then write a '1' to bit 1 of the
 267                          *          PhyCtrl register.
 268                          *
 269                          * To do this, right shift the MSB of ST by the value:
 270                          * [field length - 1 - #ST bits already written]
 271                          * then left shift this result by 1.
 272                          */
 273                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 274                         data &= IPG_PC_MGMTDATA;
 275                         data |= polarity | IPG_PC_MGMTDIR;
 276
 277                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 278                 }
 279         }
 280
 281         send_three_state(ioaddr, polarity);
 282
 283         read_phy_bit(ioaddr, polarity);
 284
 285         /*
 286          * For a read cycle, the bits for the next two fields (TA and
 287          * DATA) are driven by the PHY (the IPG reads these bits).
 288          */
 289         for (i = 0; i < p[6].len; i++) {
 290                 p[6].field |=
 291                     (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
 292         }
 293
 294         send_three_state(ioaddr, polarity);
 295         send_three_state(ioaddr, polarity);
 296         send_three_state(ioaddr, polarity);
 297         send_end(ioaddr, polarity);
 298
 299         /* Return the value of the DATA field. */
 300         return p[6].field;
 301 }
 302
 303 /*
 304  * Write to a register from the Physical Layer device located
 305  * on the IPG NIC, using the IPG PHYCTRL register.
 306  */
 307 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
 308 {
 309         void __iomem *ioaddr = ipg_ioaddr(dev);
 310         /*
 311          * The GMII mangement frame structure for a read is as follows:
 312          *
 313          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 314          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 315          *
 316          * <32 1s> = 32 consecutive logic 1 values
 317          * A = bit of Physical Layer device address (MSB first)
 318          * R = bit of register address (MSB first)
 319          * z = High impedance state
 320          * D = bit of write data (MSB first)
 321          *
 322          * Transmission order is 'Preamble' field first, bits transmitted
 323          * left to right (first to last).
 324          */
 325         struct {
 326                 u32 field;
 327                 unsigned int len;
 328         } p[] = {
 329                 { GMII_PREAMBLE,        32 },   /* Preamble */
 330                 { GMII_ST,              2  },   /* ST */
 331                 { GMII_WRITE,           2  },   /* OP */
 332                 { phy_id,               5  },   /* PHYAD */
 333                 { phy_reg,              5  },   /* REGAD */
 334                 { 0x0002,               2  },   /* TA */
 335                 { val & 0xffff,         16 },   /* DATA */
 336                 { 0x0000,               1  }    /* IDLE */
 337         };
 338         unsigned int i, j;
 339         u8 polarity, data;
 340
 341         polarity  = ipg_r8(PHY_CTRL);
 342         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 343
 344         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 345         for (j = 0; j < 7; j++) {
 346                 for (i = 0; i < p[j].len; i++) {
 347                         /* For each variable length field, the MSB must be
 348                          * transmitted first. Rotate through the field bits,
 349                          * starting with the MSB, and move each bit into the
 350                          * the 1st (2^1) bit position (this is the bit position
 351                          * corresponding to the MgmtData bit of the PhyCtrl
 352                          * register for the IPG).
 353                          *
 354                          * Example: ST = 01;
 355                          *
 356                          *          First write a '0' to bit 1 of the PhyCtrl
 357                          *          register, then write a '1' to bit 1 of the
 358                          *          PhyCtrl register.
 359                          *
 360                          * To do this, right shift the MSB of ST by the value:
 361                          * [field length - 1 - #ST bits already written]
 362                          * then left shift this result by 1.
 363                          */
 364                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 365                         data &= IPG_PC_MGMTDATA;
 366                         data |= polarity | IPG_PC_MGMTDIR;
 367
 368                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 369                 }
 370         }
 371
 372         /* The last cycle is a tri-state, so read from the PHY. */
 373         for (j = 7; j < 8; j++) {
 374                 for (i = 0; i < p[j].len; i++) {
 375                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
 376
 377                         p[j].field |= ((ipg_r8(PHY_CTRL) &
 378                                 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
 379
 380                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
 381                 }
 382         }
 383 }
 384
 385 static void ipg_set_led_mode(struct net_device *dev)
 386 {
 387         struct ipg_nic_private *sp = netdev_priv(dev);
 388         void __iomem *ioaddr = sp->ioaddr;
 389         u32 mode;
 390
 391         mode = ipg_r32(ASIC_CTRL);
 392         mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
 393
 394         if ((sp->led_mode & 0x03) > 1)
 395                 mode |= IPG_AC_LED_MODE_BIT_1;  /* Write Asic Control Bit 29 */
 396
 397         if ((sp->led_mode & 0x01) == 1)
 398                 mode |= IPG_AC_LED_MODE;        /* Write Asic Control Bit 14 */
 399
 400         if ((sp->led_mode & 0x08) == 8)
 401                 mode |= IPG_AC_LED_SPEED;       /* Write Asic Control Bit 27 */
 402
 403         ipg_w32(mode, ASIC_CTRL);
 404 }
 405
 406 static void ipg_set_phy_set(struct net_device *dev)
 407 {
 408         struct ipg_nic_private *sp = netdev_priv(dev);
 409         void __iomem *ioaddr = sp->ioaddr;
 410         int physet;
 411
 412         physet = ipg_r8(PHY_SET);
 413         physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
 414         physet |= ((sp->led_mode & 0x70) >> 4);
 415         ipg_w8(physet, PHY_SET);
 416 }
 417
 418 static int ipg_reset(struct net_device *dev, u32 resetflags)
 419 {
 420         /* Assert functional resets via the IPG AsicCtrl
 421          * register as specified by the 'resetflags' input
 422          * parameter.
 423          */
 424         void __iomem *ioaddr = ipg_ioaddr(dev);
 425         unsigned int timeout_count = 0;
 426
 427         IPG_DEBUG_MSG("_reset\n");
 428
 429         ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
 430
 431         /* Delay added to account for problem with 10Mbps reset. */
 432         mdelay(IPG_AC_RESETWAIT);
 433
 434         while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
 435                 mdelay(IPG_AC_RESETWAIT);
 436                 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
 437                         return -ETIME;
 438         }
 439         /* Set LED Mode in Asic Control */
 440         ipg_set_led_mode(dev);
 441
 442         /* Set PHYSet Register Value */
 443         ipg_set_phy_set(dev);
 444         return 0;
 445 }
 446
 447 /* Find the GMII PHY address. */
 448 static int ipg_find_phyaddr(struct net_device *dev)
 449 {
 450         unsigned int phyaddr, i;
 451
 452         for (i = 0; i < 32; i++) {
 453                 u32 status;
 454
 455                 /* Search for the correct PHY address among 32 possible. */
 456                 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
 457
 458                 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
 459                    GMII_PHY_ID1
 460                  */
 461
 462                 status = mdio_read(dev, phyaddr, MII_BMSR);
 463
 464                 if ((status != 0xFFFF) && (status != 0))
 465                         return phyaddr;
 466         }
 467
 468         return 0x1f;
 469 }
 470
 471 /*
 472  * Configure IPG based on result of IEEE 802.3 PHY
 473  * auto-negotiation.
 474  */
 475 static int ipg_config_autoneg(struct net_device *dev)
 476 {
 477         struct ipg_nic_private *sp = netdev_priv(dev);
 478         void __iomem *ioaddr = sp->ioaddr;
 479         unsigned int txflowcontrol;
 480         unsigned int rxflowcontrol;
 481         unsigned int fullduplex;
 482         u32 mac_ctrl_val;
 483         u32 asicctrl;
 484         u8 phyctrl;
 485
 486         IPG_DEBUG_MSG("_config_autoneg\n");
 487
 488         asicctrl = ipg_r32(ASIC_CTRL);
 489         phyctrl = ipg_r8(PHY_CTRL);
 490         mac_ctrl_val = ipg_r32(MAC_CTRL);
 491
 492         /* Set flags for use in resolving auto-negotation, assuming
 493          * non-1000Mbps, half duplex, no flow control.
 494          */
 495         fullduplex = 0;
 496         txflowcontrol = 0;
 497         rxflowcontrol = 0;
 498
 499         /* To accomodate a problem in 10Mbps operation,
 500          * set a global flag if PHY running in 10Mbps mode.
 501          */
 502         sp->tenmbpsmode = 0;
 503
 504         printk(KERN_INFO "%s: Link speed = ", dev->name);
 505
 506         /* Determine actual speed of operation. */
 507         switch (phyctrl & IPG_PC_LINK_SPEED) {
 508         case IPG_PC_LINK_SPEED_10MBPS:
 509                 printk("10Mbps.\n");
 510                 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
 511                        dev->name);
 512                 sp->tenmbpsmode = 1;
 513                 break;
 514         case IPG_PC_LINK_SPEED_100MBPS:
 515                 printk("100Mbps.\n");
 516                 break;
 517         case IPG_PC_LINK_SPEED_1000MBPS:
 518                 printk("1000Mbps.\n");
 519                 break;
 520         default:
 521                 printk("undefined!\n");
 522                 return 0;
 523         }
 524
 525         if (phyctrl & IPG_PC_DUPLEX_STATUS) {
 526                 fullduplex = 1;
 527                 txflowcontrol = 1;
 528                 rxflowcontrol = 1;
 529         }
 530
 531         /* Configure full duplex, and flow control. */
 532         if (fullduplex == 1) {
 533                 /* Configure IPG for full duplex operation. */
 534                 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
 535
 536                 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
 537
 538                 if (txflowcontrol == 1) {
 539                         printk("TX flow control");
 540                         mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
 541                 } else {
 542                         printk("no TX flow control");
 543                         mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
 544                 }
 545
 546                 if (rxflowcontrol == 1) {
 547                         printk(", RX flow control.");
 548                         mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
 549                 } else {
 550                         printk(", no RX flow control.");
 551                         mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 552                 }
 553
 554                 printk("\n");
 555         } else {
 556                 /* Configure IPG for half duplex operation. */
 557                 printk(KERN_INFO "%s: setting half duplex, "
 558                        "no TX flow control, no RX flow control.\n", dev->name);
 559
 560                 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
 561                         ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
 562                         ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 563         }
 564         ipg_w32(mac_ctrl_val, MAC_CTRL);
 565         return 0;
 566 }
 567
 568 /* Determine and configure multicast operation and set
 569  * receive mode for IPG.
 570  */
 571 static void ipg_nic_set_multicast_list(struct net_device *dev)
 572 {
 573         void __iomem *ioaddr = ipg_ioaddr(dev);
 574         struct dev_mc_list *mc_list_ptr;
 575         unsigned int hashindex;
 576         u32 hashtable[2];
 577         u8 receivemode;
 578
 579         IPG_DEBUG_MSG("_nic_set_multicast_list\n");
 580
 581         receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
 582
 583         if (dev->flags & IFF_PROMISC) {
 584                 /* NIC to be configured in promiscuous mode. */
 585                 receivemode = IPG_RM_RECEIVEALLFRAMES;
 586         } else if ((dev->flags & IFF_ALLMULTI) ||
 587                    ((dev->flags & IFF_MULTICAST) &&
 588                     (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
 589                 /* NIC to be configured to receive all multicast
 590                  * frames. */
 591                 receivemode |= IPG_RM_RECEIVEMULTICAST;
 592         } else if ((dev->flags & IFF_MULTICAST) && (dev->mc_count > 0)) {
 593                 /* NIC to be configured to receive selected
 594                  * multicast addresses. */
 595                 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
 596         }
 597
 598         /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
 599          * The IPG applies a cyclic-redundancy-check (the same CRC
 600          * used to calculate the frame data FCS) to the destination
 601          * address all incoming multicast frames whose destination
 602          * address has the multicast bit set. The least significant
 603          * 6 bits of the CRC result are used as an addressing index
 604          * into the hash table. If the value of the bit addressed by
 605          * this index is a 1, the frame is passed to the host system.
 606          */
 607
 608         /* Clear hashtable. */
 609         hashtable[0] = 0x00000000;
 610         hashtable[1] = 0x00000000;
 611
 612         /* Cycle through all multicast addresses to filter. */
 613         for (mc_list_ptr = dev->mc_list;
 614              mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
 615                 /* Calculate CRC result for each multicast address. */
 616                 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
 617                                      ETH_ALEN);
 618
 619                 /* Use only the least significant 6 bits. */
 620                 hashindex = hashindex & 0x3F;
 621
 622                 /* Within "hashtable", set bit number "hashindex"
 623                  * to a logic 1.
 624                  */
 625                 set_bit(hashindex, (void *)hashtable);
 626         }
 627
 628         /* Write the value of the hashtable, to the 4, 16 bit
 629          * HASHTABLE IPG registers.
 630          */
 631         ipg_w32(hashtable[0], HASHTABLE_0);
 632         ipg_w32(hashtable[1], HASHTABLE_1);
 633
 634         ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
 635
 636         IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
 637 }
 638
 639 static int ipg_io_config(struct net_device *dev)
 640 {
 641         struct ipg_nic_private *sp = netdev_priv(dev);
 642         void __iomem *ioaddr = ipg_ioaddr(dev);
 643         u32 origmacctrl;
 644         u32 restoremacctrl;
 645
 646         IPG_DEBUG_MSG("_io_config\n");
 647
 648         origmacctrl = ipg_r32(MAC_CTRL);
 649
 650         restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
 651
 652         /* Based on compilation option, determine if FCS is to be
 653          * stripped on receive frames by IPG.
 654          */
 655         if (!IPG_STRIP_FCS_ON_RX)
 656                 restoremacctrl |= IPG_MC_RCV_FCS;
 657
 658         /* Determine if transmitter and/or receiver are
 659          * enabled so we may restore MACCTRL correctly.
 660          */
 661         if (origmacctrl & IPG_MC_TX_ENABLED)
 662                 restoremacctrl |= IPG_MC_TX_ENABLE;
 663
 664         if (origmacctrl & IPG_MC_RX_ENABLED)
 665                 restoremacctrl |= IPG_MC_RX_ENABLE;
 666
 667         /* Transmitter and receiver must be disabled before setting
 668          * IFSSelect.
 669          */
 670         ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
 671                 IPG_MC_RSVD_MASK, MAC_CTRL);
 672
 673         /* Now that transmitter and receiver are disabled, write
 674          * to IFSSelect.
 675          */
 676         ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
 677
 678         /* Set RECEIVEMODE register. */
 679         ipg_nic_set_multicast_list(dev);
 680
 681         ipg_w16(sp->max_rxframe_size, MAX_FRAME_SIZE);
 682
 683         ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE,   RX_DMA_POLL_PERIOD);
 684         ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
 685         ipg_w8(IPG_RXDMABURSTTHRESH_VALUE,  RX_DMA_BURST_THRESH);
 686         ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE,   TX_DMA_POLL_PERIOD);
 687         ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
 688         ipg_w8(IPG_TXDMABURSTTHRESH_VALUE,  TX_DMA_BURST_THRESH);
 689         ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
 690                  IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
 691                  IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
 692                  IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
 693         ipg_w16(IPG_FLOWONTHRESH_VALUE,  FLOW_ON_THRESH);
 694         ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
 695
 696         /* IPG multi-frag frame bug workaround.
 697          * Per silicon revision B3 eratta.
 698          */
 699         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
 700
 701         /* IPG TX poll now bug workaround.
 702          * Per silicon revision B3 eratta.
 703          */
 704         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
 705
 706         /* IPG RX poll now bug workaround.
 707          * Per silicon revision B3 eratta.
 708          */
 709         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
 710
 711         /* Now restore MACCTRL to original setting. */
 712         ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
 713
 714         /* Disable unused RMON statistics. */
 715         ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
 716
 717         /* Disable unused MIB statistics. */
 718         ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
 719                 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
 720                 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
 721                 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
 722                 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
 723                 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
 724
 725         return 0;
 726 }
 727
 728 /*
 729  * Create a receive buffer within system memory and update
 730  * NIC private structure appropriately.
 731  */
 732 static int ipg_get_rxbuff(struct net_device *dev, int entry)
 733 {
 734         struct ipg_nic_private *sp = netdev_priv(dev);
 735         struct ipg_rx *rxfd = sp->rxd + entry;
 736         struct sk_buff *skb;
 737         u64 rxfragsize;
 738
 739         IPG_DEBUG_MSG("_get_rxbuff\n");
 740
 741         skb = netdev_alloc_skb(dev, sp->rxsupport_size + NET_IP_ALIGN);
 742         if (!skb) {
 743                 sp->rx_buff[entry] = NULL;
 744                 return -ENOMEM;
 745         }
 746
 747         /* Adjust the data start location within the buffer to
 748          * align IP address field to a 16 byte boundary.
 749          */
 750         skb_reserve(skb, NET_IP_ALIGN);
 751
 752         /* Associate the receive buffer with the IPG NIC. */
 753         skb->dev = dev;
 754
 755         /* Save the address of the sk_buff structure. */
 756         sp->rx_buff[entry] = skb;
 757
 758         rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
 759                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
 760
 761         /* Set the RFD fragment length. */
 762         rxfragsize = sp->rxfrag_size;
 763         rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
 764
 765         return 0;
 766 }
 767
 768 static int init_rfdlist(struct net_device *dev)
 769 {
 770         struct ipg_nic_private *sp = netdev_priv(dev);
 771         void __iomem *ioaddr = sp->ioaddr;
 772         unsigned int i;
 773
 774         IPG_DEBUG_MSG("_init_rfdlist\n");
 775
 776         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 777                 struct ipg_rx *rxfd = sp->rxd + i;
 778
 779                 if (sp->rx_buff[i]) {
 780                         pci_unmap_single(sp->pdev,
 781                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
 782                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
 783                         dev_kfree_skb_irq(sp->rx_buff[i]);
 784                         sp->rx_buff[i] = NULL;
 785                 }
 786
 787                 /* Clear out the RFS field. */
 788                 rxfd->rfs = 0x0000000000000000;
 789
 790                 if (ipg_get_rxbuff(dev, i) < 0) {
 791                         /*
 792                          * A receive buffer was not ready, break the
 793                          * RFD list here.
 794                          */
 795                         IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
 796
 797                         /* Just in case we cannot allocate a single RFD.
 798                          * Should not occur.
 799                          */
 800                         if (i == 0) {
 801                                 printk(KERN_ERR "%s: No memory available"
 802                                         " for RFD list.\n", dev->name);
 803                                 return -ENOMEM;
 804                         }
 805                 }
 806
 807                 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
 808                         sizeof(struct ipg_rx)*(i + 1));
 809         }
 810         sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
 811
 812         sp->rx_current = 0;
 813         sp->rx_dirty = 0;
 814
 815         /* Write the location of the RFDList to the IPG. */
 816         ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
 817         ipg_w32(0x00000000, RFD_LIST_PTR_1);
 818
 819         return 0;
 820 }
 821
 822 static void init_tfdlist(struct net_device *dev)
 823 {
 824         struct ipg_nic_private *sp = netdev_priv(dev);
 825         void __iomem *ioaddr = sp->ioaddr;
 826         unsigned int i;
 827
 828         IPG_DEBUG_MSG("_init_tfdlist\n");
 829
 830         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 831                 struct ipg_tx *txfd = sp->txd + i;
 832
 833                 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
 834
 835                 if (sp->tx_buff[i]) {
 836                         dev_kfree_skb_irq(sp->tx_buff[i]);
 837                         sp->tx_buff[i] = NULL;
 838                 }
 839
 840                 txfd->next_desc = cpu_to_le64(sp->txd_map +
 841                         sizeof(struct ipg_tx)*(i + 1));
 842         }
 843         sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
 844
 845         sp->tx_current = 0;
 846         sp->tx_dirty = 0;
 847
 848         /* Write the location of the TFDList to the IPG. */
 849         IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
 850                        (u32) sp->txd_map);
 851         ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
 852         ipg_w32(0x00000000, TFD_LIST_PTR_1);
 853
 854         sp->reset_current_tfd = 1;
 855 }
 856
 857 /*
 858  * Free all transmit buffers which have already been transfered
 859  * via DMA to the IPG.
 860  */
 861 static void ipg_nic_txfree(struct net_device *dev)
 862 {
 863         struct ipg_nic_private *sp = netdev_priv(dev);
 864         unsigned int released, pending, dirty;
 865
 866         IPG_DEBUG_MSG("_nic_txfree\n");
 867
 868         pending = sp->tx_current - sp->tx_dirty;
 869         dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
 870
 871         for (released = 0; released < pending; released++) {
 872                 struct sk_buff *skb = sp->tx_buff[dirty];
 873                 struct ipg_tx *txfd = sp->txd + dirty;
 874
 875                 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
 876
 877                 /* Look at each TFD's TFC field beginning
 878                  * at the last freed TFD up to the current TFD.
 879                  * If the TFDDone bit is set, free the associated
 880                  * buffer.
 881                  */
 882                 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
 883                         break;
 884
 885                 /* Free the transmit buffer. */
 886                 if (skb) {
 887                         pci_unmap_single(sp->pdev,
 888                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
 889                                 skb->len, PCI_DMA_TODEVICE);
 890
 891                         dev_kfree_skb_irq(skb);
 892
 893                         sp->tx_buff[dirty] = NULL;
 894                 }
 895                 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
 896         }
 897
 898         sp->tx_dirty += released;
 899
 900         if (netif_queue_stopped(dev) &&
 901             (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
 902                 netif_wake_queue(dev);
 903         }
 904 }
 905
 906 static void ipg_tx_timeout(struct net_device *dev)
 907 {
 908         struct ipg_nic_private *sp = netdev_priv(dev);
 909         void __iomem *ioaddr = sp->ioaddr;
 910
 911         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
 912                   IPG_AC_FIFO);
 913
 914         spin_lock_irq(&sp->lock);
 915
 916         /* Re-configure after DMA reset. */
 917         if (ipg_io_config(dev) < 0) {
 918                 printk(KERN_INFO "%s: Error during re-configuration.\n",
 919                        dev->name);
 920         }
 921
 922         init_tfdlist(dev);
 923
 924         spin_unlock_irq(&sp->lock);
 925
 926         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
 927                 MAC_CTRL);
 928 }
 929
 930 /*
 931  * For TxComplete interrupts, free all transmit
 932  * buffers which have already been transfered via DMA
 933  * to the IPG.
 934  */
 935 static void ipg_nic_txcleanup(struct net_device *dev)
 936 {
 937         struct ipg_nic_private *sp = netdev_priv(dev);
 938         void __iomem *ioaddr = sp->ioaddr;
 939         unsigned int i;
 940
 941         IPG_DEBUG_MSG("_nic_txcleanup\n");
 942
 943         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 944                 /* Reading the TXSTATUS register clears the
 945                  * TX_COMPLETE interrupt.
 946                  */
 947                 u32 txstatusdword = ipg_r32(TX_STATUS);
 948
 949                 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
 950
 951                 /* Check for Transmit errors. Error bits only valid if
 952                  * TX_COMPLETE bit in the TXSTATUS register is a 1.
 953                  */
 954                 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
 955                         break;
 956
 957                 /* If in 10Mbps mode, indicate transmit is ready. */
 958                 if (sp->tenmbpsmode) {
 959                         netif_wake_queue(dev);
 960                 }
 961
 962                 /* Transmit error, increment stat counters. */
 963                 if (txstatusdword & IPG_TS_TX_ERROR) {
 964                         IPG_DEBUG_MSG("Transmit error.\n");
 965                         sp->stats.tx_errors++;
 966                 }
 967
 968                 /* Late collision, re-enable transmitter. */
 969                 if (txstatusdword & IPG_TS_LATE_COLLISION) {
 970                         IPG_DEBUG_MSG("Late collision on transmit.\n");
 971                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 972                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 973                 }
 974
 975                 /* Maximum collisions, re-enable transmitter. */
 976                 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
 977                         IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
 978                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 979                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 980                 }
 981
 982                 /* Transmit underrun, reset and re-enable
 983                  * transmitter.
 984                  */
 985                 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
 986                         IPG_DEBUG_MSG("Transmitter underrun.\n");
 987                         sp->stats.tx_fifo_errors++;
 988                         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
 989                                   IPG_AC_NETWORK | IPG_AC_FIFO);
 990
 991                         /* Re-configure after DMA reset. */
 992                         if (ipg_io_config(dev) < 0) {
 993                                 printk(KERN_INFO
 994                                        "%s: Error during re-configuration.\n",
 995                                        dev->name);
 996                         }
 997                         init_tfdlist(dev);
 998
 999                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
1000                                 IPG_MC_RSVD_MASK, MAC_CTRL);
1001                 }
1002         }
1003
1004         ipg_nic_txfree(dev);
1005 }
1006
1007 /* Provides statistical information about the IPG NIC. */
1008 static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1009 {
1010         struct ipg_nic_private *sp = netdev_priv(dev);
1011         void __iomem *ioaddr = sp->ioaddr;
1012         u16 temp1;
1013         u16 temp2;
1014
1015         IPG_DEBUG_MSG("_nic_get_stats\n");
1016
1017         /* Check to see if the NIC has been initialized via nic_open,
1018          * before trying to read statistic registers.
1019          */
1020         if (!test_bit(__LINK_STATE_START, &dev->state))
1021                 return &sp->stats;
1022
1023         sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1024         sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1025         sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1026         sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1027         temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1028         sp->stats.rx_errors += temp1;
1029         sp->stats.rx_missed_errors += temp1;
1030         temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1031                 ipg_r32(IPG_LATECOLLISIONS);
1032         temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1033         sp->stats.collisions += temp1;
1034         sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1035         sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1036                 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1037         sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1038
1039         /* detailed tx_errors */
1040         sp->stats.tx_carrier_errors += temp2;
1041
1042         /* detailed rx_errors */
1043         sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1044                 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1045         sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1046
1047         /* Unutilized IPG statistic registers. */
1048         ipg_r32(IPG_MCSTFRAMESRCVDOK);
1049
1050         return &sp->stats;
1051 }
1052
1053 /* Restore used receive buffers. */
1054 static int ipg_nic_rxrestore(struct net_device *dev)
1055 {
1056         struct ipg_nic_private *sp = netdev_priv(dev);
1057         const unsigned int curr = sp->rx_current;
1058         unsigned int dirty = sp->rx_dirty;
1059
1060         IPG_DEBUG_MSG("_nic_rxrestore\n");
1061
1062         for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1063                 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1064
1065                 /* rx_copybreak may poke hole here and there. */
1066                 if (sp->rx_buff[entry])
1067                         continue;
1068
1069                 /* Generate a new receive buffer to replace the
1070                  * current buffer (which will be released by the
1071                  * Linux system).
1072                  */
1073                 if (ipg_get_rxbuff(dev, entry) < 0) {
1074                         IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1075
1076                         break;
1077                 }
1078
1079                 /* Reset the RFS field. */
1080                 sp->rxd[entry].rfs = 0x0000000000000000;
1081         }
1082         sp->rx_dirty = dirty;
1083
1084         return 0;
1085 }
1086
1087 /* use jumboindex and jumbosize to control jumbo frame status
1088  * initial status is jumboindex=-1 and jumbosize=0
1089  * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1090  * 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1091  * 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1092  *               previous receiving and need to continue dumping the current one
1093  */
1094 enum {
1095         NORMAL_PACKET,
1096         ERROR_PACKET
1097 };
1098
1099 enum {
1100         FRAME_NO_START_NO_END   = 0,
1101         FRAME_WITH_START                = 1,
1102         FRAME_WITH_END          = 10,
1103         FRAME_WITH_START_WITH_END = 11
1104 };
1105
1106 static void ipg_nic_rx_free_skb(struct net_device *dev)
1107 {
1108         struct ipg_nic_private *sp = netdev_priv(dev);
1109         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1110
1111         if (sp->rx_buff[entry]) {
1112                 struct ipg_rx *rxfd = sp->rxd + entry;
1113
1114                 pci_unmap_single(sp->pdev,
1115                         le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1116                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1117                 dev_kfree_skb_irq(sp->rx_buff[entry]);
1118                 sp->rx_buff[entry] = NULL;
1119         }
1120 }
1121
1122 static int ipg_nic_rx_check_frame_type(struct net_device *dev)
1123 {
1124         struct ipg_nic_private *sp = netdev_priv(dev);
1125         struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1126         int type = FRAME_NO_START_NO_END;
1127
1128         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1129                 type += FRAME_WITH_START;
1130         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1131                 type += FRAME_WITH_END;
1132         return type;
1133 }
1134
1135 static int ipg_nic_rx_check_error(struct net_device *dev)
1136 {
1137         struct ipg_nic_private *sp = netdev_priv(dev);
1138         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1139         struct ipg_rx *rxfd = sp->rxd + entry;
1140
1141         if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1142              (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1143               IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1144               IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1145                 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1146                               (unsigned long) rxfd->rfs);
1147
1148                 /* Increment general receive error statistic. */
1149                 sp->stats.rx_errors++;
1150
1151                 /* Increment detailed receive error statistics. */
1152                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1153                         IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1154
1155                         sp->stats.rx_fifo_errors++;
1156                 }
1157
1158                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1159                         IPG_DEBUG_MSG("RX runt occured.\n");
1160                         sp->stats.rx_length_errors++;
1161                 }
1162
1163                 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1164                  * error count handled by a IPG statistic register.
1165                  */
1166
1167                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1168                         IPG_DEBUG_MSG("RX alignment error occured.\n");
1169                         sp->stats.rx_frame_errors++;
1170                 }
1171
1172                 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1173                  * handled by a IPG statistic register.
1174                  */
1175
1176                 /* Free the memory associated with the RX
1177                  * buffer since it is erroneous and we will
1178                  * not pass it to higher layer processes.
1179                  */
1180                 if (sp->rx_buff[entry]) {
1181                         pci_unmap_single(sp->pdev,
1182                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1183                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1184
1185                         dev_kfree_skb_irq(sp->rx_buff[entry]);
1186                         sp->rx_buff[entry] = NULL;
1187                 }
1188                 return ERROR_PACKET;
1189         }
1190         return NORMAL_PACKET;
1191 }
1192
1193 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1194                                           struct ipg_nic_private *sp,
1195                                           struct ipg_rx *rxfd, unsigned entry)
1196 {
1197         struct ipg_jumbo *jumbo = &sp->jumbo;
1198         struct sk_buff *skb;
1199         int framelen;
1200
1201         if (jumbo->found_start) {
1202                 dev_kfree_skb_irq(jumbo->skb);
1203                 jumbo->found_start = 0;
1204                 jumbo->current_size = 0;
1205                 jumbo->skb = NULL;
1206         }
1207
1208         /* 1: found error, 0 no error */
1209         if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1210                 return;
1211
1212         skb = sp->rx_buff[entry];
1213         if (!skb)
1214                 return;
1215
1216         /* accept this frame and send to upper layer */
1217         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1218         if (framelen > sp->rxfrag_size)
1219                 framelen = sp->rxfrag_size;
1220
1221         skb_put(skb, framelen);
1222         skb->protocol = eth_type_trans(skb, dev);
1223         skb->ip_summed = CHECKSUM_NONE;
1224         netif_rx(skb);
1225         dev->last_rx = jiffies;
1226         sp->rx_buff[entry] = NULL;
1227 }
1228
1229 static void ipg_nic_rx_with_start(struct net_device *dev,
1230                                   struct ipg_nic_private *sp,
1231                                   struct ipg_rx *rxfd, unsigned entry)
1232 {
1233         struct ipg_jumbo *jumbo = &sp->jumbo;
1234         struct pci_dev *pdev = sp->pdev;
1235         struct sk_buff *skb;
1236
1237         /* 1: found error, 0 no error */
1238         if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1239                 return;
1240
1241         /* accept this frame and send to upper layer */
1242         skb = sp->rx_buff[entry];
1243         if (!skb)
1244                 return;
1245
1246         if (jumbo->found_start)
1247                 dev_kfree_skb_irq(jumbo->skb);
1248
1249         pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1250                          sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1251
1252         skb_put(skb, sp->rxfrag_size);
1253
1254         jumbo->found_start = 1;
1255         jumbo->current_size = sp->rxfrag_size;
1256         jumbo->skb = skb;
1257
1258         sp->rx_buff[entry] = NULL;
1259         dev->last_rx = jiffies;
1260 }
1261
1262 static void ipg_nic_rx_with_end(struct net_device *dev,
1263                                 struct ipg_nic_private *sp,
1264                                 struct ipg_rx *rxfd, unsigned entry)
1265 {
1266         struct ipg_jumbo *jumbo = &sp->jumbo;
1267
1268         /* 1: found error, 0 no error */
1269         if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1270                 struct sk_buff *skb = sp->rx_buff[entry];
1271
1272                 if (!skb)
1273                         return;
1274
1275                 if (jumbo->found_start) {
1276                         int framelen, endframelen;
1277
1278                         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1279
1280                         endframelen = framelen - jumbo->current_size;
1281                         if (framelen > sp->rxsupport_size)
1282                                 dev_kfree_skb_irq(jumbo->skb);
1283                         else {
1284                                 memcpy(skb_put(jumbo->skb, endframelen),
1285                                        skb->data, endframelen);
1286
1287                                 jumbo->skb->protocol =
1288                                     eth_type_trans(jumbo->skb, dev);
1289
1290                                 jumbo->skb->ip_summed = CHECKSUM_NONE;
1291                                 netif_rx(jumbo->skb);
1292                         }
1293                 }
1294
1295                 dev->last_rx = jiffies;
1296                 jumbo->found_start = 0;
1297                 jumbo->current_size = 0;
1298                 jumbo->skb = NULL;
1299
1300                 ipg_nic_rx_free_skb(dev);
1301         } else {
1302                 dev_kfree_skb_irq(jumbo->skb);
1303                 jumbo->found_start = 0;
1304                 jumbo->current_size = 0;
1305                 jumbo->skb = NULL;
1306         }
1307 }
1308
1309 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1310                                        struct ipg_nic_private *sp,
1311                                        struct ipg_rx *rxfd, unsigned entry)
1312 {
1313         struct ipg_jumbo *jumbo = &sp->jumbo;
1314
1315         /* 1: found error, 0 no error */
1316         if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1317                 struct sk_buff *skb = sp->rx_buff[entry];
1318
1319                 if (skb) {
1320                         if (jumbo->found_start) {
1321                                 jumbo->current_size += sp->rxfrag_size;
1322                                 if (jumbo->current_size <= sp->rxsupport_size) {
1323                                         memcpy(skb_put(jumbo->skb,
1324                                                        sp->rxfrag_size),
1325                                                skb->data, sp->rxfrag_size);
1326                                 }
1327                         }
1328                         dev->last_rx = jiffies;
1329                         ipg_nic_rx_free_skb(dev);
1330                 }
1331         } else {
1332                 dev_kfree_skb_irq(jumbo->skb);
1333                 jumbo->found_start = 0;
1334                 jumbo->current_size = 0;
1335                 jumbo->skb = NULL;
1336         }
1337 }
1338
1339 static int ipg_nic_rx_jumbo(struct net_device *dev)
1340 {
1341         struct ipg_nic_private *sp = netdev_priv(dev);
1342         unsigned int curr = sp->rx_current;
1343         void __iomem *ioaddr = sp->ioaddr;
1344         unsigned int i;
1345
1346         IPG_DEBUG_MSG("_nic_rx\n");
1347
1348         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1349                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1350                 struct ipg_rx *rxfd = sp->rxd + entry;
1351
1352                 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1353                         break;
1354
1355                 switch (ipg_nic_rx_check_frame_type(dev)) {
1356                 case FRAME_WITH_START_WITH_END:
1357                         ipg_nic_rx_with_start_and_end(dev, sp, rxfd, entry);
1358                         break;
1359                 case FRAME_WITH_START:
1360                         ipg_nic_rx_with_start(dev, sp, rxfd, entry);
1361                         break;
1362                 case FRAME_WITH_END:
1363                         ipg_nic_rx_with_end(dev, sp, rxfd, entry);
1364                         break;
1365                 case FRAME_NO_START_NO_END:
1366                         ipg_nic_rx_no_start_no_end(dev, sp, rxfd, entry);
1367                         break;
1368                 }
1369         }
1370
1371         sp->rx_current = curr;
1372
1373         if (i == IPG_MAXRFDPROCESS_COUNT) {
1374                 /* There are more RFDs to process, however the
1375                  * allocated amount of RFD processing time has
1376                  * expired. Assert Interrupt Requested to make
1377                  * sure we come back to process the remaining RFDs.
1378                  */
1379                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1380         }
1381
1382         ipg_nic_rxrestore(dev);
1383
1384         return 0;
1385 }
1386
1387 static int ipg_nic_rx(struct net_device *dev)
1388 {
1389         /* Transfer received Ethernet frames to higher network layers. */
1390         struct ipg_nic_private *sp = netdev_priv(dev);
1391         unsigned int curr = sp->rx_current;
1392         void __iomem *ioaddr = sp->ioaddr;
1393         struct ipg_rx *rxfd;
1394         unsigned int i;
1395
1396         IPG_DEBUG_MSG("_nic_rx\n");
1397
1398 #define __RFS_MASK \
1399         cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1400
1401         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1402                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1403                 struct sk_buff *skb = sp->rx_buff[entry];
1404                 unsigned int framelen;
1405
1406                 rxfd = sp->rxd + entry;
1407
1408                 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1409                         break;
1410
1411                 /* Get received frame length. */
1412                 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1413
1414                 /* Check for jumbo frame arrival with too small
1415                  * RXFRAG_SIZE.
1416                  */
1417                 if (framelen > sp->rxfrag_size) {
1418                         IPG_DEBUG_MSG
1419                             ("RFS FrameLen > allocated fragment size.\n");
1420
1421                         framelen = sp->rxfrag_size;
1422                 }
1423
1424                 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1425                        (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1426                         IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1427                         IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1428
1429                         IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1430                                       (unsigned long int) rxfd->rfs);
1431
1432                         /* Increment general receive error statistic. */
1433                         sp->stats.rx_errors++;
1434
1435                         /* Increment detailed receive error statistics. */
1436                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1437                                 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1438                                 sp->stats.rx_fifo_errors++;
1439                         }
1440
1441                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1442                                 IPG_DEBUG_MSG("RX runt occured.\n");
1443                                 sp->stats.rx_length_errors++;
1444                         }
1445
1446                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1447                         /* Do nothing, error count handled by a IPG
1448                          * statistic register.
1449                          */
1450
1451                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1452                                 IPG_DEBUG_MSG("RX alignment error occured.\n");
1453                                 sp->stats.rx_frame_errors++;
1454                         }
1455
1456                         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1457                         /* Do nothing, error count handled by a IPG
1458                          * statistic register.
1459                          */
1460
1461                         /* Free the memory associated with the RX
1462                          * buffer since it is erroneous and we will
1463                          * not pass it to higher layer processes.
1464                          */
1465                         if (skb) {
1466                                 __le64 info = rxfd->frag_info;
1467
1468                                 pci_unmap_single(sp->pdev,
1469                                         le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1470                                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1471
1472                                 dev_kfree_skb_irq(skb);
1473                         }
1474                 } else {
1475
1476                         /* Adjust the new buffer length to accomodate the size
1477                          * of the received frame.
1478                          */
1479                         skb_put(skb, framelen);
1480
1481                         /* Set the buffer's protocol field to Ethernet. */
1482                         skb->protocol = eth_type_trans(skb, dev);
1483
1484                         /* The IPG encountered an error with (or
1485                          * there were no) IP/TCP/UDP checksums.
1486                          * This may or may not indicate an invalid
1487                          * IP/TCP/UDP frame was received. Let the
1488                          * upper layer decide.
1489                          */
1490                         skb->ip_summed = CHECKSUM_NONE;
1491
1492                         /* Hand off frame for higher layer processing.
1493                          * The function netif_rx() releases the sk_buff
1494                          * when processing completes.
1495                          */
1496                         netif_rx(skb);
1497
1498                         /* Record frame receive time (jiffies = Linux
1499                          * kernel current time stamp).
1500                          */
1501                         dev->last_rx = jiffies;
1502                 }
1503
1504                 /* Assure RX buffer is not reused by IPG. */
1505                 sp->rx_buff[entry] = NULL;
1506         }
1507
1508         /*
1509          * If there are more RFDs to proces and the allocated amount of RFD
1510          * processing time has expired, assert Interrupt Requested to make
1511          * sure we come back to process the remaining RFDs.
1512          */
1513         if (i == IPG_MAXRFDPROCESS_COUNT)
1514                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1515
1516 #ifdef IPG_DEBUG
1517         /* Check if the RFD list contained no receive frame data. */
1518         if (!i)
1519                 sp->EmptyRFDListCount++;
1520 #endif
1521         while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1522                !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1523                  (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1524                 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1525
1526                 rxfd = sp->rxd + entry;
1527
1528                 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1529
1530                 /* An unexpected event, additional code needed to handle
1531                  * properly. So for the time being, just disregard the
1532                  * frame.
1533                  */
1534
1535                 /* Free the memory associated with the RX
1536                  * buffer since it is erroneous and we will
1537                  * not pass it to higher layer processes.
1538                  */
1539                 if (sp->rx_buff[entry]) {
1540                         pci_unmap_single(sp->pdev,
1541                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1542                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1543                         dev_kfree_skb_irq(sp->rx_buff[entry]);
1544                 }
1545
1546                 /* Assure RX buffer is not reused by IPG. */
1547                 sp->rx_buff[entry] = NULL;
1548         }
1549
1550         sp->rx_current = curr;
1551
1552         /* Check to see if there are a minimum number of used
1553          * RFDs before restoring any (should improve performance.)
1554          */
1555         if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1556                 ipg_nic_rxrestore(dev);
1557
1558         return 0;
1559 }
1560
1561 static void ipg_reset_after_host_error(struct work_struct *work)
1562 {
1563         struct ipg_nic_private *sp =
1564                 container_of(work, struct ipg_nic_private, task.work);
1565         struct net_device *dev = sp->dev;
1566
1567         IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1568
1569         /*
1570          * Acknowledge HostError interrupt by resetting
1571          * IPG DMA and HOST.
1572          */
1573         ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1574
1575         init_rfdlist(dev);
1576         init_tfdlist(dev);
1577
1578         if (ipg_io_config(dev) < 0) {
1579                 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1580                        dev->name);
1581                 schedule_delayed_work(&sp->task, HZ);
1582         }
1583 }
1584
1585 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1586 {
1587         struct net_device *dev = dev_inst;
1588         struct ipg_nic_private *sp = netdev_priv(dev);
1589         void __iomem *ioaddr = sp->ioaddr;
1590         unsigned int handled = 0;
1591         u16 status;
1592
1593         IPG_DEBUG_MSG("_interrupt_handler\n");
1594
1595         if (sp->is_jumbo)
1596                 ipg_nic_rxrestore(dev);
1597
1598         spin_lock(&sp->lock);
1599
1600         /* Get interrupt source information, and acknowledge
1601          * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1602          * IntRequested, MacControlFrame, LinkEvent) interrupts
1603          * if issued. Also, all IPG interrupts are disabled by
1604          * reading IntStatusAck.
1605          */
1606         status = ipg_r16(INT_STATUS_ACK);
1607
1608         IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1609
1610         /* Shared IRQ of remove event. */
1611         if (!(status & IPG_IS_RSVD_MASK))
1612                 goto out_enable;
1613
1614         handled = 1;
1615
1616         if (unlikely(!netif_running(dev)))
1617                 goto out_unlock;
1618
1619         /* If RFDListEnd interrupt, restore all used RFDs. */
1620         if (status & IPG_IS_RFD_LIST_END) {
1621                 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1622
1623                 /* The RFD list end indicates an RFD was encountered
1624                  * with a 0 NextPtr, or with an RFDDone bit set to 1
1625                  * (indicating the RFD is not read for use by the
1626                  * IPG.) Try to restore all RFDs.
1627                  */
1628                 ipg_nic_rxrestore(dev);
1629
1630 #ifdef IPG_DEBUG
1631                 /* Increment the RFDlistendCount counter. */
1632                 sp->RFDlistendCount++;
1633 #endif
1634         }
1635
1636         /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1637          * IntRequested interrupt, process received frames. */
1638         if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1639             (status & IPG_IS_RFD_LIST_END) ||
1640             (status & IPG_IS_RX_DMA_COMPLETE) ||
1641             (status & IPG_IS_INT_REQUESTED)) {
1642 #ifdef IPG_DEBUG
1643                 /* Increment the RFD list checked counter if interrupted
1644                  * only to check the RFD list. */
1645                 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1646                                 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1647                                (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1648                                 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1649                                 IPG_IS_UPDATE_STATS)))
1650                         sp->RFDListCheckedCount++;
1651 #endif
1652
1653                 if (sp->is_jumbo)
1654                         ipg_nic_rx_jumbo(dev);
1655                 else
1656                         ipg_nic_rx(dev);
1657         }
1658
1659         /* If TxDMAComplete interrupt, free used TFDs. */
1660         if (status & IPG_IS_TX_DMA_COMPLETE)
1661                 ipg_nic_txfree(dev);
1662
1663         /* TxComplete interrupts indicate one of numerous actions.
1664          * Determine what action to take based on TXSTATUS register.
1665          */
1666         if (status & IPG_IS_TX_COMPLETE)
1667                 ipg_nic_txcleanup(dev);
1668
1669         /* If UpdateStats interrupt, update Linux Ethernet statistics */
1670         if (status & IPG_IS_UPDATE_STATS)
1671                 ipg_nic_get_stats(dev);
1672
1673         /* If HostError interrupt, reset IPG. */
1674         if (status & IPG_IS_HOST_ERROR) {
1675                 IPG_DDEBUG_MSG("HostError Interrupt\n");
1676
1677                 schedule_delayed_work(&sp->task, 0);
1678         }
1679
1680         /* If LinkEvent interrupt, resolve autonegotiation. */
1681         if (status & IPG_IS_LINK_EVENT) {
1682                 if (ipg_config_autoneg(dev) < 0)
1683                         printk(KERN_INFO "%s: Auto-negotiation error.\n",
1684                                dev->name);
1685         }
1686
1687         /* If MACCtrlFrame interrupt, do nothing. */
1688         if (status & IPG_IS_MAC_CTRL_FRAME)
1689                 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1690
1691         /* If RxComplete interrupt, do nothing. */
1692         if (status & IPG_IS_RX_COMPLETE)
1693                 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1694
1695         /* If RxEarly interrupt, do nothing. */
1696         if (status & IPG_IS_RX_EARLY)
1697                 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1698
1699 out_enable:
1700         /* Re-enable IPG interrupts. */
1701         ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1702                 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1703                 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1704 out_unlock:
1705         spin_unlock(&sp->lock);
1706
1707         return IRQ_RETVAL(handled);
1708 }
1709
1710 static void ipg_rx_clear(struct ipg_nic_private *sp)
1711 {
1712         unsigned int i;
1713
1714         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1715                 if (sp->rx_buff[i]) {
1716                         struct ipg_rx *rxfd = sp->rxd + i;
1717
1718                         dev_kfree_skb_irq(sp->rx_buff[i]);
1719                         sp->rx_buff[i] = NULL;
1720                         pci_unmap_single(sp->pdev,
1721                                 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1722                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1723                 }
1724         }
1725 }
1726
1727 static void ipg_tx_clear(struct ipg_nic_private *sp)
1728 {
1729         unsigned int i;
1730
1731         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1732                 if (sp->tx_buff[i]) {
1733                         struct ipg_tx *txfd = sp->txd + i;
1734
1735                         pci_unmap_single(sp->pdev,
1736                                 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1737                                 sp->tx_buff[i]->len, PCI_DMA_TODEVICE);
1738
1739                         dev_kfree_skb_irq(sp->tx_buff[i]);
1740
1741                         sp->tx_buff[i] = NULL;
1742                 }
1743         }
1744 }
1745
1746 static int ipg_nic_open(struct net_device *dev)
1747 {
1748         struct ipg_nic_private *sp = netdev_priv(dev);
1749         void __iomem *ioaddr = sp->ioaddr;
1750         struct pci_dev *pdev = sp->pdev;
1751         int rc;
1752
1753         IPG_DEBUG_MSG("_nic_open\n");
1754
1755         sp->rx_buf_sz = sp->rxsupport_size;
1756
1757         /* Check for interrupt line conflicts, and request interrupt
1758          * line for IPG.
1759          *
1760          * IMPORTANT: Disable IPG interrupts prior to registering
1761          *            IRQ.
1762          */
1763         ipg_w16(0x0000, INT_ENABLE);
1764
1765         /* Register the interrupt line to be used by the IPG within
1766          * the Linux system.
1767          */
1768         rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1769                          dev->name, dev);
1770         if (rc < 0) {
1771                 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1772                        dev->name);
1773                 goto out;
1774         }
1775
1776         dev->irq = pdev->irq;
1777
1778         rc = -ENOMEM;
1779
1780         sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1781                                      &sp->rxd_map, GFP_KERNEL);
1782         if (!sp->rxd)
1783                 goto err_free_irq_0;
1784
1785         sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1786                                      &sp->txd_map, GFP_KERNEL);
1787         if (!sp->txd)
1788                 goto err_free_rx_1;
1789
1790         rc = init_rfdlist(dev);
1791         if (rc < 0) {
1792                 printk(KERN_INFO "%s: Error during configuration.\n",
1793                        dev->name);
1794                 goto err_free_tx_2;
1795         }
1796
1797         init_tfdlist(dev);
1798
1799         rc = ipg_io_config(dev);
1800         if (rc < 0) {
1801                 printk(KERN_INFO "%s: Error during configuration.\n",
1802                        dev->name);
1803                 goto err_release_tfdlist_3;
1804         }
1805
1806         /* Resolve autonegotiation. */
1807         if (ipg_config_autoneg(dev) < 0)
1808                 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1809
1810         /* initialize JUMBO Frame control variable */
1811         sp->jumbo.found_start = 0;
1812         sp->jumbo.current_size = 0;
1813         sp->jumbo.skb = NULL;
1814
1815         /* Enable transmit and receive operation of the IPG. */
1816         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1817                  IPG_MC_RSVD_MASK, MAC_CTRL);
1818
1819         netif_start_queue(dev);
1820 out:
1821         return rc;
1822
1823 err_release_tfdlist_3:
1824         ipg_tx_clear(sp);
1825         ipg_rx_clear(sp);
1826 err_free_tx_2:
1827         dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1828 err_free_rx_1:
1829         dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1830 err_free_irq_0:
1831         free_irq(pdev->irq, dev);
1832         goto out;
1833 }
1834
1835 static int ipg_nic_stop(struct net_device *dev)
1836 {
1837         struct ipg_nic_private *sp = netdev_priv(dev);
1838         void __iomem *ioaddr = sp->ioaddr;
1839         struct pci_dev *pdev = sp->pdev;
1840
1841         IPG_DEBUG_MSG("_nic_stop\n");
1842
1843         netif_stop_queue(dev);
1844
1845         IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1846         IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1847         IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1848         IPG_DUMPTFDLIST(dev);
1849
1850         do {
1851                 (void) ipg_r16(INT_STATUS_ACK);
1852
1853                 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1854
1855                 synchronize_irq(pdev->irq);
1856         } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1857
1858         ipg_rx_clear(sp);
1859
1860         ipg_tx_clear(sp);
1861
1862         pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1863         pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1864
1865         free_irq(pdev->irq, dev);
1866
1867         return 0;
1868 }
1869
1870 static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1871 {
1872         struct ipg_nic_private *sp = netdev_priv(dev);
1873         void __iomem *ioaddr = sp->ioaddr;
1874         unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1875         unsigned long flags;
1876         struct ipg_tx *txfd;
1877
1878         IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1879
1880         /* If in 10Mbps mode, stop the transmit queue so
1881          * no more transmit frames are accepted.
1882          */
1883         if (sp->tenmbpsmode)
1884                 netif_stop_queue(dev);
1885
1886         if (sp->reset_current_tfd) {
1887                 sp->reset_current_tfd = 0;
1888                 entry = 0;
1889         }
1890
1891         txfd = sp->txd + entry;
1892
1893         sp->tx_buff[entry] = skb;
1894
1895         /* Clear all TFC fields, except TFDDONE. */
1896         txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1897
1898         /* Specify the TFC field within the TFD. */
1899         txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1900                 (IPG_TFC_FRAMEID & sp->tx_current) |
1901                 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1902         /*
1903          * 16--17 (WordAlign) <- 3 (disable),
1904          * 0--15 (FrameId) <- sp->tx_current,
1905          * 24--27 (FragCount) <- 1
1906          */
1907
1908         /* Request TxComplete interrupts at an interval defined
1909          * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1910          * Request TxComplete interrupt for every frame
1911          * if in 10Mbps mode to accomodate problem with 10Mbps
1912          * processing.
1913          */
1914         if (sp->tenmbpsmode)
1915                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1916         txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1917         /* Based on compilation option, determine if FCS is to be
1918          * appended to transmit frame by IPG.
1919          */
1920         if (!(IPG_APPEND_FCS_ON_TX))
1921                 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1922
1923         /* Based on compilation option, determine if IP, TCP and/or
1924          * UDP checksums are to be added to transmit frame by IPG.
1925          */
1926         if (IPG_ADD_IPCHECKSUM_ON_TX)
1927                 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1928
1929         if (IPG_ADD_TCPCHECKSUM_ON_TX)
1930                 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1931
1932         if (IPG_ADD_UDPCHECKSUM_ON_TX)
1933                 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1934
1935         /* Based on compilation option, determine if VLAN tag info is to be
1936          * inserted into transmit frame by IPG.
1937          */
1938         if (IPG_INSERT_MANUAL_VLAN_TAG) {
1939                 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1940                         ((u64) IPG_MANUAL_VLAN_VID << 32) |
1941                         ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1942                         ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1943         }
1944
1945         /* The fragment start location within system memory is defined
1946          * by the sk_buff structure's data field. The physical address
1947          * of this location within the system's virtual memory space
1948          * is determined using the IPG_HOST2BUS_MAP function.
1949          */
1950         txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1951                 skb->len, PCI_DMA_TODEVICE));
1952
1953         /* The length of the fragment within system memory is defined by
1954          * the sk_buff structure's len field.
1955          */
1956         txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1957                 ((u64) (skb->len & 0xffff) << 48));
1958
1959         /* Clear the TFDDone bit last to indicate the TFD is ready
1960          * for transfer to the IPG.
1961          */
1962         txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1963
1964         spin_lock_irqsave(&sp->lock, flags);
1965
1966         sp->tx_current++;
1967
1968         mmiowb();
1969
1970         ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1971
1972         if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
1973                 netif_stop_queue(dev);
1974
1975         spin_unlock_irqrestore(&sp->lock, flags);
1976
1977         return NETDEV_TX_OK;
1978 }
1979
1980 static void ipg_set_phy_default_param(unsigned char rev,
1981                                       struct net_device *dev, int phy_address)
1982 {
1983         unsigned short length;
1984         unsigned char revision;
1985         unsigned short *phy_param;
1986         unsigned short address, value;
1987
1988         phy_param = &DefaultPhyParam[0];
1989         length = *phy_param & 0x00FF;
1990         revision = (unsigned char)((*phy_param) >> 8);
1991         phy_param++;
1992         while (length != 0) {
1993                 if (rev == revision) {
1994                         while (length > 1) {
1995                                 address = *phy_param;
1996                                 value = *(phy_param + 1);
1997                                 phy_param += 2;
1998                                 mdio_write(dev, phy_address, address, value);
1999                                 length -= 4;
2000                         }
2001                         break;
2002                 } else {
2003                         phy_param += length / 2;
2004                         length = *phy_param & 0x00FF;
2005                         revision = (unsigned char)((*phy_param) >> 8);
2006                         phy_param++;
2007                 }
2008         }
2009 }
2010
2011 static int read_eeprom(struct net_device *dev, int eep_addr)
2012 {
2013         void __iomem *ioaddr = ipg_ioaddr(dev);
2014         unsigned int i;
2015         int ret = 0;
2016         u16 value;
2017
2018         value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2019         ipg_w16(value, EEPROM_CTRL);
2020
2021         for (i = 0; i < 1000; i++) {
2022                 u16 data;
2023
2024                 mdelay(10);
2025                 data = ipg_r16(EEPROM_CTRL);
2026                 if (!(data & IPG_EC_EEPROM_BUSY)) {
2027                         ret = ipg_r16(EEPROM_DATA);
2028                         break;
2029                 }
2030         }
2031         return ret;
2032 }
2033
2034 static void ipg_init_mii(struct net_device *dev)
2035 {
2036         struct ipg_nic_private *sp = netdev_priv(dev);
2037         struct mii_if_info *mii_if = &sp->mii_if;
2038         int phyaddr;
2039
2040         mii_if->dev          = dev;
2041         mii_if->mdio_read    = mdio_read;
2042         mii_if->mdio_write   = mdio_write;
2043         mii_if->phy_id_mask  = 0x1f;
2044         mii_if->reg_num_mask = 0x1f;
2045
2046         mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2047
2048         if (phyaddr != 0x1f) {
2049                 u16 mii_phyctrl, mii_1000cr;
2050                 u8 revisionid = 0;
2051
2052                 mii_1000cr  = mdio_read(dev, phyaddr, MII_CTRL1000);
2053                 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2054                         GMII_PHY_1000BASETCONTROL_PreferMaster;
2055                 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2056
2057                 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2058
2059                 /* Set default phyparam */
2060                 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2061                 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2062
2063                 /* Reset PHY */
2064                 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2065                 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2066
2067         }
2068 }
2069
2070 static int ipg_hw_init(struct net_device *dev)
2071 {
2072         struct ipg_nic_private *sp = netdev_priv(dev);
2073         void __iomem *ioaddr = sp->ioaddr;
2074         unsigned int i;
2075         int rc;
2076
2077         /* Read/Write and Reset EEPROM Value */
2078         /* Read LED Mode Configuration from EEPROM */
2079         sp->led_mode = read_eeprom(dev, 6);
2080
2081         /* Reset all functions within the IPG. Do not assert
2082          * RST_OUT as not compatible with some PHYs.
2083          */
2084         rc = ipg_reset(dev, IPG_RESET_MASK);
2085         if (rc < 0)
2086                 goto out;
2087
2088         ipg_init_mii(dev);
2089
2090         /* Read MAC Address from EEPROM */
2091         for (i = 0; i < 3; i++)
2092                 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2093
2094         for (i = 0; i < 3; i++)
2095                 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2096
2097         /* Set station address in ethernet_device structure. */
2098         dev->dev_addr[0] =  ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2099         dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2100         dev->dev_addr[2] =  ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2101         dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2102         dev->dev_addr[4] =  ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2103         dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2104 out:
2105         return rc;
2106 }
2107
2108 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2109 {
2110         struct ipg_nic_private *sp = netdev_priv(dev);
2111         int rc;
2112
2113         mutex_lock(&sp->mii_mutex);
2114         rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2115         mutex_unlock(&sp->mii_mutex);
2116
2117         return rc;
2118 }
2119
2120 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2121 {
2122         struct ipg_nic_private *sp = netdev_priv(dev);
2123         int err;
2124
2125         /* Function to accomodate changes to Maximum Transfer Unit
2126          * (or MTU) of IPG NIC. Cannot use default function since
2127          * the default will not allow for MTU > 1500 bytes.
2128          */
2129
2130         IPG_DEBUG_MSG("_nic_change_mtu\n");
2131
2132         /*
2133          * Check that the new MTU value is between 68 (14 byte header, 46 byte
2134          * payload, 4 byte FCS) and 10 KB, which is the largest supported MTU.
2135          */
2136         if (new_mtu < 68 || new_mtu > 10240)
2137                 return -EINVAL;
2138
2139         err = ipg_nic_stop(dev);
2140         if (err)
2141                 return err;
2142
2143         dev->mtu = new_mtu;
2144
2145         sp->max_rxframe_size = new_mtu;
2146
2147         sp->rxfrag_size = new_mtu;
2148         if (sp->rxfrag_size > 4088)
2149                 sp->rxfrag_size = 4088;
2150
2151         sp->rxsupport_size = sp->max_rxframe_size;
2152
2153         if (new_mtu > 0x0600)
2154                 sp->is_jumbo = true;
2155         else
2156                 sp->is_jumbo = false;
2157
2158         return ipg_nic_open(dev);
2159 }
2160
2161 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2162 {
2163         struct ipg_nic_private *sp = netdev_priv(dev);
2164         int rc;
2165
2166         mutex_lock(&sp->mii_mutex);
2167         rc = mii_ethtool_gset(&sp->mii_if, cmd);
2168         mutex_unlock(&sp->mii_mutex);
2169
2170         return rc;
2171 }
2172
2173 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2174 {
2175         struct ipg_nic_private *sp = netdev_priv(dev);
2176         int rc;
2177
2178         mutex_lock(&sp->mii_mutex);
2179         rc = mii_ethtool_sset(&sp->mii_if, cmd);
2180         mutex_unlock(&sp->mii_mutex);
2181
2182         return rc;
2183 }
2184
2185 static int ipg_nway_reset(struct net_device *dev)
2186 {
2187         struct ipg_nic_private *sp = netdev_priv(dev);
2188         int rc;
2189
2190         mutex_lock(&sp->mii_mutex);
2191         rc = mii_nway_restart(&sp->mii_if);
2192         mutex_unlock(&sp->mii_mutex);
2193
2194         return rc;
2195 }
2196
2197 static struct ethtool_ops ipg_ethtool_ops = {
2198         .get_settings = ipg_get_settings,
2199         .set_settings = ipg_set_settings,
2200         .nway_reset   = ipg_nway_reset,
2201 };
2202
2203 static void __devexit ipg_remove(struct pci_dev *pdev)
2204 {
2205         struct net_device *dev = pci_get_drvdata(pdev);
2206         struct ipg_nic_private *sp = netdev_priv(dev);
2207
2208         IPG_DEBUG_MSG("_remove\n");
2209
2210         /* Un-register Ethernet device. */
2211         unregister_netdev(dev);
2212
2213         pci_iounmap(pdev, sp->ioaddr);
2214
2215         pci_release_regions(pdev);
2216
2217         free_netdev(dev);
2218         pci_disable_device(pdev);
2219         pci_set_drvdata(pdev, NULL);
2220 }
2221
2222 static int __devinit ipg_probe(struct pci_dev *pdev,
2223                                const struct pci_device_id *id)
2224 {
2225         unsigned int i = id->driver_data;
2226         struct ipg_nic_private *sp;
2227         struct net_device *dev;
2228         void __iomem *ioaddr;
2229         int rc;
2230
2231         rc = pci_enable_device(pdev);
2232         if (rc < 0)
2233                 goto out;
2234
2235         printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2236
2237         pci_set_master(pdev);
2238
2239         rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2240         if (rc < 0) {
2241                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2242                 if (rc < 0) {
2243                         printk(KERN_ERR "%s: DMA config failed.\n",
2244                                pci_name(pdev));
2245                         goto err_disable_0;
2246                 }
2247         }
2248
2249         /*
2250          * Initialize net device.
2251          */
2252         dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2253         if (!dev) {
2254                 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2255                 rc = -ENOMEM;
2256                 goto err_disable_0;
2257         }
2258
2259         sp = netdev_priv(dev);
2260         spin_lock_init(&sp->lock);
2261         mutex_init(&sp->mii_mutex);
2262
2263         sp->is_jumbo = IPG_IS_JUMBO;
2264         sp->rxfrag_size = IPG_RXFRAG_SIZE;
2265         sp->rxsupport_size = IPG_RXSUPPORT_SIZE;
2266         sp->max_rxframe_size = IPG_MAX_RXFRAME_SIZE;
2267
2268         /* Declare IPG NIC functions for Ethernet device methods.
2269          */
2270         dev->open = &ipg_nic_open;
2271         dev->stop = &ipg_nic_stop;
2272         dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2273         dev->get_stats = &ipg_nic_get_stats;
2274         dev->set_multicast_list = &ipg_nic_set_multicast_list;
2275         dev->do_ioctl = ipg_ioctl;
2276         dev->tx_timeout = ipg_tx_timeout;
2277         dev->change_mtu = &ipg_nic_change_mtu;
2278
2279         SET_NETDEV_DEV(dev, &pdev->dev);
2280         SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2281
2282         rc = pci_request_regions(pdev, DRV_NAME);
2283         if (rc)
2284                 goto err_free_dev_1;
2285
2286         ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2287         if (!ioaddr) {
2288                 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2289                 rc = -EIO;
2290                 goto err_release_regions_2;
2291         }
2292
2293         /* Save the pointer to the PCI device information. */
2294         sp->ioaddr = ioaddr;
2295         sp->pdev = pdev;
2296         sp->dev = dev;
2297
2298         INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2299
2300         pci_set_drvdata(pdev, dev);
2301
2302         rc = ipg_hw_init(dev);
2303         if (rc < 0)
2304                 goto err_unmap_3;
2305
2306         rc = register_netdev(dev);
2307         if (rc < 0)
2308                 goto err_unmap_3;
2309
2310         printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2311 out:
2312         return rc;
2313
2314 err_unmap_3:
2315         pci_iounmap(pdev, ioaddr);
2316 err_release_regions_2:
2317         pci_release_regions(pdev);
2318 err_free_dev_1:
2319         free_netdev(dev);
2320 err_disable_0:
2321         pci_disable_device(pdev);
2322         goto out;
2323 }
2324
2325 static struct pci_driver ipg_pci_driver = {
2326         .name           = IPG_DRIVER_NAME,
2327         .id_table       = ipg_pci_tbl,
2328         .probe          = ipg_probe,
2329         .remove         = __devexit_p(ipg_remove),
2330 };
2331
2332 static int __init ipg_init_module(void)
2333 {
2334         return pci_register_driver(&ipg_pci_driver);
2335 }
2336
2337 static void __exit ipg_exit_module(void)
2338 {
2339         pci_unregister_driver(&ipg_pci_driver);
2340 }
2341
2342 module_init(ipg_init_module);
2343 module_exit(ipg_exit_module);