1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/power.h>
13 #include <asm/system.h>
15 #include <asm/syscalls.h>
17 #include <asm/uaccess.h>
20 unsigned long idle_halt;
21 EXPORT_SYMBOL(idle_halt);
22 unsigned long idle_nomwait;
23 EXPORT_SYMBOL(idle_nomwait);
25 struct kmem_cache *task_xstate_cachep;
27 DEFINE_TRACE(power_start);
28 DEFINE_TRACE(power_end);
30 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
33 if (src->thread.xstate) {
34 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
36 if (!dst->thread.xstate)
38 WARN_ON((unsigned long)dst->thread.xstate & 15);
39 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
44 void free_thread_xstate(struct task_struct *tsk)
46 if (tsk->thread.xstate) {
47 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
48 tsk->thread.xstate = NULL;
52 void free_thread_info(struct thread_info *ti)
54 free_thread_xstate(ti->task);
55 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
58 void arch_task_cache_init(void)
61 kmem_cache_create("task_xstate", xstate_size,
62 __alignof__(union thread_xstate),
67 * Free current thread data structures etc..
69 void exit_thread(void)
71 struct task_struct *me = current;
72 struct thread_struct *t = &me->thread;
73 unsigned long *bp = t->io_bitmap_ptr;
76 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
78 t->io_bitmap_ptr = NULL;
79 clear_thread_flag(TIF_IO_BITMAP);
81 * Careful, clear this in the TSS too:
83 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
89 ds_exit_thread(current);
92 void flush_thread(void)
94 struct task_struct *tsk = current;
97 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
98 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
99 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
100 clear_tsk_thread_flag(tsk, TIF_IA32);
102 set_tsk_thread_flag(tsk, TIF_IA32);
103 current_thread_info()->status |= TS_COMPAT;
108 clear_tsk_thread_flag(tsk, TIF_DEBUG);
110 tsk->thread.debugreg0 = 0;
111 tsk->thread.debugreg1 = 0;
112 tsk->thread.debugreg2 = 0;
113 tsk->thread.debugreg3 = 0;
114 tsk->thread.debugreg6 = 0;
115 tsk->thread.debugreg7 = 0;
116 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
118 * Forget coprocessor state..
120 tsk->fpu_counter = 0;
125 static void hard_disable_TSC(void)
127 write_cr4(read_cr4() | X86_CR4_TSD);
130 void disable_TSC(void)
133 if (!test_and_set_thread_flag(TIF_NOTSC))
135 * Must flip the CPU state synchronously with
136 * TIF_NOTSC in the current running context.
142 static void hard_enable_TSC(void)
144 write_cr4(read_cr4() & ~X86_CR4_TSD);
147 static void enable_TSC(void)
150 if (test_and_clear_thread_flag(TIF_NOTSC))
152 * Must flip the CPU state synchronously with
153 * TIF_NOTSC in the current running context.
159 int get_tsc_mode(unsigned long adr)
163 if (test_thread_flag(TIF_NOTSC))
164 val = PR_TSC_SIGSEGV;
168 return put_user(val, (unsigned int __user *)adr);
171 int set_tsc_mode(unsigned int val)
173 if (val == PR_TSC_SIGSEGV)
175 else if (val == PR_TSC_ENABLE)
183 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
184 struct tss_struct *tss)
186 struct thread_struct *prev, *next;
188 prev = &prev_p->thread;
189 next = &next_p->thread;
191 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
192 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
193 ds_switch_to(prev_p, next_p);
194 else if (next->debugctlmsr != prev->debugctlmsr)
195 update_debugctlmsr(next->debugctlmsr);
197 if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
198 set_debugreg(next->debugreg0, 0);
199 set_debugreg(next->debugreg1, 1);
200 set_debugreg(next->debugreg2, 2);
201 set_debugreg(next->debugreg3, 3);
203 set_debugreg(next->debugreg6, 6);
204 set_debugreg(next->debugreg7, 7);
207 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
208 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
209 /* prev and next are different */
210 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
216 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
218 * Copy the relevant range of the IO bitmap.
219 * Normally this is 128 bytes or less:
221 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
222 max(prev->io_bitmap_max, next->io_bitmap_max));
223 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
225 * Clear any possible leftover bits:
227 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
231 int sys_fork(struct pt_regs *regs)
233 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
237 * This is trivial, and on the face of it looks like it
238 * could equally well be done in user mode.
240 * Not so, for quite unobvious reasons - register pressure.
241 * In user mode vfork() cannot have a stack frame, and if
242 * done by calling the "clone()" system call directly, you
243 * do not have enough call-clobbered registers to hold all
244 * the information you need.
246 int sys_vfork(struct pt_regs *regs)
248 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
254 * Idle related variables and functions
256 unsigned long boot_option_idle_override = 0;
257 EXPORT_SYMBOL(boot_option_idle_override);
260 * Powermanagement idle function, if any..
262 void (*pm_idle)(void);
263 EXPORT_SYMBOL(pm_idle);
267 * This halt magic was a workaround for ancient floppy DMA
268 * wreckage. It should be safe to remove.
270 static int hlt_counter;
271 void disable_hlt(void)
275 EXPORT_SYMBOL(disable_hlt);
277 void enable_hlt(void)
281 EXPORT_SYMBOL(enable_hlt);
283 static inline int hlt_use_halt(void)
285 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
288 static inline int hlt_use_halt(void)
295 * We use this if we don't have any better
298 void default_idle(void)
300 if (hlt_use_halt()) {
301 struct power_trace it;
303 trace_power_start(&it, POWER_CSTATE, 1);
304 current_thread_info()->status &= ~TS_POLLING;
306 * TS_POLLING-cleared state must be visible before we
312 safe_halt(); /* enables interrupts racelessly */
315 current_thread_info()->status |= TS_POLLING;
316 trace_power_end(&it);
319 /* loop is done by the caller */
323 #ifdef CONFIG_APM_MODULE
324 EXPORT_SYMBOL(default_idle);
327 void stop_this_cpu(void *dummy)
333 set_cpu_online(smp_processor_id(), false);
334 disable_local_APIC();
337 if (hlt_works(smp_processor_id()))
342 static void do_nothing(void *unused)
347 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
348 * pm_idle and update to new pm_idle value. Required while changing pm_idle
349 * handler on SMP systems.
351 * Caller must have changed pm_idle to the new value before the call. Old
352 * pm_idle value will not be used by any CPU after the return of this function.
354 void cpu_idle_wait(void)
357 /* kick all the CPUs so that they exit out of pm_idle */
358 smp_call_function(do_nothing, NULL, 1);
360 EXPORT_SYMBOL_GPL(cpu_idle_wait);
363 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
364 * which can obviate IPI to trigger checking of need_resched.
365 * We execute MONITOR against need_resched and enter optimized wait state
366 * through MWAIT. Whenever someone changes need_resched, we would be woken
367 * up from MWAIT (without an IPI).
369 * New with Core Duo processors, MWAIT can take some hints based on CPU
372 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
374 struct power_trace it;
376 trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
377 if (!need_resched()) {
378 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
379 clflush((void *)¤t_thread_info()->flags);
381 __monitor((void *)¤t_thread_info()->flags, 0, 0);
386 trace_power_end(&it);
389 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
390 static void mwait_idle(void)
392 struct power_trace it;
393 if (!need_resched()) {
394 trace_power_start(&it, POWER_CSTATE, 1);
395 if (cpu_has(¤t_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
396 clflush((void *)¤t_thread_info()->flags);
398 __monitor((void *)¤t_thread_info()->flags, 0, 0);
404 trace_power_end(&it);
410 * On SMP it's slightly faster (but much more power-consuming!)
411 * to poll the ->work.need_resched flag instead of waiting for the
412 * cross-CPU IPI to arrive. Use this option with caution.
414 static void poll_idle(void)
416 struct power_trace it;
418 trace_power_start(&it, POWER_CSTATE, 0);
420 while (!need_resched())
422 trace_power_end(&it);
426 * mwait selection logic:
428 * It depends on the CPU. For AMD CPUs that support MWAIT this is
429 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
430 * then depend on a clock divisor and current Pstate of the core. If
431 * all cores of a processor are in halt state (C1) the processor can
432 * enter the C1E (C1 enhanced) state. If mwait is used this will never
435 * idle=mwait overrides this decision and forces the usage of mwait.
437 static int __cpuinitdata force_mwait;
439 #define MWAIT_INFO 0x05
440 #define MWAIT_ECX_EXTENDED_INFO 0x01
441 #define MWAIT_EDX_C1 0xf0
443 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
445 u32 eax, ebx, ecx, edx;
450 if (c->cpuid_level < MWAIT_INFO)
453 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
454 /* Check, whether EDX has extended info about MWAIT */
455 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
459 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
462 return (edx & MWAIT_EDX_C1);
466 * Check for AMD CPUs, which have potentially C1E support
468 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
470 if (c->x86_vendor != X86_VENDOR_AMD)
476 /* Family 0x0f models < rev F do not have C1E */
477 if (c->x86 == 0x0f && c->x86_model < 0x40)
483 static cpumask_var_t c1e_mask;
484 static int c1e_detected;
486 void c1e_remove_cpu(int cpu)
488 if (c1e_mask != NULL)
489 cpumask_clear_cpu(cpu, c1e_mask);
493 * C1E aware idle routine. We check for C1E active in the interrupt
494 * pending message MSR. If we detect C1E, then we handle it the same
495 * way as C3 power states (local apic timer and TSC stop)
497 static void c1e_idle(void)
505 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
506 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
508 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
509 mark_tsc_unstable("TSC halt in AMD C1E");
510 printk(KERN_INFO "System has AMD C1E enabled\n");
511 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
516 int cpu = smp_processor_id();
518 if (!cpumask_test_cpu(cpu, c1e_mask)) {
519 cpumask_set_cpu(cpu, c1e_mask);
521 * Force broadcast so ACPI can not interfere. Needs
522 * to run with interrupts enabled as it uses
526 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
528 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
532 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
537 * The switch back from broadcast mode needs to be
538 * called with interrupts disabled.
541 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
547 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
550 if (pm_idle == poll_idle && smp_num_siblings > 1) {
551 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
552 " performance may degrade.\n");
558 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
560 * One CPU supports mwait => All CPUs supports mwait
562 printk(KERN_INFO "using mwait in idle threads.\n");
563 pm_idle = mwait_idle;
564 } else if (check_c1e_idle(c)) {
565 printk(KERN_INFO "using C1E aware idle routine\n");
568 pm_idle = default_idle;
571 void __init init_c1e_mask(void)
573 /* If we're using c1e_idle, we need to allocate c1e_mask. */
574 if (pm_idle == c1e_idle) {
575 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
576 cpumask_clear(c1e_mask);
580 static int __init idle_setup(char *str)
585 if (!strcmp(str, "poll")) {
586 printk("using polling idle threads.\n");
588 } else if (!strcmp(str, "mwait"))
590 else if (!strcmp(str, "halt")) {
592 * When the boot option of idle=halt is added, halt is
593 * forced to be used for CPU idle. In such case CPU C2/C3
594 * won't be used again.
595 * To continue to load the CPU idle driver, don't touch
596 * the boot_option_idle_override.
598 pm_idle = default_idle;
601 } else if (!strcmp(str, "nomwait")) {
603 * If the boot option of "idle=nomwait" is added,
604 * it means that mwait will be disabled for CPU C2/C3
605 * states. In such case it won't touch the variable
606 * of boot_option_idle_override.
613 boot_option_idle_override = 1;
616 early_param("idle", idle_setup);
618 unsigned long arch_align_stack(unsigned long sp)
620 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
621 sp -= get_random_int() % 8192;
625 unsigned long arch_randomize_brk(struct mm_struct *mm)
627 unsigned long range_end = mm->brk + 0x02000000;
628 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;