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   1 /*
   2  * linux/arch/arm/mach-omap1/mcbsp.c
   3  *
   4  * Copyright (C) 2008 Instituto Nokia de Tecnologia
   5  * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Multichannel mode not supported.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/platform_device.h>
  19
  20 #include <mach/irqs.h>
  21 #include <mach/dma.h>
  22 #include <mach/irqs.h>
  23 #include <mach/mux.h>
  24 #include <mach/cpu.h>
  25 #include <mach/mcbsp.h>
  26 #include <mach/dsp_common.h>
  27
  28 #define DPS_RSTCT2_PER_EN       (1 << 0)
  29 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
  30
  31 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  32 const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
  33 #endif
  34
  35 static void omap1_mcbsp_request(unsigned int id)
  36 {
  37         /*
  38          * On 1510, 1610 and 1710, McBSP1 and McBSP3
  39          * are DSP public peripherals.
  40          */
  41         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
  42                 omap_dsp_request_mem();
  43                 /*
  44                  * DSP external peripheral reset
  45                  * FIXME: This should be moved to dsp code
  46                  */
  47                 __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
  48                                 DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
  49         }
  50 }
  51
  52 static void omap1_mcbsp_free(unsigned int id)
  53 {
  54         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
  55                 omap_dsp_release_mem();
  56 }
  57
  58 static struct omap_mcbsp_ops omap1_mcbsp_ops = {
  59         .request        = omap1_mcbsp_request,
  60         .free           = omap1_mcbsp_free,
  61 };
  62
  63 #ifdef CONFIG_ARCH_OMAP730
  64 static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
  65         {
  66                 .phys_base      = OMAP730_MCBSP1_BASE,
  67                 .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
  68                 .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
  69                 .rx_irq         = INT_730_McBSP1RX,
  70                 .tx_irq         = INT_730_McBSP1TX,
  71                 .ops            = &omap1_mcbsp_ops,
  72         },
  73         {
  74                 .phys_base      = OMAP730_MCBSP2_BASE,
  75                 .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
  76                 .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
  77                 .rx_irq         = INT_730_McBSP2RX,
  78                 .tx_irq         = INT_730_McBSP2TX,
  79                 .ops            = &omap1_mcbsp_ops,
  80         },
  81 };
  82 #define OMAP730_MCBSP_PDATA_SZ          ARRAY_SIZE(omap730_mcbsp_pdata)
  83 #else
  84 #define omap730_mcbsp_pdata             NULL
  85 #define OMAP730_MCBSP_PDATA_SZ          0
  86 #endif
  87
  88 #ifdef CONFIG_ARCH_OMAP15XX
  89 static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
  90         {
  91                 .phys_base      = OMAP1510_MCBSP1_BASE,
  92                 .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
  93                 .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
  94                 .rx_irq         = INT_McBSP1RX,
  95                 .tx_irq         = INT_McBSP1TX,
  96                 .ops            = &omap1_mcbsp_ops,
  97                 .clk_names      = clk_names,
  98                 .num_clks       = 3,
  99         },
 100         {
 101                 .phys_base      = OMAP1510_MCBSP2_BASE,
 102                 .dma_rx_sync    = OMAP_DMA_MCBSP2_RX,
 103                 .dma_tx_sync    = OMAP_DMA_MCBSP2_TX,
 104                 .rx_irq         = INT_1510_SPI_RX,
 105                 .tx_irq         = INT_1510_SPI_TX,
 106                 .ops            = &omap1_mcbsp_ops,
 107         },
 108         {
 109                 .phys_base      = OMAP1510_MCBSP3_BASE,
 110                 .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
 111                 .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
 112                 .rx_irq         = INT_McBSP3RX,
 113                 .tx_irq         = INT_McBSP3TX,
 114                 .ops            = &omap1_mcbsp_ops,
 115                 .clk_names      = clk_names,
 116                 .num_clks       = 3,
 117         },
 118 };
 119 #define OMAP15XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap15xx_mcbsp_pdata)
 120 #else
 121 #define omap15xx_mcbsp_pdata            NULL
 122 #define OMAP15XX_MCBSP_PDATA_SZ         0
 123 #endif
 124
 125 #ifdef CONFIG_ARCH_OMAP16XX
 126 static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
 127         {
 128                 .phys_base      = OMAP1610_MCBSP1_BASE,
 129                 .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
 130                 .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
 131                 .rx_irq         = INT_McBSP1RX,
 132                 .tx_irq         = INT_McBSP1TX,
 133                 .ops            = &omap1_mcbsp_ops,
 134                 .clk_names      = clk_names,
 135                 .num_clks       = 3,
 136         },
 137         {
 138                 .phys_base      = OMAP1610_MCBSP2_BASE,
 139                 .dma_rx_sync    = OMAP_DMA_MCBSP2_RX,
 140                 .dma_tx_sync    = OMAP_DMA_MCBSP2_TX,
 141                 .rx_irq         = INT_1610_McBSP2_RX,
 142                 .tx_irq         = INT_1610_McBSP2_TX,
 143                 .ops            = &omap1_mcbsp_ops,
 144         },
 145         {
 146                 .phys_base      = OMAP1610_MCBSP3_BASE,
 147                 .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
 148                 .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
 149                 .rx_irq         = INT_McBSP3RX,
 150                 .tx_irq         = INT_McBSP3TX,
 151                 .ops            = &omap1_mcbsp_ops,
 152                 .clk_names      = clk_names,
 153                 .num_clks       = 3,
 154         },
 155 };
 156 #define OMAP16XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap16xx_mcbsp_pdata)
 157 #else
 158 #define omap16xx_mcbsp_pdata            NULL
 159 #define OMAP16XX_MCBSP_PDATA_SZ         0
 160 #endif
 161
 162 int __init omap1_mcbsp_init(void)
 163 {
 164         if (cpu_is_omap730())
 165                 omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ;
 166         if (cpu_is_omap15xx())
 167                 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
 168         if (cpu_is_omap16xx())
 169                 omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
 170
 171         mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
 172                                                                 GFP_KERNEL);
 173         if (!mcbsp_ptr)
 174                 return -ENOMEM;
 175
 176         if (cpu_is_omap730())
 177                 omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
 178                                                 OMAP730_MCBSP_PDATA_SZ);
 179
 180         if (cpu_is_omap15xx())
 181                 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
 182                                                 OMAP15XX_MCBSP_PDATA_SZ);
 183
 184         if (cpu_is_omap16xx())
 185                 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
 186                                                 OMAP16XX_MCBSP_PDATA_SZ);
 187
 188         return omap_mcbsp_init();
 189 }
 190
 191 arch_initcall(omap1_mcbsp_init);