Merge branch 'drm-patches' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[linux-2.6] / arch / x86_64 / kernel / nmi.c
1 /*
2  *  linux/arch/x86_64/nmi.c
3  *
4  *  NMI watchdog support on APIC systems
5  *
6  *  Started by Ingo Molnar <mingo@redhat.com>
7  *
8  *  Fixes:
9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
11  *  Pavel Machek and
12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
13  */
14
15 #include <linux/mm.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/sysdev.h>
20 #include <linux/nmi.h>
21 #include <linux/sysctl.h>
22 #include <linux/kprobes.h>
23
24 #include <asm/smp.h>
25 #include <asm/nmi.h>
26 #include <asm/proto.h>
27 #include <asm/kdebug.h>
28 #include <asm/mce.h>
29 #include <asm/intel_arch_perfmon.h>
30
31 int unknown_nmi_panic;
32 int nmi_watchdog_enabled;
33 int panic_on_unrecovered_nmi;
34
35 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
36  * evtsel_nmi_owner tracks the ownership of the event selection
37  * - different performance counters/ event selection may be reserved for
38  *   different subsystems this reservation system just tries to coordinate
39  *   things a little
40  */
41 static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
42 static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
43
44 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
45  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
46  */
47 #define NMI_MAX_COUNTER_BITS 66
48
49 /* nmi_active:
50  * >0: the lapic NMI watchdog is active, but can be disabled
51  * <0: the lapic NMI watchdog has not been set up, and cannot
52  *     be enabled
53  *  0: the lapic NMI watchdog is disabled, but can be enabled
54  */
55 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
56 int panic_on_timeout;
57
58 unsigned int nmi_watchdog = NMI_DEFAULT;
59 static unsigned int nmi_hz = HZ;
60
61 struct nmi_watchdog_ctlblk {
62         int enabled;
63         u64 check_bit;
64         unsigned int cccr_msr;
65         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
66         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
67 };
68 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
69
70 /* local prototypes */
71 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
72
73 /* converts an msr to an appropriate reservation bit */
74 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
75 {
76         /* returns the bit offset of the performance counter register */
77         switch (boot_cpu_data.x86_vendor) {
78         case X86_VENDOR_AMD:
79                 return (msr - MSR_K7_PERFCTR0);
80         case X86_VENDOR_INTEL:
81                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
82                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
83                 else
84                         return (msr - MSR_P4_BPU_PERFCTR0);
85         }
86         return 0;
87 }
88
89 /* converts an msr to an appropriate reservation bit */
90 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
91 {
92         /* returns the bit offset of the event selection register */
93         switch (boot_cpu_data.x86_vendor) {
94         case X86_VENDOR_AMD:
95                 return (msr - MSR_K7_EVNTSEL0);
96         case X86_VENDOR_INTEL:
97                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
98                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
99                 else
100                         return (msr - MSR_P4_BSU_ESCR0);
101         }
102         return 0;
103 }
104
105 /* checks for a bit availability (hack for oprofile) */
106 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
107 {
108         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
109
110         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
111 }
112
113 /* checks the an msr for availability */
114 int avail_to_resrv_perfctr_nmi(unsigned int msr)
115 {
116         unsigned int counter;
117
118         counter = nmi_perfctr_msr_to_bit(msr);
119         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
120
121         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
122 }
123
124 int reserve_perfctr_nmi(unsigned int msr)
125 {
126         unsigned int counter;
127
128         counter = nmi_perfctr_msr_to_bit(msr);
129         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
130
131         if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
132                 return 1;
133         return 0;
134 }
135
136 void release_perfctr_nmi(unsigned int msr)
137 {
138         unsigned int counter;
139
140         counter = nmi_perfctr_msr_to_bit(msr);
141         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
142
143         clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
144 }
145
146 int reserve_evntsel_nmi(unsigned int msr)
147 {
148         unsigned int counter;
149
150         counter = nmi_evntsel_msr_to_bit(msr);
151         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
152
153         if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
154                 return 1;
155         return 0;
156 }
157
158 void release_evntsel_nmi(unsigned int msr)
159 {
160         unsigned int counter;
161
162         counter = nmi_evntsel_msr_to_bit(msr);
163         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
164
165         clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
166 }
167
168 static __cpuinit inline int nmi_known_cpu(void)
169 {
170         switch (boot_cpu_data.x86_vendor) {
171         case X86_VENDOR_AMD:
172                 return boot_cpu_data.x86 == 15;
173         case X86_VENDOR_INTEL:
174                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
175                         return 1;
176                 else
177                         return (boot_cpu_data.x86 == 15);
178         }
179         return 0;
180 }
181
182 /* Run after command line and cpu_init init, but before all other checks */
183 void nmi_watchdog_default(void)
184 {
185         if (nmi_watchdog != NMI_DEFAULT)
186                 return;
187         if (nmi_known_cpu())
188                 nmi_watchdog = NMI_LOCAL_APIC;
189         else
190                 nmi_watchdog = NMI_IO_APIC;
191 }
192
193 #ifdef CONFIG_SMP
194 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
195  * the CPU is idle. To make sure the NMI watchdog really ticks on all
196  * CPUs during the test make them busy.
197  */
198 static __init void nmi_cpu_busy(void *data)
199 {
200         volatile int *endflag = data;
201         local_irq_enable_in_hardirq();
202         /* Intentionally don't use cpu_relax here. This is
203            to make sure that the performance counter really ticks,
204            even if there is a simulator or similar that catches the
205            pause instruction. On a real HT machine this is fine because
206            all other CPUs are busy with "useless" delay loops and don't
207            care if they get somewhat less cycles. */
208         while (*endflag == 0)
209                 barrier();
210 }
211 #endif
212
213 int __init check_nmi_watchdog (void)
214 {
215         volatile int endflag = 0;
216         int *counts;
217         int cpu;
218
219         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
220                 return 0;
221
222         if (!atomic_read(&nmi_active))
223                 return 0;
224
225         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
226         if (!counts)
227                 return -1;
228
229         printk(KERN_INFO "testing NMI watchdog ... ");
230
231 #ifdef CONFIG_SMP
232         if (nmi_watchdog == NMI_LOCAL_APIC)
233                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
234 #endif
235
236         for (cpu = 0; cpu < NR_CPUS; cpu++)
237                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
238         local_irq_enable();
239         mdelay((10*1000)/nmi_hz); // wait 10 ticks
240
241         for_each_online_cpu(cpu) {
242                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
243                         continue;
244                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
245                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
246                                cpu,
247                                counts[cpu],
248                                cpu_pda(cpu)->__nmi_count);
249                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
250                         atomic_dec(&nmi_active);
251                 }
252         }
253         if (!atomic_read(&nmi_active)) {
254                 kfree(counts);
255                 atomic_set(&nmi_active, -1);
256                 return -1;
257         }
258         endflag = 1;
259         printk("OK.\n");
260
261         /* now that we know it works we can reduce NMI frequency to
262            something more reasonable; makes a difference in some configs */
263         if (nmi_watchdog == NMI_LOCAL_APIC) {
264                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
265
266                 nmi_hz = 1;
267                 /*
268                  * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
269                  * are writable, with higher bits sign extending from bit 31.
270                  * So, we can only program the counter with 31 bit values and
271                  * 32nd bit should be 1, for 33.. to be 1.
272                  * Find the appropriate nmi_hz
273                  */
274                 if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0 &&
275                         ((u64)cpu_khz * 1000) > 0x7fffffffULL) {
276                         nmi_hz = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
277                 }
278         }
279
280         kfree(counts);
281         return 0;
282 }
283
284 int __init setup_nmi_watchdog(char *str)
285 {
286         int nmi;
287
288         if (!strncmp(str,"panic",5)) {
289                 panic_on_timeout = 1;
290                 str = strchr(str, ',');
291                 if (!str)
292                         return 1;
293                 ++str;
294         }
295
296         get_option(&str, &nmi);
297
298         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
299                 return 0;
300
301         if ((nmi == NMI_LOCAL_APIC) && (nmi_known_cpu() == 0))
302                 return 0;  /* no lapic support */
303         nmi_watchdog = nmi;
304         return 1;
305 }
306
307 __setup("nmi_watchdog=", setup_nmi_watchdog);
308
309 static void disable_lapic_nmi_watchdog(void)
310 {
311         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
312
313         if (atomic_read(&nmi_active) <= 0)
314                 return;
315
316         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
317
318         BUG_ON(atomic_read(&nmi_active) != 0);
319 }
320
321 static void enable_lapic_nmi_watchdog(void)
322 {
323         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
324
325         /* are we already enabled */
326         if (atomic_read(&nmi_active) != 0)
327                 return;
328
329         /* are we lapic aware */
330         if (nmi_known_cpu() <= 0)
331                 return;
332
333         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
334         touch_nmi_watchdog();
335 }
336
337 void disable_timer_nmi_watchdog(void)
338 {
339         BUG_ON(nmi_watchdog != NMI_IO_APIC);
340
341         if (atomic_read(&nmi_active) <= 0)
342                 return;
343
344         disable_irq(0);
345         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
346
347         BUG_ON(atomic_read(&nmi_active) != 0);
348 }
349
350 void enable_timer_nmi_watchdog(void)
351 {
352         BUG_ON(nmi_watchdog != NMI_IO_APIC);
353
354         if (atomic_read(&nmi_active) == 0) {
355                 touch_nmi_watchdog();
356                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
357                 enable_irq(0);
358         }
359 }
360
361 #ifdef CONFIG_PM
362
363 static int nmi_pm_active; /* nmi_active before suspend */
364
365 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
366 {
367         /* only CPU0 goes here, other CPUs should be offline */
368         nmi_pm_active = atomic_read(&nmi_active);
369         stop_apic_nmi_watchdog(NULL);
370         BUG_ON(atomic_read(&nmi_active) != 0);
371         return 0;
372 }
373
374 static int lapic_nmi_resume(struct sys_device *dev)
375 {
376         /* only CPU0 goes here, other CPUs should be offline */
377         if (nmi_pm_active > 0) {
378                 setup_apic_nmi_watchdog(NULL);
379                 touch_nmi_watchdog();
380         }
381         return 0;
382 }
383
384 static struct sysdev_class nmi_sysclass = {
385         set_kset_name("lapic_nmi"),
386         .resume         = lapic_nmi_resume,
387         .suspend        = lapic_nmi_suspend,
388 };
389
390 static struct sys_device device_lapic_nmi = {
391         .id             = 0,
392         .cls    = &nmi_sysclass,
393 };
394
395 static int __init init_lapic_nmi_sysfs(void)
396 {
397         int error;
398
399         /* should really be a BUG_ON but b/c this is an
400          * init call, it just doesn't work.  -dcz
401          */
402         if (nmi_watchdog != NMI_LOCAL_APIC)
403                 return 0;
404
405         if ( atomic_read(&nmi_active) < 0 )
406                 return 0;
407
408         error = sysdev_class_register(&nmi_sysclass);
409         if (!error)
410                 error = sysdev_register(&device_lapic_nmi);
411         return error;
412 }
413 /* must come after the local APIC's device_initcall() */
414 late_initcall(init_lapic_nmi_sysfs);
415
416 #endif  /* CONFIG_PM */
417
418 /*
419  * Activate the NMI watchdog via the local APIC.
420  * Original code written by Keith Owens.
421  */
422
423 /* Note that these events don't tick when the CPU idles. This means
424    the frequency varies with CPU load. */
425
426 #define K7_EVNTSEL_ENABLE       (1 << 22)
427 #define K7_EVNTSEL_INT          (1 << 20)
428 #define K7_EVNTSEL_OS           (1 << 17)
429 #define K7_EVNTSEL_USR          (1 << 16)
430 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
431 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
432
433 static int setup_k7_watchdog(void)
434 {
435         unsigned int perfctr_msr, evntsel_msr;
436         unsigned int evntsel;
437         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
438
439         perfctr_msr = MSR_K7_PERFCTR0;
440         evntsel_msr = MSR_K7_EVNTSEL0;
441         if (!reserve_perfctr_nmi(perfctr_msr))
442                 goto fail;
443
444         if (!reserve_evntsel_nmi(evntsel_msr))
445                 goto fail1;
446
447         /* Simulator may not support it */
448         if (checking_wrmsrl(evntsel_msr, 0UL))
449                 goto fail2;
450         wrmsrl(perfctr_msr, 0UL);
451
452         evntsel = K7_EVNTSEL_INT
453                 | K7_EVNTSEL_OS
454                 | K7_EVNTSEL_USR
455                 | K7_NMI_EVENT;
456
457         /* setup the timer */
458         wrmsr(evntsel_msr, evntsel, 0);
459         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
460         apic_write(APIC_LVTPC, APIC_DM_NMI);
461         evntsel |= K7_EVNTSEL_ENABLE;
462         wrmsr(evntsel_msr, evntsel, 0);
463
464         wd->perfctr_msr = perfctr_msr;
465         wd->evntsel_msr = evntsel_msr;
466         wd->cccr_msr = 0;  //unused
467         wd->check_bit = 1ULL<<63;
468         return 1;
469 fail2:
470         release_evntsel_nmi(evntsel_msr);
471 fail1:
472         release_perfctr_nmi(perfctr_msr);
473 fail:
474         return 0;
475 }
476
477 static void stop_k7_watchdog(void)
478 {
479         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
480
481         wrmsr(wd->evntsel_msr, 0, 0);
482
483         release_evntsel_nmi(wd->evntsel_msr);
484         release_perfctr_nmi(wd->perfctr_msr);
485 }
486
487 /* Note that these events don't tick when the CPU idles. This means
488    the frequency varies with CPU load. */
489
490 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
491 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
492 #define P4_ESCR_OS              (1<<3)
493 #define P4_ESCR_USR             (1<<2)
494 #define P4_CCCR_OVF_PMI0        (1<<26)
495 #define P4_CCCR_OVF_PMI1        (1<<27)
496 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
497 #define P4_CCCR_COMPLEMENT      (1<<19)
498 #define P4_CCCR_COMPARE         (1<<18)
499 #define P4_CCCR_REQUIRED        (3<<16)
500 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
501 #define P4_CCCR_ENABLE          (1<<12)
502 #define P4_CCCR_OVF             (1<<31)
503 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
504    CRU_ESCR0 (with any non-null event selector) through a complemented
505    max threshold. [IA32-Vol3, Section 14.9.9] */
506
507 static int setup_p4_watchdog(void)
508 {
509         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
510         unsigned int evntsel, cccr_val;
511         unsigned int misc_enable, dummy;
512         unsigned int ht_num;
513         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
514
515         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
516         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
517                 return 0;
518
519 #ifdef CONFIG_SMP
520         /* detect which hyperthread we are on */
521         if (smp_num_siblings == 2) {
522                 unsigned int ebx, apicid;
523
524                 ebx = cpuid_ebx(1);
525                 apicid = (ebx >> 24) & 0xff;
526                 ht_num = apicid & 1;
527         } else
528 #endif
529                 ht_num = 0;
530
531         /* performance counters are shared resources
532          * assign each hyperthread its own set
533          * (re-use the ESCR0 register, seems safe
534          * and keeps the cccr_val the same)
535          */
536         if (!ht_num) {
537                 /* logical cpu 0 */
538                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
539                 evntsel_msr = MSR_P4_CRU_ESCR0;
540                 cccr_msr = MSR_P4_IQ_CCCR0;
541                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
542         } else {
543                 /* logical cpu 1 */
544                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
545                 evntsel_msr = MSR_P4_CRU_ESCR0;
546                 cccr_msr = MSR_P4_IQ_CCCR1;
547                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
548         }
549
550         if (!reserve_perfctr_nmi(perfctr_msr))
551                 goto fail;
552
553         if (!reserve_evntsel_nmi(evntsel_msr))
554                 goto fail1;
555
556         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
557                 | P4_ESCR_OS
558                 | P4_ESCR_USR;
559
560         cccr_val |= P4_CCCR_THRESHOLD(15)
561                  | P4_CCCR_COMPLEMENT
562                  | P4_CCCR_COMPARE
563                  | P4_CCCR_REQUIRED;
564
565         wrmsr(evntsel_msr, evntsel, 0);
566         wrmsr(cccr_msr, cccr_val, 0);
567         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
568         apic_write(APIC_LVTPC, APIC_DM_NMI);
569         cccr_val |= P4_CCCR_ENABLE;
570         wrmsr(cccr_msr, cccr_val, 0);
571
572         wd->perfctr_msr = perfctr_msr;
573         wd->evntsel_msr = evntsel_msr;
574         wd->cccr_msr = cccr_msr;
575         wd->check_bit = 1ULL<<39;
576         return 1;
577 fail1:
578         release_perfctr_nmi(perfctr_msr);
579 fail:
580         return 0;
581 }
582
583 static void stop_p4_watchdog(void)
584 {
585         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
586
587         wrmsr(wd->cccr_msr, 0, 0);
588         wrmsr(wd->evntsel_msr, 0, 0);
589
590         release_evntsel_nmi(wd->evntsel_msr);
591         release_perfctr_nmi(wd->perfctr_msr);
592 }
593
594 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
595 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
596
597 static int setup_intel_arch_watchdog(void)
598 {
599         unsigned int ebx;
600         union cpuid10_eax eax;
601         unsigned int unused;
602         unsigned int perfctr_msr, evntsel_msr;
603         unsigned int evntsel;
604         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
605
606         /*
607          * Check whether the Architectural PerfMon supports
608          * Unhalted Core Cycles Event or not.
609          * NOTE: Corresponding bit = 0 in ebx indicates event present.
610          */
611         cpuid(10, &(eax.full), &ebx, &unused, &unused);
612         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
613             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
614                 goto fail;
615
616         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
617         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
618
619         if (!reserve_perfctr_nmi(perfctr_msr))
620                 goto fail;
621
622         if (!reserve_evntsel_nmi(evntsel_msr))
623                 goto fail1;
624
625         wrmsrl(perfctr_msr, 0UL);
626
627         evntsel = ARCH_PERFMON_EVENTSEL_INT
628                 | ARCH_PERFMON_EVENTSEL_OS
629                 | ARCH_PERFMON_EVENTSEL_USR
630                 | ARCH_PERFMON_NMI_EVENT_SEL
631                 | ARCH_PERFMON_NMI_EVENT_UMASK;
632
633         /* setup the timer */
634         wrmsr(evntsel_msr, evntsel, 0);
635         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
636
637         apic_write(APIC_LVTPC, APIC_DM_NMI);
638         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
639         wrmsr(evntsel_msr, evntsel, 0);
640
641         wd->perfctr_msr = perfctr_msr;
642         wd->evntsel_msr = evntsel_msr;
643         wd->cccr_msr = 0;  //unused
644         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
645         return 1;
646 fail1:
647         release_perfctr_nmi(perfctr_msr);
648 fail:
649         return 0;
650 }
651
652 static void stop_intel_arch_watchdog(void)
653 {
654         unsigned int ebx;
655         union cpuid10_eax eax;
656         unsigned int unused;
657         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
658
659         /*
660          * Check whether the Architectural PerfMon supports
661          * Unhalted Core Cycles Event or not.
662          * NOTE: Corresponding bit = 0 in ebx indicates event present.
663          */
664         cpuid(10, &(eax.full), &ebx, &unused, &unused);
665         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
666             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
667                 return;
668
669         wrmsr(wd->evntsel_msr, 0, 0);
670
671         release_evntsel_nmi(wd->evntsel_msr);
672         release_perfctr_nmi(wd->perfctr_msr);
673 }
674
675 void setup_apic_nmi_watchdog(void *unused)
676 {
677         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
678
679         /* only support LOCAL and IO APICs for now */
680         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
681             (nmi_watchdog != NMI_IO_APIC))
682                 return;
683
684         if (wd->enabled == 1)
685                 return;
686
687         /* cheap hack to support suspend/resume */
688         /* if cpu0 is not active neither should the other cpus */
689         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
690                 return;
691
692         if (nmi_watchdog == NMI_LOCAL_APIC) {
693                 switch (boot_cpu_data.x86_vendor) {
694                 case X86_VENDOR_AMD:
695                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
696                                 return;
697                         if (!setup_k7_watchdog())
698                                 return;
699                         break;
700                 case X86_VENDOR_INTEL:
701                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
702                                 if (!setup_intel_arch_watchdog())
703                                         return;
704                                 break;
705                         }
706                         if (!setup_p4_watchdog())
707                                 return;
708                         break;
709                 default:
710                         return;
711                 }
712         }
713         wd->enabled = 1;
714         atomic_inc(&nmi_active);
715 }
716
717 void stop_apic_nmi_watchdog(void *unused)
718 {
719         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
720
721         /* only support LOCAL and IO APICs for now */
722         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
723             (nmi_watchdog != NMI_IO_APIC))
724                 return;
725
726         if (wd->enabled == 0)
727                 return;
728
729         if (nmi_watchdog == NMI_LOCAL_APIC) {
730                 switch (boot_cpu_data.x86_vendor) {
731                 case X86_VENDOR_AMD:
732                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
733                                 return;
734                         stop_k7_watchdog();
735                         break;
736                 case X86_VENDOR_INTEL:
737                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
738                                 stop_intel_arch_watchdog();
739                                 break;
740                         }
741                         stop_p4_watchdog();
742                         break;
743                 default:
744                         return;
745                 }
746         }
747         wd->enabled = 0;
748         atomic_dec(&nmi_active);
749 }
750
751 /*
752  * the best way to detect whether a CPU has a 'hard lockup' problem
753  * is to check it's local APIC timer IRQ counts. If they are not
754  * changing then that CPU has some problem.
755  *
756  * as these watchdog NMI IRQs are generated on every CPU, we only
757  * have to check the current processor.
758  */
759
760 static DEFINE_PER_CPU(unsigned, last_irq_sum);
761 static DEFINE_PER_CPU(local_t, alert_counter);
762 static DEFINE_PER_CPU(int, nmi_touch);
763
764 void touch_nmi_watchdog (void)
765 {
766         if (nmi_watchdog > 0) {
767                 unsigned cpu;
768
769                 /*
770                  * Tell other CPUs to reset their alert counters. We cannot
771                  * do it ourselves because the alert count increase is not
772                  * atomic.
773                  */
774                 for_each_present_cpu (cpu)
775                         per_cpu(nmi_touch, cpu) = 1;
776         }
777
778         touch_softlockup_watchdog();
779 }
780
781 int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
782 {
783         int sum;
784         int touched = 0;
785         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
786         u64 dummy;
787         int rc=0;
788
789         /* check for other users first */
790         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
791                         == NOTIFY_STOP) {
792                 rc = 1;
793                 touched = 1;
794         }
795
796         sum = read_pda(apic_timer_irqs);
797         if (__get_cpu_var(nmi_touch)) {
798                 __get_cpu_var(nmi_touch) = 0;
799                 touched = 1;
800         }
801
802 #ifdef CONFIG_X86_MCE
803         /* Could check oops_in_progress here too, but it's safer
804            not too */
805         if (atomic_read(&mce_entry) > 0)
806                 touched = 1;
807 #endif
808         /* if the apic timer isn't firing, this cpu isn't doing much */
809         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
810                 /*
811                  * Ayiee, looks like this CPU is stuck ...
812                  * wait a few IRQs (5 seconds) before doing the oops ...
813                  */
814                 local_inc(&__get_cpu_var(alert_counter));
815                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
816                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
817                                 panic_on_timeout);
818         } else {
819                 __get_cpu_var(last_irq_sum) = sum;
820                 local_set(&__get_cpu_var(alert_counter), 0);
821         }
822
823         /* see if the nmi watchdog went off */
824         if (wd->enabled) {
825                 if (nmi_watchdog == NMI_LOCAL_APIC) {
826                         rdmsrl(wd->perfctr_msr, dummy);
827                         if (dummy & wd->check_bit){
828                                 /* this wasn't a watchdog timer interrupt */
829                                 goto done;
830                         }
831
832                         /* only Intel uses the cccr msr */
833                         if (wd->cccr_msr != 0) {
834                                 /*
835                                  * P4 quirks:
836                                  * - An overflown perfctr will assert its interrupt
837                                  *   until the OVF flag in its CCCR is cleared.
838                                  * - LVTPC is masked on interrupt and must be
839                                  *   unmasked by the LVTPC handler.
840                                  */
841                                 rdmsrl(wd->cccr_msr, dummy);
842                                 dummy &= ~P4_CCCR_OVF;
843                                 wrmsrl(wd->cccr_msr, dummy);
844                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
845                         } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
846                                 /*
847                                  * ArchPerfom/Core Duo needs to re-unmask
848                                  * the apic vector
849                                  */
850                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
851                         }
852                         /* start the cycle over again */
853                         wrmsrl(wd->perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
854                         rc = 1;
855                 } else  if (nmi_watchdog == NMI_IO_APIC) {
856                         /* don't know how to accurately check for this.
857                          * just assume it was a watchdog timer interrupt
858                          * This matches the old behaviour.
859                          */
860                         rc = 1;
861                 } else
862                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
863         }
864 done:
865         return rc;
866 }
867
868 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
869 {
870         nmi_enter();
871         add_pda(__nmi_count,1);
872         default_do_nmi(regs);
873         nmi_exit();
874 }
875
876 int do_nmi_callback(struct pt_regs * regs, int cpu)
877 {
878 #ifdef CONFIG_SYSCTL
879         if (unknown_nmi_panic)
880                 return unknown_nmi_panic_callback(regs, cpu);
881 #endif
882         return 0;
883 }
884
885 #ifdef CONFIG_SYSCTL
886
887 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
888 {
889         unsigned char reason = get_nmi_reason();
890         char buf[64];
891
892         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
893         die_nmi(buf, regs, 1);  /* Always panic here */
894         return 0;
895 }
896
897 /*
898  * proc handler for /proc/sys/kernel/nmi
899  */
900 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
901                         void __user *buffer, size_t *length, loff_t *ppos)
902 {
903         int old_state;
904
905         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
906         old_state = nmi_watchdog_enabled;
907         proc_dointvec(table, write, file, buffer, length, ppos);
908         if (!!old_state == !!nmi_watchdog_enabled)
909                 return 0;
910
911         if (atomic_read(&nmi_active) < 0) {
912                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
913                 return -EIO;
914         }
915
916         /* if nmi_watchdog is not set yet, then set it */
917         nmi_watchdog_default();
918
919         if (nmi_watchdog == NMI_LOCAL_APIC) {
920                 if (nmi_watchdog_enabled)
921                         enable_lapic_nmi_watchdog();
922                 else
923                         disable_lapic_nmi_watchdog();
924         } else {
925                 printk( KERN_WARNING
926                         "NMI watchdog doesn't know what hardware to touch\n");
927                 return -EIO;
928         }
929         return 0;
930 }
931
932 #endif
933
934 EXPORT_SYMBOL(nmi_active);
935 EXPORT_SYMBOL(nmi_watchdog);
936 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
937 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
938 EXPORT_SYMBOL(reserve_perfctr_nmi);
939 EXPORT_SYMBOL(release_perfctr_nmi);
940 EXPORT_SYMBOL(reserve_evntsel_nmi);
941 EXPORT_SYMBOL(release_evntsel_nmi);
942 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
943 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
944 EXPORT_SYMBOL(touch_nmi_watchdog);