git.oblomov.eu Git - linux-2.6/blob - arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c

   1 /*
   2  * Toshiba rbtx4927 specific setup
   3  *
   4  * Author: MontaVista Software, Inc.
   5  *         source@mvista.com
   6  *
   7  * Copyright 2001-2002 MontaVista Software Inc.
   8  *
   9  * Copyright (C) 1996, 97, 2001, 04  Ralf Baechle (ralf@linux-mips.org)
  10  * Copyright (C) 2000 RidgeRun, Inc.
  11  * Author: RidgeRun, Inc.
  12  *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  13  *
  14  * Copyright 2001 MontaVista Software Inc.
  15  * Author: jsun@mvista.com or jsun@junsun.net
  16  *
  17  * Copyright 2002 MontaVista Software Inc.
  18  * Author: Michael Pruznick, michael_pruznick@mvista.com
  19  *
  20  * Copyright (C) 2000-2001 Toshiba Corporation
  21  *
  22  * Copyright (C) 2004 MontaVista Software Inc.
  23  * Author: Manish Lachwani, mlachwani@mvista.com
  24  *
  25  *  This program is free software; you can redistribute it and/or modify it
  26  *  under the terms of the GNU General Public License as published by the
  27  *  Free Software Foundation; either version 2 of the License, or (at your
  28  *  option) any later version.
  29  *
  30  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  31  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  32  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  33  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  34  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  35  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  36  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  38  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  39  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  *  You should have received a copy of the GNU General Public License along
  42  *  with this program; if not, write to the Free Software Foundation, Inc.,
  43  *  675 Mass Ave, Cambridge, MA 02139, USA.
  44  */
  45 #include <linux/init.h>
  46 #include <linux/kernel.h>
  47 #include <linux/types.h>
  48 #include <linux/mm.h>
  49 #include <linux/swap.h>
  50 #include <linux/ioport.h>
  51 #include <linux/sched.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/pci.h>
  54 #include <linux/timex.h>
  55 #include <linux/pm.h>
  56
  57 #include <asm/bootinfo.h>
  58 #include <asm/page.h>
  59 #include <asm/io.h>
  60 #include <asm/irq.h>
  61 #include <asm/processor.h>
  62 #include <asm/ptrace.h>
  63 #include <asm/reboot.h>
  64 #include <asm/time.h>
  65 #include <linux/bootmem.h>
  66 #include <linux/blkdev.h>
  67 #ifdef CONFIG_RTC_DS1742
  68 #include <linux/ds1742rtc.h>
  69 #endif
  70 #ifdef CONFIG_TOSHIBA_FPCIB0
  71 #include <asm/tx4927/smsc_fdc37m81x.h>
  72 #endif
  73 #include <asm/tx4927/toshiba_rbtx4927.h>
  74 #ifdef CONFIG_PCI
  75 #include <asm/tx4927/tx4927_pci.h>
  76 #endif
  77 #ifdef CONFIG_BLK_DEV_IDEPCI
  78 #include <linux/hdreg.h>
  79 #include <linux/ide.h>
  80 #endif
  81 #ifdef CONFIG_SERIAL_TXX9
  82 #include <linux/tty.h>
  83 #include <linux/serial.h>
  84 #include <linux/serial_core.h>
  85 #endif
  86
  87 #undef TOSHIBA_RBTX4927_SETUP_DEBUG
  88
  89 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
  90 #define TOSHIBA_RBTX4927_SETUP_NONE        0x00000000
  91
  92 #define TOSHIBA_RBTX4927_SETUP_INFO        ( 1 <<  0 )
  93 #define TOSHIBA_RBTX4927_SETUP_WARN        ( 1 <<  1 )
  94 #define TOSHIBA_RBTX4927_SETUP_EROR        ( 1 <<  2 )
  95
  96 #define TOSHIBA_RBTX4927_SETUP_EFWFU       ( 1 <<  3 )
  97 #define TOSHIBA_RBTX4927_SETUP_SETUP       ( 1 <<  4 )
  98 #define TOSHIBA_RBTX4927_SETUP_TIME_INIT   ( 1 <<  5 )
  99 #define TOSHIBA_RBTX4927_SETUP_TIMER_SETUP ( 1 <<  6 )
 100 #define TOSHIBA_RBTX4927_SETUP_PCIBIOS     ( 1 <<  7 )
 101 #define TOSHIBA_RBTX4927_SETUP_PCI1        ( 1 <<  8 )
 102 #define TOSHIBA_RBTX4927_SETUP_PCI2        ( 1 <<  9 )
 103 #define TOSHIBA_RBTX4927_SETUP_PCI66       ( 1 << 10 )
 104
 105 #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
 106 #endif
 107
 108 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 109 static const u32 toshiba_rbtx4927_setup_debug_flag =
 110     (TOSHIBA_RBTX4927_SETUP_NONE | TOSHIBA_RBTX4927_SETUP_INFO |
 111      TOSHIBA_RBTX4927_SETUP_WARN | TOSHIBA_RBTX4927_SETUP_EROR |
 112      TOSHIBA_RBTX4927_SETUP_EFWFU | TOSHIBA_RBTX4927_SETUP_SETUP |
 113      TOSHIBA_RBTX4927_SETUP_TIME_INIT | TOSHIBA_RBTX4927_SETUP_TIMER_SETUP
 114      | TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
 115      TOSHIBA_RBTX4927_SETUP_PCI2 | TOSHIBA_RBTX4927_SETUP_PCI66);
 116 #endif
 117
 118 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 119 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
 120         if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
 121         { \
 122            char tmp[100]; \
 123            sprintf( tmp, str ); \
 124            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
 125         }
 126 #else
 127 #define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...)
 128 #endif
 129
 130 /* These functions are used for rebooting or halting the machine*/
 131 extern void toshiba_rbtx4927_restart(char *command);
 132 extern void toshiba_rbtx4927_halt(void);
 133 extern void toshiba_rbtx4927_power_off(void);
 134
 135 int tx4927_using_backplane = 0;
 136
 137 extern void gt64120_time_init(void);
 138 extern void toshiba_rbtx4927_irq_setup(void);
 139
 140 #ifdef CONFIG_PCI
 141 #define CONFIG_TX4927BUG_WORKAROUND
 142 #undef TX4927_SUPPORT_COMMAND_IO
 143 #undef  TX4927_SUPPORT_PCI_66
 144 int tx4927_cpu_clock = 100000000;       /* 100MHz */
 145 unsigned long mips_pci_io_base;
 146 unsigned long mips_pci_io_size;
 147 unsigned long mips_pci_mem_base;
 148 unsigned long mips_pci_mem_size;
 149 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
 150 unsigned long mips_pci_io_pciaddr = 0;
 151 unsigned long mips_memory_upper;
 152 static int tx4927_ccfg_toeon = 1;
 153 static int tx4927_pcic_trdyto = 0;      /* default: disabled */
 154 unsigned long tx4927_ce_base[8];
 155 void tx4927_pci_setup(void);
 156 void tx4927_reset_pci_pcic(void);
 157 int tx4927_pci66 = 0;           /* 0:auto */
 158 #endif
 159
 160 char *toshiba_name = "";
 161
 162 #ifdef CONFIG_PCI
 163 static void tx4927_pcierr_interrupt(int irq, void *dev_id,
 164                                     struct pt_regs *regs)
 165 {
 166 #ifdef CONFIG_BLK_DEV_IDEPCI
 167         /* ignore MasterAbort for ide probing... */
 168         if (irq == TX4927_IRQ_IRC_PCIERR &&
 169             ((tx4927_pcicptr->pcistatus >> 16) & 0xf900) ==
 170             PCI_STATUS_REC_MASTER_ABORT) {
 171                 tx4927_pcicptr->pcistatus =
 172                     (tx4927_pcicptr->
 173                      pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
 174                                                 << 16);
 175
 176                 return;
 177         }
 178 #endif
 179         printk("PCI error interrupt (irq 0x%x).\n", irq);
 180
 181         printk("pcistat:%04x, g2pstatus:%08lx, pcicstatus:%08lx\n",
 182                (unsigned short) (tx4927_pcicptr->pcistatus >> 16),
 183                tx4927_pcicptr->g2pstatus, tx4927_pcicptr->pcicstatus);
 184         printk("ccfg:%08lx, tear:%02lx_%08lx\n",
 185                (unsigned long) tx4927_ccfgptr->ccfg,
 186                (unsigned long) (tx4927_ccfgptr->tear >> 32),
 187                (unsigned long) tx4927_ccfgptr->tear);
 188         show_regs(regs);
 189 }
 190
 191 void __init toshiba_rbtx4927_pci_irq_init(void)
 192 {
 193         return;
 194 }
 195
 196 void tx4927_reset_pci_pcic(void)
 197 {
 198         /* Reset PCI Bus */
 199         *tx4927_pcireset_ptr = 1;
 200         /* Reset PCIC */
 201         tx4927_ccfgptr->clkctr |= TX4927_CLKCTR_PCIRST;
 202         udelay(10000);
 203         /* clear PCIC reset */
 204         tx4927_ccfgptr->clkctr &= ~TX4927_CLKCTR_PCIRST;
 205         *tx4927_pcireset_ptr = 0;
 206 }
 207 #endif /* CONFIG_PCI */
 208
 209 #ifdef CONFIG_PCI
 210 void print_pci_status(void)
 211 {
 212         printk("PCI STATUS %lx\n", tx4927_pcicptr->pcistatus);
 213         printk("PCIC STATUS %lx\n", tx4927_pcicptr->pcicstatus);
 214 }
 215
 216 extern struct pci_controller tx4927_controller;
 217
 218 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
 219                                     int top_bus, int busnr, int devfn)
 220 {
 221         static struct pci_dev dev;
 222         static struct pci_bus bus;
 223
 224         dev.sysdata = (void *)hose;
 225         dev.devfn = devfn;
 226         bus.number = busnr;
 227         bus.ops = hose->pci_ops;
 228         bus.parent = NULL;
 229         dev.bus = &bus;
 230
 231         return &dev;
 232 }
 233
 234 #define EARLY_PCI_OP(rw, size, type)                                    \
 235 static int early_##rw##_config_##size(struct pci_controller *hose,      \
 236         int top_bus, int bus, int devfn, int offset, type value)        \
 237 {                                                                       \
 238         return pci_##rw##_config_##size(                                \
 239                 fake_pci_dev(hose, top_bus, bus, devfn),                \
 240                 offset, value);                                         \
 241 }
 242
 243 EARLY_PCI_OP(read, byte, u8 *)
 244 EARLY_PCI_OP(read, word, u16 *)
 245 EARLY_PCI_OP(read, dword, u32 *)
 246 EARLY_PCI_OP(write, byte, u8)
 247 EARLY_PCI_OP(write, word, u16)
 248 EARLY_PCI_OP(write, dword, u32)
 249
 250 static int __init tx4927_pcibios_init(void)
 251 {
 252         unsigned int id;
 253         u32 pci_devfn;
 254         int devfn_start = 0;
 255         int devfn_stop = 0xff;
 256         int busno = 0; /* One bus on the Toshiba */
 257         struct pci_controller *hose = &tx4927_controller;
 258
 259         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 260                                        "-\n");
 261
 262         for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
 263                 early_read_config_dword(hose, busno, busno, pci_devfn,
 264                                         PCI_VENDOR_ID, &id);
 265
 266                 if (id == 0xffffffff) {
 267                         continue;
 268                 }
 269
 270                 if (id == 0x94601055) {
 271                         u8 v08_64;
 272                         u32 v32_b0;
 273                         u8 v08_e1;
 274                         char *s = " sb/isa --";
 275
 276                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 277                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 278                              s);
 279
 280                         early_read_config_byte(hose, busno, busno,
 281                                                pci_devfn, 0x64, &v08_64);
 282                         early_read_config_dword(hose, busno, busno,
 283                                                 pci_devfn, 0xb0, &v32_b0);
 284                         early_read_config_byte(hose, busno, busno,
 285                                                pci_devfn, 0xe1, &v08_e1);
 286
 287                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 288                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 289                              ":%s beg 0x64 = 0x%02x\n", s, v08_64);
 290                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 291                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 292                              ":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
 293                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 294                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 295                              ":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
 296
 297                         /* serial irq control */
 298                         v08_64 = 0xd0;
 299
 300                         /* serial irq pin */
 301                         v32_b0 |= 0x00010000;
 302
 303                         /* ide irq on isa14 */
 304                         v08_e1 &= 0xf0;
 305                         v08_e1 |= 0x0d;
 306
 307                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 308                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 309                              ":%s mid 0x64 = 0x%02x\n", s, v08_64);
 310                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 311                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 312                              ":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
 313                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 314                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 315                              ":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
 316
 317                         early_write_config_byte(hose, busno, busno,
 318                                                 pci_devfn, 0x64, v08_64);
 319                         early_write_config_dword(hose, busno, busno,
 320                                                  pci_devfn, 0xb0, v32_b0);
 321                         early_write_config_byte(hose, busno, busno,
 322                                                 pci_devfn, 0xe1, v08_e1);
 323
 324 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 325                         {
 326                                 early_read_config_byte(hose, busno, busno,
 327                                                        pci_devfn, 0x64,
 328                                                        &v08_64);
 329                                 early_read_config_dword(hose, busno, busno,
 330                                                         pci_devfn, 0xb0,
 331                                                         &v32_b0);
 332                                 early_read_config_byte(hose, busno, busno,
 333                                                        pci_devfn, 0xe1,
 334                                                        &v08_e1);
 335
 336                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 337                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 338                                      ":%s end 0x64 = 0x%02x\n", s, v08_64);
 339                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 340                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 341                                      ":%s end 0xb0 = 0x%02x\n", s, v32_b0);
 342                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 343                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 344                                      ":%s end 0xe1 = 0x%02x\n", s, v08_e1);
 345                         }
 346 #endif
 347
 348                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 349                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 350                              s);
 351                 }
 352
 353                 if (id == 0x91301055) {
 354                         u8 v08_04;
 355                         u8 v08_09;
 356                         u8 v08_41;
 357                         u8 v08_43;
 358                         u8 v08_5c;
 359                         char *s = " sb/ide --";
 360
 361                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 362                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
 363                              s);
 364
 365                         early_read_config_byte(hose, busno, busno,
 366                                                pci_devfn, 0x04, &v08_04);
 367                         early_read_config_byte(hose, busno, busno,
 368                                                pci_devfn, 0x09, &v08_09);
 369                         early_read_config_byte(hose, busno, busno,
 370                                                pci_devfn, 0x41, &v08_41);
 371                         early_read_config_byte(hose, busno, busno,
 372                                                pci_devfn, 0x43, &v08_43);
 373                         early_read_config_byte(hose, busno, busno,
 374                                                pci_devfn, 0x5c, &v08_5c);
 375
 376                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 377                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 378                              ":%s beg 0x04 = 0x%02x\n", s, v08_04);
 379                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 380                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 381                              ":%s beg 0x09 = 0x%02x\n", s, v08_09);
 382                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 383                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 384                              ":%s beg 0x41 = 0x%02x\n", s, v08_41);
 385                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 386                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 387                              ":%s beg 0x43 = 0x%02x\n", s, v08_43);
 388                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 389                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 390                              ":%s beg 0x5c = 0x%02x\n", s, v08_5c);
 391
 392                         /* enable ide master/io */
 393                         v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 394
 395                         /* enable ide native mode */
 396                         v08_09 |= 0x05;
 397
 398                         /* enable primary ide */
 399                         v08_41 |= 0x80;
 400
 401                         /* enable secondary ide */
 402                         v08_43 |= 0x80;
 403
 404                         /*
 405                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 406                          *
 407                          * This line of code is intended to provide the user with a work
 408                          * around solution to the anomalies cited in SMSC's anomaly sheet
 409                          * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
 410                          *
 411                          * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
 412                          */
 413                         v08_5c |= 0x01;
 414
 415                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 416                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 417                              ":%s mid 0x04 = 0x%02x\n", s, v08_04);
 418                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 419                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 420                              ":%s mid 0x09 = 0x%02x\n", s, v08_09);
 421                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 422                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 423                              ":%s mid 0x41 = 0x%02x\n", s, v08_41);
 424                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 425                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 426                              ":%s mid 0x43 = 0x%02x\n", s, v08_43);
 427                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 428                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 429                              ":%s mid 0x5c = 0x%02x\n", s, v08_5c);
 430
 431                         early_write_config_byte(hose, busno, busno,
 432                                                 pci_devfn, 0x5c, v08_5c);
 433                         early_write_config_byte(hose, busno, busno,
 434                                                 pci_devfn, 0x04, v08_04);
 435                         early_write_config_byte(hose, busno, busno,
 436                                                 pci_devfn, 0x09, v08_09);
 437                         early_write_config_byte(hose, busno, busno,
 438                                                 pci_devfn, 0x41, v08_41);
 439                         early_write_config_byte(hose, busno, busno,
 440                                                 pci_devfn, 0x43, v08_43);
 441
 442 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 443                         {
 444                                 early_read_config_byte(hose, busno, busno,
 445                                                        pci_devfn, 0x04,
 446                                                        &v08_04);
 447                                 early_read_config_byte(hose, busno, busno,
 448                                                        pci_devfn, 0x09,
 449                                                        &v08_09);
 450                                 early_read_config_byte(hose, busno, busno,
 451                                                        pci_devfn, 0x41,
 452                                                        &v08_41);
 453                                 early_read_config_byte(hose, busno, busno,
 454                                                        pci_devfn, 0x43,
 455                                                        &v08_43);
 456                                 early_read_config_byte(hose, busno, busno,
 457                                                        pci_devfn, 0x5c,
 458                                                        &v08_5c);
 459
 460                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 461                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 462                                      ":%s end 0x04 = 0x%02x\n", s, v08_04);
 463                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 464                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 465                                      ":%s end 0x09 = 0x%02x\n", s, v08_09);
 466                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 467                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 468                                      ":%s end 0x41 = 0x%02x\n", s, v08_41);
 469                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 470                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 471                                      ":%s end 0x43 = 0x%02x\n", s, v08_43);
 472                                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 473                                     (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 474                                      ":%s end 0x5c = 0x%02x\n", s, v08_5c);
 475                         }
 476 #endif
 477
 478                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 479                             (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
 480                              s);
 481                 }
 482
 483         }
 484
 485         register_pci_controller(&tx4927_controller);
 486         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
 487                                        "+\n");
 488
 489         return 0;
 490 }
 491
 492 arch_initcall(tx4927_pcibios_init);
 493
 494 extern struct resource pci_io_resource;
 495 extern struct resource pci_mem_resource;
 496
 497 void tx4927_pci_setup(void)
 498 {
 499         static int called = 0;
 500         extern unsigned int tx4927_get_mem_size(void);
 501
 502         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
 503
 504         mips_memory_upper = tx4927_get_mem_size() << 20;
 505         mips_memory_upper += KSEG0;
 506         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 507                                        "0x%08lx=mips_memory_upper\n",
 508                                        mips_memory_upper);
 509         mips_pci_io_base = TX4927_PCIIO;
 510         mips_pci_io_size = TX4927_PCIIO_SIZE;
 511         mips_pci_mem_base = TX4927_PCIMEM;
 512         mips_pci_mem_size = TX4927_PCIMEM_SIZE;
 513
 514         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 515                                        "0x%08lx=mips_pci_io_base\n",
 516                                        mips_pci_io_base);
 517         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 518                                        "0x%08lx=mips_pci_io_size\n",
 519                                        mips_pci_io_size);
 520         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 521                                        "0x%08lx=mips_pci_mem_base\n",
 522                                        mips_pci_mem_base);
 523         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 524                                        "0x%08lx=mips_pci_mem_size\n",
 525                                        mips_pci_mem_size);
 526         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 527                                        "0x%08lx=pci_io_resource.start\n",
 528                                        pci_io_resource.start);
 529         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 530                                        "0x%08lx=pci_io_resource.end\n",
 531                                        pci_io_resource.end);
 532         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 533                                        "0x%08lx=pci_mem_resource.start\n",
 534                                        pci_mem_resource.start);
 535         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 536                                        "0x%08lx=pci_mem_resource.end\n",
 537                                        pci_mem_resource.end);
 538         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 539                                        "0x%08lx=mips_io_port_base",
 540                                        mips_io_port_base);
 541         if (!called) {
 542                 printk
 543                     ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
 544                      toshiba_name,
 545                      (unsigned short) (tx4927_pcicptr->pciid >> 16),
 546                      (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
 547                      (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
 548                      (!(tx4927_ccfgptr->
 549                         ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
 550                      "Internal");
 551                 called = 1;
 552         }
 553         printk("%s PCIC --%s PCICLK:",toshiba_name,
 554                (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
 555         if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
 556                 int pciclk = 0;
 557                 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 558                         switch ((unsigned long) tx4927_ccfgptr->
 559                                 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 560                         case TX4937_CCFG_PCIDIVMODE_4:
 561                                 pciclk = tx4927_cpu_clock / 4;
 562                                 break;
 563                         case TX4937_CCFG_PCIDIVMODE_4_5:
 564                                 pciclk = tx4927_cpu_clock * 2 / 9;
 565                                 break;
 566                         case TX4937_CCFG_PCIDIVMODE_5:
 567                                 pciclk = tx4927_cpu_clock / 5;
 568                                 break;
 569                         case TX4937_CCFG_PCIDIVMODE_5_5:
 570                                 pciclk = tx4927_cpu_clock * 2 / 11;
 571                                 break;
 572                         case TX4937_CCFG_PCIDIVMODE_8:
 573                                 pciclk = tx4927_cpu_clock / 8;
 574                                 break;
 575                         case TX4937_CCFG_PCIDIVMODE_9:
 576                                 pciclk = tx4927_cpu_clock / 9;
 577                                 break;
 578                         case TX4937_CCFG_PCIDIVMODE_10:
 579                                 pciclk = tx4927_cpu_clock / 10;
 580                                 break;
 581                         case TX4937_CCFG_PCIDIVMODE_11:
 582                                 pciclk = tx4927_cpu_clock / 11;
 583                                 break;
 584                         }
 585
 586                 else
 587                         switch ((unsigned long) tx4927_ccfgptr->
 588                                 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 589                         case TX4927_CCFG_PCIDIVMODE_2_5:
 590                                 pciclk = tx4927_cpu_clock * 2 / 5;
 591                                 break;
 592                         case TX4927_CCFG_PCIDIVMODE_3:
 593                                 pciclk = tx4927_cpu_clock / 3;
 594                                 break;
 595                         case TX4927_CCFG_PCIDIVMODE_5:
 596                                 pciclk = tx4927_cpu_clock / 5;
 597                                 break;
 598                         case TX4927_CCFG_PCIDIVMODE_6:
 599                                 pciclk = tx4927_cpu_clock / 6;
 600                                 break;
 601                         }
 602
 603                 printk("Internal(%dMHz)", pciclk / 1000000);
 604         } else {
 605                 int pciclk = 0;
 606                 int pciclk_setting = *tx4927_pci_clk_ptr;
 607                 switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
 608                 case TX4927_PCI_CLK_33:
 609                         pciclk = 33333333;
 610                         break;
 611                 case TX4927_PCI_CLK_25:
 612                         pciclk = 25000000;
 613                         break;
 614                 case TX4927_PCI_CLK_66:
 615                         pciclk = 66666666;
 616                         break;
 617                 case TX4927_PCI_CLK_50:
 618                         pciclk = 50000000;
 619                         break;
 620                 }
 621                 printk("External(%dMHz)", pciclk / 1000000);
 622         }
 623         printk("\n");
 624
 625
 626
 627         /* GB->PCI mappings */
 628         tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
 629         tx4927_pcicptr->g2piogbase = mips_pci_io_base |
 630 #ifdef __BIG_ENDIAN
 631             TX4927_PCIC_G2PIOGBASE_ECHG
 632 #else
 633             TX4927_PCIC_G2PIOGBASE_BSDIS
 634 #endif
 635             ;
 636
 637         tx4927_pcicptr->g2piopbase = 0;
 638
 639         tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
 640         tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
 641 #ifdef __BIG_ENDIAN
 642             TX4927_PCIC_G2PMnGBASE_ECHG
 643 #else
 644             TX4927_PCIC_G2PMnGBASE_BSDIS
 645 #endif
 646             ;
 647         tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
 648
 649         tx4927_pcicptr->g2pmmask[1] = 0;
 650         tx4927_pcicptr->g2pmgbase[1] = 0;
 651         tx4927_pcicptr->g2pmpbase[1] = 0;
 652         tx4927_pcicptr->g2pmmask[2] = 0;
 653         tx4927_pcicptr->g2pmgbase[2] = 0;
 654         tx4927_pcicptr->g2pmpbase[2] = 0;
 655
 656
 657         /* PCI->GB mappings (I/O 256B) */
 658         tx4927_pcicptr->p2giopbase = 0; /* 256B */
 659
 660         /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
 661         tx4927_pcicptr->p2gm0plbase = 0;
 662         tx4927_pcicptr->p2gm0pubase = 0;
 663         tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
 664 #ifdef __BIG_ENDIAN
 665             TX4927_PCIC_P2GMnGBASE_TECHG
 666 #else
 667             TX4927_PCIC_P2GMnGBASE_TBSDIS
 668 #endif
 669             ;
 670
 671         /* PCI->GB mappings (MEM 16MB) -not used */
 672         tx4927_pcicptr->p2gm1plbase = 0xffffffff;
 673 #ifdef CONFIG_TX4927BUG_WORKAROUND
 674         /*
 675          * TX4927-PCIC-BUG: P2GM1PUBASE must be 0
 676          * if P2GM0PUBASE was 0.
 677          */
 678         tx4927_pcicptr->p2gm1pubase = 0;
 679 #else
 680         tx4927_pcicptr->p2gm1pubase = 0xffffffff;
 681 #endif
 682         tx4927_pcicptr->p2gmgbase[1] = 0;
 683
 684         /* PCI->GB mappings (MEM 1MB) -not used */
 685         tx4927_pcicptr->p2gm2pbase = 0xffffffff;
 686         tx4927_pcicptr->p2gmgbase[2] = 0;
 687
 688
 689         /* Enable Initiator Memory 0 Space, I/O Space, Config */
 690         tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
 691         tx4927_pcicptr->pciccfg |=
 692             TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
 693             TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
 694
 695
 696         /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
 697         tx4927_pcicptr->pcicfg1 = 0;
 698
 699         if (tx4927_pcic_trdyto >= 0) {
 700                 tx4927_pcicptr->g2ptocnt &= ~0xff;
 701                 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
 702         }
 703
 704         /* Clear All Local Bus Status */
 705         tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
 706         /* Enable All Local Bus Interrupts */
 707         tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
 708         /* Clear All Initiator Status */
 709         tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
 710         /* Enable All Initiator Interrupts */
 711         tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
 712         /* Clear All PCI Status Error */
 713         tx4927_pcicptr->pcistatus =
 714             (tx4927_pcicptr->pcistatus & 0x0000ffff) |
 715             (TX4927_PCIC_PCISTATUS_ALL << 16);
 716         /* Enable All PCI Status Error Interrupts */
 717         tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
 718
 719         /* PCIC Int => IRC IRQ16 */
 720         tx4927_pcicptr->pcicfg2 =
 721             (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
 722
 723         if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
 724                 /* XXX */
 725         } else {
 726                 /* Reset Bus Arbiter */
 727                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
 728                 /* Enable Bus Arbiter */
 729                 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
 730         }
 731
 732         tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
 733             PCI_COMMAND_MEMORY |
 734             PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
 735
 736         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
 737                                        ":pci setup complete:\n");
 738         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
 739 }
 740
 741 #endif /* CONFIG_PCI */
 742
 743 void toshiba_rbtx4927_restart(char *command)
 744 {
 745         printk(KERN_NOTICE "System Rebooting...\n");
 746
 747         /* enable the s/w reset register */
 748         reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET);
 749
 750         /* wait for enable to be seen */
 751         while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) &
 752                 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
 753
 754         /* do a s/w reset */
 755         reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET);
 756
 757         /* do something passive while waiting for reset */
 758         local_irq_disable();
 759         while (1)
 760                 asm_wait();
 761
 762         /* no return */
 763 }
 764
 765
 766 void toshiba_rbtx4927_halt(void)
 767 {
 768         printk(KERN_NOTICE "System Halted\n");
 769         local_irq_disable();
 770         while (1) {
 771                 asm_wait();
 772         }
 773         /* no return */
 774 }
 775
 776 void toshiba_rbtx4927_power_off(void)
 777 {
 778         toshiba_rbtx4927_halt();
 779         /* no return */
 780 }
 781
 782 void __init toshiba_rbtx4927_setup(void)
 783 {
 784         vu32 cp0_config;
 785         char *argptr;
 786
 787         printk("CPU is %s\n", toshiba_name);
 788
 789         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 790                                        "-\n");
 791
 792         /* f/w leaves this on at startup */
 793         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 794                                        ":Clearing STO_ERL.\n");
 795         clear_c0_status(ST0_ERL);
 796
 797         /* enable caches -- HCP5 does this, pmon does not */
 798         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 799                                        ":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
 800         cp0_config = read_c0_config();
 801         cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
 802         write_c0_config(cp0_config);
 803
 804 #ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
 805         {
 806                 extern void dump_cp0(char *);
 807                 dump_cp0("toshiba_rbtx4927_early_fw_fixup");
 808         }
 809 #endif
 810
 811         /* setup irq stuff */
 812         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 813                                        ":Setting up tx4927 pic.\n");
 814         TX4927_WR(0xff1ff604, 0x00000400);      /* irq trigger */
 815         TX4927_WR(0xff1ff608, 0x00000000);      /* irq trigger */
 816
 817         /* setup serial stuff */
 818         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 819                                        ":Setting up tx4927 sio.\n");
 820         TX4927_WR(0xff1ff314, 0x00000000);      /* h/w flow control off */
 821         TX4927_WR(0xff1ff414, 0x00000000);      /* h/w flow control off */
 822
 823         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 824                                        "+\n");
 825
 826         set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
 827         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 828                                        ":mips_io_port_base=0x%08lx\n",
 829                                        mips_io_port_base);
 830
 831         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 832                                        ":Resource\n");
 833         ioport_resource.end = 0xffffffff;
 834         iomem_resource.end = 0xffffffff;
 835
 836         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
 837                                        ":ResetRoutines\n");
 838         _machine_restart = toshiba_rbtx4927_restart;
 839         _machine_halt = toshiba_rbtx4927_halt;
 840         pm_power_off = toshiba_rbtx4927_power_off;
 841
 842 #ifdef CONFIG_PCI
 843
 844         /* PCIC */
 845         /*
 846            * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
 847            *
 848            * For TX4927:
 849            * PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
 850            * CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
 851            * CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
 852            * CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
 853            * CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
 854            * i.e. S9[3]: ON (83MHz), OFF (100MHz)
 855            *
 856            * For TX4937:
 857            * PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
 858            * PCIDIVMODE[10] is 0.
 859            * CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
 860            * CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
 861            * CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
 862            * CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
 863            * CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
 864            * CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
 865            *
 866          */
 867         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 868                                        "ccfg is %lx, PCIDIVMODE is %x\n",
 869                                        (unsigned long) tx4927_ccfgptr->ccfg,
 870                                        (unsigned long) tx4927_ccfgptr->ccfg &
 871                                        (mips_machtype == MACH_TOSHIBA_RBTX4937 ?
 872                                         TX4937_CCFG_PCIDIVMODE_MASK :
 873                                         TX4927_CCFG_PCIDIVMODE_MASK));
 874
 875         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
 876                                        "PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
 877                                        (unsigned long) tx4927_ccfgptr->
 878                                        ccfg & TX4927_CCFG_PCI66,
 879                                        (unsigned long) tx4927_ccfgptr->
 880                                        ccfg & TX4927_CCFG_PCIMIDE,
 881                                        (unsigned long) tx4927_ccfgptr->
 882                                        ccfg & TX4927_CCFG_PCIXARB);
 883
 884         if (mips_machtype == MACH_TOSHIBA_RBTX4937)
 885                 switch ((unsigned long)tx4927_ccfgptr->
 886                         ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
 887                 case TX4937_CCFG_PCIDIVMODE_8:
 888                 case TX4937_CCFG_PCIDIVMODE_4:
 889                         tx4927_cpu_clock = 266666666;   /* 266MHz */
 890                         break;
 891                 case TX4937_CCFG_PCIDIVMODE_9:
 892                 case TX4937_CCFG_PCIDIVMODE_4_5:
 893                         tx4927_cpu_clock = 300000000;   /* 300MHz */
 894                         break;
 895                 default:
 896                         tx4927_cpu_clock = 333333333;   /* 333MHz */
 897                 }
 898         else
 899                 switch ((unsigned long)tx4927_ccfgptr->
 900                         ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
 901                 case TX4927_CCFG_PCIDIVMODE_2_5:
 902                 case TX4927_CCFG_PCIDIVMODE_5:
 903                         tx4927_cpu_clock = 166666666;   /* 166MHz */
 904                         break;
 905                 default:
 906                         tx4927_cpu_clock = 200000000;   /* 200MHz */
 907                 }
 908
 909         /* CCFG */
 910         /* enable Timeout BusError */
 911         if (tx4927_ccfg_toeon)
 912                 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
 913
 914         /* SDRAMC fixup */
 915 #ifdef CONFIG_TX4927BUG_WORKAROUND
 916         /*
 917          * TX4927-BUG: INF 01-01-18/ BUG 01-01-22
 918          * G-bus timeout error detection is incorrect
 919          */
 920         if (tx4927_ccfg_toeon)
 921                 tx4927_sdramcptr->tr |= 0x02000000;     /* RCD:3tck */
 922 #endif
 923
 924         tx4927_pci_setup();
 925         if (tx4927_using_backplane == 1)
 926                 printk("backplane board IS installed\n");
 927         else
 928                 printk("No Backplane \n");
 929
 930         /* this is on ISA bus behind PCI bus, so need PCI up first */
 931 #ifdef CONFIG_TOSHIBA_FPCIB0
 932         {
 933                 if (tx4927_using_backplane) {
 934                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 935                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 936                              ":fpcibo=yes\n");
 937
 938                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 939                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 940                              ":smsc_fdc37m81x_init()\n");
 941                         smsc_fdc37m81x_init(0x3f0);
 942
 943                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 944                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 945                              ":smsc_fdc37m81x_config_beg()\n");
 946                         smsc_fdc37m81x_config_beg();
 947
 948                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 949                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 950                              ":smsc_fdc37m81x_config_set(KBD)\n");
 951                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
 952                                                   SMSC_FDC37M81X_KBD);
 953                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
 954                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
 955                         smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
 956                                                   1);
 957
 958                         smsc_fdc37m81x_config_end();
 959                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 960                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 961                              ":smsc_fdc37m81x_config_end()\n");
 962                 } else {
 963                         TOSHIBA_RBTX4927_SETUP_DPRINTK
 964                             (TOSHIBA_RBTX4927_SETUP_SETUP,
 965                              ":fpcibo=not_found\n");
 966                 }
 967         }
 968 #else
 969         {
 970                 TOSHIBA_RBTX4927_SETUP_DPRINTK
 971                     (TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
 972         }
 973 #endif
 974
 975 #endif /* CONFIG_PCI */
 976
 977 #ifdef CONFIG_SERIAL_TXX9
 978         {
 979                 extern int early_serial_txx9_setup(struct uart_port *port);
 980                 int i;
 981                 struct uart_port req;
 982                 for(i = 0; i < 2; i++) {
 983                         memset(&req, 0, sizeof(req));
 984                         req.line = i;
 985                         req.iotype = UPIO_MEM;
 986                         req.membase = (char *)(0xff1ff300 + i * 0x100);
 987                         req.mapbase = 0xff1ff300 + i * 0x100;
 988                         req.irq = 32 + i;
 989                         req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
 990                         req.uartclk = 50000000;
 991                         early_serial_txx9_setup(&req);
 992                 }
 993         }
 994 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
 995         argptr = prom_getcmdline();
 996         if (strstr(argptr, "console=") == NULL) {
 997                 strcat(argptr, " console=ttyS0,38400");
 998         }
 999 #endif
1000 #endif
1001
1002 #ifdef CONFIG_ROOT_NFS
1003         argptr = prom_getcmdline();
1004         if (strstr(argptr, "root=") == NULL) {
1005                 strcat(argptr, " root=/dev/nfs rw");
1006         }
1007 #endif
1008
1009
1010 #ifdef CONFIG_IP_PNP
1011         argptr = prom_getcmdline();
1012         if (strstr(argptr, "ip=") == NULL) {
1013                 strcat(argptr, " ip=any");
1014         }
1015 #endif
1016
1017
1018         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
1019                                "+\n");
1020 }
1021
1022 #ifdef CONFIG_RTC_DS1742
1023 extern unsigned long rtc_ds1742_get_time(void);
1024 extern int rtc_ds1742_set_time(unsigned long);
1025 extern void rtc_ds1742_wait(void);
1026 #endif
1027
1028 void __init
1029 toshiba_rbtx4927_time_init(void)
1030 {
1031         u32 c1;
1032         u32 c2;
1033
1034         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "-\n");
1035
1036 #ifdef CONFIG_RTC_DS1742
1037
1038         rtc_mips_get_time = rtc_ds1742_get_time;
1039         rtc_mips_set_time = rtc_ds1742_set_time;
1040
1041         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1042                                        ":rtc_ds1742_init()-\n");
1043         rtc_ds1742_init(0xbc010000);
1044         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1045                                        ":rtc_ds1742_init()+\n");
1046
1047         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1048                                        ":Calibrate mips_hpt_frequency-\n");
1049         rtc_ds1742_wait();
1050
1051         /* get the count */
1052         c1 = read_c0_count();
1053
1054         /* wait for the seconds to change again */
1055         rtc_ds1742_wait();
1056
1057         /* get the count again */
1058         c2 = read_c0_count();
1059
1060         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1061                                        ":Calibrate mips_hpt_frequency+\n");
1062         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1063                                        ":c1=%12u\n", c1);
1064         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1065                                        ":c2=%12u\n", c2);
1066
1067         /* this diff is as close as we are going to get to counter ticks per sec */
1068         mips_hpt_frequency = abs(c2 - c1);
1069         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1070                                        ":f1=%12u\n", mips_hpt_frequency);
1071
1072         /* round to 1/10th of a MHz */
1073         mips_hpt_frequency /= (100 * 1000);
1074         mips_hpt_frequency *= (100 * 1000);
1075         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT,
1076                                        ":f2=%12u\n", mips_hpt_frequency);
1077
1078         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_INFO,
1079                                        ":mips_hpt_frequency=%uHz (%uMHz)\n",
1080                                        mips_hpt_frequency,
1081                                        mips_hpt_frequency / 1000000);
1082 #else
1083         mips_hpt_frequency = 100000000;
1084 #endif
1085
1086         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIME_INIT, "+\n");
1087
1088 }
1089
1090 void __init toshiba_rbtx4927_timer_setup(struct irqaction *irq)
1091 {
1092         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1093                                        "-\n");
1094         TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_TIMER_SETUP,
1095                                        "+\n");
1096 }