3 * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
4 * Copied and modified Carsten Langgaard's time.c
6 * Carsten Langgaard, carstenl@mips.com
7 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
9 * ########################################################################
11 * This program is free software; you can distribute it and/or modify it
12 * under the terms of the GNU General Public License (Version 2) as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
24 * ########################################################################
26 * Setting up the clock on the MIPS boards.
28 * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
29 * will use the user interface gettimeofday() functions from the
30 * arch/mips/kernel/time.c, and we provide the clock interrupt processing
31 * and the timer offset compute functions. If CONFIG_PM is selected,
32 * we also ensure the 32KHz timer is available. -- Dan
35 #include <linux/types.h>
36 #include <linux/init.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/sched.h>
39 #include <linux/spinlock.h>
40 #include <linux/hardirq.h>
42 #include <asm/compiler.h>
43 #include <asm/mipsregs.h>
45 #include <asm/div64.h>
46 #include <asm/mach-au1x00/au1000.h>
48 #include <linux/mc146818rtc.h>
49 #include <linux/timex.h>
51 static unsigned long r4k_offset; /* Amount to increment compare reg each time */
52 static unsigned long r4k_cur; /* What counter should be at next timer irq */
54 extern int allow_au1k_wait; /* default off for CP0 Counter */
57 #if HZ < 100 || HZ > 1000
58 #error "unsupported HZ value! Must be in [100,1000]"
60 #define MATCH20_INC (328*100/HZ) /* magic number 328 is for HZ=100... */
61 extern void startup_match20_interrupt(irq_handler_t handler);
62 static unsigned long last_pc0, last_match20;
65 static DEFINE_SPINLOCK(time_lock);
67 static inline void ack_r4ktimer(unsigned long newval)
69 write_c0_compare(newval);
73 * There are a lot of conceptually broken versions of the MIPS timer interrupt
74 * handler floating around. This one is rather different, but the algorithm
75 * is provably more robust.
79 void mips_timer_interrupt(void)
84 kstat_this_cpu.irqs[irq]++;
90 kstat_this_cpu.irqs[irq]++;
93 update_process_times(user_mode(get_irq_regs()));
95 r4k_cur += r4k_offset;
96 ack_r4ktimer(r4k_cur);
98 } while (((unsigned long)read_c0_count()
99 - r4k_cur) < 0x7fffffff);
110 irqreturn_t counter0_irq(int irq, void *dev_id)
114 static int jiffie_drift = 0;
116 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
117 /* should never happen! */
118 printk(KERN_WARNING "counter 0 w status error\n");
122 pc0 = au_readl(SYS_TOYREAD);
123 if (pc0 < last_match20) {
124 /* counter overflowed */
125 time_elapsed = (0xffffffff - last_match20) + pc0;
128 time_elapsed = pc0 - last_match20;
131 while (time_elapsed > 0) {
134 update_process_times(user_mode(get_irq_regs()));
136 time_elapsed -= MATCH20_INC;
137 last_match20 += MATCH20_INC;
142 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
145 /* our counter ticks at 10.009765625 ms/tick, we we're running
146 * almost 10uS too slow per tick.
149 if (jiffie_drift >= 999) {
151 do_timer(1); /* increment jiffies by one */
153 update_process_times(user_mode(get_irq_regs()));
160 /* When we wakeup from sleep, we have to "catch up" on all of the
161 * timer ticks we have missed.
164 wakeup_counter0_adjust(void)
169 pc0 = au_readl(SYS_TOYREAD);
170 if (pc0 < last_match20) {
171 /* counter overflowed */
172 time_elapsed = (0xffffffff - last_match20) + pc0;
175 time_elapsed = pc0 - last_match20;
178 while (time_elapsed > 0) {
179 time_elapsed -= MATCH20_INC;
180 last_match20 += MATCH20_INC;
184 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
189 /* This is just for debugging to set the timer for a sleep delay.
192 wakeup_counter0_set(int ticks)
196 pc0 = au_readl(SYS_TOYREAD);
198 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
203 /* I haven't found anyone that doesn't use a 12 MHz source clock,
204 * but just in case.....
206 #define AU1000_SRC_CLK 12000000
209 * We read the real processor speed from the PLL. This is important
210 * because it is more accurate than computing it from the 32KHz
211 * counter, if it exists. If we don't have an accurate processor
212 * speed, all of the peripherals that derive their clocks based on
213 * this advertised speed will introduce error and sometimes not work
214 * properly. This function is futher convoluted to still allow configurations
215 * to do that in case they have really, really old silicon with a
216 * write-only PLL register, that we need the 32KHz when power management
217 * "wait" is enabled, and we need to detect if the 32KHz isn't present
218 * but requested......got it? :-) -- Dan
220 unsigned long cal_r4koff(void)
222 unsigned long cpu_speed;
224 unsigned long counter;
226 spin_lock_irqsave(&time_lock, flags);
228 /* Power management cares if we don't have a 32KHz counter.
231 counter = au_readl(SYS_COUNTER_CNTRL);
232 if (counter & SYS_CNTRL_E0) {
233 int trim_divide = 16;
235 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
237 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
238 /* RTC now ticks at 32.768/16 kHz */
239 au_writel(trim_divide-1, SYS_RTCTRIM);
240 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
242 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
243 au_writel (0, SYS_TOYWRITE);
244 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
246 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
250 /* The 32KHz oscillator isn't running, so assume there
251 * isn't one and grab the processor speed from the PLL.
252 * NOTE: some old silicon doesn't allow reading the PLL.
254 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
257 mips_hpt_frequency = cpu_speed;
258 // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
259 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
260 spin_unlock_irqrestore(&time_lock, flags);
261 return (cpu_speed / HZ);
264 void __init plat_timer_setup(struct irqaction *irq)
266 unsigned int est_freq;
268 printk("calculating r4koff... ");
269 r4k_offset = cal_r4koff();
270 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
272 //est_freq = 2*r4k_offset*HZ;
273 est_freq = r4k_offset*HZ;
274 est_freq += 5000; /* round */
275 est_freq -= est_freq%10000;
276 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
277 (est_freq%1000000)*100/1000000);
278 set_au1x00_speed(est_freq);
279 set_au1x00_lcd_clock(); // program the LCD clock
281 r4k_cur = (read_c0_count() + r4k_offset);
282 write_c0_compare(r4k_cur);
286 * setup counter 0, since it keeps ticking after a
287 * 'wait' instruction has been executed. The CP0 timer and
288 * counter 1 do NOT continue running after 'wait'
290 * It's too early to call request_irq() here, so we handle
291 * counter 0 interrupt as a special irq and it doesn't show
292 * up under /proc/interrupts.
294 * Check to ensure we really have a 32KHz oscillator before
297 if (no_au1xxx_32khz) {
298 unsigned int c0_status;
300 printk("WARNING: no 32KHz clock found.\n");
302 /* Ensure we get CPO_COUNTER interrupts.
304 c0_status = read_c0_status();
305 c0_status |= IE_IRQ5;
306 write_c0_status(c0_status);
309 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
310 au_writel(0, SYS_TOYWRITE);
311 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
313 au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
314 au_writel(~0, SYS_WAKESRC);
316 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
318 /* setup match20 to interrupt once every HZ */
319 last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
320 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
322 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
323 startup_match20_interrupt(counter0_irq);
325 /* We can use the real 'wait' instruction.
333 void __init au1xxx_time_init(void)