Pull dock-bay into release branch
[linux-2.6] / arch / powerpc / sysdev / mpic.c
1 /*
2  *  arch/powerpc/kernel/mpic.c
3  *
4  *  Driver for interrupt controllers following the OpenPIC standard, the
5  *  common implementation beeing IBM's MPIC. This driver also can deal
6  *  with various broken implementations of this HW.
7  *
8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9  *
10  *  This file is subject to the terms and conditions of the GNU General Public
11  *  License.  See the file COPYING in the main directory of this archive
12  *  for more details.
13  */
14
15 #undef DEBUG
16 #undef DEBUG_IPI
17 #undef DEBUG_IRQ
18 #undef DEBUG_LOW
19
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
32 #include <asm/io.h>
33 #include <asm/pgtable.h>
34 #include <asm/irq.h>
35 #include <asm/machdep.h>
36 #include <asm/mpic.h>
37 #include <asm/smp.h>
38
39 #include "mpic.h"
40
41 #ifdef DEBUG
42 #define DBG(fmt...) printk(fmt)
43 #else
44 #define DBG(fmt...)
45 #endif
46
47 static struct mpic *mpics;
48 static struct mpic *mpic_primary;
49 static DEFINE_SPINLOCK(mpic_lock);
50
51 #ifdef CONFIG_PPC32     /* XXX for now */
52 #ifdef CONFIG_IRQ_ALL_CPUS
53 #define distribute_irqs (1)
54 #else
55 #define distribute_irqs (0)
56 #endif
57 #endif
58
59 #ifdef CONFIG_MPIC_WEIRD
60 static u32 mpic_infos[][MPIC_IDX_END] = {
61         [0] = { /* Original OpenPIC compatible MPIC */
62                 MPIC_GREG_BASE,
63                 MPIC_GREG_FEATURE_0,
64                 MPIC_GREG_GLOBAL_CONF_0,
65                 MPIC_GREG_VENDOR_ID,
66                 MPIC_GREG_IPI_VECTOR_PRI_0,
67                 MPIC_GREG_IPI_STRIDE,
68                 MPIC_GREG_SPURIOUS,
69                 MPIC_GREG_TIMER_FREQ,
70
71                 MPIC_TIMER_BASE,
72                 MPIC_TIMER_STRIDE,
73                 MPIC_TIMER_CURRENT_CNT,
74                 MPIC_TIMER_BASE_CNT,
75                 MPIC_TIMER_VECTOR_PRI,
76                 MPIC_TIMER_DESTINATION,
77
78                 MPIC_CPU_BASE,
79                 MPIC_CPU_STRIDE,
80                 MPIC_CPU_IPI_DISPATCH_0,
81                 MPIC_CPU_IPI_DISPATCH_STRIDE,
82                 MPIC_CPU_CURRENT_TASK_PRI,
83                 MPIC_CPU_WHOAMI,
84                 MPIC_CPU_INTACK,
85                 MPIC_CPU_EOI,
86
87                 MPIC_IRQ_BASE,
88                 MPIC_IRQ_STRIDE,
89                 MPIC_IRQ_VECTOR_PRI,
90                 MPIC_VECPRI_VECTOR_MASK,
91                 MPIC_VECPRI_POLARITY_POSITIVE,
92                 MPIC_VECPRI_POLARITY_NEGATIVE,
93                 MPIC_VECPRI_SENSE_LEVEL,
94                 MPIC_VECPRI_SENSE_EDGE,
95                 MPIC_VECPRI_POLARITY_MASK,
96                 MPIC_VECPRI_SENSE_MASK,
97                 MPIC_IRQ_DESTINATION
98         },
99         [1] = { /* Tsi108/109 PIC */
100                 TSI108_GREG_BASE,
101                 TSI108_GREG_FEATURE_0,
102                 TSI108_GREG_GLOBAL_CONF_0,
103                 TSI108_GREG_VENDOR_ID,
104                 TSI108_GREG_IPI_VECTOR_PRI_0,
105                 TSI108_GREG_IPI_STRIDE,
106                 TSI108_GREG_SPURIOUS,
107                 TSI108_GREG_TIMER_FREQ,
108
109                 TSI108_TIMER_BASE,
110                 TSI108_TIMER_STRIDE,
111                 TSI108_TIMER_CURRENT_CNT,
112                 TSI108_TIMER_BASE_CNT,
113                 TSI108_TIMER_VECTOR_PRI,
114                 TSI108_TIMER_DESTINATION,
115
116                 TSI108_CPU_BASE,
117                 TSI108_CPU_STRIDE,
118                 TSI108_CPU_IPI_DISPATCH_0,
119                 TSI108_CPU_IPI_DISPATCH_STRIDE,
120                 TSI108_CPU_CURRENT_TASK_PRI,
121                 TSI108_CPU_WHOAMI,
122                 TSI108_CPU_INTACK,
123                 TSI108_CPU_EOI,
124
125                 TSI108_IRQ_BASE,
126                 TSI108_IRQ_STRIDE,
127                 TSI108_IRQ_VECTOR_PRI,
128                 TSI108_VECPRI_VECTOR_MASK,
129                 TSI108_VECPRI_POLARITY_POSITIVE,
130                 TSI108_VECPRI_POLARITY_NEGATIVE,
131                 TSI108_VECPRI_SENSE_LEVEL,
132                 TSI108_VECPRI_SENSE_EDGE,
133                 TSI108_VECPRI_POLARITY_MASK,
134                 TSI108_VECPRI_SENSE_MASK,
135                 TSI108_IRQ_DESTINATION
136         },
137 };
138
139 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
140
141 #else /* CONFIG_MPIC_WEIRD */
142
143 #define MPIC_INFO(name) MPIC_##name
144
145 #endif /* CONFIG_MPIC_WEIRD */
146
147 /*
148  * Register accessor functions
149  */
150
151
152 static inline u32 _mpic_read(enum mpic_reg_type type,
153                              struct mpic_reg_bank *rb,
154                              unsigned int reg)
155 {
156         switch(type) {
157 #ifdef CONFIG_PPC_DCR
158         case mpic_access_dcr:
159                 return dcr_read(rb->dhost,
160                                 rb->dbase + reg + rb->doff);
161 #endif
162         case mpic_access_mmio_be:
163                 return in_be32(rb->base + (reg >> 2));
164         case mpic_access_mmio_le:
165         default:
166                 return in_le32(rb->base + (reg >> 2));
167         }
168 }
169
170 static inline void _mpic_write(enum mpic_reg_type type,
171                                struct mpic_reg_bank *rb,
172                                unsigned int reg, u32 value)
173 {
174         switch(type) {
175 #ifdef CONFIG_PPC_DCR
176         case mpic_access_dcr:
177                 return dcr_write(rb->dhost,
178                                  rb->dbase + reg + rb->doff, value);
179 #endif
180         case mpic_access_mmio_be:
181                 return out_be32(rb->base + (reg >> 2), value);
182         case mpic_access_mmio_le:
183         default:
184                 return out_le32(rb->base + (reg >> 2), value);
185         }
186 }
187
188 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
189 {
190         enum mpic_reg_type type = mpic->reg_type;
191         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
192                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
193
194         if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
195                 type = mpic_access_mmio_be;
196         return _mpic_read(type, &mpic->gregs, offset);
197 }
198
199 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
200 {
201         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
202                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
203
204         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
205 }
206
207 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
208 {
209         unsigned int cpu = 0;
210
211         if (mpic->flags & MPIC_PRIMARY)
212                 cpu = hard_smp_processor_id();
213         return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
214 }
215
216 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
217 {
218         unsigned int cpu = 0;
219
220         if (mpic->flags & MPIC_PRIMARY)
221                 cpu = hard_smp_processor_id();
222
223         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
224 }
225
226 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
227 {
228         unsigned int    isu = src_no >> mpic->isu_shift;
229         unsigned int    idx = src_no & mpic->isu_mask;
230
231         return _mpic_read(mpic->reg_type, &mpic->isus[isu],
232                           reg + (idx * MPIC_INFO(IRQ_STRIDE)));
233 }
234
235 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
236                                    unsigned int reg, u32 value)
237 {
238         unsigned int    isu = src_no >> mpic->isu_shift;
239         unsigned int    idx = src_no & mpic->isu_mask;
240
241         _mpic_write(mpic->reg_type, &mpic->isus[isu],
242                     reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
243 }
244
245 #define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
246 #define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
247 #define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
248 #define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
249 #define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
250 #define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
251 #define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
252 #define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
253
254
255 /*
256  * Low level utility functions
257  */
258
259
260 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr,
261                            struct mpic_reg_bank *rb, unsigned int offset,
262                            unsigned int size)
263 {
264         rb->base = ioremap(phys_addr + offset, size);
265         BUG_ON(rb->base == NULL);
266 }
267
268 #ifdef CONFIG_PPC_DCR
269 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
270                           unsigned int offset, unsigned int size)
271 {
272         rb->dbase = mpic->dcr_base;
273         rb->doff = offset;
274         rb->dhost = dcr_map(mpic->of_node, rb->dbase + rb->doff, size);
275         BUG_ON(!DCR_MAP_OK(rb->dhost));
276 }
277
278 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr,
279                             struct mpic_reg_bank *rb, unsigned int offset,
280                             unsigned int size)
281 {
282         if (mpic->flags & MPIC_USES_DCR)
283                 _mpic_map_dcr(mpic, rb, offset, size);
284         else
285                 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
286 }
287 #else /* CONFIG_PPC_DCR */
288 #define mpic_map(m,p,b,o,s)     _mpic_map_mmio(m,p,b,o,s)
289 #endif /* !CONFIG_PPC_DCR */
290
291
292
293 /* Check if we have one of those nice broken MPICs with a flipped endian on
294  * reads from IPI registers
295  */
296 static void __init mpic_test_broken_ipi(struct mpic *mpic)
297 {
298         u32 r;
299
300         mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
301         r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
302
303         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
304                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
305                 mpic->flags |= MPIC_BROKEN_IPI;
306         }
307 }
308
309 #ifdef CONFIG_MPIC_U3_HT_IRQS
310
311 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
312  * to force the edge setting on the MPIC and do the ack workaround.
313  */
314 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
315 {
316         if (source >= 128 || !mpic->fixups)
317                 return 0;
318         return mpic->fixups[source].base != NULL;
319 }
320
321
322 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
323 {
324         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
325
326         if (fixup->applebase) {
327                 unsigned int soff = (fixup->index >> 3) & ~3;
328                 unsigned int mask = 1U << (fixup->index & 0x1f);
329                 writel(mask, fixup->applebase + soff);
330         } else {
331                 spin_lock(&mpic->fixup_lock);
332                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
333                 writel(fixup->data, fixup->base + 4);
334                 spin_unlock(&mpic->fixup_lock);
335         }
336 }
337
338 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
339                                       unsigned int irqflags)
340 {
341         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
342         unsigned long flags;
343         u32 tmp;
344
345         if (fixup->base == NULL)
346                 return;
347
348         DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
349             source, irqflags, fixup->index);
350         spin_lock_irqsave(&mpic->fixup_lock, flags);
351         /* Enable and configure */
352         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
353         tmp = readl(fixup->base + 4);
354         tmp &= ~(0x23U);
355         if (irqflags & IRQ_LEVEL)
356                 tmp |= 0x22;
357         writel(tmp, fixup->base + 4);
358         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
359
360 #ifdef CONFIG_PM
361         /* use the lowest bit inverted to the actual HW,
362          * set if this fixup was enabled, clear otherwise */
363         mpic->save_data[source].fixup_data = tmp | 1;
364 #endif
365 }
366
367 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
368                                        unsigned int irqflags)
369 {
370         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
371         unsigned long flags;
372         u32 tmp;
373
374         if (fixup->base == NULL)
375                 return;
376
377         DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
378
379         /* Disable */
380         spin_lock_irqsave(&mpic->fixup_lock, flags);
381         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
382         tmp = readl(fixup->base + 4);
383         tmp |= 1;
384         writel(tmp, fixup->base + 4);
385         spin_unlock_irqrestore(&mpic->fixup_lock, flags);
386
387 #ifdef CONFIG_PM
388         /* use the lowest bit inverted to the actual HW,
389          * set if this fixup was enabled, clear otherwise */
390         mpic->save_data[source].fixup_data = tmp & ~1;
391 #endif
392 }
393
394 #ifdef CONFIG_PCI_MSI
395 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
396                                     unsigned int devfn)
397 {
398         u8 __iomem *base;
399         u8 pos, flags;
400         u64 addr = 0;
401
402         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
403              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
404                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
405                 if (id == PCI_CAP_ID_HT) {
406                         id = readb(devbase + pos + 3);
407                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
408                                 break;
409                 }
410         }
411
412         if (pos == 0)
413                 return;
414
415         base = devbase + pos;
416
417         flags = readb(base + HT_MSI_FLAGS);
418         if (!(flags & HT_MSI_FLAGS_FIXED)) {
419                 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
420                 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
421         }
422
423         printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
424                 PCI_SLOT(devfn), PCI_FUNC(devfn),
425                 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
426
427         if (!(flags & HT_MSI_FLAGS_ENABLE))
428                 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
429 }
430 #else
431 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
432                                     unsigned int devfn)
433 {
434         return;
435 }
436 #endif
437
438 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
439                                     unsigned int devfn, u32 vdid)
440 {
441         int i, irq, n;
442         u8 __iomem *base;
443         u32 tmp;
444         u8 pos;
445
446         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
447              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
448                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
449                 if (id == PCI_CAP_ID_HT) {
450                         id = readb(devbase + pos + 3);
451                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
452                                 break;
453                 }
454         }
455         if (pos == 0)
456                 return;
457
458         base = devbase + pos;
459         writeb(0x01, base + 2);
460         n = (readl(base + 4) >> 16) & 0xff;
461
462         printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
463                " has %d irqs\n",
464                devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
465
466         for (i = 0; i <= n; i++) {
467                 writeb(0x10 + 2 * i, base + 2);
468                 tmp = readl(base + 4);
469                 irq = (tmp >> 16) & 0xff;
470                 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
471                 /* mask it , will be unmasked later */
472                 tmp |= 0x1;
473                 writel(tmp, base + 4);
474                 mpic->fixups[irq].index = i;
475                 mpic->fixups[irq].base = base;
476                 /* Apple HT PIC has a non-standard way of doing EOIs */
477                 if ((vdid & 0xffff) == 0x106b)
478                         mpic->fixups[irq].applebase = devbase + 0x60;
479                 else
480                         mpic->fixups[irq].applebase = NULL;
481                 writeb(0x11 + 2 * i, base + 2);
482                 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
483         }
484 }
485  
486
487 static void __init mpic_scan_ht_pics(struct mpic *mpic)
488 {
489         unsigned int devfn;
490         u8 __iomem *cfgspace;
491
492         printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
493
494         /* Allocate fixups array */
495         mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
496         BUG_ON(mpic->fixups == NULL);
497         memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
498
499         /* Init spinlock */
500         spin_lock_init(&mpic->fixup_lock);
501
502         /* Map U3 config space. We assume all IO-APICs are on the primary bus
503          * so we only need to map 64kB.
504          */
505         cfgspace = ioremap(0xf2000000, 0x10000);
506         BUG_ON(cfgspace == NULL);
507
508         /* Now we scan all slots. We do a very quick scan, we read the header
509          * type, vendor ID and device ID only, that's plenty enough
510          */
511         for (devfn = 0; devfn < 0x100; devfn++) {
512                 u8 __iomem *devbase = cfgspace + (devfn << 8);
513                 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
514                 u32 l = readl(devbase + PCI_VENDOR_ID);
515                 u16 s;
516
517                 DBG("devfn %x, l: %x\n", devfn, l);
518
519                 /* If no device, skip */
520                 if (l == 0xffffffff || l == 0x00000000 ||
521                     l == 0x0000ffff || l == 0xffff0000)
522                         goto next;
523                 /* Check if is supports capability lists */
524                 s = readw(devbase + PCI_STATUS);
525                 if (!(s & PCI_STATUS_CAP_LIST))
526                         goto next;
527
528                 mpic_scan_ht_pic(mpic, devbase, devfn, l);
529                 mpic_scan_ht_msi(mpic, devbase, devfn);
530
531         next:
532                 /* next device, if function 0 */
533                 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
534                         devfn += 7;
535         }
536 }
537
538 #else /* CONFIG_MPIC_U3_HT_IRQS */
539
540 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
541 {
542         return 0;
543 }
544
545 static void __init mpic_scan_ht_pics(struct mpic *mpic)
546 {
547 }
548
549 #endif /* CONFIG_MPIC_U3_HT_IRQS */
550
551
552 #define mpic_irq_to_hw(virq)    ((unsigned int)irq_map[virq].hwirq)
553
554 /* Find an mpic associated with a given linux interrupt */
555 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
556 {
557         unsigned int src = mpic_irq_to_hw(irq);
558         struct mpic *mpic;
559
560         if (irq < NUM_ISA_INTERRUPTS)
561                 return NULL;
562
563         mpic = irq_desc[irq].chip_data;
564
565         if (is_ipi)
566                 *is_ipi = (src >= mpic->ipi_vecs[0] &&
567                            src <= mpic->ipi_vecs[3]);
568
569         return mpic;
570 }
571
572 /* Convert a cpu mask from logical to physical cpu numbers. */
573 static inline u32 mpic_physmask(u32 cpumask)
574 {
575         int i;
576         u32 mask = 0;
577
578         for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
579                 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
580         return mask;
581 }
582
583 #ifdef CONFIG_SMP
584 /* Get the mpic structure from the IPI number */
585 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
586 {
587         return irq_desc[ipi].chip_data;
588 }
589 #endif
590
591 /* Get the mpic structure from the irq number */
592 static inline struct mpic * mpic_from_irq(unsigned int irq)
593 {
594         return irq_desc[irq].chip_data;
595 }
596
597 /* Send an EOI */
598 static inline void mpic_eoi(struct mpic *mpic)
599 {
600         mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
601         (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
602 }
603
604 #ifdef CONFIG_SMP
605 static irqreturn_t mpic_ipi_action(int irq, void *dev_id)
606 {
607         struct mpic *mpic;
608
609         mpic = mpic_find(irq, NULL);
610         smp_message_recv(mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]);
611
612         return IRQ_HANDLED;
613 }
614 #endif /* CONFIG_SMP */
615
616 /*
617  * Linux descriptor level callbacks
618  */
619
620
621 void mpic_unmask_irq(unsigned int irq)
622 {
623         unsigned int loops = 100000;
624         struct mpic *mpic = mpic_from_irq(irq);
625         unsigned int src = mpic_irq_to_hw(irq);
626
627         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
628
629         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
630                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
631                        ~MPIC_VECPRI_MASK);
632         /* make sure mask gets to controller before we return to user */
633         do {
634                 if (!loops--) {
635                         printk(KERN_ERR "mpic_enable_irq timeout\n");
636                         break;
637                 }
638         } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
639 }
640
641 void mpic_mask_irq(unsigned int irq)
642 {
643         unsigned int loops = 100000;
644         struct mpic *mpic = mpic_from_irq(irq);
645         unsigned int src = mpic_irq_to_hw(irq);
646
647         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
648
649         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
650                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
651                        MPIC_VECPRI_MASK);
652
653         /* make sure mask gets to controller before we return to user */
654         do {
655                 if (!loops--) {
656                         printk(KERN_ERR "mpic_enable_irq timeout\n");
657                         break;
658                 }
659         } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
660 }
661
662 void mpic_end_irq(unsigned int irq)
663 {
664         struct mpic *mpic = mpic_from_irq(irq);
665
666 #ifdef DEBUG_IRQ
667         DBG("%s: end_irq: %d\n", mpic->name, irq);
668 #endif
669         /* We always EOI on end_irq() even for edge interrupts since that
670          * should only lower the priority, the MPIC should have properly
671          * latched another edge interrupt coming in anyway
672          */
673
674         mpic_eoi(mpic);
675 }
676
677 #ifdef CONFIG_MPIC_U3_HT_IRQS
678
679 static void mpic_unmask_ht_irq(unsigned int irq)
680 {
681         struct mpic *mpic = mpic_from_irq(irq);
682         unsigned int src = mpic_irq_to_hw(irq);
683
684         mpic_unmask_irq(irq);
685
686         if (irq_desc[irq].status & IRQ_LEVEL)
687                 mpic_ht_end_irq(mpic, src);
688 }
689
690 static unsigned int mpic_startup_ht_irq(unsigned int irq)
691 {
692         struct mpic *mpic = mpic_from_irq(irq);
693         unsigned int src = mpic_irq_to_hw(irq);
694
695         mpic_unmask_irq(irq);
696         mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
697
698         return 0;
699 }
700
701 static void mpic_shutdown_ht_irq(unsigned int irq)
702 {
703         struct mpic *mpic = mpic_from_irq(irq);
704         unsigned int src = mpic_irq_to_hw(irq);
705
706         mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
707         mpic_mask_irq(irq);
708 }
709
710 static void mpic_end_ht_irq(unsigned int irq)
711 {
712         struct mpic *mpic = mpic_from_irq(irq);
713         unsigned int src = mpic_irq_to_hw(irq);
714
715 #ifdef DEBUG_IRQ
716         DBG("%s: end_irq: %d\n", mpic->name, irq);
717 #endif
718         /* We always EOI on end_irq() even for edge interrupts since that
719          * should only lower the priority, the MPIC should have properly
720          * latched another edge interrupt coming in anyway
721          */
722
723         if (irq_desc[irq].status & IRQ_LEVEL)
724                 mpic_ht_end_irq(mpic, src);
725         mpic_eoi(mpic);
726 }
727 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
728
729 #ifdef CONFIG_SMP
730
731 static void mpic_unmask_ipi(unsigned int irq)
732 {
733         struct mpic *mpic = mpic_from_ipi(irq);
734         unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
735
736         DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
737         mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
738 }
739
740 static void mpic_mask_ipi(unsigned int irq)
741 {
742         /* NEVER disable an IPI... that's just plain wrong! */
743 }
744
745 static void mpic_end_ipi(unsigned int irq)
746 {
747         struct mpic *mpic = mpic_from_ipi(irq);
748
749         /*
750          * IPIs are marked IRQ_PER_CPU. This has the side effect of
751          * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
752          * applying to them. We EOI them late to avoid re-entering.
753          * We mark IPI's with IRQF_DISABLED as they must run with
754          * irqs disabled.
755          */
756         mpic_eoi(mpic);
757 }
758
759 #endif /* CONFIG_SMP */
760
761 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
762 {
763         struct mpic *mpic = mpic_from_irq(irq);
764         unsigned int src = mpic_irq_to_hw(irq);
765
766         cpumask_t tmp;
767
768         cpus_and(tmp, cpumask, cpu_online_map);
769
770         mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
771                        mpic_physmask(cpus_addr(tmp)[0]));       
772 }
773
774 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
775 {
776         /* Now convert sense value */
777         switch(type & IRQ_TYPE_SENSE_MASK) {
778         case IRQ_TYPE_EDGE_RISING:
779                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
780                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
781         case IRQ_TYPE_EDGE_FALLING:
782         case IRQ_TYPE_EDGE_BOTH:
783                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
784                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
785         case IRQ_TYPE_LEVEL_HIGH:
786                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
787                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
788         case IRQ_TYPE_LEVEL_LOW:
789         default:
790                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
791                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
792         }
793 }
794
795 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
796 {
797         struct mpic *mpic = mpic_from_irq(virq);
798         unsigned int src = mpic_irq_to_hw(virq);
799         struct irq_desc *desc = get_irq_desc(virq);
800         unsigned int vecpri, vold, vnew;
801
802         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
803             mpic, virq, src, flow_type);
804
805         if (src >= mpic->irq_count)
806                 return -EINVAL;
807
808         if (flow_type == IRQ_TYPE_NONE)
809                 if (mpic->senses && src < mpic->senses_count)
810                         flow_type = mpic->senses[src];
811         if (flow_type == IRQ_TYPE_NONE)
812                 flow_type = IRQ_TYPE_LEVEL_LOW;
813
814         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
815         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
816         if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
817                 desc->status |= IRQ_LEVEL;
818
819         if (mpic_is_ht_interrupt(mpic, src))
820                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
821                         MPIC_VECPRI_SENSE_EDGE;
822         else
823                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
824
825         vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
826         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
827                         MPIC_INFO(VECPRI_SENSE_MASK));
828         vnew |= vecpri;
829         if (vold != vnew)
830                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
831
832         return 0;
833 }
834
835 static struct irq_chip mpic_irq_chip = {
836         .mask           = mpic_mask_irq,
837         .unmask         = mpic_unmask_irq,
838         .eoi            = mpic_end_irq,
839         .set_type       = mpic_set_irq_type,
840 };
841
842 #ifdef CONFIG_SMP
843 static struct irq_chip mpic_ipi_chip = {
844         .mask           = mpic_mask_ipi,
845         .unmask         = mpic_unmask_ipi,
846         .eoi            = mpic_end_ipi,
847 };
848 #endif /* CONFIG_SMP */
849
850 #ifdef CONFIG_MPIC_U3_HT_IRQS
851 static struct irq_chip mpic_irq_ht_chip = {
852         .startup        = mpic_startup_ht_irq,
853         .shutdown       = mpic_shutdown_ht_irq,
854         .mask           = mpic_mask_irq,
855         .unmask         = mpic_unmask_ht_irq,
856         .eoi            = mpic_end_ht_irq,
857         .set_type       = mpic_set_irq_type,
858 };
859 #endif /* CONFIG_MPIC_U3_HT_IRQS */
860
861
862 static int mpic_host_match(struct irq_host *h, struct device_node *node)
863 {
864         struct mpic *mpic = h->host_data;
865
866         /* Exact match, unless mpic node is NULL */
867         return mpic->of_node == NULL || mpic->of_node == node;
868 }
869
870 static int mpic_host_map(struct irq_host *h, unsigned int virq,
871                          irq_hw_number_t hw)
872 {
873         struct mpic *mpic = h->host_data;
874         struct irq_chip *chip;
875
876         DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
877
878         if (hw == mpic->spurious_vec)
879                 return -EINVAL;
880
881 #ifdef CONFIG_SMP
882         else if (hw >= mpic->ipi_vecs[0]) {
883                 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
884
885                 DBG("mpic: mapping as IPI\n");
886                 set_irq_chip_data(virq, mpic);
887                 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
888                                          handle_percpu_irq);
889                 return 0;
890         }
891 #endif /* CONFIG_SMP */
892
893         if (hw >= mpic->irq_count)
894                 return -EINVAL;
895
896         mpic_msi_reserve_hwirq(mpic, hw);
897
898         /* Default chip */
899         chip = &mpic->hc_irq;
900
901 #ifdef CONFIG_MPIC_U3_HT_IRQS
902         /* Check for HT interrupts, override vecpri */
903         if (mpic_is_ht_interrupt(mpic, hw))
904                 chip = &mpic->hc_ht_irq;
905 #endif /* CONFIG_MPIC_U3_HT_IRQS */
906
907         DBG("mpic: mapping to irq chip @%p\n", chip);
908
909         set_irq_chip_data(virq, mpic);
910         set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
911
912         /* Set default irq type */
913         set_irq_type(virq, IRQ_TYPE_NONE);
914
915         return 0;
916 }
917
918 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
919                            u32 *intspec, unsigned int intsize,
920                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
921
922 {
923         static unsigned char map_mpic_senses[4] = {
924                 IRQ_TYPE_EDGE_RISING,
925                 IRQ_TYPE_LEVEL_LOW,
926                 IRQ_TYPE_LEVEL_HIGH,
927                 IRQ_TYPE_EDGE_FALLING,
928         };
929
930         *out_hwirq = intspec[0];
931         if (intsize > 1) {
932                 u32 mask = 0x3;
933
934                 /* Apple invented a new race of encoding on machines with
935                  * an HT APIC. They encode, among others, the index within
936                  * the HT APIC. We don't care about it here since thankfully,
937                  * it appears that they have the APIC already properly
938                  * configured, and thus our current fixup code that reads the
939                  * APIC config works fine. However, we still need to mask out
940                  * bits in the specifier to make sure we only get bit 0 which
941                  * is the level/edge bit (the only sense bit exposed by Apple),
942                  * as their bit 1 means something else.
943                  */
944                 if (machine_is(powermac))
945                         mask = 0x1;
946                 *out_flags = map_mpic_senses[intspec[1] & mask];
947         } else
948                 *out_flags = IRQ_TYPE_NONE;
949
950         DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
951             intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
952
953         return 0;
954 }
955
956 static struct irq_host_ops mpic_host_ops = {
957         .match = mpic_host_match,
958         .map = mpic_host_map,
959         .xlate = mpic_host_xlate,
960 };
961
962 /*
963  * Exported functions
964  */
965
966 struct mpic * __init mpic_alloc(struct device_node *node,
967                                 phys_addr_t phys_addr,
968                                 unsigned int flags,
969                                 unsigned int isu_size,
970                                 unsigned int irq_count,
971                                 const char *name)
972 {
973         struct mpic     *mpic;
974         u32             reg;
975         const char      *vers;
976         int             i;
977         int             intvec_top;
978         u64             paddr = phys_addr;
979
980         mpic = alloc_bootmem(sizeof(struct mpic));
981         if (mpic == NULL)
982                 return NULL;
983         
984         memset(mpic, 0, sizeof(struct mpic));
985         mpic->name = name;
986         mpic->of_node = of_node_get(node);
987
988         mpic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR, isu_size,
989                                        &mpic_host_ops,
990                                        flags & MPIC_LARGE_VECTORS ? 2048 : 256);
991         if (mpic->irqhost == NULL) {
992                 of_node_put(node);
993                 return NULL;
994         }
995
996         mpic->irqhost->host_data = mpic;
997         mpic->hc_irq = mpic_irq_chip;
998         mpic->hc_irq.typename = name;
999         if (flags & MPIC_PRIMARY)
1000                 mpic->hc_irq.set_affinity = mpic_set_affinity;
1001 #ifdef CONFIG_MPIC_U3_HT_IRQS
1002         mpic->hc_ht_irq = mpic_irq_ht_chip;
1003         mpic->hc_ht_irq.typename = name;
1004         if (flags & MPIC_PRIMARY)
1005                 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1006 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1007
1008 #ifdef CONFIG_SMP
1009         mpic->hc_ipi = mpic_ipi_chip;
1010         mpic->hc_ipi.typename = name;
1011 #endif /* CONFIG_SMP */
1012
1013         mpic->flags = flags;
1014         mpic->isu_size = isu_size;
1015         mpic->irq_count = irq_count;
1016         mpic->num_sources = 0; /* so far */
1017
1018         if (flags & MPIC_LARGE_VECTORS)
1019                 intvec_top = 2047;
1020         else
1021                 intvec_top = 255;
1022
1023         mpic->timer_vecs[0] = intvec_top - 8;
1024         mpic->timer_vecs[1] = intvec_top - 7;
1025         mpic->timer_vecs[2] = intvec_top - 6;
1026         mpic->timer_vecs[3] = intvec_top - 5;
1027         mpic->ipi_vecs[0]   = intvec_top - 4;
1028         mpic->ipi_vecs[1]   = intvec_top - 3;
1029         mpic->ipi_vecs[2]   = intvec_top - 2;
1030         mpic->ipi_vecs[3]   = intvec_top - 1;
1031         mpic->spurious_vec  = intvec_top;
1032
1033         /* Check for "big-endian" in device-tree */
1034         if (node && of_get_property(node, "big-endian", NULL) != NULL)
1035                 mpic->flags |= MPIC_BIG_ENDIAN;
1036
1037
1038 #ifdef CONFIG_MPIC_WEIRD
1039         mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1040 #endif
1041
1042         /* default register type */
1043         mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1044                 mpic_access_mmio_be : mpic_access_mmio_le;
1045
1046         /* If no physical address is passed in, a device-node is mandatory */
1047         BUG_ON(paddr == 0 && node == NULL);
1048
1049         /* If no physical address passed in, check if it's dcr based */
1050         if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL)
1051                 mpic->flags |= MPIC_USES_DCR;
1052
1053 #ifdef CONFIG_PPC_DCR
1054         if (mpic->flags & MPIC_USES_DCR) {
1055                 const u32 *dbasep;
1056                 dbasep = of_get_property(node, "dcr-reg", NULL);
1057                 BUG_ON(dbasep == NULL);
1058                 mpic->dcr_base = *dbasep;
1059                 mpic->reg_type = mpic_access_dcr;
1060         }
1061 #else
1062         BUG_ON (mpic->flags & MPIC_USES_DCR);
1063 #endif /* CONFIG_PPC_DCR */
1064
1065         /* If the MPIC is not DCR based, and no physical address was passed
1066          * in, try to obtain one
1067          */
1068         if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1069                 const u32 *reg;
1070                 reg = of_get_property(node, "reg", NULL);
1071                 BUG_ON(reg == NULL);
1072                 paddr = of_translate_address(node, reg);
1073                 BUG_ON(paddr == OF_BAD_ADDR);
1074         }
1075
1076         /* Map the global registers */
1077         mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1078         mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1079
1080         /* Reset */
1081         if (flags & MPIC_WANTS_RESET) {
1082                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1083                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1084                            | MPIC_GREG_GCONF_RESET);
1085                 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1086                        & MPIC_GREG_GCONF_RESET)
1087                         mb();
1088         }
1089
1090         /* Read feature register, calculate num CPUs and, for non-ISU
1091          * MPICs, num sources as well. On ISU MPICs, sources are counted
1092          * as ISUs are added
1093          */
1094         reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1095         mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1096                           >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1097         if (isu_size == 0)
1098                 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1099                                      >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1100
1101         /* Map the per-CPU registers */
1102         for (i = 0; i < mpic->num_cpus; i++) {
1103                 mpic_map(mpic, paddr, &mpic->cpuregs[i],
1104                          MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1105                          0x1000);
1106         }
1107
1108         /* Initialize main ISU if none provided */
1109         if (mpic->isu_size == 0) {
1110                 mpic->isu_size = mpic->num_sources;
1111                 mpic_map(mpic, paddr, &mpic->isus[0],
1112                          MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1113         }
1114         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1115         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1116
1117         /* Display version */
1118         switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
1119         case 1:
1120                 vers = "1.0";
1121                 break;
1122         case 2:
1123                 vers = "1.2";
1124                 break;
1125         case 3:
1126                 vers = "1.3";
1127                 break;
1128         default:
1129                 vers = "<unknown>";
1130                 break;
1131         }
1132         printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1133                " max %d CPUs\n",
1134                name, vers, (unsigned long long)paddr, mpic->num_cpus);
1135         printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1136                mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1137
1138         mpic->next = mpics;
1139         mpics = mpic;
1140
1141         if (flags & MPIC_PRIMARY) {
1142                 mpic_primary = mpic;
1143                 irq_set_default_host(mpic->irqhost);
1144         }
1145
1146         return mpic;
1147 }
1148
1149 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1150                             phys_addr_t paddr)
1151 {
1152         unsigned int isu_first = isu_num * mpic->isu_size;
1153
1154         BUG_ON(isu_num >= MPIC_MAX_ISU);
1155
1156         mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1157                  MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1158         if ((isu_first + mpic->isu_size) > mpic->num_sources)
1159                 mpic->num_sources = isu_first + mpic->isu_size;
1160 }
1161
1162 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1163 {
1164         mpic->senses = senses;
1165         mpic->senses_count = count;
1166 }
1167
1168 void __init mpic_init(struct mpic *mpic)
1169 {
1170         int i;
1171
1172         BUG_ON(mpic->num_sources == 0);
1173
1174         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1175
1176         /* Set current processor priority to max */
1177         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1178
1179         /* Initialize timers: just disable them all */
1180         for (i = 0; i < 4; i++) {
1181                 mpic_write(mpic->tmregs,
1182                            i * MPIC_INFO(TIMER_STRIDE) +
1183                            MPIC_INFO(TIMER_DESTINATION), 0);
1184                 mpic_write(mpic->tmregs,
1185                            i * MPIC_INFO(TIMER_STRIDE) +
1186                            MPIC_INFO(TIMER_VECTOR_PRI),
1187                            MPIC_VECPRI_MASK |
1188                            (mpic->timer_vecs[0] + i));
1189         }
1190
1191         /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1192         mpic_test_broken_ipi(mpic);
1193         for (i = 0; i < 4; i++) {
1194                 mpic_ipi_write(i,
1195                                MPIC_VECPRI_MASK |
1196                                (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1197                                (mpic->ipi_vecs[0] + i));
1198         }
1199
1200         /* Initialize interrupt sources */
1201         if (mpic->irq_count == 0)
1202                 mpic->irq_count = mpic->num_sources;
1203
1204         /* Do the HT PIC fixups on U3 broken mpic */
1205         DBG("MPIC flags: %x\n", mpic->flags);
1206         if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1207                 mpic_scan_ht_pics(mpic);
1208                 mpic_u3msi_init(mpic);
1209         }
1210
1211         for (i = 0; i < mpic->num_sources; i++) {
1212                 /* start with vector = source number, and masked */
1213                 u32 vecpri = MPIC_VECPRI_MASK | i |
1214                         (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1215                 
1216                 /* init hw */
1217                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1218                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1219                                1 << hard_smp_processor_id());
1220         }
1221         
1222         /* Init spurious vector */
1223         mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1224
1225         /* Disable 8259 passthrough, if supported */
1226         if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1227                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1228                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1229                            | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1230
1231         /* Set current processor priority to 0 */
1232         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1233
1234 #ifdef CONFIG_PM
1235         /* allocate memory to save mpic state */
1236         mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1237         BUG_ON(mpic->save_data == NULL);
1238 #endif
1239 }
1240
1241 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1242 {
1243         u32 v;
1244
1245         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1246         v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1247         v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1248         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1249 }
1250
1251 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1252 {
1253         unsigned long flags;
1254         u32 v;
1255
1256         spin_lock_irqsave(&mpic_lock, flags);
1257         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1258         if (enable)
1259                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1260         else
1261                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1262         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1263         spin_unlock_irqrestore(&mpic_lock, flags);
1264 }
1265
1266 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1267 {
1268         int is_ipi;
1269         struct mpic *mpic = mpic_find(irq, &is_ipi);
1270         unsigned int src = mpic_irq_to_hw(irq);
1271         unsigned long flags;
1272         u32 reg;
1273
1274         spin_lock_irqsave(&mpic_lock, flags);
1275         if (is_ipi) {
1276                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1277                         ~MPIC_VECPRI_PRIORITY_MASK;
1278                 mpic_ipi_write(src - mpic->ipi_vecs[0],
1279                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1280         } else {
1281                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1282                         & ~MPIC_VECPRI_PRIORITY_MASK;
1283                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1284                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1285         }
1286         spin_unlock_irqrestore(&mpic_lock, flags);
1287 }
1288
1289 unsigned int mpic_irq_get_priority(unsigned int irq)
1290 {
1291         int is_ipi;
1292         struct mpic *mpic = mpic_find(irq, &is_ipi);
1293         unsigned int src = mpic_irq_to_hw(irq);
1294         unsigned long flags;
1295         u32 reg;
1296
1297         spin_lock_irqsave(&mpic_lock, flags);
1298         if (is_ipi)
1299                 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]);
1300         else
1301                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1302         spin_unlock_irqrestore(&mpic_lock, flags);
1303         return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1304 }
1305
1306 void mpic_setup_this_cpu(void)
1307 {
1308 #ifdef CONFIG_SMP
1309         struct mpic *mpic = mpic_primary;
1310         unsigned long flags;
1311         u32 msk = 1 << hard_smp_processor_id();
1312         unsigned int i;
1313
1314         BUG_ON(mpic == NULL);
1315
1316         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1317
1318         spin_lock_irqsave(&mpic_lock, flags);
1319
1320         /* let the mpic know we want intrs. default affinity is 0xffffffff
1321          * until changed via /proc. That's how it's done on x86. If we want
1322          * it differently, then we should make sure we also change the default
1323          * values of irq_desc[].affinity in irq.c.
1324          */
1325         if (distribute_irqs) {
1326                 for (i = 0; i < mpic->num_sources ; i++)
1327                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1328                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1329         }
1330
1331         /* Set current processor priority to 0 */
1332         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1333
1334         spin_unlock_irqrestore(&mpic_lock, flags);
1335 #endif /* CONFIG_SMP */
1336 }
1337
1338 int mpic_cpu_get_priority(void)
1339 {
1340         struct mpic *mpic = mpic_primary;
1341
1342         return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1343 }
1344
1345 void mpic_cpu_set_priority(int prio)
1346 {
1347         struct mpic *mpic = mpic_primary;
1348
1349         prio &= MPIC_CPU_TASKPRI_MASK;
1350         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1351 }
1352
1353 /*
1354  * XXX: someone who knows mpic should check this.
1355  * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1356  * or can we reset the mpic in the new kernel?
1357  */
1358 void mpic_teardown_this_cpu(int secondary)
1359 {
1360         struct mpic *mpic = mpic_primary;
1361         unsigned long flags;
1362         u32 msk = 1 << hard_smp_processor_id();
1363         unsigned int i;
1364
1365         BUG_ON(mpic == NULL);
1366
1367         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1368         spin_lock_irqsave(&mpic_lock, flags);
1369
1370         /* let the mpic know we don't want intrs.  */
1371         for (i = 0; i < mpic->num_sources ; i++)
1372                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1373                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1374
1375         /* Set current processor priority to max */
1376         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1377
1378         spin_unlock_irqrestore(&mpic_lock, flags);
1379 }
1380
1381
1382 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1383 {
1384         struct mpic *mpic = mpic_primary;
1385
1386         BUG_ON(mpic == NULL);
1387
1388 #ifdef DEBUG_IPI
1389         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1390 #endif
1391
1392         mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1393                        ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1394                        mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1395 }
1396
1397 unsigned int mpic_get_one_irq(struct mpic *mpic)
1398 {
1399         u32 src;
1400
1401         src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1402 #ifdef DEBUG_LOW
1403         DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1404 #endif
1405         if (unlikely(src == mpic->spurious_vec)) {
1406                 if (mpic->flags & MPIC_SPV_EOI)
1407                         mpic_eoi(mpic);
1408                 return NO_IRQ;
1409         }
1410         return irq_linear_revmap(mpic->irqhost, src);
1411 }
1412
1413 unsigned int mpic_get_irq(void)
1414 {
1415         struct mpic *mpic = mpic_primary;
1416
1417         BUG_ON(mpic == NULL);
1418
1419         return mpic_get_one_irq(mpic);
1420 }
1421
1422
1423 #ifdef CONFIG_SMP
1424 void mpic_request_ipis(void)
1425 {
1426         struct mpic *mpic = mpic_primary;
1427         int i, err;
1428         static char *ipi_names[] = {
1429                 "IPI0 (call function)",
1430                 "IPI1 (reschedule)",
1431                 "IPI2 (unused)",
1432                 "IPI3 (debugger break)",
1433         };
1434         BUG_ON(mpic == NULL);
1435
1436         printk(KERN_INFO "mpic: requesting IPIs ... \n");
1437
1438         for (i = 0; i < 4; i++) {
1439                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1440                                                        mpic->ipi_vecs[0] + i);
1441                 if (vipi == NO_IRQ) {
1442                         printk(KERN_ERR "Failed to map IPI %d\n", i);
1443                         break;
1444                 }
1445                 err = request_irq(vipi, mpic_ipi_action,
1446                                   IRQF_DISABLED|IRQF_PERCPU,
1447                                   ipi_names[i], mpic);
1448                 if (err) {
1449                         printk(KERN_ERR "Request of irq %d for IPI %d failed\n",
1450                                vipi, i);
1451                         break;
1452                 }
1453         }
1454 }
1455
1456 void smp_mpic_message_pass(int target, int msg)
1457 {
1458         /* make sure we're sending something that translates to an IPI */
1459         if ((unsigned int)msg > 3) {
1460                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1461                        smp_processor_id(), msg);
1462                 return;
1463         }
1464         switch (target) {
1465         case MSG_ALL:
1466                 mpic_send_ipi(msg, 0xffffffff);
1467                 break;
1468         case MSG_ALL_BUT_SELF:
1469                 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1470                 break;
1471         default:
1472                 mpic_send_ipi(msg, 1 << target);
1473                 break;
1474         }
1475 }
1476
1477 int __init smp_mpic_probe(void)
1478 {
1479         int nr_cpus;
1480
1481         DBG("smp_mpic_probe()...\n");
1482
1483         nr_cpus = cpus_weight(cpu_possible_map);
1484
1485         DBG("nr_cpus: %d\n", nr_cpus);
1486
1487         if (nr_cpus > 1)
1488                 mpic_request_ipis();
1489
1490         return nr_cpus;
1491 }
1492
1493 void __devinit smp_mpic_setup_cpu(int cpu)
1494 {
1495         mpic_setup_this_cpu();
1496 }
1497 #endif /* CONFIG_SMP */
1498
1499 #ifdef CONFIG_PM
1500 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1501 {
1502         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1503         int i;
1504
1505         for (i = 0; i < mpic->num_sources; i++) {
1506                 mpic->save_data[i].vecprio =
1507                         mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1508                 mpic->save_data[i].dest =
1509                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1510         }
1511
1512         return 0;
1513 }
1514
1515 static int mpic_resume(struct sys_device *dev)
1516 {
1517         struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1518         int i;
1519
1520         for (i = 0; i < mpic->num_sources; i++) {
1521                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1522                                mpic->save_data[i].vecprio);
1523                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1524                                mpic->save_data[i].dest);
1525
1526 #ifdef CONFIG_MPIC_U3_HT_IRQS
1527         {
1528                 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1529
1530                 if (fixup->base) {
1531                         /* we use the lowest bit in an inverted meaning */
1532                         if ((mpic->save_data[i].fixup_data & 1) == 0)
1533                                 continue;
1534
1535                         /* Enable and configure */
1536                         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1537
1538                         writel(mpic->save_data[i].fixup_data & ~1,
1539                                fixup->base + 4);
1540                 }
1541         }
1542 #endif
1543         } /* end for loop */
1544
1545         return 0;
1546 }
1547 #endif
1548
1549 static struct sysdev_class mpic_sysclass = {
1550 #ifdef CONFIG_PM
1551         .resume = mpic_resume,
1552         .suspend = mpic_suspend,
1553 #endif
1554         set_kset_name("mpic"),
1555 };
1556
1557 static int mpic_init_sys(void)
1558 {
1559         struct mpic *mpic = mpics;
1560         int error, id = 0;
1561
1562         error = sysdev_class_register(&mpic_sysclass);
1563
1564         while (mpic && !error) {
1565                 mpic->sysdev.cls = &mpic_sysclass;
1566                 mpic->sysdev.id = id++;
1567                 error = sysdev_register(&mpic->sysdev);
1568                 mpic = mpic->next;
1569         }
1570         return error;
1571 }
1572
1573 device_initcall(mpic_init_sys);