git.oblomov.eu Git - linux-2.6/blob - arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28
  29 #include <asm/desc.h>
  30
  31 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  32
  33 MODULE_AUTHOR("Qumranet");
  34 MODULE_LICENSE("GPL");
  35
  36 #define IOPM_ALLOC_ORDER 2
  37 #define MSRPM_ALLOC_ORDER 1
  38
  39 #define DR7_GD_MASK (1 << 13)
  40 #define DR6_BD_MASK (1 << 13)
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_FEATURE_SVML (1 << 2)
  48
  49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  50
  51 /* enable NPT for AMD64 and X86 with PAE */
  52 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  53 static bool npt_enabled = true;
  54 #else
  55 static bool npt_enabled = false;
  56 #endif
  57 static int npt = 1;
  58
  59 module_param(npt, int, S_IRUGO);
  60
  61 static void kvm_reput_irq(struct vcpu_svm *svm);
  62 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  63
  64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  65 {
  66         return container_of(vcpu, struct vcpu_svm, vcpu);
  67 }
  68
  69 static unsigned long iopm_base;
  70
  71 struct kvm_ldttss_desc {
  72         u16 limit0;
  73         u16 base0;
  74         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  75         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  76         u32 base3;
  77         u32 zero1;
  78 } __attribute__((packed));
  79
  80 struct svm_cpu_data {
  81         int cpu;
  82
  83         u64 asid_generation;
  84         u32 max_asid;
  85         u32 next_asid;
  86         struct kvm_ldttss_desc *tss_desc;
  87
  88         struct page *save_area;
  89 };
  90
  91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  92 static uint32_t svm_features;
  93
  94 struct svm_init_data {
  95         int cpu;
  96         int r;
  97 };
  98
  99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 100
 101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 102 #define MSRS_RANGE_SIZE 2048
 103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 104
 105 #define MAX_INST_SIZE 15
 106
 107 static inline u32 svm_has(u32 feat)
 108 {
 109         return svm_features & feat;
 110 }
 111
 112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 113 {
 114         int word_index = __ffs(vcpu->arch.irq_summary);
 115         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 116         int irq = word_index * BITS_PER_LONG + bit_index;
 117
 118         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 119         if (!vcpu->arch.irq_pending[word_index])
 120                 clear_bit(word_index, &vcpu->arch.irq_summary);
 121         return irq;
 122 }
 123
 124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 125 {
 126         set_bit(irq, vcpu->arch.irq_pending);
 127         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 128 }
 129
 130 static inline void clgi(void)
 131 {
 132         asm volatile (__ex(SVM_CLGI));
 133 }
 134
 135 static inline void stgi(void)
 136 {
 137         asm volatile (__ex(SVM_STGI));
 138 }
 139
 140 static inline void invlpga(unsigned long addr, u32 asid)
 141 {
 142         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 143 }
 144
 145 static inline unsigned long kvm_read_cr2(void)
 146 {
 147         unsigned long cr2;
 148
 149         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 150         return cr2;
 151 }
 152
 153 static inline void kvm_write_cr2(unsigned long val)
 154 {
 155         asm volatile ("mov %0, %%cr2" :: "r" (val));
 156 }
 157
 158 static inline unsigned long read_dr6(void)
 159 {
 160         unsigned long dr6;
 161
 162         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 163         return dr6;
 164 }
 165
 166 static inline void write_dr6(unsigned long val)
 167 {
 168         asm volatile ("mov %0, %%dr6" :: "r" (val));
 169 }
 170
 171 static inline unsigned long read_dr7(void)
 172 {
 173         unsigned long dr7;
 174
 175         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 176         return dr7;
 177 }
 178
 179 static inline void write_dr7(unsigned long val)
 180 {
 181         asm volatile ("mov %0, %%dr7" :: "r" (val));
 182 }
 183
 184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 185 {
 186         to_svm(vcpu)->asid_generation--;
 187 }
 188
 189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 190 {
 191         force_new_asid(vcpu);
 192 }
 193
 194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 195 {
 196         if (!npt_enabled && !(efer & EFER_LMA))
 197                 efer &= ~EFER_LME;
 198
 199         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 200         vcpu->arch.shadow_efer = efer;
 201 }
 202
 203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 204                                 bool has_error_code, u32 error_code)
 205 {
 206         struct vcpu_svm *svm = to_svm(vcpu);
 207
 208         svm->vmcb->control.event_inj = nr
 209                 | SVM_EVTINJ_VALID
 210                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 211                 | SVM_EVTINJ_TYPE_EXEPT;
 212         svm->vmcb->control.event_inj_err = error_code;
 213 }
 214
 215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 220 }
 221
 222 static int is_external_interrupt(u32 info)
 223 {
 224         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 225         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 226 }
 227
 228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 229 {
 230         struct vcpu_svm *svm = to_svm(vcpu);
 231
 232         if (!svm->next_rip) {
 233                 printk(KERN_DEBUG "%s: NOP\n", __func__);
 234                 return;
 235         }
 236         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 237                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 238                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 239
 240         kvm_rip_write(vcpu, svm->next_rip);
 241         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 242
 243         vcpu->arch.interrupt_window_open = 1;
 244 }
 245
 246 static int has_svm(void)
 247 {
 248         uint32_t eax, ebx, ecx, edx;
 249
 250         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 251                 printk(KERN_INFO "has_svm: not amd\n");
 252                 return 0;
 253         }
 254
 255         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 256         if (eax < SVM_CPUID_FUNC) {
 257                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 258                 return 0;
 259         }
 260
 261         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 262         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 263                 printk(KERN_DEBUG "has_svm: svm not available\n");
 264                 return 0;
 265         }
 266         return 1;
 267 }
 268
 269 static void svm_hardware_disable(void *garbage)
 270 {
 271         uint64_t efer;
 272
 273         wrmsrl(MSR_VM_HSAVE_PA, 0);
 274         rdmsrl(MSR_EFER, efer);
 275         wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 276 }
 277
 278 static void svm_hardware_enable(void *garbage)
 279 {
 280
 281         struct svm_cpu_data *svm_data;
 282         uint64_t efer;
 283         struct desc_ptr gdt_descr;
 284         struct desc_struct *gdt;
 285         int me = raw_smp_processor_id();
 286
 287         if (!has_svm()) {
 288                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 289                 return;
 290         }
 291         svm_data = per_cpu(svm_data, me);
 292
 293         if (!svm_data) {
 294                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 295                        me);
 296                 return;
 297         }
 298
 299         svm_data->asid_generation = 1;
 300         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 301         svm_data->next_asid = svm_data->max_asid + 1;
 302
 303         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 304         gdt = (struct desc_struct *)gdt_descr.address;
 305         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 306
 307         rdmsrl(MSR_EFER, efer);
 308         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 309
 310         wrmsrl(MSR_VM_HSAVE_PA,
 311                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 312 }
 313
 314 static void svm_cpu_uninit(int cpu)
 315 {
 316         struct svm_cpu_data *svm_data
 317                 = per_cpu(svm_data, raw_smp_processor_id());
 318
 319         if (!svm_data)
 320                 return;
 321
 322         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 323         __free_page(svm_data->save_area);
 324         kfree(svm_data);
 325 }
 326
 327 static int svm_cpu_init(int cpu)
 328 {
 329         struct svm_cpu_data *svm_data;
 330         int r;
 331
 332         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 333         if (!svm_data)
 334                 return -ENOMEM;
 335         svm_data->cpu = cpu;
 336         svm_data->save_area = alloc_page(GFP_KERNEL);
 337         r = -ENOMEM;
 338         if (!svm_data->save_area)
 339                 goto err_1;
 340
 341         per_cpu(svm_data, cpu) = svm_data;
 342
 343         return 0;
 344
 345 err_1:
 346         kfree(svm_data);
 347         return r;
 348
 349 }
 350
 351 static void set_msr_interception(u32 *msrpm, unsigned msr,
 352                                  int read, int write)
 353 {
 354         int i;
 355
 356         for (i = 0; i < NUM_MSR_MAPS; i++) {
 357                 if (msr >= msrpm_ranges[i] &&
 358                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 359                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 360                                           msrpm_ranges[i]) * 2;
 361
 362                         u32 *base = msrpm + (msr_offset / 32);
 363                         u32 msr_shift = msr_offset % 32;
 364                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 365                         *base = (*base & ~(0x3 << msr_shift)) |
 366                                 (mask << msr_shift);
 367                         return;
 368                 }
 369         }
 370         BUG();
 371 }
 372
 373 static void svm_vcpu_init_msrpm(u32 *msrpm)
 374 {
 375         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 376
 377 #ifdef CONFIG_X86_64
 378         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 379         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 380         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 381         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 382         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 383         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 384 #endif
 385         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 386         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 387         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 388         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 389 }
 390
 391 static void svm_enable_lbrv(struct vcpu_svm *svm)
 392 {
 393         u32 *msrpm = svm->msrpm;
 394
 395         svm->vmcb->control.lbr_ctl = 1;
 396         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 397         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 398         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 399         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 400 }
 401
 402 static void svm_disable_lbrv(struct vcpu_svm *svm)
 403 {
 404         u32 *msrpm = svm->msrpm;
 405
 406         svm->vmcb->control.lbr_ctl = 0;
 407         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 408         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 409         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 410         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 411 }
 412
 413 static __init int svm_hardware_setup(void)
 414 {
 415         int cpu;
 416         struct page *iopm_pages;
 417         void *iopm_va;
 418         int r;
 419
 420         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 421
 422         if (!iopm_pages)
 423                 return -ENOMEM;
 424
 425         iopm_va = page_address(iopm_pages);
 426         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 427         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 428         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 429
 430         if (boot_cpu_has(X86_FEATURE_NX))
 431                 kvm_enable_efer_bits(EFER_NX);
 432
 433         for_each_online_cpu(cpu) {
 434                 r = svm_cpu_init(cpu);
 435                 if (r)
 436                         goto err;
 437         }
 438
 439         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 440
 441         if (!svm_has(SVM_FEATURE_NPT))
 442                 npt_enabled = false;
 443
 444         if (npt_enabled && !npt) {
 445                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 446                 npt_enabled = false;
 447         }
 448
 449         if (npt_enabled) {
 450                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 451                 kvm_enable_tdp();
 452         } else
 453                 kvm_disable_tdp();
 454
 455         return 0;
 456
 457 err:
 458         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 459         iopm_base = 0;
 460         return r;
 461 }
 462
 463 static __exit void svm_hardware_unsetup(void)
 464 {
 465         int cpu;
 466
 467         for_each_online_cpu(cpu)
 468                 svm_cpu_uninit(cpu);
 469
 470         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 471         iopm_base = 0;
 472 }
 473
 474 static void init_seg(struct vmcb_seg *seg)
 475 {
 476         seg->selector = 0;
 477         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 478                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 479         seg->limit = 0xffff;
 480         seg->base = 0;
 481 }
 482
 483 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 484 {
 485         seg->selector = 0;
 486         seg->attrib = SVM_SELECTOR_P_MASK | type;
 487         seg->limit = 0xffff;
 488         seg->base = 0;
 489 }
 490
 491 static void init_vmcb(struct vcpu_svm *svm)
 492 {
 493         struct vmcb_control_area *control = &svm->vmcb->control;
 494         struct vmcb_save_area *save = &svm->vmcb->save;
 495
 496         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 497                                         INTERCEPT_CR3_MASK |
 498                                         INTERCEPT_CR4_MASK;
 499
 500         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 501                                         INTERCEPT_CR3_MASK |
 502                                         INTERCEPT_CR4_MASK |
 503                                         INTERCEPT_CR8_MASK;
 504
 505         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 506                                         INTERCEPT_DR1_MASK |
 507                                         INTERCEPT_DR2_MASK |
 508                                         INTERCEPT_DR3_MASK;
 509
 510         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 511                                         INTERCEPT_DR1_MASK |
 512                                         INTERCEPT_DR2_MASK |
 513                                         INTERCEPT_DR3_MASK |
 514                                         INTERCEPT_DR5_MASK |
 515                                         INTERCEPT_DR7_MASK;
 516
 517         control->intercept_exceptions = (1 << PF_VECTOR) |
 518                                         (1 << UD_VECTOR) |
 519                                         (1 << MC_VECTOR);
 520
 521
 522         control->intercept =    (1ULL << INTERCEPT_INTR) |
 523                                 (1ULL << INTERCEPT_NMI) |
 524                                 (1ULL << INTERCEPT_SMI) |
 525                                 (1ULL << INTERCEPT_CPUID) |
 526                                 (1ULL << INTERCEPT_INVD) |
 527                                 (1ULL << INTERCEPT_HLT) |
 528                                 (1ULL << INTERCEPT_INVLPG) |
 529                                 (1ULL << INTERCEPT_INVLPGA) |
 530                                 (1ULL << INTERCEPT_IOIO_PROT) |
 531                                 (1ULL << INTERCEPT_MSR_PROT) |
 532                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 533                                 (1ULL << INTERCEPT_SHUTDOWN) |
 534                                 (1ULL << INTERCEPT_VMRUN) |
 535                                 (1ULL << INTERCEPT_VMMCALL) |
 536                                 (1ULL << INTERCEPT_VMLOAD) |
 537                                 (1ULL << INTERCEPT_VMSAVE) |
 538                                 (1ULL << INTERCEPT_STGI) |
 539                                 (1ULL << INTERCEPT_CLGI) |
 540                                 (1ULL << INTERCEPT_SKINIT) |
 541                                 (1ULL << INTERCEPT_WBINVD) |
 542                                 (1ULL << INTERCEPT_MONITOR) |
 543                                 (1ULL << INTERCEPT_MWAIT);
 544
 545         control->iopm_base_pa = iopm_base;
 546         control->msrpm_base_pa = __pa(svm->msrpm);
 547         control->tsc_offset = 0;
 548         control->int_ctl = V_INTR_MASKING_MASK;
 549
 550         init_seg(&save->es);
 551         init_seg(&save->ss);
 552         init_seg(&save->ds);
 553         init_seg(&save->fs);
 554         init_seg(&save->gs);
 555
 556         save->cs.selector = 0xf000;
 557         /* Executable/Readable Code Segment */
 558         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 559                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 560         save->cs.limit = 0xffff;
 561         /*
 562          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 563          * be consistent with it.
 564          *
 565          * Replace when we have real mode working for vmx.
 566          */
 567         save->cs.base = 0xf0000;
 568
 569         save->gdtr.limit = 0xffff;
 570         save->idtr.limit = 0xffff;
 571
 572         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 573         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 574
 575         save->efer = MSR_EFER_SVME_MASK;
 576         save->dr6 = 0xffff0ff0;
 577         save->dr7 = 0x400;
 578         save->rflags = 2;
 579         save->rip = 0x0000fff0;
 580         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 581
 582         /*
 583          * cr0 val on cpu init should be 0x60000010, we enable cpu
 584          * cache by default. the orderly way is to enable cache in bios.
 585          */
 586         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 587         save->cr4 = X86_CR4_PAE;
 588         /* rdx = ?? */
 589
 590         if (npt_enabled) {
 591                 /* Setup VMCB for Nested Paging */
 592                 control->nested_ctl = 1;
 593                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 594                                         (1ULL << INTERCEPT_INVLPG));
 595                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 596                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 597                                                 INTERCEPT_CR3_MASK);
 598                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 599                                                  INTERCEPT_CR3_MASK);
 600                 save->g_pat = 0x0007040600070406ULL;
 601                 /* enable caching because the QEMU Bios doesn't enable it */
 602                 save->cr0 = X86_CR0_ET;
 603                 save->cr3 = 0;
 604                 save->cr4 = 0;
 605         }
 606         force_new_asid(&svm->vcpu);
 607 }
 608
 609 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 610 {
 611         struct vcpu_svm *svm = to_svm(vcpu);
 612
 613         init_vmcb(svm);
 614
 615         if (vcpu->vcpu_id != 0) {
 616                 kvm_rip_write(vcpu, 0);
 617                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 618                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 619         }
 620         vcpu->arch.regs_avail = ~0;
 621         vcpu->arch.regs_dirty = ~0;
 622
 623         return 0;
 624 }
 625
 626 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 627 {
 628         struct vcpu_svm *svm;
 629         struct page *page;
 630         struct page *msrpm_pages;
 631         int err;
 632
 633         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 634         if (!svm) {
 635                 err = -ENOMEM;
 636                 goto out;
 637         }
 638
 639         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 640         if (err)
 641                 goto free_svm;
 642
 643         page = alloc_page(GFP_KERNEL);
 644         if (!page) {
 645                 err = -ENOMEM;
 646                 goto uninit;
 647         }
 648
 649         err = -ENOMEM;
 650         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 651         if (!msrpm_pages)
 652                 goto uninit;
 653         svm->msrpm = page_address(msrpm_pages);
 654         svm_vcpu_init_msrpm(svm->msrpm);
 655
 656         svm->vmcb = page_address(page);
 657         clear_page(svm->vmcb);
 658         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 659         svm->asid_generation = 0;
 660         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 661         init_vmcb(svm);
 662
 663         fx_init(&svm->vcpu);
 664         svm->vcpu.fpu_active = 1;
 665         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 666         if (svm->vcpu.vcpu_id == 0)
 667                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 668
 669         return &svm->vcpu;
 670
 671 uninit:
 672         kvm_vcpu_uninit(&svm->vcpu);
 673 free_svm:
 674         kmem_cache_free(kvm_vcpu_cache, svm);
 675 out:
 676         return ERR_PTR(err);
 677 }
 678
 679 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 680 {
 681         struct vcpu_svm *svm = to_svm(vcpu);
 682
 683         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 684         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 685         kvm_vcpu_uninit(vcpu);
 686         kmem_cache_free(kvm_vcpu_cache, svm);
 687 }
 688
 689 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 690 {
 691         struct vcpu_svm *svm = to_svm(vcpu);
 692         int i;
 693
 694         if (unlikely(cpu != vcpu->cpu)) {
 695                 u64 tsc_this, delta;
 696
 697                 /*
 698                  * Make sure that the guest sees a monotonically
 699                  * increasing TSC.
 700                  */
 701                 rdtscll(tsc_this);
 702                 delta = vcpu->arch.host_tsc - tsc_this;
 703                 svm->vmcb->control.tsc_offset += delta;
 704                 vcpu->cpu = cpu;
 705                 kvm_migrate_timers(vcpu);
 706         }
 707
 708         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 709                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 710 }
 711
 712 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 713 {
 714         struct vcpu_svm *svm = to_svm(vcpu);
 715         int i;
 716
 717         ++vcpu->stat.host_state_reload;
 718         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 719                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 720
 721         rdtscll(vcpu->arch.host_tsc);
 722 }
 723
 724 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 725 {
 726         return to_svm(vcpu)->vmcb->save.rflags;
 727 }
 728
 729 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 730 {
 731         to_svm(vcpu)->vmcb->save.rflags = rflags;
 732 }
 733
 734 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 735 {
 736         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 737
 738         switch (seg) {
 739         case VCPU_SREG_CS: return &save->cs;
 740         case VCPU_SREG_DS: return &save->ds;
 741         case VCPU_SREG_ES: return &save->es;
 742         case VCPU_SREG_FS: return &save->fs;
 743         case VCPU_SREG_GS: return &save->gs;
 744         case VCPU_SREG_SS: return &save->ss;
 745         case VCPU_SREG_TR: return &save->tr;
 746         case VCPU_SREG_LDTR: return &save->ldtr;
 747         }
 748         BUG();
 749         return NULL;
 750 }
 751
 752 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 753 {
 754         struct vmcb_seg *s = svm_seg(vcpu, seg);
 755
 756         return s->base;
 757 }
 758
 759 static void svm_get_segment(struct kvm_vcpu *vcpu,
 760                             struct kvm_segment *var, int seg)
 761 {
 762         struct vmcb_seg *s = svm_seg(vcpu, seg);
 763
 764         var->base = s->base;
 765         var->limit = s->limit;
 766         var->selector = s->selector;
 767         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 768         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 769         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 770         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 771         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 772         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 773         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 774         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 775
 776         /*
 777          * SVM always stores 0 for the 'G' bit in the CS selector in
 778          * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 779          * Intel's VMENTRY has a check on the 'G' bit.
 780          */
 781         if (seg == VCPU_SREG_CS)
 782                 var->g = s->limit > 0xfffff;
 783
 784         /*
 785          * Work around a bug where the busy flag in the tr selector
 786          * isn't exposed
 787          */
 788         if (seg == VCPU_SREG_TR)
 789                 var->type |= 0x2;
 790
 791         var->unusable = !var->present;
 792 }
 793
 794 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 795 {
 796         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 797
 798         return save->cpl;
 799 }
 800
 801 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 802 {
 803         struct vcpu_svm *svm = to_svm(vcpu);
 804
 805         dt->limit = svm->vmcb->save.idtr.limit;
 806         dt->base = svm->vmcb->save.idtr.base;
 807 }
 808
 809 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 810 {
 811         struct vcpu_svm *svm = to_svm(vcpu);
 812
 813         svm->vmcb->save.idtr.limit = dt->limit;
 814         svm->vmcb->save.idtr.base = dt->base ;
 815 }
 816
 817 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 818 {
 819         struct vcpu_svm *svm = to_svm(vcpu);
 820
 821         dt->limit = svm->vmcb->save.gdtr.limit;
 822         dt->base = svm->vmcb->save.gdtr.base;
 823 }
 824
 825 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 826 {
 827         struct vcpu_svm *svm = to_svm(vcpu);
 828
 829         svm->vmcb->save.gdtr.limit = dt->limit;
 830         svm->vmcb->save.gdtr.base = dt->base ;
 831 }
 832
 833 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 834 {
 835 }
 836
 837 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 838 {
 839         struct vcpu_svm *svm = to_svm(vcpu);
 840
 841 #ifdef CONFIG_X86_64
 842         if (vcpu->arch.shadow_efer & EFER_LME) {
 843                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 844                         vcpu->arch.shadow_efer |= EFER_LMA;
 845                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 846                 }
 847
 848                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 849                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 850                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 851                 }
 852         }
 853 #endif
 854         if (npt_enabled)
 855                 goto set;
 856
 857         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 858                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 859                 vcpu->fpu_active = 1;
 860         }
 861
 862         vcpu->arch.cr0 = cr0;
 863         cr0 |= X86_CR0_PG | X86_CR0_WP;
 864         if (!vcpu->fpu_active) {
 865                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 866                 cr0 |= X86_CR0_TS;
 867         }
 868 set:
 869         /*
 870          * re-enable caching here because the QEMU bios
 871          * does not do it - this results in some delay at
 872          * reboot
 873          */
 874         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 875         svm->vmcb->save.cr0 = cr0;
 876 }
 877
 878 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 879 {
 880         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 881         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 882
 883         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 884                 force_new_asid(vcpu);
 885
 886         vcpu->arch.cr4 = cr4;
 887         if (!npt_enabled)
 888                 cr4 |= X86_CR4_PAE;
 889         cr4 |= host_cr4_mce;
 890         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 891 }
 892
 893 static void svm_set_segment(struct kvm_vcpu *vcpu,
 894                             struct kvm_segment *var, int seg)
 895 {
 896         struct vcpu_svm *svm = to_svm(vcpu);
 897         struct vmcb_seg *s = svm_seg(vcpu, seg);
 898
 899         s->base = var->base;
 900         s->limit = var->limit;
 901         s->selector = var->selector;
 902         if (var->unusable)
 903                 s->attrib = 0;
 904         else {
 905                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 906                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 907                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 908                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 909                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 910                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 911                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 912                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 913         }
 914         if (seg == VCPU_SREG_CS)
 915                 svm->vmcb->save.cpl
 916                         = (svm->vmcb->save.cs.attrib
 917                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 918
 919 }
 920
 921 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 922 {
 923         return -EOPNOTSUPP;
 924 }
 925
 926 static int svm_get_irq(struct kvm_vcpu *vcpu)
 927 {
 928         struct vcpu_svm *svm = to_svm(vcpu);
 929         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 930
 931         if (is_external_interrupt(exit_int_info))
 932                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 933         return -1;
 934 }
 935
 936 static void load_host_msrs(struct kvm_vcpu *vcpu)
 937 {
 938 #ifdef CONFIG_X86_64
 939         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 940 #endif
 941 }
 942
 943 static void save_host_msrs(struct kvm_vcpu *vcpu)
 944 {
 945 #ifdef CONFIG_X86_64
 946         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 947 #endif
 948 }
 949
 950 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 951 {
 952         if (svm_data->next_asid > svm_data->max_asid) {
 953                 ++svm_data->asid_generation;
 954                 svm_data->next_asid = 1;
 955                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 956         }
 957
 958         svm->vcpu.cpu = svm_data->cpu;
 959         svm->asid_generation = svm_data->asid_generation;
 960         svm->vmcb->control.asid = svm_data->next_asid++;
 961 }
 962
 963 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 964 {
 965         unsigned long val = to_svm(vcpu)->db_regs[dr];
 966         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 967         return val;
 968 }
 969
 970 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 971                        int *exception)
 972 {
 973         struct vcpu_svm *svm = to_svm(vcpu);
 974
 975         *exception = 0;
 976
 977         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 978                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 979                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 980                 *exception = DB_VECTOR;
 981                 return;
 982         }
 983
 984         switch (dr) {
 985         case 0 ... 3:
 986                 svm->db_regs[dr] = value;
 987                 return;
 988         case 4 ... 5:
 989                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 990                         *exception = UD_VECTOR;
 991                         return;
 992                 }
 993         case 7: {
 994                 if (value & ~((1ULL << 32) - 1)) {
 995                         *exception = GP_VECTOR;
 996                         return;
 997                 }
 998                 svm->vmcb->save.dr7 = value;
 999                 return;
1000         }
1001         default:
1002                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1003                        __func__, dr);
1004                 *exception = UD_VECTOR;
1005                 return;
1006         }
1007 }
1008
1009 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1010 {
1011         u32 exit_int_info = svm->vmcb->control.exit_int_info;
1012         struct kvm *kvm = svm->vcpu.kvm;
1013         u64 fault_address;
1014         u32 error_code;
1015         bool event_injection = false;
1016
1017         if (!irqchip_in_kernel(kvm) &&
1018             is_external_interrupt(exit_int_info)) {
1019                 event_injection = true;
1020                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1021         }
1022
1023         fault_address  = svm->vmcb->control.exit_info_2;
1024         error_code = svm->vmcb->control.exit_info_1;
1025
1026         if (!npt_enabled)
1027                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1028                             (u32)fault_address, (u32)(fault_address >> 32),
1029                             handler);
1030         else
1031                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1032                             (u32)fault_address, (u32)(fault_address >> 32),
1033                             handler);
1034         /*
1035          * FIXME: Tis shouldn't be necessary here, but there is a flush
1036          * missing in the MMU code. Until we find this bug, flush the
1037          * complete TLB here on an NPF
1038          */
1039         if (npt_enabled)
1040                 svm_flush_tlb(&svm->vcpu);
1041
1042         if (!npt_enabled && event_injection)
1043                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1044         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1045 }
1046
1047 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1048 {
1049         int er;
1050
1051         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1052         if (er != EMULATE_DONE)
1053                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1054         return 1;
1055 }
1056
1057 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1058 {
1059         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1060         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1061                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1062         svm->vcpu.fpu_active = 1;
1063
1064         return 1;
1065 }
1066
1067 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1068 {
1069         /*
1070          * On an #MC intercept the MCE handler is not called automatically in
1071          * the host. So do it by hand here.
1072          */
1073         asm volatile (
1074                 "int $0x12\n");
1075         /* not sure if we ever come back to this point */
1076
1077         return 1;
1078 }
1079
1080 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1081 {
1082         /*
1083          * VMCB is undefined after a SHUTDOWN intercept
1084          * so reinitialize it.
1085          */
1086         clear_page(svm->vmcb);
1087         init_vmcb(svm);
1088
1089         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1090         return 0;
1091 }
1092
1093 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1094 {
1095         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1096         int size, down, in, string, rep;
1097         unsigned port;
1098
1099         ++svm->vcpu.stat.io_exits;
1100
1101         svm->next_rip = svm->vmcb->control.exit_info_2;
1102
1103         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1104
1105         if (string) {
1106                 if (emulate_instruction(&svm->vcpu,
1107                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1108                         return 0;
1109                 return 1;
1110         }
1111
1112         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1113         port = io_info >> 16;
1114         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1115         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1116         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1117
1118         skip_emulated_instruction(&svm->vcpu);
1119         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1120 }
1121
1122 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1123 {
1124         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1125         return 1;
1126 }
1127
1128 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1129 {
1130         ++svm->vcpu.stat.irq_exits;
1131         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1132         return 1;
1133 }
1134
1135 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1136 {
1137         return 1;
1138 }
1139
1140 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1141 {
1142         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1143         skip_emulated_instruction(&svm->vcpu);
1144         return kvm_emulate_halt(&svm->vcpu);
1145 }
1146
1147 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1148 {
1149         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1150         skip_emulated_instruction(&svm->vcpu);
1151         kvm_emulate_hypercall(&svm->vcpu);
1152         return 1;
1153 }
1154
1155 static int invalid_op_interception(struct vcpu_svm *svm,
1156                                    struct kvm_run *kvm_run)
1157 {
1158         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1159         return 1;
1160 }
1161
1162 static int task_switch_interception(struct vcpu_svm *svm,
1163                                     struct kvm_run *kvm_run)
1164 {
1165         u16 tss_selector;
1166
1167         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1168         if (svm->vmcb->control.exit_info_2 &
1169             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1170                 return kvm_task_switch(&svm->vcpu, tss_selector,
1171                                        TASK_SWITCH_IRET);
1172         if (svm->vmcb->control.exit_info_2 &
1173             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1174                 return kvm_task_switch(&svm->vcpu, tss_selector,
1175                                        TASK_SWITCH_JMP);
1176         return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1177 }
1178
1179 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1180 {
1181         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1182         kvm_emulate_cpuid(&svm->vcpu);
1183         return 1;
1184 }
1185
1186 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1187 {
1188         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1189                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1190         return 1;
1191 }
1192
1193 static int emulate_on_interception(struct vcpu_svm *svm,
1194                                    struct kvm_run *kvm_run)
1195 {
1196         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1197                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1198         return 1;
1199 }
1200
1201 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1202 {
1203         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1204         if (irqchip_in_kernel(svm->vcpu.kvm))
1205                 return 1;
1206         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1207         return 0;
1208 }
1209
1210 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1211 {
1212         struct vcpu_svm *svm = to_svm(vcpu);
1213
1214         switch (ecx) {
1215         case MSR_IA32_TIME_STAMP_COUNTER: {
1216                 u64 tsc;
1217
1218                 rdtscll(tsc);
1219                 *data = svm->vmcb->control.tsc_offset + tsc;
1220                 break;
1221         }
1222         case MSR_K6_STAR:
1223                 *data = svm->vmcb->save.star;
1224                 break;
1225 #ifdef CONFIG_X86_64
1226         case MSR_LSTAR:
1227                 *data = svm->vmcb->save.lstar;
1228                 break;
1229         case MSR_CSTAR:
1230                 *data = svm->vmcb->save.cstar;
1231                 break;
1232         case MSR_KERNEL_GS_BASE:
1233                 *data = svm->vmcb->save.kernel_gs_base;
1234                 break;
1235         case MSR_SYSCALL_MASK:
1236                 *data = svm->vmcb->save.sfmask;
1237                 break;
1238 #endif
1239         case MSR_IA32_SYSENTER_CS:
1240                 *data = svm->vmcb->save.sysenter_cs;
1241                 break;
1242         case MSR_IA32_SYSENTER_EIP:
1243                 *data = svm->vmcb->save.sysenter_eip;
1244                 break;
1245         case MSR_IA32_SYSENTER_ESP:
1246                 *data = svm->vmcb->save.sysenter_esp;
1247                 break;
1248         /* Nobody will change the following 5 values in the VMCB so
1249            we can safely return them on rdmsr. They will always be 0
1250            until LBRV is implemented. */
1251         case MSR_IA32_DEBUGCTLMSR:
1252                 *data = svm->vmcb->save.dbgctl;
1253                 break;
1254         case MSR_IA32_LASTBRANCHFROMIP:
1255                 *data = svm->vmcb->save.br_from;
1256                 break;
1257         case MSR_IA32_LASTBRANCHTOIP:
1258                 *data = svm->vmcb->save.br_to;
1259                 break;
1260         case MSR_IA32_LASTINTFROMIP:
1261                 *data = svm->vmcb->save.last_excp_from;
1262                 break;
1263         case MSR_IA32_LASTINTTOIP:
1264                 *data = svm->vmcb->save.last_excp_to;
1265                 break;
1266         default:
1267                 return kvm_get_msr_common(vcpu, ecx, data);
1268         }
1269         return 0;
1270 }
1271
1272 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1273 {
1274         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1275         u64 data;
1276
1277         if (svm_get_msr(&svm->vcpu, ecx, &data))
1278                 kvm_inject_gp(&svm->vcpu, 0);
1279         else {
1280                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1281                             (u32)(data >> 32), handler);
1282
1283                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
1284                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1285                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1286                 skip_emulated_instruction(&svm->vcpu);
1287         }
1288         return 1;
1289 }
1290
1291 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1292 {
1293         struct vcpu_svm *svm = to_svm(vcpu);
1294
1295         switch (ecx) {
1296         case MSR_IA32_TIME_STAMP_COUNTER: {
1297                 u64 tsc;
1298
1299                 rdtscll(tsc);
1300                 svm->vmcb->control.tsc_offset = data - tsc;
1301                 break;
1302         }
1303         case MSR_K6_STAR:
1304                 svm->vmcb->save.star = data;
1305                 break;
1306 #ifdef CONFIG_X86_64
1307         case MSR_LSTAR:
1308                 svm->vmcb->save.lstar = data;
1309                 break;
1310         case MSR_CSTAR:
1311                 svm->vmcb->save.cstar = data;
1312                 break;
1313         case MSR_KERNEL_GS_BASE:
1314                 svm->vmcb->save.kernel_gs_base = data;
1315                 break;
1316         case MSR_SYSCALL_MASK:
1317                 svm->vmcb->save.sfmask = data;
1318                 break;
1319 #endif
1320         case MSR_IA32_SYSENTER_CS:
1321                 svm->vmcb->save.sysenter_cs = data;
1322                 break;
1323         case MSR_IA32_SYSENTER_EIP:
1324                 svm->vmcb->save.sysenter_eip = data;
1325                 break;
1326         case MSR_IA32_SYSENTER_ESP:
1327                 svm->vmcb->save.sysenter_esp = data;
1328                 break;
1329         case MSR_IA32_DEBUGCTLMSR:
1330                 if (!svm_has(SVM_FEATURE_LBRV)) {
1331                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1332                                         __func__, data);
1333                         break;
1334                 }
1335                 if (data & DEBUGCTL_RESERVED_BITS)
1336                         return 1;
1337
1338                 svm->vmcb->save.dbgctl = data;
1339                 if (data & (1ULL<<0))
1340                         svm_enable_lbrv(svm);
1341                 else
1342                         svm_disable_lbrv(svm);
1343                 break;
1344         case MSR_K7_EVNTSEL0:
1345         case MSR_K7_EVNTSEL1:
1346         case MSR_K7_EVNTSEL2:
1347         case MSR_K7_EVNTSEL3:
1348         case MSR_K7_PERFCTR0:
1349         case MSR_K7_PERFCTR1:
1350         case MSR_K7_PERFCTR2:
1351         case MSR_K7_PERFCTR3:
1352                 /*
1353                  * Just discard all writes to the performance counters; this
1354                  * should keep both older linux and windows 64-bit guests
1355                  * happy
1356                  */
1357                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1358
1359                 break;
1360         default:
1361                 return kvm_set_msr_common(vcpu, ecx, data);
1362         }
1363         return 0;
1364 }
1365
1366 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1367 {
1368         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1369         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
1370                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1371
1372         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1373                     handler);
1374
1375         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1376         if (svm_set_msr(&svm->vcpu, ecx, data))
1377                 kvm_inject_gp(&svm->vcpu, 0);
1378         else
1379                 skip_emulated_instruction(&svm->vcpu);
1380         return 1;
1381 }
1382
1383 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1384 {
1385         if (svm->vmcb->control.exit_info_1)
1386                 return wrmsr_interception(svm, kvm_run);
1387         else
1388                 return rdmsr_interception(svm, kvm_run);
1389 }
1390
1391 static int interrupt_window_interception(struct vcpu_svm *svm,
1392                                    struct kvm_run *kvm_run)
1393 {
1394         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1395
1396         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1397         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1398         /*
1399          * If the user space waits to inject interrupts, exit as soon as
1400          * possible
1401          */
1402         if (kvm_run->request_interrupt_window &&
1403             !svm->vcpu.arch.irq_summary) {
1404                 ++svm->vcpu.stat.irq_window_exits;
1405                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1406                 return 0;
1407         }
1408
1409         return 1;
1410 }
1411
1412 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1413                                       struct kvm_run *kvm_run) = {
1414         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1415         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1416         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1417         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1418         /* for now: */
1419         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1420         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1421         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1422         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1423         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1424         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1425         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1426         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1427         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1428         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1429         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1430         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1431         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1432         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1433         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1434         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1435         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1436         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1437         [SVM_EXIT_INTR]                         = intr_interception,
1438         [SVM_EXIT_NMI]                          = nmi_interception,
1439         [SVM_EXIT_SMI]                          = nop_on_interception,
1440         [SVM_EXIT_INIT]                         = nop_on_interception,
1441         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1442         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1443         [SVM_EXIT_CPUID]                        = cpuid_interception,
1444         [SVM_EXIT_INVD]                         = emulate_on_interception,
1445         [SVM_EXIT_HLT]                          = halt_interception,
1446         [SVM_EXIT_INVLPG]                       = invlpg_interception,
1447         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1448         [SVM_EXIT_IOIO]                         = io_interception,
1449         [SVM_EXIT_MSR]                          = msr_interception,
1450         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1451         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1452         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1453         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1454         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1455         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1456         [SVM_EXIT_STGI]                         = invalid_op_interception,
1457         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1458         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1459         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1460         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1461         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1462         [SVM_EXIT_NPF]                          = pf_interception,
1463 };
1464
1465 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1466 {
1467         struct vcpu_svm *svm = to_svm(vcpu);
1468         u32 exit_code = svm->vmcb->control.exit_code;
1469
1470         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1471                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1472
1473         if (npt_enabled) {
1474                 int mmu_reload = 0;
1475                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1476                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1477                         mmu_reload = 1;
1478                 }
1479                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1480                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1481                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1482                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1483                                 kvm_inject_gp(vcpu, 0);
1484                                 return 1;
1485                         }
1486                 }
1487                 if (mmu_reload) {
1488                         kvm_mmu_reset_context(vcpu);
1489                         kvm_mmu_load(vcpu);
1490                 }
1491         }
1492
1493         kvm_reput_irq(svm);
1494
1495         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1496                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1497                 kvm_run->fail_entry.hardware_entry_failure_reason
1498                         = svm->vmcb->control.exit_code;
1499                 return 0;
1500         }
1501
1502         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1503             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1504             exit_code != SVM_EXIT_NPF)
1505                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1506                        "exit_code 0x%x\n",
1507                        __func__, svm->vmcb->control.exit_int_info,
1508                        exit_code);
1509
1510         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1511             || !svm_exit_handlers[exit_code]) {
1512                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1513                 kvm_run->hw.hardware_exit_reason = exit_code;
1514                 return 0;
1515         }
1516
1517         return svm_exit_handlers[exit_code](svm, kvm_run);
1518 }
1519
1520 static void reload_tss(struct kvm_vcpu *vcpu)
1521 {
1522         int cpu = raw_smp_processor_id();
1523
1524         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1525         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1526         load_TR_desc();
1527 }
1528
1529 static void pre_svm_run(struct vcpu_svm *svm)
1530 {
1531         int cpu = raw_smp_processor_id();
1532
1533         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1534
1535         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1536         if (svm->vcpu.cpu != cpu ||
1537             svm->asid_generation != svm_data->asid_generation)
1538                 new_asid(svm, svm_data);
1539 }
1540
1541
1542 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1543 {
1544         struct vmcb_control_area *control;
1545
1546         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1547
1548         ++svm->vcpu.stat.irq_injections;
1549         control = &svm->vmcb->control;
1550         control->int_vector = irq;
1551         control->int_ctl &= ~V_INTR_PRIO_MASK;
1552         control->int_ctl |= V_IRQ_MASK |
1553                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1554 }
1555
1556 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1557 {
1558         struct vcpu_svm *svm = to_svm(vcpu);
1559
1560         svm_inject_irq(svm, irq);
1561 }
1562
1563 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1564 {
1565         struct vcpu_svm *svm = to_svm(vcpu);
1566         struct vmcb *vmcb = svm->vmcb;
1567         int max_irr, tpr;
1568
1569         if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1570                 return;
1571
1572         vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1573
1574         max_irr = kvm_lapic_find_highest_irr(vcpu);
1575         if (max_irr == -1)
1576                 return;
1577
1578         tpr = kvm_lapic_get_cr8(vcpu) << 4;
1579
1580         if (tpr >= (max_irr & 0xf0))
1581                 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1582 }
1583
1584 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1585 {
1586         struct vcpu_svm *svm = to_svm(vcpu);
1587         struct vmcb *vmcb = svm->vmcb;
1588         int intr_vector = -1;
1589
1590         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1591             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1592                 intr_vector = vmcb->control.exit_int_info &
1593                               SVM_EVTINJ_VEC_MASK;
1594                 vmcb->control.exit_int_info = 0;
1595                 svm_inject_irq(svm, intr_vector);
1596                 goto out;
1597         }
1598
1599         if (vmcb->control.int_ctl & V_IRQ_MASK)
1600                 goto out;
1601
1602         if (!kvm_cpu_has_interrupt(vcpu))
1603                 goto out;
1604
1605         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1606             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1607             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1608                 /* unable to deliver irq, set pending irq */
1609                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1610                 svm_inject_irq(svm, 0x0);
1611                 goto out;
1612         }
1613         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1614         intr_vector = kvm_cpu_get_interrupt(vcpu);
1615         svm_inject_irq(svm, intr_vector);
1616         kvm_timer_intr_post(vcpu, intr_vector);
1617 out:
1618         update_cr8_intercept(vcpu);
1619 }
1620
1621 static void kvm_reput_irq(struct vcpu_svm *svm)
1622 {
1623         struct vmcb_control_area *control = &svm->vmcb->control;
1624
1625         if ((control->int_ctl & V_IRQ_MASK)
1626             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1627                 control->int_ctl &= ~V_IRQ_MASK;
1628                 push_irq(&svm->vcpu, control->int_vector);
1629         }
1630
1631         svm->vcpu.arch.interrupt_window_open =
1632                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1633 }
1634
1635 static void svm_do_inject_vector(struct vcpu_svm *svm)
1636 {
1637         struct kvm_vcpu *vcpu = &svm->vcpu;
1638         int word_index = __ffs(vcpu->arch.irq_summary);
1639         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1640         int irq = word_index * BITS_PER_LONG + bit_index;
1641
1642         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1643         if (!vcpu->arch.irq_pending[word_index])
1644                 clear_bit(word_index, &vcpu->arch.irq_summary);
1645         svm_inject_irq(svm, irq);
1646 }
1647
1648 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1649                                        struct kvm_run *kvm_run)
1650 {
1651         struct vcpu_svm *svm = to_svm(vcpu);
1652         struct vmcb_control_area *control = &svm->vmcb->control;
1653
1654         svm->vcpu.arch.interrupt_window_open =
1655                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1656                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1657
1658         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1659                 /*
1660                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1661                  */
1662                 svm_do_inject_vector(svm);
1663
1664         /*
1665          * Interrupts blocked.  Wait for unblock.
1666          */
1667         if (!svm->vcpu.arch.interrupt_window_open &&
1668             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1669                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1670          else
1671                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1672 }
1673
1674 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1675 {
1676         return 0;
1677 }
1678
1679 static void save_db_regs(unsigned long *db_regs)
1680 {
1681         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1682         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1683         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1684         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1685 }
1686
1687 static void load_db_regs(unsigned long *db_regs)
1688 {
1689         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1690         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1691         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1692         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1693 }
1694
1695 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1696 {
1697         force_new_asid(vcpu);
1698 }
1699
1700 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1701 {
1702 }
1703
1704 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1705 {
1706         struct vcpu_svm *svm = to_svm(vcpu);
1707
1708         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1709                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1710                 kvm_lapic_set_tpr(vcpu, cr8);
1711         }
1712 }
1713
1714 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1715 {
1716         struct vcpu_svm *svm = to_svm(vcpu);
1717         u64 cr8;
1718
1719         if (!irqchip_in_kernel(vcpu->kvm))
1720                 return;
1721
1722         cr8 = kvm_get_cr8(vcpu);
1723         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1724         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1725 }
1726
1727 #ifdef CONFIG_X86_64
1728 #define R "r"
1729 #else
1730 #define R "e"
1731 #endif
1732
1733 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1734 {
1735         struct vcpu_svm *svm = to_svm(vcpu);
1736         u16 fs_selector;
1737         u16 gs_selector;
1738         u16 ldt_selector;
1739
1740         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
1741         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
1742         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
1743
1744         pre_svm_run(svm);
1745
1746         sync_lapic_to_cr8(vcpu);
1747
1748         save_host_msrs(vcpu);
1749         fs_selector = kvm_read_fs();
1750         gs_selector = kvm_read_gs();
1751         ldt_selector = kvm_read_ldt();
1752         svm->host_cr2 = kvm_read_cr2();
1753         svm->host_dr6 = read_dr6();
1754         svm->host_dr7 = read_dr7();
1755         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1756         /* required for live migration with NPT */
1757         if (npt_enabled)
1758                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1759
1760         if (svm->vmcb->save.dr7 & 0xff) {
1761                 write_dr7(0);
1762                 save_db_regs(svm->host_db_regs);
1763                 load_db_regs(svm->db_regs);
1764         }
1765
1766         clgi();
1767
1768         local_irq_enable();
1769
1770         asm volatile (
1771                 "push %%"R"bp; \n\t"
1772                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
1773                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
1774                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
1775                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
1776                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
1777                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
1778 #ifdef CONFIG_X86_64
1779                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1780                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1781                 "mov %c[r10](%[svm]), %%r10 \n\t"
1782                 "mov %c[r11](%[svm]), %%r11 \n\t"
1783                 "mov %c[r12](%[svm]), %%r12 \n\t"
1784                 "mov %c[r13](%[svm]), %%r13 \n\t"
1785                 "mov %c[r14](%[svm]), %%r14 \n\t"
1786                 "mov %c[r15](%[svm]), %%r15 \n\t"
1787 #endif
1788
1789                 /* Enter guest mode */
1790                 "push %%"R"ax \n\t"
1791                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
1792                 __ex(SVM_VMLOAD) "\n\t"
1793                 __ex(SVM_VMRUN) "\n\t"
1794                 __ex(SVM_VMSAVE) "\n\t"
1795                 "pop %%"R"ax \n\t"
1796
1797                 /* Save guest registers, load host registers */
1798                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
1799                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
1800                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
1801                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
1802                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
1803                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
1804 #ifdef CONFIG_X86_64
1805                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1806                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1807                 "mov %%r10, %c[r10](%[svm]) \n\t"
1808                 "mov %%r11, %c[r11](%[svm]) \n\t"
1809                 "mov %%r12, %c[r12](%[svm]) \n\t"
1810                 "mov %%r13, %c[r13](%[svm]) \n\t"
1811                 "mov %%r14, %c[r14](%[svm]) \n\t"
1812                 "mov %%r15, %c[r15](%[svm]) \n\t"
1813 #endif
1814                 "pop %%"R"bp"
1815                 :
1816                 : [svm]"a"(svm),
1817                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1818                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1819                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1820                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1821                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1822                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1823                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1824 #ifdef CONFIG_X86_64
1825                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1826                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1827                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1828                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1829                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1830                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1831                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1832                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1833 #endif
1834                 : "cc", "memory"
1835                 , R"bx", R"cx", R"dx", R"si", R"di"
1836 #ifdef CONFIG_X86_64
1837                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1838 #endif
1839                 );
1840
1841         if ((svm->vmcb->save.dr7 & 0xff))
1842                 load_db_regs(svm->host_db_regs);
1843
1844         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1845         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
1846         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
1847         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
1848
1849         write_dr6(svm->host_dr6);
1850         write_dr7(svm->host_dr7);
1851         kvm_write_cr2(svm->host_cr2);
1852
1853         kvm_load_fs(fs_selector);
1854         kvm_load_gs(gs_selector);
1855         kvm_load_ldt(ldt_selector);
1856         load_host_msrs(vcpu);
1857
1858         reload_tss(vcpu);
1859
1860         local_irq_disable();
1861
1862         stgi();
1863
1864         sync_cr8_to_lapic(vcpu);
1865
1866         svm->next_rip = 0;
1867 }
1868
1869 #undef R
1870
1871 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1872 {
1873         struct vcpu_svm *svm = to_svm(vcpu);
1874
1875         if (npt_enabled) {
1876                 svm->vmcb->control.nested_cr3 = root;
1877                 force_new_asid(vcpu);
1878                 return;
1879         }
1880
1881         svm->vmcb->save.cr3 = root;
1882         force_new_asid(vcpu);
1883
1884         if (vcpu->fpu_active) {
1885                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1886                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1887                 vcpu->fpu_active = 0;
1888         }
1889 }
1890
1891 static int is_disabled(void)
1892 {
1893         u64 vm_cr;
1894
1895         rdmsrl(MSR_VM_CR, vm_cr);
1896         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1897                 return 1;
1898
1899         return 0;
1900 }
1901
1902 static void
1903 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1904 {
1905         /*
1906          * Patch in the VMMCALL instruction:
1907          */
1908         hypercall[0] = 0x0f;
1909         hypercall[1] = 0x01;
1910         hypercall[2] = 0xd9;
1911 }
1912
1913 static void svm_check_processor_compat(void *rtn)
1914 {
1915         *(int *)rtn = 0;
1916 }
1917
1918 static bool svm_cpu_has_accelerated_tpr(void)
1919 {
1920         return false;
1921 }
1922
1923 static int get_npt_level(void)
1924 {
1925 #ifdef CONFIG_X86_64
1926         return PT64_ROOT_LEVEL;
1927 #else
1928         return PT32E_ROOT_LEVEL;
1929 #endif
1930 }
1931
1932 static int svm_get_mt_mask_shift(void)
1933 {
1934         return 0;
1935 }
1936
1937 static struct kvm_x86_ops svm_x86_ops = {
1938         .cpu_has_kvm_support = has_svm,
1939         .disabled_by_bios = is_disabled,
1940         .hardware_setup = svm_hardware_setup,
1941         .hardware_unsetup = svm_hardware_unsetup,
1942         .check_processor_compatibility = svm_check_processor_compat,
1943         .hardware_enable = svm_hardware_enable,
1944         .hardware_disable = svm_hardware_disable,
1945         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1946
1947         .vcpu_create = svm_create_vcpu,
1948         .vcpu_free = svm_free_vcpu,
1949         .vcpu_reset = svm_vcpu_reset,
1950
1951         .prepare_guest_switch = svm_prepare_guest_switch,
1952         .vcpu_load = svm_vcpu_load,
1953         .vcpu_put = svm_vcpu_put,
1954
1955         .set_guest_debug = svm_guest_debug,
1956         .get_msr = svm_get_msr,
1957         .set_msr = svm_set_msr,
1958         .get_segment_base = svm_get_segment_base,
1959         .get_segment = svm_get_segment,
1960         .set_segment = svm_set_segment,
1961         .get_cpl = svm_get_cpl,
1962         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1963         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1964         .set_cr0 = svm_set_cr0,
1965         .set_cr3 = svm_set_cr3,
1966         .set_cr4 = svm_set_cr4,
1967         .set_efer = svm_set_efer,
1968         .get_idt = svm_get_idt,
1969         .set_idt = svm_set_idt,
1970         .get_gdt = svm_get_gdt,
1971         .set_gdt = svm_set_gdt,
1972         .get_dr = svm_get_dr,
1973         .set_dr = svm_set_dr,
1974         .get_rflags = svm_get_rflags,
1975         .set_rflags = svm_set_rflags,
1976
1977         .tlb_flush = svm_flush_tlb,
1978
1979         .run = svm_vcpu_run,
1980         .handle_exit = handle_exit,
1981         .skip_emulated_instruction = skip_emulated_instruction,
1982         .patch_hypercall = svm_patch_hypercall,
1983         .get_irq = svm_get_irq,
1984         .set_irq = svm_set_irq,
1985         .queue_exception = svm_queue_exception,
1986         .exception_injected = svm_exception_injected,
1987         .inject_pending_irq = svm_intr_assist,
1988         .inject_pending_vectors = do_interrupt_requests,
1989
1990         .set_tss_addr = svm_set_tss_addr,
1991         .get_tdp_level = get_npt_level,
1992         .get_mt_mask_shift = svm_get_mt_mask_shift,
1993 };
1994
1995 static int __init svm_init(void)
1996 {
1997         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1998                               THIS_MODULE);
1999 }
2000
2001 static void __exit svm_exit(void)
2002 {
2003         kvm_exit();
2004 }
2005
2006 module_init(svm_init)
2007 module_exit(svm_exit)