2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
9 #define LX_NODE_BASE 10
11 #define MIPSCPU_INT_BASE 16
12 #define MIPS_CPU_RTLX_IRQ 0
14 #define RTLX_VERSION 1
15 #define RTLX_xID 0x12345600
16 #define RTLX_ID (RTLX_xID | RTLX_VERSION)
17 #define RTLX_CHANNELS 8
20 RTLX_STATE_UNUSED = 0,
21 RTLX_STATE_INITIALISED,
22 RTLX_STATE_REMOTE_READY,
26 #define RTLX_BUFFER_SIZE 1024
27 /* each channel supports read and write.
28 linux (vpe0) reads lx_buffer and writes rt_buffer
29 SP (vpe1) reads rt_buffer and writes lx_buffer
31 typedef struct rtlx_channel {
32 enum rtlx_state rt_state;
33 enum rtlx_state lx_state;
37 /* read and write indexes per buffer */
38 int rt_write, rt_read;
41 int lx_write, lx_read;
48 typedef struct rtlx_info {
50 enum rtlx_state state;
52 struct rtlx_channel channel[RTLX_CHANNELS];