git.oblomov.eu Git - linux-2.6/blob - drivers/usb/host/ohci-q.c

   1 /*
   2  * OHCI HCD (Host Controller Driver) for USB.
   3  *
   4  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5  * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6  *
   7  * This file is licenced under the GPL.
   8  */
   9
  10 #include <linux/irq.h>
  11
  12 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
  13 {
  14         int             last = urb_priv->length - 1;
  15
  16         if (last >= 0) {
  17                 int             i;
  18                 struct td       *td;
  19
  20                 for (i = 0; i <= last; i++) {
  21                         td = urb_priv->td [i];
  22                         if (td)
  23                                 td_free (hc, td);
  24                 }
  25         }
  26
  27         list_del (&urb_priv->pending);
  28         kfree (urb_priv);
  29 }
  30
  31 /*-------------------------------------------------------------------------*/
  32
  33 /*
  34  * URB goes back to driver, and isn't reissued.
  35  * It's completely gone from HC data structures.
  36  * PRECONDITION:  ohci lock held, irqs blocked.
  37  */
  38 static void
  39 finish_urb (struct ohci_hcd *ohci, struct urb *urb)
  40 __releases(ohci->lock)
  41 __acquires(ohci->lock)
  42 {
  43         // ASSERT (urb->hcpriv != 0);
  44
  45         urb_free_priv (ohci, urb->hcpriv);
  46         urb->hcpriv = NULL;
  47
  48         spin_lock (&urb->lock);
  49         if (likely (urb->status == -EINPROGRESS))
  50                 urb->status = 0;
  51         /* report short control reads right even though the data TD always
  52          * has TD_R set.  (much simpler, but creates the 1-td limit.)
  53          */
  54         if (unlikely (urb->transfer_flags & URB_SHORT_NOT_OK)
  55                         && unlikely (usb_pipecontrol (urb->pipe))
  56                         && urb->actual_length < urb->transfer_buffer_length
  57                         && usb_pipein (urb->pipe)
  58                         && urb->status == 0) {
  59                 urb->status = -EREMOTEIO;
  60         }
  61         spin_unlock (&urb->lock);
  62
  63         switch (usb_pipetype (urb->pipe)) {
  64         case PIPE_ISOCHRONOUS:
  65                 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
  66                 break;
  67         case PIPE_INTERRUPT:
  68                 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
  69                 break;
  70         }
  71
  72 #ifdef OHCI_VERBOSE_DEBUG
  73         urb_print (urb, "RET", usb_pipeout (urb->pipe));
  74 #endif
  75
  76         /* urb->complete() can reenter this HCD */
  77         usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
  78         spin_unlock (&ohci->lock);
  79         usb_hcd_giveback_urb (ohci_to_hcd(ohci), urb);
  80         spin_lock (&ohci->lock);
  81
  82         /* stop periodic dma if it's not needed */
  83         if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
  84                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
  85                 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
  86                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
  87         }
  88 }
  89
  90
  91 /*-------------------------------------------------------------------------*
  92  * ED handling functions
  93  *-------------------------------------------------------------------------*/
  94
  95 /* search for the right schedule branch to use for a periodic ed.
  96  * does some load balancing; returns the branch, or negative errno.
  97  */
  98 static int balance (struct ohci_hcd *ohci, int interval, int load)
  99 {
 100         int     i, branch = -ENOSPC;
 101
 102         /* iso periods can be huge; iso tds specify frame numbers */
 103         if (interval > NUM_INTS)
 104                 interval = NUM_INTS;
 105
 106         /* search for the least loaded schedule branch of that period
 107          * that has enough bandwidth left unreserved.
 108          */
 109         for (i = 0; i < interval ; i++) {
 110                 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
 111                         int     j;
 112
 113                         /* usb 1.1 says 90% of one frame */
 114                         for (j = i; j < NUM_INTS; j += interval) {
 115                                 if ((ohci->load [j] + load) > 900)
 116                                         break;
 117                         }
 118                         if (j < NUM_INTS)
 119                                 continue;
 120                         branch = i;
 121                 }
 122         }
 123         return branch;
 124 }
 125
 126 /*-------------------------------------------------------------------------*/
 127
 128 /* both iso and interrupt requests have periods; this routine puts them
 129  * into the schedule tree in the apppropriate place.  most iso devices use
 130  * 1msec periods, but that's not required.
 131  */
 132 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
 133 {
 134         unsigned        i;
 135
 136         ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
 137                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 138                 ed, ed->branch, ed->load, ed->interval);
 139
 140         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 141                 struct ed       **prev = &ohci->periodic [i];
 142                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 143                 struct ed       *here = *prev;
 144
 145                 /* sorting each branch by period (slow before fast)
 146                  * lets us share the faster parts of the tree.
 147                  * (plus maybe: put interrupt eds before iso)
 148                  */
 149                 while (here && ed != here) {
 150                         if (ed->interval > here->interval)
 151                                 break;
 152                         prev = &here->ed_next;
 153                         prev_p = &here->hwNextED;
 154                         here = *prev;
 155                 }
 156                 if (ed != here) {
 157                         ed->ed_next = here;
 158                         if (here)
 159                                 ed->hwNextED = *prev_p;
 160                         wmb ();
 161                         *prev = ed;
 162                         *prev_p = cpu_to_hc32(ohci, ed->dma);
 163                         wmb();
 164                 }
 165                 ohci->load [i] += ed->load;
 166         }
 167         ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
 168 }
 169
 170 /* link an ed into one of the HC chains */
 171
 172 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
 173 {
 174         int     branch;
 175
 176         if (ohci_to_hcd(ohci)->state == HC_STATE_QUIESCING)
 177                 return -EAGAIN;
 178
 179         ed->state = ED_OPER;
 180         ed->ed_prev = NULL;
 181         ed->ed_next = NULL;
 182         ed->hwNextED = 0;
 183         if (quirk_zfmicro(ohci)
 184                         && (ed->type == PIPE_INTERRUPT)
 185                         && !(ohci->eds_scheduled++))
 186                 mod_timer(&ohci->unlink_watchdog, round_jiffies_relative(HZ));
 187         wmb ();
 188
 189         /* we care about rm_list when setting CLE/BLE in case the HC was at
 190          * work on some TD when CLE/BLE was turned off, and isn't quiesced
 191          * yet.  finish_unlinks() restarts as needed, some upcoming INTR_SF.
 192          *
 193          * control and bulk EDs are doubly linked (ed_next, ed_prev), but
 194          * periodic ones are singly linked (ed_next). that's because the
 195          * periodic schedule encodes a tree like figure 3-5 in the ohci
 196          * spec:  each qh can have several "previous" nodes, and the tree
 197          * doesn't have unused/idle descriptors.
 198          */
 199         switch (ed->type) {
 200         case PIPE_CONTROL:
 201                 if (ohci->ed_controltail == NULL) {
 202                         WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
 203                         ohci_writel (ohci, ed->dma,
 204                                         &ohci->regs->ed_controlhead);
 205                 } else {
 206                         ohci->ed_controltail->ed_next = ed;
 207                         ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
 208                                                                 ed->dma);
 209                 }
 210                 ed->ed_prev = ohci->ed_controltail;
 211                 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
 212                         wmb();
 213                         ohci->hc_control |= OHCI_CTRL_CLE;
 214                         ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
 215                         ohci_writel (ohci, ohci->hc_control,
 216                                         &ohci->regs->control);
 217                 }
 218                 ohci->ed_controltail = ed;
 219                 break;
 220
 221         case PIPE_BULK:
 222                 if (ohci->ed_bulktail == NULL) {
 223                         WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
 224                         ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
 225                 } else {
 226                         ohci->ed_bulktail->ed_next = ed;
 227                         ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
 228                                                                 ed->dma);
 229                 }
 230                 ed->ed_prev = ohci->ed_bulktail;
 231                 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
 232                         wmb();
 233                         ohci->hc_control |= OHCI_CTRL_BLE;
 234                         ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
 235                         ohci_writel (ohci, ohci->hc_control,
 236                                         &ohci->regs->control);
 237                 }
 238                 ohci->ed_bulktail = ed;
 239                 break;
 240
 241         // case PIPE_INTERRUPT:
 242         // case PIPE_ISOCHRONOUS:
 243         default:
 244                 branch = balance (ohci, ed->interval, ed->load);
 245                 if (branch < 0) {
 246                         ohci_dbg (ohci,
 247                                 "ERR %d, interval %d msecs, load %d\n",
 248                                 branch, ed->interval, ed->load);
 249                         // FIXME if there are TDs queued, fail them!
 250                         return branch;
 251                 }
 252                 ed->branch = branch;
 253                 periodic_link (ohci, ed);
 254         }
 255
 256         /* the HC may not see the schedule updates yet, but if it does
 257          * then they'll be properly ordered.
 258          */
 259         return 0;
 260 }
 261
 262 /*-------------------------------------------------------------------------*/
 263
 264 /* scan the periodic table to find and unlink this ED */
 265 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
 266 {
 267         int     i;
 268
 269         for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
 270                 struct ed       *temp;
 271                 struct ed       **prev = &ohci->periodic [i];
 272                 __hc32          *prev_p = &ohci->hcca->int_table [i];
 273
 274                 while (*prev && (temp = *prev) != ed) {
 275                         prev_p = &temp->hwNextED;
 276                         prev = &temp->ed_next;
 277                 }
 278                 if (*prev) {
 279                         *prev_p = ed->hwNextED;
 280                         *prev = ed->ed_next;
 281                 }
 282                 ohci->load [i] -= ed->load;
 283         }
 284         ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
 285
 286         ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
 287                 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
 288                 ed, ed->branch, ed->load, ed->interval);
 289 }
 290
 291 /* unlink an ed from one of the HC chains.
 292  * just the link to the ed is unlinked.
 293  * the link from the ed still points to another operational ed or 0
 294  * so the HC can eventually finish the processing of the unlinked ed
 295  * (assuming it already started that, which needn't be true).
 296  *
 297  * ED_UNLINK is a transient state: the HC may still see this ED, but soon
 298  * it won't.  ED_SKIP means the HC will finish its current transaction,
 299  * but won't start anything new.  The TD queue may still grow; device
 300  * drivers don't know about this HCD-internal state.
 301  *
 302  * When the HC can't see the ED, something changes ED_UNLINK to one of:
 303  *
 304  *  - ED_OPER: when there's any request queued, the ED gets rescheduled
 305  *    immediately.  HC should be working on them.
 306  *
 307  *  - ED_IDLE:  when there's no TD queue. there's no reason for the HC
 308  *    to care about this ED; safe to disable the endpoint.
 309  *
 310  * When finish_unlinks() runs later, after SOF interrupt, it will often
 311  * complete one or more URB unlinks before making that state change.
 312  */
 313 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
 314 {
 315         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 316         wmb ();
 317         ed->state = ED_UNLINK;
 318
 319         /* To deschedule something from the control or bulk list, just
 320          * clear CLE/BLE and wait.  There's no safe way to scrub out list
 321          * head/current registers until later, and "later" isn't very
 322          * tightly specified.  Figure 6-5 and Section 6.4.2.2 show how
 323          * the HC is reading the ED queues (while we modify them).
 324          *
 325          * For now, ed_schedule() is "later".  It might be good paranoia
 326          * to scrub those registers in finish_unlinks(), in case of bugs
 327          * that make the HC try to use them.
 328          */
 329         switch (ed->type) {
 330         case PIPE_CONTROL:
 331                 /* remove ED from the HC's list: */
 332                 if (ed->ed_prev == NULL) {
 333                         if (!ed->hwNextED) {
 334                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 335                                 ohci_writel (ohci, ohci->hc_control,
 336                                                 &ohci->regs->control);
 337                                 // a ohci_readl() later syncs CLE with the HC
 338                         } else
 339                                 ohci_writel (ohci,
 340                                         hc32_to_cpup (ohci, &ed->hwNextED),
 341                                         &ohci->regs->ed_controlhead);
 342                 } else {
 343                         ed->ed_prev->ed_next = ed->ed_next;
 344                         ed->ed_prev->hwNextED = ed->hwNextED;
 345                 }
 346                 /* remove ED from the HCD's list: */
 347                 if (ohci->ed_controltail == ed) {
 348                         ohci->ed_controltail = ed->ed_prev;
 349                         if (ohci->ed_controltail)
 350                                 ohci->ed_controltail->ed_next = NULL;
 351                 } else if (ed->ed_next) {
 352                         ed->ed_next->ed_prev = ed->ed_prev;
 353                 }
 354                 break;
 355
 356         case PIPE_BULK:
 357                 /* remove ED from the HC's list: */
 358                 if (ed->ed_prev == NULL) {
 359                         if (!ed->hwNextED) {
 360                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 361                                 ohci_writel (ohci, ohci->hc_control,
 362                                                 &ohci->regs->control);
 363                                 // a ohci_readl() later syncs BLE with the HC
 364                         } else
 365                                 ohci_writel (ohci,
 366                                         hc32_to_cpup (ohci, &ed->hwNextED),
 367                                         &ohci->regs->ed_bulkhead);
 368                 } else {
 369                         ed->ed_prev->ed_next = ed->ed_next;
 370                         ed->ed_prev->hwNextED = ed->hwNextED;
 371                 }
 372                 /* remove ED from the HCD's list: */
 373                 if (ohci->ed_bulktail == ed) {
 374                         ohci->ed_bulktail = ed->ed_prev;
 375                         if (ohci->ed_bulktail)
 376                                 ohci->ed_bulktail->ed_next = NULL;
 377                 } else if (ed->ed_next) {
 378                         ed->ed_next->ed_prev = ed->ed_prev;
 379                 }
 380                 break;
 381
 382         // case PIPE_INTERRUPT:
 383         // case PIPE_ISOCHRONOUS:
 384         default:
 385                 periodic_unlink (ohci, ed);
 386                 break;
 387         }
 388 }
 389
 390
 391 /*-------------------------------------------------------------------------*/
 392
 393 /* get and maybe (re)init an endpoint. init _should_ be done only as part
 394  * of enumeration, usb_set_configuration() or usb_set_interface().
 395  */
 396 static struct ed *ed_get (
 397         struct ohci_hcd         *ohci,
 398         struct usb_host_endpoint *ep,
 399         struct usb_device       *udev,
 400         unsigned int            pipe,
 401         int                     interval
 402 ) {
 403         struct ed               *ed;
 404         unsigned long           flags;
 405
 406         spin_lock_irqsave (&ohci->lock, flags);
 407
 408         if (!(ed = ep->hcpriv)) {
 409                 struct td       *td;
 410                 int             is_out;
 411                 u32             info;
 412
 413                 ed = ed_alloc (ohci, GFP_ATOMIC);
 414                 if (!ed) {
 415                         /* out of memory */
 416                         goto done;
 417                 }
 418
 419                 /* dummy td; end of td list for ed */
 420                 td = td_alloc (ohci, GFP_ATOMIC);
 421                 if (!td) {
 422                         /* out of memory */
 423                         ed_free (ohci, ed);
 424                         ed = NULL;
 425                         goto done;
 426                 }
 427                 ed->dummy = td;
 428                 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
 429                 ed->hwHeadP = ed->hwTailP;      /* ED_C, ED_H zeroed */
 430                 ed->state = ED_IDLE;
 431
 432                 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
 433
 434                 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
 435                  * suceeds ... otherwise we wouldn't need "pipe".
 436                  */
 437                 info = usb_pipedevice (pipe);
 438                 ed->type = usb_pipetype(pipe);
 439
 440                 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
 441                 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
 442                 if (udev->speed == USB_SPEED_LOW)
 443                         info |= ED_LOWSPEED;
 444                 /* only control transfers store pids in tds */
 445                 if (ed->type != PIPE_CONTROL) {
 446                         info |= is_out ? ED_OUT : ED_IN;
 447                         if (ed->type != PIPE_BULK) {
 448                                 /* periodic transfers... */
 449                                 if (ed->type == PIPE_ISOCHRONOUS)
 450                                         info |= ED_ISO;
 451                                 else if (interval > 32) /* iso can be bigger */
 452                                         interval = 32;
 453                                 ed->interval = interval;
 454                                 ed->load = usb_calc_bus_time (
 455                                         udev->speed, !is_out,
 456                                         ed->type == PIPE_ISOCHRONOUS,
 457                                         le16_to_cpu(ep->desc.wMaxPacketSize))
 458                                                 / 1000;
 459                         }
 460                 }
 461                 ed->hwINFO = cpu_to_hc32(ohci, info);
 462
 463                 ep->hcpriv = ed;
 464         }
 465
 466 done:
 467         spin_unlock_irqrestore (&ohci->lock, flags);
 468         return ed;
 469 }
 470
 471 /*-------------------------------------------------------------------------*/
 472
 473 /* request unlinking of an endpoint from an operational HC.
 474  * put the ep on the rm_list
 475  * real work is done at the next start frame (SF) hardware interrupt
 476  * caller guarantees HCD is running, so hardware access is safe,
 477  * and that ed->state is ED_OPER
 478  */
 479 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
 480 {
 481         ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
 482         ed_deschedule (ohci, ed);
 483
 484         /* rm_list is just singly linked, for simplicity */
 485         ed->ed_next = ohci->ed_rm_list;
 486         ed->ed_prev = NULL;
 487         ohci->ed_rm_list = ed;
 488
 489         /* enable SOF interrupt */
 490         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
 491         ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
 492         // flush those writes, and get latest HCCA contents
 493         (void) ohci_readl (ohci, &ohci->regs->control);
 494
 495         /* SF interrupt might get delayed; record the frame counter value that
 496          * indicates when the HC isn't looking at it, so concurrent unlinks
 497          * behave.  frame_no wraps every 2^16 msec, and changes right before
 498          * SF is triggered.
 499          */
 500         ed->tick = ohci_frame_no(ohci) + 1;
 501
 502 }
 503
 504 /*-------------------------------------------------------------------------*
 505  * TD handling functions
 506  *-------------------------------------------------------------------------*/
 507
 508 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 509
 510 static void
 511 td_fill (struct ohci_hcd *ohci, u32 info,
 512         dma_addr_t data, int len,
 513         struct urb *urb, int index)
 514 {
 515         struct td               *td, *td_pt;
 516         struct urb_priv         *urb_priv = urb->hcpriv;
 517         int                     is_iso = info & TD_ISO;
 518         int                     hash;
 519
 520         // ASSERT (index < urb_priv->length);
 521
 522         /* aim for only one interrupt per urb.  mostly applies to control
 523          * and iso; other urbs rarely need more than one TD per urb.
 524          * this way, only final tds (or ones with an error) cause IRQs.
 525          * at least immediately; use DI=6 in case any control request is
 526          * tempted to die part way through.  (and to force the hc to flush
 527          * its donelist soonish, even on unlink paths.)
 528          *
 529          * NOTE: could delay interrupts even for the last TD, and get fewer
 530          * interrupts ... increasing per-urb latency by sharing interrupts.
 531          * Drivers that queue bulk urbs may request that behavior.
 532          */
 533         if (index != (urb_priv->length - 1)
 534                         || (urb->transfer_flags & URB_NO_INTERRUPT))
 535                 info |= TD_DI_SET (6);
 536
 537         /* use this td as the next dummy */
 538         td_pt = urb_priv->td [index];
 539
 540         /* fill the old dummy TD */
 541         td = urb_priv->td [index] = urb_priv->ed->dummy;
 542         urb_priv->ed->dummy = td_pt;
 543
 544         td->ed = urb_priv->ed;
 545         td->next_dl_td = NULL;
 546         td->index = index;
 547         td->urb = urb;
 548         td->data_dma = data;
 549         if (!len)
 550                 data = 0;
 551
 552         td->hwINFO = cpu_to_hc32 (ohci, info);
 553         if (is_iso) {
 554                 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
 555                 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
 556                                                 (data & 0x0FFF) | 0xE000);
 557                 td->ed->last_iso = info & 0xffff;
 558         } else {
 559                 td->hwCBP = cpu_to_hc32 (ohci, data);
 560         }
 561         if (data)
 562                 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
 563         else
 564                 td->hwBE = 0;
 565         td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
 566
 567         /* append to queue */
 568         list_add_tail (&td->td_list, &td->ed->td_list);
 569
 570         /* hash it for later reverse mapping */
 571         hash = TD_HASH_FUNC (td->td_dma);
 572         td->td_hash = ohci->td_hash [hash];
 573         ohci->td_hash [hash] = td;
 574
 575         /* HC might read the TD (or cachelines) right away ... */
 576         wmb ();
 577         td->ed->hwTailP = td->hwNextTD;
 578 }
 579
 580 /*-------------------------------------------------------------------------*/
 581
 582 /* Prepare all TDs of a transfer, and queue them onto the ED.
 583  * Caller guarantees HC is active.
 584  * Usually the ED is already on the schedule, so TDs might be
 585  * processed as soon as they're queued.
 586  */
 587 static void td_submit_urb (
 588         struct ohci_hcd *ohci,
 589         struct urb      *urb
 590 ) {
 591         struct urb_priv *urb_priv = urb->hcpriv;
 592         dma_addr_t      data;
 593         int             data_len = urb->transfer_buffer_length;
 594         int             cnt = 0;
 595         u32             info = 0;
 596         int             is_out = usb_pipeout (urb->pipe);
 597         int             periodic = 0;
 598
 599         /* OHCI handles the bulk/interrupt data toggles itself.  We just
 600          * use the device toggle bits for resetting, and rely on the fact
 601          * that resetting toggle is meaningless if the endpoint is active.
 602          */
 603         if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
 604                 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
 605                         is_out, 1);
 606                 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
 607         }
 608
 609         urb_priv->td_cnt = 0;
 610         list_add (&urb_priv->pending, &ohci->pending);
 611
 612         if (data_len)
 613                 data = urb->transfer_dma;
 614         else
 615                 data = 0;
 616
 617         /* NOTE:  TD_CC is set so we can tell which TDs the HC processed by
 618          * using TD_CC_GET, as well as by seeing them on the done list.
 619          * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
 620          */
 621         switch (urb_priv->ed->type) {
 622
 623         /* Bulk and interrupt are identical except for where in the schedule
 624          * their EDs live.
 625          */
 626         case PIPE_INTERRUPT:
 627                 /* ... and periodic urbs have extra accounting */
 628                 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
 629                         && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
 630                 /* FALLTHROUGH */
 631         case PIPE_BULK:
 632                 info = is_out
 633                         ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
 634                         : TD_T_TOGGLE | TD_CC | TD_DP_IN;
 635                 /* TDs _could_ transfer up to 8K each */
 636                 while (data_len > 4096) {
 637                         td_fill (ohci, info, data, 4096, urb, cnt);
 638                         data += 4096;
 639                         data_len -= 4096;
 640                         cnt++;
 641                 }
 642                 /* maybe avoid ED halt on final TD short read */
 643                 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
 644                         info |= TD_R;
 645                 td_fill (ohci, info, data, data_len, urb, cnt);
 646                 cnt++;
 647                 if ((urb->transfer_flags & URB_ZERO_PACKET)
 648                                 && cnt < urb_priv->length) {
 649                         td_fill (ohci, info, 0, 0, urb, cnt);
 650                         cnt++;
 651                 }
 652                 /* maybe kickstart bulk list */
 653                 if (urb_priv->ed->type == PIPE_BULK) {
 654                         wmb ();
 655                         ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
 656                 }
 657                 break;
 658
 659         /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
 660          * any DATA phase works normally, and the STATUS ack is special.
 661          */
 662         case PIPE_CONTROL:
 663                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 664                 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
 665                 if (data_len > 0) {
 666                         info = TD_CC | TD_R | TD_T_DATA1;
 667                         info |= is_out ? TD_DP_OUT : TD_DP_IN;
 668                         /* NOTE:  mishandles transfers >8K, some >4K */
 669                         td_fill (ohci, info, data, data_len, urb, cnt++);
 670                 }
 671                 info = (is_out || data_len == 0)
 672                         ? TD_CC | TD_DP_IN | TD_T_DATA1
 673                         : TD_CC | TD_DP_OUT | TD_T_DATA1;
 674                 td_fill (ohci, info, data, 0, urb, cnt++);
 675                 /* maybe kickstart control list */
 676                 wmb ();
 677                 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
 678                 break;
 679
 680         /* ISO has no retransmit, so no toggle; and it uses special TDs.
 681          * Each TD could handle multiple consecutive frames (interval 1);
 682          * we could often reduce the number of TDs here.
 683          */
 684         case PIPE_ISOCHRONOUS:
 685                 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
 686                         int     frame = urb->start_frame;
 687
 688                         // FIXME scheduling should handle frame counter
 689                         // roll-around ... exotic case (and OHCI has
 690                         // a 2^16 iso range, vs other HCs max of 2^10)
 691                         frame += cnt * urb->interval;
 692                         frame &= 0xffff;
 693                         td_fill (ohci, TD_CC | TD_ISO | frame,
 694                                 data + urb->iso_frame_desc [cnt].offset,
 695                                 urb->iso_frame_desc [cnt].length, urb, cnt);
 696                 }
 697                 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
 698                         && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
 699                 break;
 700         }
 701
 702         /* start periodic dma if needed */
 703         if (periodic) {
 704                 wmb ();
 705                 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
 706                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 707         }
 708
 709         // ASSERT (urb_priv->length == cnt);
 710 }
 711
 712 /*-------------------------------------------------------------------------*
 713  * Done List handling functions
 714  *-------------------------------------------------------------------------*/
 715
 716 /* calculate transfer length/status and update the urb
 717  * PRECONDITION:  irqsafe (only for urb->status locking)
 718  */
 719 static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td)
 720 {
 721         u32     tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
 722         int     cc = 0;
 723
 724         list_del (&td->td_list);
 725
 726         /* ISO ... drivers see per-TD length/status */
 727         if (tdINFO & TD_ISO) {
 728                 u16     tdPSW = ohci_hwPSW (ohci, td, 0);
 729                 int     dlen = 0;
 730
 731                 /* NOTE:  assumes FC in tdINFO == 0, and that
 732                  * only the first of 0..MAXPSW psws is used.
 733                  */
 734
 735                 cc = (tdPSW >> 12) & 0xF;
 736                 if (tdINFO & TD_CC)     /* hc didn't touch? */
 737                         return;
 738
 739                 if (usb_pipeout (urb->pipe))
 740                         dlen = urb->iso_frame_desc [td->index].length;
 741                 else {
 742                         /* short reads are always OK for ISO */
 743                         if (cc == TD_DATAUNDERRUN)
 744                                 cc = TD_CC_NOERROR;
 745                         dlen = tdPSW & 0x3ff;
 746                 }
 747                 urb->actual_length += dlen;
 748                 urb->iso_frame_desc [td->index].actual_length = dlen;
 749                 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
 750
 751                 if (cc != TD_CC_NOERROR)
 752                         ohci_vdbg (ohci,
 753                                 "urb %p iso td %p (%d) len %d cc %d\n",
 754                                 urb, td, 1 + td->index, dlen, cc);
 755
 756         /* BULK, INT, CONTROL ... drivers see aggregate length/status,
 757          * except that "setup" bytes aren't counted and "short" transfers
 758          * might not be reported as errors.
 759          */
 760         } else {
 761                 int     type = usb_pipetype (urb->pipe);
 762                 u32     tdBE = hc32_to_cpup (ohci, &td->hwBE);
 763
 764                 cc = TD_CC_GET (tdINFO);
 765
 766                 /* update packet status if needed (short is normally ok) */
 767                 if (cc == TD_DATAUNDERRUN
 768                                 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
 769                         cc = TD_CC_NOERROR;
 770                 if (cc != TD_CC_NOERROR && cc < 0x0E) {
 771                         spin_lock (&urb->lock);
 772                         if (urb->status == -EINPROGRESS)
 773                                 urb->status = cc_to_error [cc];
 774                         spin_unlock (&urb->lock);
 775                 }
 776
 777                 /* count all non-empty packets except control SETUP packet */
 778                 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
 779                         if (td->hwCBP == 0)
 780                                 urb->actual_length += tdBE - td->data_dma + 1;
 781                         else
 782                                 urb->actual_length +=
 783                                           hc32_to_cpup (ohci, &td->hwCBP)
 784                                         - td->data_dma;
 785                 }
 786
 787                 if (cc != TD_CC_NOERROR && cc < 0x0E)
 788                         ohci_vdbg (ohci,
 789                                 "urb %p td %p (%d) cc %d, len=%d/%d\n",
 790                                 urb, td, 1 + td->index, cc,
 791                                 urb->actual_length,
 792                                 urb->transfer_buffer_length);
 793         }
 794 }
 795
 796 /*-------------------------------------------------------------------------*/
 797
 798 static inline struct td *
 799 ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev)
 800 {
 801         struct urb              *urb = td->urb;
 802         struct ed               *ed = td->ed;
 803         struct list_head        *tmp = td->td_list.next;
 804         __hc32                  toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
 805
 806         /* clear ed halt; this is the td that caused it, but keep it inactive
 807          * until its urb->complete() has a chance to clean up.
 808          */
 809         ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
 810         wmb ();
 811         ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
 812
 813         /* put any later tds from this urb onto the donelist, after 'td',
 814          * order won't matter here: no errors, and nothing was transferred.
 815          * also patch the ed so it looks as if those tds completed normally.
 816          */
 817         while (tmp != &ed->td_list) {
 818                 struct td       *next;
 819                 __hc32          info;
 820
 821                 next = list_entry (tmp, struct td, td_list);
 822                 tmp = next->td_list.next;
 823
 824                 if (next->urb != urb)
 825                         break;
 826
 827                 /* NOTE: if multi-td control DATA segments get supported,
 828                  * this urb had one of them, this td wasn't the last td
 829                  * in that segment (TD_R clear), this ed halted because
 830                  * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
 831                  * then we need to leave the control STATUS packet queued
 832                  * and clear ED_SKIP.
 833                  */
 834                 info = next->hwINFO;
 835                 info |= cpu_to_hc32 (ohci, TD_DONE);
 836                 info &= ~cpu_to_hc32 (ohci, TD_CC);
 837                 next->hwINFO = info;
 838
 839                 next->next_dl_td = rev;
 840                 rev = next;
 841
 842                 ed->hwHeadP = next->hwNextTD | toggle;
 843         }
 844
 845         /* help for troubleshooting:  report anything that
 846          * looks odd ... that doesn't include protocol stalls
 847          * (or maybe some other things)
 848          */
 849         switch (cc) {
 850         case TD_DATAUNDERRUN:
 851                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
 852                         break;
 853                 /* fallthrough */
 854         case TD_CC_STALL:
 855                 if (usb_pipecontrol (urb->pipe))
 856                         break;
 857                 /* fallthrough */
 858         default:
 859                 ohci_dbg (ohci,
 860                         "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
 861                         urb, urb->dev->devpath,
 862                         usb_pipeendpoint (urb->pipe),
 863                         usb_pipein (urb->pipe) ? "in" : "out",
 864                         hc32_to_cpu (ohci, td->hwINFO),
 865                         cc, cc_to_error [cc]);
 866         }
 867
 868         return rev;
 869 }
 870
 871 /* replies to the request have to be on a FIFO basis so
 872  * we unreverse the hc-reversed done-list
 873  */
 874 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
 875 {
 876         u32             td_dma;
 877         struct td       *td_rev = NULL;
 878         struct td       *td = NULL;
 879
 880         td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
 881         ohci->hcca->done_head = 0;
 882         wmb();
 883
 884         /* get TD from hc's singly linked list, and
 885          * prepend to ours.  ed->td_list changes later.
 886          */
 887         while (td_dma) {
 888                 int             cc;
 889
 890                 td = dma_to_td (ohci, td_dma);
 891                 if (!td) {
 892                         ohci_err (ohci, "bad entry %8x\n", td_dma);
 893                         break;
 894                 }
 895
 896                 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
 897                 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
 898
 899                 /* Non-iso endpoints can halt on error; un-halt,
 900                  * and dequeue any other TDs from this urb.
 901                  * No other TD could have caused the halt.
 902                  */
 903                 if (cc != TD_CC_NOERROR
 904                                 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
 905                         td_rev = ed_halted (ohci, td, cc, td_rev);
 906
 907                 td->next_dl_td = td_rev;
 908                 td_rev = td;
 909                 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
 910         }
 911         return td_rev;
 912 }
 913
 914 /*-------------------------------------------------------------------------*/
 915
 916 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
 917 static void
 918 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
 919 {
 920         struct ed       *ed, **last;
 921
 922 rescan_all:
 923         for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
 924                 struct list_head        *entry, *tmp;
 925                 int                     completed, modified;
 926                 __hc32                  *prev;
 927
 928                 /* only take off EDs that the HC isn't using, accounting for
 929                  * frame counter wraps and EDs with partially retired TDs
 930                  */
 931                 if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) {
 932                         if (tick_before (tick, ed->tick)) {
 933 skip_ed:
 934                                 last = &ed->ed_next;
 935                                 continue;
 936                         }
 937
 938                         if (!list_empty (&ed->td_list)) {
 939                                 struct td       *td;
 940                                 u32             head;
 941
 942                                 td = list_entry (ed->td_list.next, struct td,
 943                                                         td_list);
 944                                 head = hc32_to_cpu (ohci, ed->hwHeadP) &
 945                                                                 TD_MASK;
 946
 947                                 /* INTR_WDH may need to clean up first */
 948                                 if (td->td_dma != head) {
 949                                         if (ed == ohci->ed_to_check)
 950                                                 ohci->ed_to_check = NULL;
 951                                         else
 952                                                 goto skip_ed;
 953                                 }
 954                         }
 955                 }
 956
 957                 /* reentrancy:  if we drop the schedule lock, someone might
 958                  * have modified this list.  normally it's just prepending
 959                  * entries (which we'd ignore), but paranoia won't hurt.
 960                  */
 961                 *last = ed->ed_next;
 962                 ed->ed_next = NULL;
 963                 modified = 0;
 964
 965                 /* unlink urbs as requested, but rescan the list after
 966                  * we call a completion since it might have unlinked
 967                  * another (earlier) urb
 968                  *
 969                  * When we get here, the HC doesn't see this ed.  But it
 970                  * must not be rescheduled until all completed URBs have
 971                  * been given back to the driver.
 972                  */
 973 rescan_this:
 974                 completed = 0;
 975                 prev = &ed->hwHeadP;
 976                 list_for_each_safe (entry, tmp, &ed->td_list) {
 977                         struct td       *td;
 978                         struct urb      *urb;
 979                         urb_priv_t      *urb_priv;
 980                         __hc32          savebits;
 981
 982                         td = list_entry (entry, struct td, td_list);
 983                         urb = td->urb;
 984                         urb_priv = td->urb->hcpriv;
 985
 986                         if (urb->status == -EINPROGRESS) {
 987                                 prev = &td->hwNextTD;
 988                                 continue;
 989                         }
 990
 991                         /* patch pointer hc uses */
 992                         savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
 993                         *prev = td->hwNextTD | savebits;
 994
 995                         /* HC may have partly processed this TD */
 996                         td_done (ohci, urb, td);
 997                         urb_priv->td_cnt++;
 998
 999                         /* if URB is done, clean up */
1000                         if (urb_priv->td_cnt == urb_priv->length) {
1001                                 modified = completed = 1;
1002                                 finish_urb (ohci, urb);
1003                         }
1004                 }
1005                 if (completed && !list_empty (&ed->td_list))
1006                         goto rescan_this;
1007
1008                 /* ED's now officially unlinked, hc doesn't see */
1009                 ed->state = ED_IDLE;
1010                 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1011                         ohci->eds_scheduled--;
1012                 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1013                 ed->hwNextED = 0;
1014                 wmb ();
1015                 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1016
1017                 /* but if there's work queued, reschedule */
1018                 if (!list_empty (&ed->td_list)) {
1019                         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))
1020                                 ed_schedule (ohci, ed);
1021                 }
1022
1023                 if (modified)
1024                         goto rescan_all;
1025         }
1026
1027         /* maybe reenable control and bulk lists */
1028         if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)
1029                         && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING
1030                         && !ohci->ed_rm_list) {
1031                 u32     command = 0, control = 0;
1032
1033                 if (ohci->ed_controltail) {
1034                         command |= OHCI_CLF;
1035                         if (quirk_zfmicro(ohci))
1036                                 mdelay(1);
1037                         if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1038                                 control |= OHCI_CTRL_CLE;
1039                                 ohci_writel (ohci, 0,
1040                                         &ohci->regs->ed_controlcurrent);
1041                         }
1042                 }
1043                 if (ohci->ed_bulktail) {
1044                         command |= OHCI_BLF;
1045                         if (quirk_zfmicro(ohci))
1046                                 mdelay(1);
1047                         if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1048                                 control |= OHCI_CTRL_BLE;
1049                                 ohci_writel (ohci, 0,
1050                                         &ohci->regs->ed_bulkcurrent);
1051                         }
1052                 }
1053
1054                 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1055                 if (control) {
1056                         ohci->hc_control |= control;
1057                         if (quirk_zfmicro(ohci))
1058                                 mdelay(1);
1059                         ohci_writel (ohci, ohci->hc_control,
1060                                         &ohci->regs->control);
1061                 }
1062                 if (command) {
1063                         if (quirk_zfmicro(ohci))
1064                                 mdelay(1);
1065                         ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1066                 }
1067         }
1068 }
1069
1070
1071
1072 /*-------------------------------------------------------------------------*/
1073
1074 /*
1075  * Used to take back a TD from the host controller. This would normally be
1076  * called from within dl_done_list, however it may be called directly if the
1077  * HC no longer sees the TD and it has not appeared on the donelist (after
1078  * two frames).  This bug has been observed on ZF Micro systems.
1079  */
1080 static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1081 {
1082         struct urb      *urb = td->urb;
1083         urb_priv_t      *urb_priv = urb->hcpriv;
1084         struct ed       *ed = td->ed;
1085
1086         /* update URB's length and status from TD */
1087         td_done(ohci, urb, td);
1088         urb_priv->td_cnt++;
1089
1090         /* If all this urb's TDs are done, call complete() */
1091         if (urb_priv->td_cnt == urb_priv->length)
1092                 finish_urb(ohci, urb);
1093
1094         /* clean schedule:  unlink EDs that are no longer busy */
1095         if (list_empty(&ed->td_list)) {
1096                 if (ed->state == ED_OPER)
1097                         start_ed_unlink(ohci, ed);
1098
1099         /* ... reenabling halted EDs only after fault cleanup */
1100         } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1101                         == cpu_to_hc32(ohci, ED_SKIP)) {
1102                 td = list_entry(ed->td_list.next, struct td, td_list);
1103                 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1104                         ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1105                         /* ... hc may need waking-up */
1106                         switch (ed->type) {
1107                         case PIPE_CONTROL:
1108                                 ohci_writel(ohci, OHCI_CLF,
1109                                                 &ohci->regs->cmdstatus);
1110                                 break;
1111                         case PIPE_BULK:
1112                                 ohci_writel(ohci, OHCI_BLF,
1113                                                 &ohci->regs->cmdstatus);
1114                                 break;
1115                         }
1116                 }
1117         }
1118 }
1119
1120 /*
1121  * Process normal completions (error or success) and clean the schedules.
1122  *
1123  * This is the main path for handing urbs back to drivers.  The only other
1124  * normal path is finish_unlinks(), which unlinks URBs using ed_rm_list,
1125  * instead of scanning the (re-reversed) donelist as this does.  There's
1126  * an abnormal path too, handling a quirk in some Compaq silicon:  URBs
1127  * with TDs that appear to be orphaned are directly reclaimed.
1128  */
1129 static void
1130 dl_done_list (struct ohci_hcd *ohci)
1131 {
1132         struct td       *td = dl_reverse_done_list (ohci);
1133
1134         while (td) {
1135                 struct td       *td_next = td->next_dl_td;
1136                 takeback_td(ohci, td);
1137                 td = td_next;
1138         }
1139 }