Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / arch / mips / kernel / smp-mt.c
1 /*
2  *  This program is free software; you can distribute it and/or modify it
3  *  under the terms of the GNU General Public License (Version 2) as
4  *  published by the Free Software Foundation.
5  *
6  *  This program is distributed in the hope it will be useful, but WITHOUT
7  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
8  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
9  *  for more details.
10  *
11  *  You should have received a copy of the GNU General Public License along
12  *  with this program; if not, write to the Free Software Foundation, Inc.,
13  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
14  *
15  * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
16  *    Elizabeth Clarke (beth@mips.com)
17  *    Ralf Baechle (ralf@linux-mips.org)
18  * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
19  */
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/cpumask.h>
23 #include <linux/interrupt.h>
24 #include <linux/compiler.h>
25
26 #include <asm/atomic.h>
27 #include <asm/cacheflush.h>
28 #include <asm/cpu.h>
29 #include <asm/processor.h>
30 #include <asm/system.h>
31 #include <asm/hardirq.h>
32 #include <asm/mmu_context.h>
33 #include <asm/smp.h>
34 #include <asm/time.h>
35 #include <asm/mipsregs.h>
36 #include <asm/mipsmtregs.h>
37 #include <asm/mips_mt.h>
38 #include <asm/mips-boards/maltaint.h>  /* This is f*cking wrong */
39
40 #define MIPS_CPU_IPI_RESCHED_IRQ 0
41 #define MIPS_CPU_IPI_CALL_IRQ 1
42
43 static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
44
45 #if 0
46 static void dump_mtregisters(int vpe, int tc)
47 {
48         printk("vpe %d tc %d\n", vpe, tc);
49
50         settc(tc);
51
52         printk("  c0 status  0x%lx\n", read_vpe_c0_status());
53         printk("  vpecontrol 0x%lx\n", read_vpe_c0_vpecontrol());
54         printk("  vpeconf0    0x%lx\n", read_vpe_c0_vpeconf0());
55         printk("  tcstatus 0x%lx\n", read_tc_c0_tcstatus());
56         printk("  tcrestart 0x%lx\n", read_tc_c0_tcrestart());
57         printk("  tcbind 0x%lx\n", read_tc_c0_tcbind());
58         printk("  tchalt 0x%lx\n", read_tc_c0_tchalt());
59 }
60 #endif
61
62 void __init sanitize_tlb_entries(void)
63 {
64         int i, tlbsiz;
65         unsigned long mvpconf0, ncpu;
66
67         if (!cpu_has_mipsmt)
68                 return;
69
70         /* Enable VPC */
71         set_c0_mvpcontrol(MVPCONTROL_VPC);
72
73         back_to_back_c0_hazard();
74
75         /* Disable TLB sharing */
76         clear_c0_mvpcontrol(MVPCONTROL_STLB);
77
78         mvpconf0 = read_c0_mvpconf0();
79
80         printk(KERN_INFO "MVPConf0 0x%lx TLBS %lx PTLBE %ld\n", mvpconf0,
81                    (mvpconf0 & MVPCONF0_TLBS) >> MVPCONF0_TLBS_SHIFT,
82                            (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT);
83
84         tlbsiz = (mvpconf0 & MVPCONF0_PTLBE) >> MVPCONF0_PTLBE_SHIFT;
85         ncpu = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
86
87         printk(" tlbsiz %d ncpu %ld\n", tlbsiz, ncpu);
88
89         if (tlbsiz > 0) {
90                 /* share them out across the vpe's */
91                 tlbsiz /= ncpu;
92
93                 printk(KERN_INFO "setting Config1.MMU_size to %d\n", tlbsiz);
94
95                 for (i = 0; i < ncpu; i++) {
96                         settc(i);
97
98                         if (i == 0)
99                                 write_c0_config1((read_c0_config1() & ~(0x3f << 25)) | (tlbsiz << 25));
100                         else
101                                 write_vpe_c0_config1((read_vpe_c0_config1() & ~(0x3f << 25)) |
102                                                    (tlbsiz << 25));
103                 }
104         }
105
106         clear_c0_mvpcontrol(MVPCONTROL_VPC);
107 }
108
109 static void ipi_resched_dispatch(void)
110 {
111         do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
112 }
113
114 static void ipi_call_dispatch(void)
115 {
116         do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ);
117 }
118
119 static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
120 {
121         return IRQ_HANDLED;
122 }
123
124 static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
125 {
126         smp_call_function_interrupt();
127
128         return IRQ_HANDLED;
129 }
130
131 static struct irqaction irq_resched = {
132         .handler        = ipi_resched_interrupt,
133         .flags          = IRQF_DISABLED,
134         .name           = "IPI_resched"
135 };
136
137 static struct irqaction irq_call = {
138         .handler        = ipi_call_interrupt,
139         .flags          = IRQF_DISABLED,
140         .name           = "IPI_call"
141 };
142
143 static void __init smp_copy_vpe_config(void)
144 {
145         write_vpe_c0_status(
146                 (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
147
148         /* set config to be the same as vpe0, particularly kseg0 coherency alg */
149         write_vpe_c0_config( read_c0_config());
150
151         /* make sure there are no software interrupts pending */
152         write_vpe_c0_cause(0);
153
154         /* Propagate Config7 */
155         write_vpe_c0_config7(read_c0_config7());
156
157         write_vpe_c0_count(read_c0_count());
158 }
159
160 static unsigned int __init smp_vpe_init(unsigned int tc, unsigned int mvpconf0,
161         unsigned int ncpu)
162 {
163         if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
164                 return ncpu;
165
166         /* Deactivate all but VPE 0 */
167         if (tc != 0) {
168                 unsigned long tmp = read_vpe_c0_vpeconf0();
169
170                 tmp &= ~VPECONF0_VPA;
171
172                 /* master VPE */
173                 tmp |= VPECONF0_MVP;
174                 write_vpe_c0_vpeconf0(tmp);
175
176                 /* Record this as available CPU */
177                 cpu_set(tc, phys_cpu_present_map);
178                 __cpu_number_map[tc]    = ++ncpu;
179                 __cpu_logical_map[ncpu] = tc;
180         }
181
182         /* Disable multi-threading with TC's */
183         write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
184
185         if (tc != 0)
186                 smp_copy_vpe_config();
187
188         return ncpu;
189 }
190
191 static void __init smp_tc_init(unsigned int tc, unsigned int mvpconf0)
192 {
193         unsigned long tmp;
194
195         if (!tc)
196                 return;
197
198         /* bind a TC to each VPE, May as well put all excess TC's
199            on the last VPE */
200         if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
201                 write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
202         else {
203                 write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);
204
205                 /* and set XTC */
206                 write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
207         }
208
209         tmp = read_tc_c0_tcstatus();
210
211         /* mark not allocated and not dynamically allocatable */
212         tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
213         tmp |= TCSTATUS_IXMT;           /* interrupt exempt */
214         write_tc_c0_tcstatus(tmp);
215
216         write_tc_c0_tchalt(TCHALT_H);
217 }
218
219 /*
220  * Common setup before any secondaries are started
221  * Make sure all CPU's are in a sensible state before we boot any of the
222  * secondarys
223  */
224 void __init plat_smp_setup(void)
225 {
226         unsigned int mvpconf0, ntc, tc, ncpu = 0;
227
228 #ifdef CONFIG_MIPS_MT_FPAFF
229         /* If we have an FPU, enroll ourselves in the FPU-full mask */
230         if (cpu_has_fpu)
231                 cpu_set(0, mt_fpu_cpumask);
232 #endif /* CONFIG_MIPS_MT_FPAFF */
233         if (!cpu_has_mipsmt)
234                 return;
235
236         /* disable MT so we can configure */
237         dvpe();
238         dmt();
239
240         mips_mt_set_cpuoptions();
241
242         /* Put MVPE's into 'configuration state' */
243         set_c0_mvpcontrol(MVPCONTROL_VPC);
244
245         mvpconf0 = read_c0_mvpconf0();
246         ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
247
248         /* we'll always have more TC's than VPE's, so loop setting everything
249            to a sensible state */
250         for (tc = 0; tc <= ntc; tc++) {
251                 settc(tc);
252
253                 smp_tc_init(tc, mvpconf0);
254                 ncpu = smp_vpe_init(tc, mvpconf0, ncpu);
255         }
256
257         /* Release config state */
258         clear_c0_mvpcontrol(MVPCONTROL_VPC);
259
260         /* We'll wait until starting the secondaries before starting MVPE */
261
262         printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
263 }
264
265 void __init plat_prepare_cpus(unsigned int max_cpus)
266 {
267         /* set up ipi interrupts */
268         if (cpu_has_vint) {
269                 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
270                 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
271         }
272
273         cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
274         cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ;
275
276         setup_irq(cpu_ipi_resched_irq, &irq_resched);
277         setup_irq(cpu_ipi_call_irq, &irq_call);
278
279         /* need to mark IPI's as IRQ_PER_CPU */
280         irq_desc[cpu_ipi_resched_irq].status |= IRQ_PER_CPU;
281         set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
282         irq_desc[cpu_ipi_call_irq].status |= IRQ_PER_CPU;
283         set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
284 }
285
286 /*
287  * Setup the PC, SP, and GP of a secondary processor and start it
288  * running!
289  * smp_bootstrap is the place to resume from
290  * __KSTK_TOS(idle) is apparently the stack pointer
291  * (unsigned long)idle->thread_info the gp
292  * assumes a 1:1 mapping of TC => VPE
293  */
294 void prom_boot_secondary(int cpu, struct task_struct *idle)
295 {
296         struct thread_info *gp = task_thread_info(idle);
297         dvpe();
298         set_c0_mvpcontrol(MVPCONTROL_VPC);
299
300         settc(cpu);
301
302         /* restart */
303         write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
304
305         /* enable the tc this vpe/cpu will be running */
306         write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
307
308         write_tc_c0_tchalt(0);
309
310         /* enable the VPE */
311         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
312
313         /* stack pointer */
314         write_tc_gpr_sp( __KSTK_TOS(idle));
315
316         /* global pointer */
317         write_tc_gpr_gp((unsigned long)gp);
318
319         flush_icache_range((unsigned long)gp,
320                            (unsigned long)(gp + sizeof(struct thread_info)));
321
322         /* finally out of configuration and into chaos */
323         clear_c0_mvpcontrol(MVPCONTROL_VPC);
324
325         evpe(EVPE_ENABLE);
326 }
327
328 void prom_init_secondary(void)
329 {
330         write_c0_status((read_c0_status() & ~ST0_IM ) |
331                         (STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP7));
332 }
333
334 void prom_smp_finish(void)
335 {
336         write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
337
338 #ifdef CONFIG_MIPS_MT_FPAFF
339         /* If we have an FPU, enroll ourselves in the FPU-full mask */
340         if (cpu_has_fpu)
341                 cpu_set(smp_processor_id(), mt_fpu_cpumask);
342 #endif /* CONFIG_MIPS_MT_FPAFF */
343
344         local_irq_enable();
345 }
346
347 void prom_cpus_done(void)
348 {
349 }
350
351 void core_send_ipi(int cpu, unsigned int action)
352 {
353         int i;
354         unsigned long flags;
355         int vpflags;
356
357         local_irq_save (flags);
358
359         vpflags = dvpe();       /* cant access the other CPU's registers whilst MVPE enabled */
360
361         switch (action) {
362         case SMP_CALL_FUNCTION:
363                 i = C_SW1;
364                 break;
365
366         case SMP_RESCHEDULE_YOURSELF:
367         default:
368                 i = C_SW0;
369                 break;
370         }
371
372         /* 1:1 mapping of vpe and tc... */
373         settc(cpu);
374         write_vpe_c0_cause(read_vpe_c0_cause() | i);
375         evpe(vpflags);
376
377         local_irq_restore(flags);
378 }