1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
2 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
5 * OMAP3430 Power/Reset Management register bits
7 * Copyright (C) 2007-2008 Texas Instruments, Inc.
8 * Copyright (C) 2007-2008 Nokia Corporation
10 * Written by Paul Walmsley
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
19 /* Shared register bits */
21 /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
22 #define OMAP3430_ON_SHIFT 24
23 #define OMAP3430_ON_MASK (0xff << 24)
24 #define OMAP3430_ONLP_SHIFT 16
25 #define OMAP3430_ONLP_MASK (0xff << 16)
26 #define OMAP3430_RET_SHIFT 8
27 #define OMAP3430_RET_MASK (0xff << 8)
28 #define OMAP3430_OFF_SHIFT 0
29 #define OMAP3430_OFF_MASK (0xff << 0)
31 /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
32 #define OMAP3430_ERROROFFSET_SHIFT 24
33 #define OMAP3430_ERROROFFSET_MASK (0xff << 24)
34 #define OMAP3430_ERRORGAIN_SHIFT 16
35 #define OMAP3430_ERRORGAIN_MASK (0xff << 16)
36 #define OMAP3430_INITVOLTAGE_SHIFT 8
37 #define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
38 #define OMAP3430_TIMEOUTEN (1 << 3)
39 #define OMAP3430_INITVDD (1 << 2)
40 #define OMAP3430_FORCEUPDATE (1 << 1)
41 #define OMAP3430_VPENABLE (1 << 0)
43 /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
44 #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
45 #define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
46 #define OMAP3430_VSTEPMIN_SHIFT 0
47 #define OMAP3430_VSTEPMIN_MASK (0xff << 0)
49 /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
50 #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
51 #define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
52 #define OMAP3430_VSTEPMAX_SHIFT 0
53 #define OMAP3430_VSTEPMAX_MASK (0xff << 0)
55 /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
56 #define OMAP3430_VDDMAX_SHIFT 24
57 #define OMAP3430_VDDMAX_MASK (0xff << 24)
58 #define OMAP3430_VDDMIN_SHIFT 16
59 #define OMAP3430_VDDMIN_MASK (0xff << 16)
60 #define OMAP3430_TIMEOUT_SHIFT 0
61 #define OMAP3430_TIMEOUT_MASK (0xffff << 0)
63 /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
64 #define OMAP3430_VPVOLTAGE_SHIFT 0
65 #define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
67 /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
68 #define OMAP3430_VPINIDLE (1 << 0)
70 /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71 #define OMAP3430_EN_PER (1 << 7)
73 /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
74 #define OMAP3430_MEMORYCHANGE (1 << 3)
76 /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
77 #define OMAP3430_LOGICSTATEST (1 << 2)
79 /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
80 #define OMAP3430_LASTLOGICSTATEENTERED (1 << 2)
83 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
84 * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
85 * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
87 #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
88 #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
90 /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
91 #define OMAP3430_WKUP_ST (1 << 0)
93 /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
94 #define OMAP3430_WKUP_EN (1 << 0)
96 /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
97 #define OMAP3430_GRPSEL_MMC2 (1 << 25)
98 #define OMAP3430_GRPSEL_MMC1 (1 << 24)
99 #define OMAP3430_GRPSEL_MCSPI4 (1 << 21)
100 #define OMAP3430_GRPSEL_MCSPI3 (1 << 20)
101 #define OMAP3430_GRPSEL_MCSPI2 (1 << 19)
102 #define OMAP3430_GRPSEL_MCSPI1 (1 << 18)
103 #define OMAP3430_GRPSEL_I2C3 (1 << 17)
104 #define OMAP3430_GRPSEL_I2C2 (1 << 16)
105 #define OMAP3430_GRPSEL_I2C1 (1 << 15)
106 #define OMAP3430_GRPSEL_UART2 (1 << 14)
107 #define OMAP3430_GRPSEL_UART1 (1 << 13)
108 #define OMAP3430_GRPSEL_GPT11 (1 << 12)
109 #define OMAP3430_GRPSEL_GPT10 (1 << 11)
110 #define OMAP3430_GRPSEL_MCBSP5 (1 << 10)
111 #define OMAP3430_GRPSEL_MCBSP1 (1 << 9)
112 #define OMAP3430_GRPSEL_HSOTGUSB (1 << 4)
113 #define OMAP3430_GRPSEL_D2D (1 << 3)
116 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
117 * PM_PWSTCTRL_PER shared bits
119 #define OMAP3430_MEMONSTATE_SHIFT 16
120 #define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
121 #define OMAP3430_MEMRETSTATE (1 << 8)
123 /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
124 #define OMAP3430_GRPSEL_GPIO6 (1 << 17)
125 #define OMAP3430_GRPSEL_GPIO5 (1 << 16)
126 #define OMAP3430_GRPSEL_GPIO4 (1 << 15)
127 #define OMAP3430_GRPSEL_GPIO3 (1 << 14)
128 #define OMAP3430_GRPSEL_GPIO2 (1 << 13)
129 #define OMAP3430_GRPSEL_UART3 (1 << 11)
130 #define OMAP3430_GRPSEL_GPT9 (1 << 10)
131 #define OMAP3430_GRPSEL_GPT8 (1 << 9)
132 #define OMAP3430_GRPSEL_GPT7 (1 << 8)
133 #define OMAP3430_GRPSEL_GPT6 (1 << 7)
134 #define OMAP3430_GRPSEL_GPT5 (1 << 6)
135 #define OMAP3430_GRPSEL_GPT4 (1 << 5)
136 #define OMAP3430_GRPSEL_GPT3 (1 << 4)
137 #define OMAP3430_GRPSEL_GPT2 (1 << 3)
138 #define OMAP3430_GRPSEL_MCBSP4 (1 << 2)
139 #define OMAP3430_GRPSEL_MCBSP3 (1 << 1)
140 #define OMAP3430_GRPSEL_MCBSP2 (1 << 0)
142 /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
143 #define OMAP3430_GRPSEL_IO (1 << 8)
144 #define OMAP3430_GRPSEL_SR2 (1 << 7)
145 #define OMAP3430_GRPSEL_SR1 (1 << 6)
146 #define OMAP3430_GRPSEL_GPIO1 (1 << 3)
147 #define OMAP3430_GRPSEL_GPT12 (1 << 1)
148 #define OMAP3430_GRPSEL_GPT1 (1 << 0)
150 /* Bits specific to each register */
152 /* RM_RSTCTRL_IVA2 */
153 #define OMAP3430_RST3_IVA2 (1 << 2)
154 #define OMAP3430_RST2_IVA2 (1 << 1)
155 #define OMAP3430_RST1_IVA2 (1 << 0)
157 /* RM_RSTST_IVA2 specific bits */
158 #define OMAP3430_EMULATION_VSEQ_RST (1 << 13)
159 #define OMAP3430_EMULATION_VHWA_RST (1 << 12)
160 #define OMAP3430_EMULATION_IVA2_RST (1 << 11)
161 #define OMAP3430_IVA2_SW_RST3 (1 << 10)
162 #define OMAP3430_IVA2_SW_RST2 (1 << 9)
163 #define OMAP3430_IVA2_SW_RST1 (1 << 8)
165 /* PM_WKDEP_IVA2 specific bits */
167 /* PM_PWSTCTRL_IVA2 specific bits */
168 #define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
169 #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
170 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
171 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
172 #define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
173 #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
174 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
175 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
176 #define OMAP3430_L2FLATMEMRETSTATE (1 << 11)
177 #define OMAP3430_SHAREDL2CACHEFLATRETSTATE (1 << 10)
178 #define OMAP3430_L1FLATMEMRETSTATE (1 << 9)
179 #define OMAP3430_SHAREDL1CACHEFLATRETSTATE (1 << 8)
181 /* PM_PWSTST_IVA2 specific bits */
182 #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
183 #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
184 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
185 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
186 #define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
187 #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
188 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
189 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
191 /* PM_PREPWSTST_IVA2 specific bits */
192 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
193 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
194 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
195 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
196 #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
197 #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
198 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
199 #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
201 /* PRM_IRQSTATUS_IVA2 specific bits */
202 #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST (1 << 2)
203 #define OMAP3430_FORCEWKUP_ST (1 << 1)
205 /* PRM_IRQENABLE_IVA2 specific bits */
206 #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN (1 << 2)
207 #define OMAP3430_FORCEWKUP_EN (1 << 1)
209 /* PRM_REVISION specific bits */
211 /* PRM_SYSCONFIG specific bits */
213 /* PRM_IRQSTATUS_MPU specific bits */
214 #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
215 #define OMAP3430ES2_SND_PERIPH_DPLL_ST (1 << 25)
216 #define OMAP3430_VC_TIMEOUTERR_ST (1 << 24)
217 #define OMAP3430_VC_RAERR_ST (1 << 23)
218 #define OMAP3430_VC_SAERR_ST (1 << 22)
219 #define OMAP3430_VP2_TRANXDONE_ST (1 << 21)
220 #define OMAP3430_VP2_EQVALUE_ST (1 << 20)
221 #define OMAP3430_VP2_NOSMPSACK_ST (1 << 19)
222 #define OMAP3430_VP2_MAXVDD_ST (1 << 18)
223 #define OMAP3430_VP2_MINVDD_ST (1 << 17)
224 #define OMAP3430_VP2_OPPCHANGEDONE_ST (1 << 16)
225 #define OMAP3430_VP1_TRANXDONE_ST (1 << 15)
226 #define OMAP3430_VP1_EQVALUE_ST (1 << 14)
227 #define OMAP3430_VP1_NOSMPSACK_ST (1 << 13)
228 #define OMAP3430_VP1_MAXVDD_ST (1 << 12)
229 #define OMAP3430_VP1_MINVDD_ST (1 << 11)
230 #define OMAP3430_VP1_OPPCHANGEDONE_ST (1 << 10)
231 #define OMAP3430_IO_ST (1 << 9)
232 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST (1 << 8)
233 #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
234 #define OMAP3430_MPU_DPLL_ST (1 << 7)
235 #define OMAP3430_MPU_DPLL_ST_SHIFT 7
236 #define OMAP3430_PERIPH_DPLL_ST (1 << 6)
237 #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
238 #define OMAP3430_CORE_DPLL_ST (1 << 5)
239 #define OMAP3430_CORE_DPLL_ST_SHIFT 5
240 #define OMAP3430_TRANSITION_ST (1 << 4)
241 #define OMAP3430_EVGENOFF_ST (1 << 3)
242 #define OMAP3430_EVGENON_ST (1 << 2)
243 #define OMAP3430_FS_USB_WKUP_ST (1 << 1)
245 /* PRM_IRQENABLE_MPU specific bits */
246 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
247 #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN (1 << 25)
248 #define OMAP3430_VC_TIMEOUTERR_EN (1 << 24)
249 #define OMAP3430_VC_RAERR_EN (1 << 23)
250 #define OMAP3430_VC_SAERR_EN (1 << 22)
251 #define OMAP3430_VP2_TRANXDONE_EN (1 << 21)
252 #define OMAP3430_VP2_EQVALUE_EN (1 << 20)
253 #define OMAP3430_VP2_NOSMPSACK_EN (1 << 19)
254 #define OMAP3430_VP2_MAXVDD_EN (1 << 18)
255 #define OMAP3430_VP2_MINVDD_EN (1 << 17)
256 #define OMAP3430_VP2_OPPCHANGEDONE_EN (1 << 16)
257 #define OMAP3430_VP1_TRANXDONE_EN (1 << 15)
258 #define OMAP3430_VP1_EQVALUE_EN (1 << 14)
259 #define OMAP3430_VP1_NOSMPSACK_EN (1 << 13)
260 #define OMAP3430_VP1_MAXVDD_EN (1 << 12)
261 #define OMAP3430_VP1_MINVDD_EN (1 << 11)
262 #define OMAP3430_VP1_OPPCHANGEDONE_EN (1 << 10)
263 #define OMAP3430_IO_EN (1 << 9)
264 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN (1 << 8)
265 #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
266 #define OMAP3430_MPU_DPLL_RECAL_EN (1 << 7)
267 #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
268 #define OMAP3430_PERIPH_DPLL_RECAL_EN (1 << 6)
269 #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
270 #define OMAP3430_CORE_DPLL_RECAL_EN (1 << 5)
271 #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
272 #define OMAP3430_TRANSITION_EN (1 << 4)
273 #define OMAP3430_EVGENOFF_EN (1 << 3)
274 #define OMAP3430_EVGENON_EN (1 << 2)
275 #define OMAP3430_FS_USB_WKUP_EN (1 << 1)
277 /* RM_RSTST_MPU specific bits */
278 #define OMAP3430_EMULATION_MPU_RST (1 << 11)
280 /* PM_WKDEP_MPU specific bits */
281 #define OMAP3430_PM_WKDEP_MPU_EN_DSS (1 << 5)
282 #define OMAP3430_PM_WKDEP_MPU_EN_IVA2 (1 << 2)
284 /* PM_EVGENCTRL_MPU */
285 #define OMAP3430_OFFLOADMODE_SHIFT 3
286 #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
287 #define OMAP3430_ONLOADMODE_SHIFT 1
288 #define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
289 #define OMAP3430_ENABLE (1 << 0)
291 /* PM_EVGENONTIM_MPU */
292 #define OMAP3430_ONTIMEVAL_SHIFT 0
293 #define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
295 /* PM_EVGENOFFTIM_MPU */
296 #define OMAP3430_OFFTIMEVAL_SHIFT 0
297 #define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
299 /* PM_PWSTCTRL_MPU specific bits */
300 #define OMAP3430_L2CACHEONSTATE_SHIFT 16
301 #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
302 #define OMAP3430_L2CACHERETSTATE (1 << 8)
303 #define OMAP3430_LOGICL1CACHERETSTATE (1 << 2)
305 /* PM_PWSTST_MPU specific bits */
306 #define OMAP3430_L2CACHESTATEST_SHIFT 6
307 #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
308 #define OMAP3430_LOGICL1CACHESTATEST (1 << 2)
310 /* PM_PREPWSTST_MPU specific bits */
311 #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
312 #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
313 #define OMAP3430_LASTLOGICL1CACHESTATEENTERED (1 << 2)
315 /* RM_RSTCTRL_CORE */
316 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON (1 << 1)
317 #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST (1 << 0)
319 /* RM_RSTST_CORE specific bits */
320 #define OMAP3430_MODEM_SECURITY_VIOL_RST (1 << 10)
321 #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON (1 << 9)
322 #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST (1 << 8)
324 /* PM_WKEN1_CORE specific bits */
326 /* PM_MPUGRPSEL1_CORE specific bits */
327 #define OMAP3430_GRPSEL_FSHOSTUSB (1 << 5)
329 /* PM_IVA2GRPSEL1_CORE specific bits */
331 /* PM_WKST1_CORE specific bits */
333 /* PM_PWSTCTRL_CORE specific bits */
334 #define OMAP3430_MEM2ONSTATE_SHIFT 18
335 #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
336 #define OMAP3430_MEM1ONSTATE_SHIFT 16
337 #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
338 #define OMAP3430_MEM2RETSTATE (1 << 9)
339 #define OMAP3430_MEM1RETSTATE (1 << 8)
341 /* PM_PWSTST_CORE specific bits */
342 #define OMAP3430_MEM2STATEST_SHIFT 6
343 #define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
344 #define OMAP3430_MEM1STATEST_SHIFT 4
345 #define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
347 /* PM_PREPWSTST_CORE specific bits */
348 #define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
349 #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
350 #define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
351 #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
353 /* RM_RSTST_GFX specific bits */
355 /* PM_WKDEP_GFX specific bits */
356 #define OMAP3430_PM_WKDEP_GFX_EN_IVA2 (1 << 2)
358 /* PM_PWSTCTRL_GFX specific bits */
360 /* PM_PWSTST_GFX specific bits */
362 /* PM_PREPWSTST_GFX specific bits */
364 /* PM_WKEN_WKUP specific bits */
365 #define OMAP3430_EN_IO (1 << 8)
367 /* PM_MPUGRPSEL_WKUP specific bits */
369 /* PM_IVA2GRPSEL_WKUP specific bits */
371 /* PM_WKST_WKUP specific bits */
372 #define OMAP3430_ST_IO (1 << 8)
375 #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
376 #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
378 /* PRM_CLKOUT_CTRL */
379 #define OMAP3430_CLKOUT_EN (1 << 7)
380 #define OMAP3430_CLKOUT_EN_SHIFT 7
382 /* RM_RSTST_DSS specific bits */
385 #define OMAP3430_PM_WKEN_DSS_EN_DSS (1 << 0)
387 /* PM_WKDEP_DSS specific bits */
388 #define OMAP3430_PM_WKDEP_DSS_EN_IVA2 (1 << 2)
390 /* PM_PWSTCTRL_DSS specific bits */
392 /* PM_PWSTST_DSS specific bits */
394 /* PM_PREPWSTST_DSS specific bits */
396 /* RM_RSTST_CAM specific bits */
398 /* PM_WKDEP_CAM specific bits */
399 #define OMAP3430_PM_WKDEP_CAM_EN_IVA2 (1 << 2)
401 /* PM_PWSTCTRL_CAM specific bits */
403 /* PM_PWSTST_CAM specific bits */
405 /* PM_PREPWSTST_CAM specific bits */
407 /* PM_PWSTCTRL_USBHOST specific bits */
408 #define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4)
410 /* RM_RSTST_PER specific bits */
412 /* PM_WKEN_PER specific bits */
414 /* PM_MPUGRPSEL_PER specific bits */
416 /* PM_IVA2GRPSEL_PER specific bits */
418 /* PM_WKST_PER specific bits */
420 /* PM_WKDEP_PER specific bits */
421 #define OMAP3430_PM_WKDEP_PER_EN_IVA2 (1 << 2)
423 /* PM_PWSTCTRL_PER specific bits */
425 /* PM_PWSTST_PER specific bits */
427 /* PM_PREPWSTST_PER specific bits */
429 /* RM_RSTST_EMU specific bits */
431 /* PM_PWSTST_EMU specific bits */
434 #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
435 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
436 #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
437 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
439 /* PRM_VC_SMPS_VOL_RA */
440 #define OMAP3430_VOLRA1_SHIFT 16
441 #define OMAP3430_VOLRA1_MASK (0xff << 16)
442 #define OMAP3430_VOLRA0_SHIFT 0
443 #define OMAP3430_VOLRA0_MASK (0xff << 0)
445 /* PRM_VC_SMPS_CMD_RA */
446 #define OMAP3430_CMDRA1_SHIFT 16
447 #define OMAP3430_CMDRA1_MASK (0xff << 16)
448 #define OMAP3430_CMDRA0_SHIFT 0
449 #define OMAP3430_CMDRA0_MASK (0xff << 0)
451 /* PRM_VC_CMD_VAL_0 specific bits */
453 /* PRM_VC_CMD_VAL_1 specific bits */
456 #define OMAP3430_CMD1 (1 << 20)
457 #define OMAP3430_RACEN1 (1 << 19)
458 #define OMAP3430_RAC1 (1 << 18)
459 #define OMAP3430_RAV1 (1 << 17)
460 #define OMAP3430_PRM_VC_CH_CONF_SA1 (1 << 16)
461 #define OMAP3430_CMD0 (1 << 4)
462 #define OMAP3430_RACEN0 (1 << 3)
463 #define OMAP3430_RAC0 (1 << 2)
464 #define OMAP3430_RAV0 (1 << 1)
465 #define OMAP3430_PRM_VC_CH_CONF_SA0 (1 << 0)
468 #define OMAP3430_HSMASTER (1 << 5)
469 #define OMAP3430_SREN (1 << 4)
470 #define OMAP3430_HSEN (1 << 3)
471 #define OMAP3430_MCODE_SHIFT 0
472 #define OMAP3430_MCODE_MASK (0x7 << 0)
474 /* PRM_VC_BYPASS_VAL */
475 #define OMAP3430_VALID (1 << 24)
476 #define OMAP3430_DATA_SHIFT 16
477 #define OMAP3430_DATA_MASK (0xff << 16)
478 #define OMAP3430_REGADDR_SHIFT 8
479 #define OMAP3430_REGADDR_MASK (0xff << 8)
480 #define OMAP3430_SLAVEADDR_SHIFT 0
481 #define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
484 #define OMAP3430_RST_DPLL3 (1 << 2)
485 #define OMAP3430_RST_GS (1 << 1)
488 #define OMAP3430_RSTTIME2_SHIFT 8
489 #define OMAP3430_RSTTIME2_MASK (0x1f << 8)
490 #define OMAP3430_RSTTIME1_SHIFT 0
491 #define OMAP3430_RSTTIME1_MASK (0xff << 0)
494 #define OMAP3430_ICECRUSHER_RST (1 << 10)
495 #define OMAP3430_ICEPICK_RST (1 << 9)
496 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST (1 << 8)
497 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST (1 << 7)
498 #define OMAP3430_EXTERNAL_WARM_RST (1 << 6)
499 #define OMAP3430_SECURE_WD_RST (1 << 5)
500 #define OMAP3430_MPU_WD_RST (1 << 4)
501 #define OMAP3430_SECURITY_VIOL_RST (1 << 3)
502 #define OMAP3430_GLOBAL_SW_RST (1 << 1)
503 #define OMAP3430_GLOBAL_COLD_RST (1 << 0)
506 #define OMAP3430_SEL_VMODE (1 << 4)
507 #define OMAP3430_SEL_OFF (1 << 3)
508 #define OMAP3430_AUTO_OFF (1 << 2)
509 #define OMAP3430_AUTO_RET (1 << 1)
510 #define OMAP3430_AUTO_SLEEP (1 << 0)
512 /* PRM_SRAM_PCHARGE */
513 #define OMAP3430_PCHARGE_TIME_SHIFT 0
514 #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
516 /* PRM_CLKSRC_CTRL */
517 #define OMAP3430_SYSCLKDIV_SHIFT 6
518 #define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
519 #define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
520 #define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
521 #define OMAP3430_SYSCLKSEL_SHIFT 0
522 #define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
525 #define OMAP3430_SETUP_TIME2_SHIFT 16
526 #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
527 #define OMAP3430_SETUP_TIME1_SHIFT 0
528 #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
531 #define OMAP3430_OFFSET_TIME_SHIFT 0
532 #define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
535 #define OMAP3430_SETUP_TIME_SHIFT 0
536 #define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
539 #define OMAP3430_OFFMODE_POL (1 << 3)
540 #define OMAP3430_CLKOUT_POL (1 << 2)
541 #define OMAP3430_CLKREQ_POL (1 << 1)
542 #define OMAP3430_EXTVOL_POL (1 << 0)
545 #define OMAP3430_OFFMODESETUPTIME_SHIFT 0
546 #define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
548 /* PRM_VP1_CONFIG specific bits */
550 /* PRM_VP1_VSTEPMIN specific bits */
552 /* PRM_VP1_VSTEPMAX specific bits */
554 /* PRM_VP1_VLIMITTO specific bits */
556 /* PRM_VP1_VOLTAGE specific bits */
558 /* PRM_VP1_STATUS specific bits */
560 /* PRM_VP2_CONFIG specific bits */
562 /* PRM_VP2_VSTEPMIN specific bits */
564 /* PRM_VP2_VSTEPMAX specific bits */
566 /* PRM_VP2_VLIMITTO specific bits */
568 /* PRM_VP2_VOLTAGE specific bits */
570 /* PRM_VP2_STATUS specific bits */
572 /* RM_RSTST_NEON specific bits */
574 /* PM_WKDEP_NEON specific bits */
576 /* PM_PWSTCTRL_NEON specific bits */
578 /* PM_PWSTST_NEON specific bits */
580 /* PM_PREPWSTST_NEON specific bits */
projects / linux-2.6 / blob