git.oblomov.eu Git - linux-2.6/blob - drivers/media/video/cx18/cx18-firmware.c

   1 /*
   2  *  cx18 firmware functions
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  19  *  02111-1307  USA
  20  */
  21
  22 #include "cx18-driver.h"
  23 #include "cx18-io.h"
  24 #include "cx18-scb.h"
  25 #include "cx18-irq.h"
  26 #include "cx18-firmware.h"
  27 #include "cx18-cards.h"
  28 #include <linux/firmware.h>
  29
  30 #define CX18_PROC_SOFT_RESET            0xc70010
  31 #define CX18_DDR_SOFT_RESET             0xc70014
  32 #define CX18_CLOCK_SELECT1              0xc71000
  33 #define CX18_CLOCK_SELECT2              0xc71004
  34 #define CX18_HALF_CLOCK_SELECT1         0xc71008
  35 #define CX18_HALF_CLOCK_SELECT2         0xc7100C
  36 #define CX18_CLOCK_POLARITY1            0xc71010
  37 #define CX18_CLOCK_POLARITY2            0xc71014
  38 #define CX18_ADD_DELAY_ENABLE1          0xc71018
  39 #define CX18_ADD_DELAY_ENABLE2          0xc7101C
  40 #define CX18_CLOCK_ENABLE1              0xc71020
  41 #define CX18_CLOCK_ENABLE2              0xc71024
  42
  43 #define CX18_REG_BUS_TIMEOUT_EN         0xc72024
  44
  45 #define CX18_FAST_CLOCK_PLL_INT         0xc78000
  46 #define CX18_FAST_CLOCK_PLL_FRAC        0xc78004
  47 #define CX18_FAST_CLOCK_PLL_POST        0xc78008
  48 #define CX18_FAST_CLOCK_PLL_PRESCALE    0xc7800C
  49 #define CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH 0xc78010
  50
  51 #define CX18_SLOW_CLOCK_PLL_INT         0xc78014
  52 #define CX18_SLOW_CLOCK_PLL_FRAC        0xc78018
  53 #define CX18_SLOW_CLOCK_PLL_POST        0xc7801C
  54 #define CX18_MPEG_CLOCK_PLL_INT         0xc78040
  55 #define CX18_MPEG_CLOCK_PLL_FRAC        0xc78044
  56 #define CX18_MPEG_CLOCK_PLL_POST        0xc78048
  57 #define CX18_PLL_POWER_DOWN             0xc78088
  58 #define CX18_SW1_INT_STATUS             0xc73104
  59 #define CX18_SW1_INT_ENABLE_PCI         0xc7311C
  60 #define CX18_SW2_INT_SET                0xc73140
  61 #define CX18_SW2_INT_STATUS             0xc73144
  62 #define CX18_ADEC_CONTROL               0xc78120
  63
  64 #define CX18_DDR_REQUEST_ENABLE         0xc80000
  65 #define CX18_DDR_CHIP_CONFIG            0xc80004
  66 #define CX18_DDR_REFRESH                0xc80008
  67 #define CX18_DDR_TIMING1                0xc8000C
  68 #define CX18_DDR_TIMING2                0xc80010
  69 #define CX18_DDR_POWER_REG              0xc8001C
  70
  71 #define CX18_DDR_TUNE_LANE              0xc80048
  72 #define CX18_DDR_INITIAL_EMRS           0xc80054
  73 #define CX18_DDR_MB_PER_ROW_7           0xc8009C
  74 #define CX18_DDR_BASE_63_ADDR           0xc804FC
  75
  76 #define CX18_WMB_CLIENT02               0xc90108
  77 #define CX18_WMB_CLIENT05               0xc90114
  78 #define CX18_WMB_CLIENT06               0xc90118
  79 #define CX18_WMB_CLIENT07               0xc9011C
  80 #define CX18_WMB_CLIENT08               0xc90120
  81 #define CX18_WMB_CLIENT09               0xc90124
  82 #define CX18_WMB_CLIENT10               0xc90128
  83 #define CX18_WMB_CLIENT11               0xc9012C
  84 #define CX18_WMB_CLIENT12               0xc90130
  85 #define CX18_WMB_CLIENT13               0xc90134
  86 #define CX18_WMB_CLIENT14               0xc90138
  87
  88 #define CX18_DSP0_INTERRUPT_MASK        0xd0004C
  89
  90 #define APU_ROM_SYNC1 0x6D676553 /* "mgeS" */
  91 #define APU_ROM_SYNC2 0x72646548 /* "rdeH" */
  92
  93 struct cx18_apu_rom_seghdr {
  94         u32 sync1;
  95         u32 sync2;
  96         u32 addr;
  97         u32 size;
  98 };
  99
 100 static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx)
 101 {
 102         const struct firmware *fw = NULL;
 103         int i, j;
 104         unsigned size;
 105         u32 __iomem *dst = (u32 __iomem *)mem;
 106         const u32 *src;
 107
 108         if (request_firmware(&fw, fn, &cx->dev->dev)) {
 109                 CX18_ERR("Unable to open firmware %s\n", fn);
 110                 CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n");
 111                 return -ENOMEM;
 112         }
 113
 114         src = (const u32 *)fw->data;
 115
 116         for (i = 0; i < fw->size; i += 4096) {
 117                 cx18_setup_page(cx, i);
 118                 for (j = i; j < fw->size && j < i + 4096; j += 4) {
 119                         /* no need for endianness conversion on the ppc */
 120                         cx18_raw_writel(cx, *src, dst);
 121                         if (cx18_raw_readl(cx, dst) != *src) {
 122                                 CX18_ERR("Mismatch at offset %x\n", i);
 123                                 release_firmware(fw);
 124                                 return -EIO;
 125                         }
 126                         dst++;
 127                         src++;
 128                 }
 129         }
 130         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
 131                 CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size);
 132         size = fw->size;
 133         release_firmware(fw);
 134         return size;
 135 }
 136
 137 static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx)
 138 {
 139         const struct firmware *fw = NULL;
 140         int i, j;
 141         unsigned size;
 142         const u32 *src;
 143         struct cx18_apu_rom_seghdr seghdr;
 144         const u8 *vers;
 145         u32 offset = 0;
 146         u32 apu_version = 0;
 147         int sz;
 148
 149         if (request_firmware(&fw, fn, &cx->dev->dev)) {
 150                 CX18_ERR("unable to open firmware %s\n", fn);
 151                 CX18_ERR("did you put the firmware in the hotplug firmware directory?\n");
 152                 return -ENOMEM;
 153         }
 154
 155         src = (const u32 *)fw->data;
 156         vers = fw->data + sizeof(seghdr);
 157         sz = fw->size;
 158
 159         apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32];
 160         while (offset + sizeof(seghdr) < fw->size) {
 161                 /* TODO: byteswapping */
 162                 memcpy(&seghdr, src + offset / 4, sizeof(seghdr));
 163                 offset += sizeof(seghdr);
 164                 if (seghdr.sync1 != APU_ROM_SYNC1 ||
 165                     seghdr.sync2 != APU_ROM_SYNC2) {
 166                         offset += seghdr.size;
 167                         continue;
 168                 }
 169                 CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr,
 170                                 seghdr.addr + seghdr.size - 1);
 171                 if (offset + seghdr.size > sz)
 172                         break;
 173                 for (i = 0; i < seghdr.size; i += 4096) {
 174                         cx18_setup_page(cx, offset + i);
 175                         for (j = i; j < seghdr.size && j < i + 4096; j += 4) {
 176                                 /* no need for endianness conversion on the ppc */
 177                                 cx18_raw_writel(cx, src[(offset + j) / 4],
 178                                                 dst + seghdr.addr + j);
 179                                 if (cx18_raw_readl(cx, dst + seghdr.addr + j)
 180                                     != src[(offset + j) / 4]) {
 181                                         CX18_ERR("Mismatch at offset %x\n",
 182                                                  offset + j);
 183                                         release_firmware(fw);
 184                                         return -EIO;
 185                                 }
 186                         }
 187                 }
 188                 offset += seghdr.size;
 189         }
 190         if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags))
 191                 CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n",
 192                                 fn, apu_version, fw->size);
 193         size = fw->size;
 194         release_firmware(fw);
 195         /* Clear bit0 for APU to start from 0 */
 196         cx18_write_reg(cx, cx18_read_reg(cx, 0xc72030) & ~1, 0xc72030);
 197         return size;
 198 }
 199
 200 void cx18_halt_firmware(struct cx18 *cx)
 201 {
 202         CX18_DEBUG_INFO("Preparing for firmware halt.\n");
 203         cx18_write_reg(cx, 0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
 204         cx18_write_reg(cx, 0x00020002, CX18_ADEC_CONTROL);
 205 }
 206
 207 void cx18_init_power(struct cx18 *cx, int lowpwr)
 208 {
 209         /* power-down Spare and AOM PLLs */
 210         /* power-up fast, slow and mpeg PLLs */
 211         cx18_write_reg(cx, 0x00000008, CX18_PLL_POWER_DOWN);
 212
 213         /* ADEC out of sleep */
 214         cx18_write_reg(cx, 0x00020000, CX18_ADEC_CONTROL);
 215
 216         /* The fast clock is at 200/245 MHz */
 217         cx18_write_reg(cx, lowpwr ? 0xD : 0x11, CX18_FAST_CLOCK_PLL_INT);
 218         cx18_write_reg(cx, lowpwr ? 0x1EFBF37 : 0x038E3D7,
 219                                                 CX18_FAST_CLOCK_PLL_FRAC);
 220
 221         cx18_write_reg(cx, 2, CX18_FAST_CLOCK_PLL_POST);
 222         cx18_write_reg(cx, 1, CX18_FAST_CLOCK_PLL_PRESCALE);
 223         cx18_write_reg(cx, 4, CX18_FAST_CLOCK_PLL_ADJUST_BANDWIDTH);
 224
 225         /* set slow clock to 125/120 MHz */
 226         cx18_write_reg(cx, lowpwr ? 0x11 : 0x10, CX18_SLOW_CLOCK_PLL_INT);
 227         cx18_write_reg(cx, lowpwr ? 0xEBAF05 : 0x18618A8,
 228                                                 CX18_SLOW_CLOCK_PLL_FRAC);
 229         cx18_write_reg(cx, 4, CX18_SLOW_CLOCK_PLL_POST);
 230
 231         /* mpeg clock pll 54MHz */
 232         cx18_write_reg(cx, 0xF, CX18_MPEG_CLOCK_PLL_INT);
 233         cx18_write_reg(cx, 0x2BCFEF, CX18_MPEG_CLOCK_PLL_FRAC);
 234         cx18_write_reg(cx, 8, CX18_MPEG_CLOCK_PLL_POST);
 235
 236         /* Defaults */
 237         /* APU = SC or SC/2 = 125/62.5 */
 238         /* EPU = SC = 125 */
 239         /* DDR = FC = 180 */
 240         /* ENC = SC = 125 */
 241         /* AI1 = SC = 125 */
 242         /* VIM2 = disabled */
 243         /* PCI = FC/2 = 90 */
 244         /* AI2 = disabled */
 245         /* DEMUX = disabled */
 246         /* AO = SC/2 = 62.5 */
 247         /* SER = 54MHz */
 248         /* VFC = disabled */
 249         /* USB = disabled */
 250
 251         cx18_write_reg(cx, lowpwr ? 0xFFFF0020 : 0x00060004,
 252                                                         CX18_CLOCK_SELECT1);
 253         cx18_write_reg(cx, lowpwr ? 0xFFFF0004 : 0x00060006,
 254                                                         CX18_CLOCK_SELECT2);
 255
 256         cx18_write_reg(cx, 0xFFFF0002, CX18_HALF_CLOCK_SELECT1);
 257         cx18_write_reg(cx, 0xFFFF0104, CX18_HALF_CLOCK_SELECT2);
 258
 259         cx18_write_reg(cx, 0xFFFF9026, CX18_CLOCK_ENABLE1);
 260         cx18_write_reg(cx, 0xFFFF3105, CX18_CLOCK_ENABLE2);
 261 }
 262
 263 void cx18_init_memory(struct cx18 *cx)
 264 {
 265         cx18_msleep_timeout(10, 0);
 266         cx18_write_reg(cx, 0x10000, CX18_DDR_SOFT_RESET);
 267         cx18_msleep_timeout(10, 0);
 268
 269         cx18_write_reg(cx, cx->card->ddr.chip_config, CX18_DDR_CHIP_CONFIG);
 270
 271         cx18_msleep_timeout(10, 0);
 272
 273         cx18_write_reg(cx, cx->card->ddr.refresh, CX18_DDR_REFRESH);
 274         cx18_write_reg(cx, cx->card->ddr.timing1, CX18_DDR_TIMING1);
 275         cx18_write_reg(cx, cx->card->ddr.timing2, CX18_DDR_TIMING2);
 276
 277         cx18_msleep_timeout(10, 0);
 278
 279         /* Initialize DQS pad time */
 280         cx18_write_reg(cx, cx->card->ddr.tune_lane, CX18_DDR_TUNE_LANE);
 281         cx18_write_reg(cx, cx->card->ddr.initial_emrs, CX18_DDR_INITIAL_EMRS);
 282
 283         cx18_msleep_timeout(10, 0);
 284
 285         cx18_write_reg(cx, 0x20000, CX18_DDR_SOFT_RESET);
 286         cx18_msleep_timeout(10, 0);
 287
 288         /* use power-down mode when idle */
 289         cx18_write_reg(cx, 0x00000010, CX18_DDR_POWER_REG);
 290
 291         cx18_write_reg(cx, 0x10001, CX18_REG_BUS_TIMEOUT_EN);
 292
 293         cx18_write_reg(cx, 0x48, CX18_DDR_MB_PER_ROW_7);
 294         cx18_write_reg(cx, 0xE0000, CX18_DDR_BASE_63_ADDR);
 295
 296         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT02);  /* AO */
 297         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT09);  /* AI2 */
 298         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT05);  /* VIM1 */
 299         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT06);  /* AI1 */
 300         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT07);  /* 3D comb */
 301         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT10);  /* ME */
 302         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT12);  /* ENC */
 303         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT13);  /* PK */
 304         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT11);  /* RC */
 305         cx18_write_reg(cx, 0x00000101, CX18_WMB_CLIENT14);  /* AVO */
 306 }
 307
 308 int cx18_firmware_init(struct cx18 *cx)
 309 {
 310         /* Allow chip to control CLKRUN */
 311         cx18_write_reg(cx, 0x5, CX18_DSP0_INTERRUPT_MASK);
 312
 313         cx18_write_reg(cx, 0x000F000F, CX18_PROC_SOFT_RESET); /* stop the fw */
 314
 315         cx18_msleep_timeout(1, 0);
 316
 317         cx18_sw1_irq_enable(cx, IRQ_CPU_TO_EPU | IRQ_APU_TO_EPU);
 318         cx18_sw2_irq_enable(cx, IRQ_CPU_TO_EPU_ACK | IRQ_APU_TO_EPU_ACK);
 319
 320         /* Only if the processor is not running */
 321         if (cx18_read_reg(cx, CX18_PROC_SOFT_RESET) & 8) {
 322                 int sz = load_apu_fw_direct("v4l-cx23418-apu.fw",
 323                                cx->enc_mem, cx);
 324
 325                 cx18_write_enc(cx, 0xE51FF004, 0);
 326                 cx18_write_enc(cx, 0xa00000, 4);  /* todo: not hardcoded */
 327                 /* Start APU */
 328                 cx18_write_reg(cx, 0x00010000, CX18_PROC_SOFT_RESET);
 329                 cx18_msleep_timeout(500, 0);
 330
 331                 sz = sz <= 0 ? sz : load_cpu_fw_direct("v4l-cx23418-cpu.fw",
 332                                         cx->enc_mem, cx);
 333
 334                 if (sz > 0) {
 335                         int retries = 0;
 336
 337                         /* start the CPU */
 338                         cx18_write_reg(cx, 0x00080000, CX18_PROC_SOFT_RESET);
 339                         while (retries++ < 50) { /* Loop for max 500mS */
 340                                 if ((cx18_read_reg(cx, CX18_PROC_SOFT_RESET)
 341                                      & 1) == 0)
 342                                         break;
 343                                 cx18_msleep_timeout(10, 0);
 344                         }
 345                         cx18_msleep_timeout(200, 0);
 346                         if (retries == 51) {
 347                                 CX18_ERR("Could not start the CPU\n");
 348                                 return -EIO;
 349                         }
 350                 }
 351                 if (sz <= 0)
 352                         return -EIO;
 353         }
 354         /* initialize GPIO */
 355         cx18_write_reg(cx, 0x14001400, 0xC78110);
 356         return 0;
 357 }