git.oblomov.eu Git - linux-2.6/blob - drivers/net/niu.c

   1 /* niu.c: Neptune ethernet driver.
   2  *
   3  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/init.h>
   8 #include <linux/pci.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/netdevice.h>
  11 #include <linux/ethtool.h>
  12 #include <linux/etherdevice.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/delay.h>
  15 #include <linux/bitops.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_ether.h>
  18 #include <linux/if_vlan.h>
  19 #include <linux/ip.h>
  20 #include <linux/in.h>
  21 #include <linux/ipv6.h>
  22 #include <linux/log2.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/crc32.h>
  25
  26 #include <linux/io.h>
  27
  28 #ifdef CONFIG_SPARC64
  29 #include <linux/of_device.h>
  30 #endif
  31
  32 #include "niu.h"
  33
  34 #define DRV_MODULE_NAME         "niu"
  35 #define PFX DRV_MODULE_NAME     ": "
  36 #define DRV_MODULE_VERSION      "0.9"
  37 #define DRV_MODULE_RELDATE      "May 4, 2008"
  38
  39 static char version[] __devinitdata =
  40         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  41
  42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  43 MODULE_DESCRIPTION("NIU ethernet driver");
  44 MODULE_LICENSE("GPL");
  45 MODULE_VERSION(DRV_MODULE_VERSION);
  46
  47 #ifndef DMA_44BIT_MASK
  48 #define DMA_44BIT_MASK  0x00000fffffffffffULL
  49 #endif
  50
  51 #ifndef readq
  52 static u64 readq(void __iomem *reg)
  53 {
  54         return (((u64)readl(reg + 0x4UL) << 32) |
  55                 (u64)readl(reg));
  56 }
  57
  58 static void writeq(u64 val, void __iomem *reg)
  59 {
  60         writel(val & 0xffffffff, reg);
  61         writel(val >> 32, reg + 0x4UL);
  62 }
  63 #endif
  64
  65 static struct pci_device_id niu_pci_tbl[] = {
  66         {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
  67         {}
  68 };
  69
  70 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
  71
  72 #define NIU_TX_TIMEOUT                  (5 * HZ)
  73
  74 #define nr64(reg)               readq(np->regs + (reg))
  75 #define nw64(reg, val)          writeq((val), np->regs + (reg))
  76
  77 #define nr64_mac(reg)           readq(np->mac_regs + (reg))
  78 #define nw64_mac(reg, val)      writeq((val), np->mac_regs + (reg))
  79
  80 #define nr64_ipp(reg)           readq(np->regs + np->ipp_off + (reg))
  81 #define nw64_ipp(reg, val)      writeq((val), np->regs + np->ipp_off + (reg))
  82
  83 #define nr64_pcs(reg)           readq(np->regs + np->pcs_off + (reg))
  84 #define nw64_pcs(reg, val)      writeq((val), np->regs + np->pcs_off + (reg))
  85
  86 #define nr64_xpcs(reg)          readq(np->regs + np->xpcs_off + (reg))
  87 #define nw64_xpcs(reg, val)     writeq((val), np->regs + np->xpcs_off + (reg))
  88
  89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
  90
  91 static int niu_debug;
  92 static int debug = -1;
  93 module_param(debug, int, 0);
  94 MODULE_PARM_DESC(debug, "NIU debug level");
  95
  96 #define niudbg(TYPE, f, a...) \
  97 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
  98                 printk(KERN_DEBUG PFX f, ## a); \
  99 } while (0)
 100
 101 #define niuinfo(TYPE, f, a...) \
 102 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 103                 printk(KERN_INFO PFX f, ## a); \
 104 } while (0)
 105
 106 #define niuwarn(TYPE, f, a...) \
 107 do {    if ((np)->msg_enable & NETIF_MSG_##TYPE) \
 108                 printk(KERN_WARNING PFX f, ## a); \
 109 } while (0)
 110
 111 #define niu_lock_parent(np, flags) \
 112         spin_lock_irqsave(&np->parent->lock, flags)
 113 #define niu_unlock_parent(np, flags) \
 114         spin_unlock_irqrestore(&np->parent->lock, flags)
 115
 116 static int serdes_init_10g_serdes(struct niu *np);
 117
 118 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
 119                                      u64 bits, int limit, int delay)
 120 {
 121         while (--limit >= 0) {
 122                 u64 val = nr64_mac(reg);
 123
 124                 if (!(val & bits))
 125                         break;
 126                 udelay(delay);
 127         }
 128         if (limit < 0)
 129                 return -ENODEV;
 130         return 0;
 131 }
 132
 133 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
 134                                         u64 bits, int limit, int delay,
 135                                         const char *reg_name)
 136 {
 137         int err;
 138
 139         nw64_mac(reg, bits);
 140         err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
 141         if (err)
 142                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 143                         "would not clear, val[%llx]\n",
 144                         np->dev->name, (unsigned long long) bits, reg_name,
 145                         (unsigned long long) nr64_mac(reg));
 146         return err;
 147 }
 148
 149 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 150 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 151         __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 152 })
 153
 154 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
 155                                      u64 bits, int limit, int delay)
 156 {
 157         while (--limit >= 0) {
 158                 u64 val = nr64_ipp(reg);
 159
 160                 if (!(val & bits))
 161                         break;
 162                 udelay(delay);
 163         }
 164         if (limit < 0)
 165                 return -ENODEV;
 166         return 0;
 167 }
 168
 169 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
 170                                         u64 bits, int limit, int delay,
 171                                         const char *reg_name)
 172 {
 173         int err;
 174         u64 val;
 175
 176         val = nr64_ipp(reg);
 177         val |= bits;
 178         nw64_ipp(reg, val);
 179
 180         err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
 181         if (err)
 182                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 183                         "would not clear, val[%llx]\n",
 184                         np->dev->name, (unsigned long long) bits, reg_name,
 185                         (unsigned long long) nr64_ipp(reg));
 186         return err;
 187 }
 188
 189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 190 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 191         __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 192 })
 193
 194 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
 195                                  u64 bits, int limit, int delay)
 196 {
 197         while (--limit >= 0) {
 198                 u64 val = nr64(reg);
 199
 200                 if (!(val & bits))
 201                         break;
 202                 udelay(delay);
 203         }
 204         if (limit < 0)
 205                 return -ENODEV;
 206         return 0;
 207 }
 208
 209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
 210 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 211         __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
 212 })
 213
 214 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
 215                                     u64 bits, int limit, int delay,
 216                                     const char *reg_name)
 217 {
 218         int err;
 219
 220         nw64(reg, bits);
 221         err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
 222         if (err)
 223                 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
 224                         "would not clear, val[%llx]\n",
 225                         np->dev->name, (unsigned long long) bits, reg_name,
 226                         (unsigned long long) nr64(reg));
 227         return err;
 228 }
 229
 230 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
 231 ({      BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
 232         __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
 233 })
 234
 235 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
 236 {
 237         u64 val = (u64) lp->timer;
 238
 239         if (on)
 240                 val |= LDG_IMGMT_ARM;
 241
 242         nw64(LDG_IMGMT(lp->ldg_num), val);
 243 }
 244
 245 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
 246 {
 247         unsigned long mask_reg, bits;
 248         u64 val;
 249
 250         if (ldn < 0 || ldn > LDN_MAX)
 251                 return -EINVAL;
 252
 253         if (ldn < 64) {
 254                 mask_reg = LD_IM0(ldn);
 255                 bits = LD_IM0_MASK;
 256         } else {
 257                 mask_reg = LD_IM1(ldn - 64);
 258                 bits = LD_IM1_MASK;
 259         }
 260
 261         val = nr64(mask_reg);
 262         if (on)
 263                 val &= ~bits;
 264         else
 265                 val |= bits;
 266         nw64(mask_reg, val);
 267
 268         return 0;
 269 }
 270
 271 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
 272 {
 273         struct niu_parent *parent = np->parent;
 274         int i;
 275
 276         for (i = 0; i <= LDN_MAX; i++) {
 277                 int err;
 278
 279                 if (parent->ldg_map[i] != lp->ldg_num)
 280                         continue;
 281
 282                 err = niu_ldn_irq_enable(np, i, on);
 283                 if (err)
 284                         return err;
 285         }
 286         return 0;
 287 }
 288
 289 static int niu_enable_interrupts(struct niu *np, int on)
 290 {
 291         int i;
 292
 293         for (i = 0; i < np->num_ldg; i++) {
 294                 struct niu_ldg *lp = &np->ldg[i];
 295                 int err;
 296
 297                 err = niu_enable_ldn_in_ldg(np, lp, on);
 298                 if (err)
 299                         return err;
 300         }
 301         for (i = 0; i < np->num_ldg; i++)
 302                 niu_ldg_rearm(np, &np->ldg[i], on);
 303
 304         return 0;
 305 }
 306
 307 static u32 phy_encode(u32 type, int port)
 308 {
 309         return (type << (port * 2));
 310 }
 311
 312 static u32 phy_decode(u32 val, int port)
 313 {
 314         return (val >> (port * 2)) & PORT_TYPE_MASK;
 315 }
 316
 317 static int mdio_wait(struct niu *np)
 318 {
 319         int limit = 1000;
 320         u64 val;
 321
 322         while (--limit > 0) {
 323                 val = nr64(MIF_FRAME_OUTPUT);
 324                 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
 325                         return val & MIF_FRAME_OUTPUT_DATA;
 326
 327                 udelay(10);
 328         }
 329
 330         return -ENODEV;
 331 }
 332
 333 static int mdio_read(struct niu *np, int port, int dev, int reg)
 334 {
 335         int err;
 336
 337         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 338         err = mdio_wait(np);
 339         if (err < 0)
 340                 return err;
 341
 342         nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
 343         return mdio_wait(np);
 344 }
 345
 346 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
 347 {
 348         int err;
 349
 350         nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
 351         err = mdio_wait(np);
 352         if (err < 0)
 353                 return err;
 354
 355         nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
 356         err = mdio_wait(np);
 357         if (err < 0)
 358                 return err;
 359
 360         return 0;
 361 }
 362
 363 static int mii_read(struct niu *np, int port, int reg)
 364 {
 365         nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
 366         return mdio_wait(np);
 367 }
 368
 369 static int mii_write(struct niu *np, int port, int reg, int data)
 370 {
 371         int err;
 372
 373         nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
 374         err = mdio_wait(np);
 375         if (err < 0)
 376                 return err;
 377
 378         return 0;
 379 }
 380
 381 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
 382 {
 383         int err;
 384
 385         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 386                          ESR2_TI_PLL_TX_CFG_L(channel),
 387                          val & 0xffff);
 388         if (!err)
 389                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 390                                  ESR2_TI_PLL_TX_CFG_H(channel),
 391                                  val >> 16);
 392         return err;
 393 }
 394
 395 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
 396 {
 397         int err;
 398
 399         err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 400                          ESR2_TI_PLL_RX_CFG_L(channel),
 401                          val & 0xffff);
 402         if (!err)
 403                 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 404                                  ESR2_TI_PLL_RX_CFG_H(channel),
 405                                  val >> 16);
 406         return err;
 407 }
 408
 409 /* Mode is always 10G fiber.  */
 410 static int serdes_init_niu(struct niu *np)
 411 {
 412         struct niu_link_config *lp = &np->link_config;
 413         u32 tx_cfg, rx_cfg;
 414         unsigned long i;
 415
 416         tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
 417         rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
 418                   PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
 419                   PLL_RX_CFG_EQ_LP_ADAPTIVE);
 420
 421         if (lp->loopback_mode == LOOPBACK_PHY) {
 422                 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
 423
 424                 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
 425                            ESR2_TI_PLL_TEST_CFG_L, test_cfg);
 426
 427                 tx_cfg |= PLL_TX_CFG_ENTEST;
 428                 rx_cfg |= PLL_RX_CFG_ENTEST;
 429         }
 430
 431         /* Initialize all 4 lanes of the SERDES.  */
 432         for (i = 0; i < 4; i++) {
 433                 int err = esr2_set_tx_cfg(np, i, tx_cfg);
 434                 if (err)
 435                         return err;
 436         }
 437
 438         for (i = 0; i < 4; i++) {
 439                 int err = esr2_set_rx_cfg(np, i, rx_cfg);
 440                 if (err)
 441                         return err;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
 448 {
 449         int err;
 450
 451         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
 452         if (err >= 0) {
 453                 *val = (err & 0xffff);
 454                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 455                                 ESR_RXTX_CTRL_H(chan));
 456                 if (err >= 0)
 457                         *val |= ((err & 0xffff) << 16);
 458                 err = 0;
 459         }
 460         return err;
 461 }
 462
 463 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
 464 {
 465         int err;
 466
 467         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 468                         ESR_GLUE_CTRL0_L(chan));
 469         if (err >= 0) {
 470                 *val = (err & 0xffff);
 471                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 472                                 ESR_GLUE_CTRL0_H(chan));
 473                 if (err >= 0) {
 474                         *val |= ((err & 0xffff) << 16);
 475                         err = 0;
 476                 }
 477         }
 478         return err;
 479 }
 480
 481 static int esr_read_reset(struct niu *np, u32 *val)
 482 {
 483         int err;
 484
 485         err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 486                         ESR_RXTX_RESET_CTRL_L);
 487         if (err >= 0) {
 488                 *val = (err & 0xffff);
 489                 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
 490                                 ESR_RXTX_RESET_CTRL_H);
 491                 if (err >= 0) {
 492                         *val |= ((err & 0xffff) << 16);
 493                         err = 0;
 494                 }
 495         }
 496         return err;
 497 }
 498
 499 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
 500 {
 501         int err;
 502
 503         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 504                          ESR_RXTX_CTRL_L(chan), val & 0xffff);
 505         if (!err)
 506                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 507                                  ESR_RXTX_CTRL_H(chan), (val >> 16));
 508         return err;
 509 }
 510
 511 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
 512 {
 513         int err;
 514
 515         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 516                         ESR_GLUE_CTRL0_L(chan), val & 0xffff);
 517         if (!err)
 518                 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 519                                  ESR_GLUE_CTRL0_H(chan), (val >> 16));
 520         return err;
 521 }
 522
 523 static int esr_reset(struct niu *np)
 524 {
 525         u32 reset;
 526         int err;
 527
 528         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 529                          ESR_RXTX_RESET_CTRL_L, 0x0000);
 530         if (err)
 531                 return err;
 532         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 533                          ESR_RXTX_RESET_CTRL_H, 0xffff);
 534         if (err)
 535                 return err;
 536         udelay(200);
 537
 538         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 539                          ESR_RXTX_RESET_CTRL_L, 0xffff);
 540         if (err)
 541                 return err;
 542         udelay(200);
 543
 544         err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
 545                          ESR_RXTX_RESET_CTRL_H, 0x0000);
 546         if (err)
 547                 return err;
 548         udelay(200);
 549
 550         err = esr_read_reset(np, &reset);
 551         if (err)
 552                 return err;
 553         if (reset != 0) {
 554                 dev_err(np->device, PFX "Port %u ESR_RESET "
 555                         "did not clear [%08x]\n",
 556                         np->port, reset);
 557                 return -ENODEV;
 558         }
 559
 560         return 0;
 561 }
 562
 563 static int serdes_init_10g(struct niu *np)
 564 {
 565         struct niu_link_config *lp = &np->link_config;
 566         unsigned long ctrl_reg, test_cfg_reg, i;
 567         u64 ctrl_val, test_cfg_val, sig, mask, val;
 568         int err;
 569
 570         switch (np->port) {
 571         case 0:
 572                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 573                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 574                 break;
 575         case 1:
 576                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 577                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 578                 break;
 579
 580         default:
 581                 return -EINVAL;
 582         }
 583         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 584                     ENET_SERDES_CTRL_SDET_1 |
 585                     ENET_SERDES_CTRL_SDET_2 |
 586                     ENET_SERDES_CTRL_SDET_3 |
 587                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 588                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 589                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 590                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 591                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 592                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 593                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 594                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 595         test_cfg_val = 0;
 596
 597         if (lp->loopback_mode == LOOPBACK_PHY) {
 598                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 599                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 600                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 601                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 602                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 603                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 604                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 605                                   ENET_SERDES_TEST_MD_3_SHIFT));
 606         }
 607
 608         nw64(ctrl_reg, ctrl_val);
 609         nw64(test_cfg_reg, test_cfg_val);
 610
 611         /* Initialize all 4 lanes of the SERDES.  */
 612         for (i = 0; i < 4; i++) {
 613                 u32 rxtx_ctrl, glue0;
 614
 615                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 616                 if (err)
 617                         return err;
 618                 err = esr_read_glue0(np, i, &glue0);
 619                 if (err)
 620                         return err;
 621
 622                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 623                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 624                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 625
 626                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 627                            ESR_GLUE_CTRL0_THCNT |
 628                            ESR_GLUE_CTRL0_BLTIME);
 629                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 630                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 631                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 632                           (BLTIME_300_CYCLES <<
 633                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 634
 635                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 636                 if (err)
 637                         return err;
 638                 err = esr_write_glue0(np, i, glue0);
 639                 if (err)
 640                         return err;
 641         }
 642
 643         err = esr_reset(np);
 644         if (err)
 645                 return err;
 646
 647         sig = nr64(ESR_INT_SIGNALS);
 648         switch (np->port) {
 649         case 0:
 650                 mask = ESR_INT_SIGNALS_P0_BITS;
 651                 val = (ESR_INT_SRDY0_P0 |
 652                        ESR_INT_DET0_P0 |
 653                        ESR_INT_XSRDY_P0 |
 654                        ESR_INT_XDP_P0_CH3 |
 655                        ESR_INT_XDP_P0_CH2 |
 656                        ESR_INT_XDP_P0_CH1 |
 657                        ESR_INT_XDP_P0_CH0);
 658                 break;
 659
 660         case 1:
 661                 mask = ESR_INT_SIGNALS_P1_BITS;
 662                 val = (ESR_INT_SRDY0_P1 |
 663                        ESR_INT_DET0_P1 |
 664                        ESR_INT_XSRDY_P1 |
 665                        ESR_INT_XDP_P1_CH3 |
 666                        ESR_INT_XDP_P1_CH2 |
 667                        ESR_INT_XDP_P1_CH1 |
 668                        ESR_INT_XDP_P1_CH0);
 669                 break;
 670
 671         default:
 672                 return -EINVAL;
 673         }
 674
 675         if ((sig & mask) != val) {
 676                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
 677                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 678                         return 0;
 679                 }
 680                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 681                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 682                 return -ENODEV;
 683         }
 684         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
 685                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
 686         return 0;
 687 }
 688
 689 static int serdes_init_1g(struct niu *np)
 690 {
 691         u64 val;
 692
 693         val = nr64(ENET_SERDES_1_PLL_CFG);
 694         val &= ~ENET_SERDES_PLL_FBDIV2;
 695         switch (np->port) {
 696         case 0:
 697                 val |= ENET_SERDES_PLL_HRATE0;
 698                 break;
 699         case 1:
 700                 val |= ENET_SERDES_PLL_HRATE1;
 701                 break;
 702         case 2:
 703                 val |= ENET_SERDES_PLL_HRATE2;
 704                 break;
 705         case 3:
 706                 val |= ENET_SERDES_PLL_HRATE3;
 707                 break;
 708         default:
 709                 return -EINVAL;
 710         }
 711         nw64(ENET_SERDES_1_PLL_CFG, val);
 712
 713         return 0;
 714 }
 715
 716 static int serdes_init_1g_serdes(struct niu *np)
 717 {
 718         struct niu_link_config *lp = &np->link_config;
 719         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
 720         u64 ctrl_val, test_cfg_val, sig, mask, val;
 721         int err;
 722         u64 reset_val, val_rd;
 723
 724         val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
 725                 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
 726                 ENET_SERDES_PLL_FBDIV0;
 727         switch (np->port) {
 728         case 0:
 729                 reset_val =  ENET_SERDES_RESET_0;
 730                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
 731                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
 732                 pll_cfg = ENET_SERDES_0_PLL_CFG;
 733                 break;
 734         case 1:
 735                 reset_val =  ENET_SERDES_RESET_1;
 736                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
 737                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
 738                 pll_cfg = ENET_SERDES_1_PLL_CFG;
 739                 break;
 740
 741         default:
 742                 return -EINVAL;
 743         }
 744         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
 745                     ENET_SERDES_CTRL_SDET_1 |
 746                     ENET_SERDES_CTRL_SDET_2 |
 747                     ENET_SERDES_CTRL_SDET_3 |
 748                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
 749                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
 750                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
 751                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
 752                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
 753                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
 754                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
 755                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
 756         test_cfg_val = 0;
 757
 758         if (lp->loopback_mode == LOOPBACK_PHY) {
 759                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
 760                                   ENET_SERDES_TEST_MD_0_SHIFT) |
 761                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 762                                   ENET_SERDES_TEST_MD_1_SHIFT) |
 763                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 764                                   ENET_SERDES_TEST_MD_2_SHIFT) |
 765                                  (ENET_TEST_MD_PAD_LOOPBACK <<
 766                                   ENET_SERDES_TEST_MD_3_SHIFT));
 767         }
 768
 769         nw64(ENET_SERDES_RESET, reset_val);
 770         mdelay(20);
 771         val_rd = nr64(ENET_SERDES_RESET);
 772         val_rd &= ~reset_val;
 773         nw64(pll_cfg, val);
 774         nw64(ctrl_reg, ctrl_val);
 775         nw64(test_cfg_reg, test_cfg_val);
 776         nw64(ENET_SERDES_RESET, val_rd);
 777         mdelay(2000);
 778
 779         /* Initialize all 4 lanes of the SERDES.  */
 780         for (i = 0; i < 4; i++) {
 781                 u32 rxtx_ctrl, glue0;
 782
 783                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
 784                 if (err)
 785                         return err;
 786                 err = esr_read_glue0(np, i, &glue0);
 787                 if (err)
 788                         return err;
 789
 790                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
 791                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
 792                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
 793
 794                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
 795                            ESR_GLUE_CTRL0_THCNT |
 796                            ESR_GLUE_CTRL0_BLTIME);
 797                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
 798                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
 799                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
 800                           (BLTIME_300_CYCLES <<
 801                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
 802
 803                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
 804                 if (err)
 805                         return err;
 806                 err = esr_write_glue0(np, i, glue0);
 807                 if (err)
 808                         return err;
 809         }
 810
 811
 812         sig = nr64(ESR_INT_SIGNALS);
 813         switch (np->port) {
 814         case 0:
 815                 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
 816                 mask = val;
 817                 break;
 818
 819         case 1:
 820                 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
 821                 mask = val;
 822                 break;
 823
 824         default:
 825                 return -EINVAL;
 826         }
 827
 828         if ((sig & mask) != val) {
 829                 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
 830                         "[%08x]\n", np->port, (int) (sig & mask), (int) val);
 831                 return -ENODEV;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int link_status_1g_serdes(struct niu *np, int *link_up_p)
 838 {
 839         struct niu_link_config *lp = &np->link_config;
 840         int link_up;
 841         u64 val;
 842         u16 current_speed;
 843         unsigned long flags;
 844         u8 current_duplex;
 845
 846         link_up = 0;
 847         current_speed = SPEED_INVALID;
 848         current_duplex = DUPLEX_INVALID;
 849
 850         spin_lock_irqsave(&np->lock, flags);
 851
 852         val = nr64_pcs(PCS_MII_STAT);
 853
 854         if (val & PCS_MII_STAT_LINK_STATUS) {
 855                 link_up = 1;
 856                 current_speed = SPEED_1000;
 857                 current_duplex = DUPLEX_FULL;
 858         }
 859
 860         lp->active_speed = current_speed;
 861         lp->active_duplex = current_duplex;
 862         spin_unlock_irqrestore(&np->lock, flags);
 863
 864         *link_up_p = link_up;
 865         return 0;
 866 }
 867
 868 static int link_status_10g_serdes(struct niu *np, int *link_up_p)
 869 {
 870         unsigned long flags;
 871         struct niu_link_config *lp = &np->link_config;
 872         int link_up = 0;
 873         int link_ok = 1;
 874         u64 val, val2;
 875         u16 current_speed;
 876         u8 current_duplex;
 877
 878         if (!(np->flags & NIU_FLAGS_10G))
 879                 return link_status_1g_serdes(np, link_up_p);
 880
 881         current_speed = SPEED_INVALID;
 882         current_duplex = DUPLEX_INVALID;
 883         spin_lock_irqsave(&np->lock, flags);
 884
 885         val = nr64_xpcs(XPCS_STATUS(0));
 886         val2 = nr64_mac(XMAC_INTER2);
 887         if (val2 & 0x01000000)
 888                 link_ok = 0;
 889
 890         if ((val & 0x1000ULL) && link_ok) {
 891                 link_up = 1;
 892                 current_speed = SPEED_10000;
 893                 current_duplex = DUPLEX_FULL;
 894         }
 895         lp->active_speed = current_speed;
 896         lp->active_duplex = current_duplex;
 897         spin_unlock_irqrestore(&np->lock, flags);
 898         *link_up_p = link_up;
 899         return 0;
 900 }
 901
 902 static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
 903 {
 904         struct niu_link_config *lp = &np->link_config;
 905         u16 current_speed, bmsr;
 906         unsigned long flags;
 907         u8 current_duplex;
 908         int err, link_up;
 909
 910         link_up = 0;
 911         current_speed = SPEED_INVALID;
 912         current_duplex = DUPLEX_INVALID;
 913
 914         spin_lock_irqsave(&np->lock, flags);
 915
 916         err = -EINVAL;
 917
 918         err = mii_read(np, np->phy_addr, MII_BMSR);
 919         if (err < 0)
 920                 goto out;
 921
 922         bmsr = err;
 923         if (bmsr & BMSR_LSTATUS) {
 924                 u16 adv, lpa, common, estat;
 925
 926                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
 927                 if (err < 0)
 928                         goto out;
 929                 adv = err;
 930
 931                 err = mii_read(np, np->phy_addr, MII_LPA);
 932                 if (err < 0)
 933                         goto out;
 934                 lpa = err;
 935
 936                 common = adv & lpa;
 937
 938                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
 939                 if (err < 0)
 940                         goto out;
 941                 estat = err;
 942                 link_up = 1;
 943                 current_speed = SPEED_1000;
 944                 current_duplex = DUPLEX_FULL;
 945
 946         }
 947         lp->active_speed = current_speed;
 948         lp->active_duplex = current_duplex;
 949         err = 0;
 950
 951 out:
 952         spin_unlock_irqrestore(&np->lock, flags);
 953
 954         *link_up_p = link_up;
 955         return err;
 956 }
 957
 958 static int bcm8704_reset(struct niu *np)
 959 {
 960         int err, limit;
 961
 962         err = mdio_read(np, np->phy_addr,
 963                         BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
 964         if (err < 0)
 965                 return err;
 966         err |= BMCR_RESET;
 967         err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
 968                          MII_BMCR, err);
 969         if (err)
 970                 return err;
 971
 972         limit = 1000;
 973         while (--limit >= 0) {
 974                 err = mdio_read(np, np->phy_addr,
 975                                 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
 976                 if (err < 0)
 977                         return err;
 978                 if (!(err & BMCR_RESET))
 979                         break;
 980         }
 981         if (limit < 0) {
 982                 dev_err(np->device, PFX "Port %u PHY will not reset "
 983                         "(bmcr=%04x)\n", np->port, (err & 0xffff));
 984                 return -ENODEV;
 985         }
 986         return 0;
 987 }
 988
 989 /* When written, certain PHY registers need to be read back twice
 990  * in order for the bits to settle properly.
 991  */
 992 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
 993 {
 994         int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
 995         if (err < 0)
 996                 return err;
 997         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
 998         if (err < 0)
 999                 return err;
1000         return 0;
1001 }
1002
1003 static int bcm8706_init_user_dev3(struct niu *np)
1004 {
1005         int err;
1006
1007
1008         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1009                         BCM8704_USER_OPT_DIGITAL_CTRL);
1010         if (err < 0)
1011                 return err;
1012         err &= ~USER_ODIG_CTRL_GPIOS;
1013         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1014         err |=  USER_ODIG_CTRL_RESV2;
1015         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1016                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1017         if (err)
1018                 return err;
1019
1020         mdelay(1000);
1021
1022         return 0;
1023 }
1024
1025 static int bcm8704_init_user_dev3(struct niu *np)
1026 {
1027         int err;
1028
1029         err = mdio_write(np, np->phy_addr,
1030                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1031                          (USER_CONTROL_OPTXRST_LVL |
1032                           USER_CONTROL_OPBIASFLT_LVL |
1033                           USER_CONTROL_OBTMPFLT_LVL |
1034                           USER_CONTROL_OPPRFLT_LVL |
1035                           USER_CONTROL_OPTXFLT_LVL |
1036                           USER_CONTROL_OPRXLOS_LVL |
1037                           USER_CONTROL_OPRXFLT_LVL |
1038                           USER_CONTROL_OPTXON_LVL |
1039                           (0x3f << USER_CONTROL_RES1_SHIFT)));
1040         if (err)
1041                 return err;
1042
1043         err = mdio_write(np, np->phy_addr,
1044                          BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1045                          (USER_PMD_TX_CTL_XFP_CLKEN |
1046                           (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1047                           (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1048                           USER_PMD_TX_CTL_TSCK_LPWREN));
1049         if (err)
1050                 return err;
1051
1052         err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1053         if (err)
1054                 return err;
1055         err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1056         if (err)
1057                 return err;
1058
1059         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1060                         BCM8704_USER_OPT_DIGITAL_CTRL);
1061         if (err < 0)
1062                 return err;
1063         err &= ~USER_ODIG_CTRL_GPIOS;
1064         err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1065         err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1066                          BCM8704_USER_OPT_DIGITAL_CTRL, err);
1067         if (err)
1068                 return err;
1069
1070         mdelay(1000);
1071
1072         return 0;
1073 }
1074
1075 static int mrvl88x2011_act_led(struct niu *np, int val)
1076 {
1077         int     err;
1078
1079         err  = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1080                 MRVL88X2011_LED_8_TO_11_CTL);
1081         if (err < 0)
1082                 return err;
1083
1084         err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1085         err |=  MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1086
1087         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1088                           MRVL88X2011_LED_8_TO_11_CTL, err);
1089 }
1090
1091 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1092 {
1093         int     err;
1094
1095         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1096                         MRVL88X2011_LED_BLINK_CTL);
1097         if (err >= 0) {
1098                 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1099                 err |= (rate << 4);
1100
1101                 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1102                                  MRVL88X2011_LED_BLINK_CTL, err);
1103         }
1104
1105         return err;
1106 }
1107
1108 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1109 {
1110         int     err;
1111
1112         /* Set LED functions */
1113         err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1114         if (err)
1115                 return err;
1116
1117         /* led activity */
1118         err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1119         if (err)
1120                 return err;
1121
1122         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1123                         MRVL88X2011_GENERAL_CTL);
1124         if (err < 0)
1125                 return err;
1126
1127         err |= MRVL88X2011_ENA_XFPREFCLK;
1128
1129         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1130                          MRVL88X2011_GENERAL_CTL, err);
1131         if (err < 0)
1132                 return err;
1133
1134         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1135                         MRVL88X2011_PMA_PMD_CTL_1);
1136         if (err < 0)
1137                 return err;
1138
1139         if (np->link_config.loopback_mode == LOOPBACK_MAC)
1140                 err |= MRVL88X2011_LOOPBACK;
1141         else
1142                 err &= ~MRVL88X2011_LOOPBACK;
1143
1144         err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1145                          MRVL88X2011_PMA_PMD_CTL_1, err);
1146         if (err < 0)
1147                 return err;
1148
1149         /* Enable PMD  */
1150         return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1151                           MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1152 }
1153
1154
1155 static int xcvr_diag_bcm870x(struct niu *np)
1156 {
1157         u16 analog_stat0, tx_alarm_status;
1158         int err = 0;
1159
1160 #if 1
1161         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1162                         MII_STAT1000);
1163         if (err < 0)
1164                 return err;
1165         pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1166                 np->port, err);
1167
1168         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1169         if (err < 0)
1170                 return err;
1171         pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1172                 np->port, err);
1173
1174         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1175                         MII_NWAYTEST);
1176         if (err < 0)
1177                 return err;
1178         pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1179                 np->port, err);
1180 #endif
1181
1182         /* XXX dig this out it might not be so useful XXX */
1183         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1184                         BCM8704_USER_ANALOG_STATUS0);
1185         if (err < 0)
1186                 return err;
1187         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1188                         BCM8704_USER_ANALOG_STATUS0);
1189         if (err < 0)
1190                 return err;
1191         analog_stat0 = err;
1192
1193         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1194                         BCM8704_USER_TX_ALARM_STATUS);
1195         if (err < 0)
1196                 return err;
1197         err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1198                         BCM8704_USER_TX_ALARM_STATUS);
1199         if (err < 0)
1200                 return err;
1201         tx_alarm_status = err;
1202
1203         if (analog_stat0 != 0x03fc) {
1204                 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1205                         pr_info(PFX "Port %u cable not connected "
1206                                 "or bad cable.\n", np->port);
1207                 } else if (analog_stat0 == 0x639c) {
1208                         pr_info(PFX "Port %u optical module is bad "
1209                                 "or missing.\n", np->port);
1210                 }
1211         }
1212
1213         return 0;
1214 }
1215
1216 static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1217 {
1218         struct niu_link_config *lp = &np->link_config;
1219         int err;
1220
1221         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1222                         MII_BMCR);
1223         if (err < 0)
1224                 return err;
1225
1226         err &= ~BMCR_LOOPBACK;
1227
1228         if (lp->loopback_mode == LOOPBACK_MAC)
1229                 err |= BMCR_LOOPBACK;
1230
1231         err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1232                          MII_BMCR, err);
1233         if (err)
1234                 return err;
1235
1236         return 0;
1237 }
1238
1239 static int xcvr_init_10g_bcm8706(struct niu *np)
1240 {
1241         int err = 0;
1242         u64 val;
1243
1244         if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1245             (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1246                         return err;
1247
1248         val = nr64_mac(XMAC_CONFIG);
1249         val &= ~XMAC_CONFIG_LED_POLARITY;
1250         val |= XMAC_CONFIG_FORCE_LED_ON;
1251         nw64_mac(XMAC_CONFIG, val);
1252
1253         val = nr64(MIF_CONFIG);
1254         val |= MIF_CONFIG_INDIRECT_MODE;
1255         nw64(MIF_CONFIG, val);
1256
1257         err = bcm8704_reset(np);
1258         if (err)
1259                 return err;
1260
1261         err = xcvr_10g_set_lb_bcm870x(np);
1262         if (err)
1263                 return err;
1264
1265         err = bcm8706_init_user_dev3(np);
1266         if (err)
1267                 return err;
1268
1269         err = xcvr_diag_bcm870x(np);
1270         if (err)
1271                 return err;
1272
1273         return 0;
1274 }
1275
1276 static int xcvr_init_10g_bcm8704(struct niu *np)
1277 {
1278         int err;
1279
1280         err = bcm8704_reset(np);
1281         if (err)
1282                 return err;
1283
1284         err = bcm8704_init_user_dev3(np);
1285         if (err)
1286                 return err;
1287
1288         err = xcvr_10g_set_lb_bcm870x(np);
1289         if (err)
1290                 return err;
1291
1292         err =  xcvr_diag_bcm870x(np);
1293         if (err)
1294                 return err;
1295
1296         return 0;
1297 }
1298
1299 static int xcvr_init_10g(struct niu *np)
1300 {
1301         int phy_id, err;
1302         u64 val;
1303
1304         val = nr64_mac(XMAC_CONFIG);
1305         val &= ~XMAC_CONFIG_LED_POLARITY;
1306         val |= XMAC_CONFIG_FORCE_LED_ON;
1307         nw64_mac(XMAC_CONFIG, val);
1308
1309         /* XXX shared resource, lock parent XXX */
1310         val = nr64(MIF_CONFIG);
1311         val |= MIF_CONFIG_INDIRECT_MODE;
1312         nw64(MIF_CONFIG, val);
1313
1314         phy_id = phy_decode(np->parent->port_phy, np->port);
1315         phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1316
1317         /* handle different phy types */
1318         switch (phy_id & NIU_PHY_ID_MASK) {
1319         case NIU_PHY_ID_MRVL88X2011:
1320                 err = xcvr_init_10g_mrvl88x2011(np);
1321                 break;
1322
1323         default: /* bcom 8704 */
1324                 err = xcvr_init_10g_bcm8704(np);
1325                 break;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int mii_reset(struct niu *np)
1332 {
1333         int limit, err;
1334
1335         err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1336         if (err)
1337                 return err;
1338
1339         limit = 1000;
1340         while (--limit >= 0) {
1341                 udelay(500);
1342                 err = mii_read(np, np->phy_addr, MII_BMCR);
1343                 if (err < 0)
1344                         return err;
1345                 if (!(err & BMCR_RESET))
1346                         break;
1347         }
1348         if (limit < 0) {
1349                 dev_err(np->device, PFX "Port %u MII would not reset, "
1350                         "bmcr[%04x]\n", np->port, err);
1351                 return -ENODEV;
1352         }
1353
1354         return 0;
1355 }
1356
1357 static int xcvr_init_1g_rgmii(struct niu *np)
1358 {
1359         int err;
1360         u64 val;
1361         u16 bmcr, bmsr, estat;
1362
1363         val = nr64(MIF_CONFIG);
1364         val &= ~MIF_CONFIG_INDIRECT_MODE;
1365         nw64(MIF_CONFIG, val);
1366
1367         err = mii_reset(np);
1368         if (err)
1369                 return err;
1370
1371         err = mii_read(np, np->phy_addr, MII_BMSR);
1372         if (err < 0)
1373                 return err;
1374         bmsr = err;
1375
1376         estat = 0;
1377         if (bmsr & BMSR_ESTATEN) {
1378                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1379                 if (err < 0)
1380                         return err;
1381                 estat = err;
1382         }
1383
1384         bmcr = 0;
1385         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1386         if (err)
1387                 return err;
1388
1389         if (bmsr & BMSR_ESTATEN) {
1390                 u16 ctrl1000 = 0;
1391
1392                 if (estat & ESTATUS_1000_TFULL)
1393                         ctrl1000 |= ADVERTISE_1000FULL;
1394                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1395                 if (err)
1396                         return err;
1397         }
1398
1399         bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1400
1401         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1402         if (err)
1403                 return err;
1404
1405         err = mii_read(np, np->phy_addr, MII_BMCR);
1406         if (err < 0)
1407                 return err;
1408         bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1409
1410         err = mii_read(np, np->phy_addr, MII_BMSR);
1411         if (err < 0)
1412                 return err;
1413
1414         return 0;
1415 }
1416
1417 static int mii_init_common(struct niu *np)
1418 {
1419         struct niu_link_config *lp = &np->link_config;
1420         u16 bmcr, bmsr, adv, estat;
1421         int err;
1422
1423         err = mii_reset(np);
1424         if (err)
1425                 return err;
1426
1427         err = mii_read(np, np->phy_addr, MII_BMSR);
1428         if (err < 0)
1429                 return err;
1430         bmsr = err;
1431
1432         estat = 0;
1433         if (bmsr & BMSR_ESTATEN) {
1434                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1435                 if (err < 0)
1436                         return err;
1437                 estat = err;
1438         }
1439
1440         bmcr = 0;
1441         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1442         if (err)
1443                 return err;
1444
1445         if (lp->loopback_mode == LOOPBACK_MAC) {
1446                 bmcr |= BMCR_LOOPBACK;
1447                 if (lp->active_speed == SPEED_1000)
1448                         bmcr |= BMCR_SPEED1000;
1449                 if (lp->active_duplex == DUPLEX_FULL)
1450                         bmcr |= BMCR_FULLDPLX;
1451         }
1452
1453         if (lp->loopback_mode == LOOPBACK_PHY) {
1454                 u16 aux;
1455
1456                 aux = (BCM5464R_AUX_CTL_EXT_LB |
1457                        BCM5464R_AUX_CTL_WRITE_1);
1458                 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1459                 if (err)
1460                         return err;
1461         }
1462
1463         /* XXX configurable XXX */
1464         /* XXX for now don't advertise half-duplex or asym pause... XXX */
1465         adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1466         if (bmsr & BMSR_10FULL)
1467                 adv |= ADVERTISE_10FULL;
1468         if (bmsr & BMSR_100FULL)
1469                 adv |= ADVERTISE_100FULL;
1470         err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1471         if (err)
1472                 return err;
1473
1474         if (bmsr & BMSR_ESTATEN) {
1475                 u16 ctrl1000 = 0;
1476
1477                 if (estat & ESTATUS_1000_TFULL)
1478                         ctrl1000 |= ADVERTISE_1000FULL;
1479                 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1480                 if (err)
1481                         return err;
1482         }
1483         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1484
1485         err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1486         if (err)
1487                 return err;
1488
1489         err = mii_read(np, np->phy_addr, MII_BMCR);
1490         if (err < 0)
1491                 return err;
1492         err = mii_read(np, np->phy_addr, MII_BMSR);
1493         if (err < 0)
1494                 return err;
1495 #if 0
1496         pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1497                 np->port, bmcr, bmsr);
1498 #endif
1499
1500         return 0;
1501 }
1502
1503 static int xcvr_init_1g(struct niu *np)
1504 {
1505         u64 val;
1506
1507         /* XXX shared resource, lock parent XXX */
1508         val = nr64(MIF_CONFIG);
1509         val &= ~MIF_CONFIG_INDIRECT_MODE;
1510         nw64(MIF_CONFIG, val);
1511
1512         return mii_init_common(np);
1513 }
1514
1515 static int niu_xcvr_init(struct niu *np)
1516 {
1517         const struct niu_phy_ops *ops = np->phy_ops;
1518         int err;
1519
1520         err = 0;
1521         if (ops->xcvr_init)
1522                 err = ops->xcvr_init(np);
1523
1524         return err;
1525 }
1526
1527 static int niu_serdes_init(struct niu *np)
1528 {
1529         const struct niu_phy_ops *ops = np->phy_ops;
1530         int err;
1531
1532         err = 0;
1533         if (ops->serdes_init)
1534                 err = ops->serdes_init(np);
1535
1536         return err;
1537 }
1538
1539 static void niu_init_xif(struct niu *);
1540 static void niu_handle_led(struct niu *, int status);
1541
1542 static int niu_link_status_common(struct niu *np, int link_up)
1543 {
1544         struct niu_link_config *lp = &np->link_config;
1545         struct net_device *dev = np->dev;
1546         unsigned long flags;
1547
1548         if (!netif_carrier_ok(dev) && link_up) {
1549                 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1550                        dev->name,
1551                        (lp->active_speed == SPEED_10000 ?
1552                         "10Gb/sec" :
1553                         (lp->active_speed == SPEED_1000 ?
1554                          "1Gb/sec" :
1555                          (lp->active_speed == SPEED_100 ?
1556                           "100Mbit/sec" : "10Mbit/sec"))),
1557                        (lp->active_duplex == DUPLEX_FULL ?
1558                         "full" : "half"));
1559
1560                 spin_lock_irqsave(&np->lock, flags);
1561                 niu_init_xif(np);
1562                 niu_handle_led(np, 1);
1563                 spin_unlock_irqrestore(&np->lock, flags);
1564
1565                 netif_carrier_on(dev);
1566         } else if (netif_carrier_ok(dev) && !link_up) {
1567                 niuwarn(LINK, "%s: Link is down\n", dev->name);
1568                 spin_lock_irqsave(&np->lock, flags);
1569                 niu_handle_led(np, 0);
1570                 spin_unlock_irqrestore(&np->lock, flags);
1571                 netif_carrier_off(dev);
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1578 {
1579         int err, link_up, pma_status, pcs_status;
1580
1581         link_up = 0;
1582
1583         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1584                         MRVL88X2011_10G_PMD_STATUS_2);
1585         if (err < 0)
1586                 goto out;
1587
1588         /* Check PMA/PMD Register: 1.0001.2 == 1 */
1589         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1590                         MRVL88X2011_PMA_PMD_STATUS_1);
1591         if (err < 0)
1592                 goto out;
1593
1594         pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1595
1596         /* Check PMC Register : 3.0001.2 == 1: read twice */
1597         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1598                         MRVL88X2011_PMA_PMD_STATUS_1);
1599         if (err < 0)
1600                 goto out;
1601
1602         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1603                         MRVL88X2011_PMA_PMD_STATUS_1);
1604         if (err < 0)
1605                 goto out;
1606
1607         pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1608
1609         /* Check XGXS Register : 4.0018.[0-3,12] */
1610         err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1611                         MRVL88X2011_10G_XGXS_LANE_STAT);
1612         if (err < 0)
1613                 goto out;
1614
1615         if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1616                     PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1617                     PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1618                     0x800))
1619                 link_up = (pma_status && pcs_status) ? 1 : 0;
1620
1621         np->link_config.active_speed = SPEED_10000;
1622         np->link_config.active_duplex = DUPLEX_FULL;
1623         err = 0;
1624 out:
1625         mrvl88x2011_act_led(np, (link_up ?
1626                                  MRVL88X2011_LED_CTL_PCS_ACT :
1627                                  MRVL88X2011_LED_CTL_OFF));
1628
1629         *link_up_p = link_up;
1630         return err;
1631 }
1632
1633 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1634 {
1635         int err, link_up;
1636         link_up = 0;
1637
1638         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1639                         BCM8704_PMD_RCV_SIGDET);
1640         if (err < 0)
1641                 goto out;
1642         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1643                 err = 0;
1644                 goto out;
1645         }
1646
1647         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1648                         BCM8704_PCS_10G_R_STATUS);
1649         if (err < 0)
1650                 goto out;
1651
1652         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1653                 err = 0;
1654                 goto out;
1655         }
1656
1657         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1658                         BCM8704_PHYXS_XGXS_LANE_STAT);
1659         if (err < 0)
1660                 goto out;
1661         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1662                     PHYXS_XGXS_LANE_STAT_MAGIC |
1663                     PHYXS_XGXS_LANE_STAT_PATTEST |
1664                     PHYXS_XGXS_LANE_STAT_LANE3 |
1665                     PHYXS_XGXS_LANE_STAT_LANE2 |
1666                     PHYXS_XGXS_LANE_STAT_LANE1 |
1667                     PHYXS_XGXS_LANE_STAT_LANE0)) {
1668                 err = 0;
1669                 np->link_config.active_speed = SPEED_INVALID;
1670                 np->link_config.active_duplex = DUPLEX_INVALID;
1671                 goto out;
1672         }
1673
1674         link_up = 1;
1675         np->link_config.active_speed = SPEED_10000;
1676         np->link_config.active_duplex = DUPLEX_FULL;
1677         err = 0;
1678
1679 out:
1680         *link_up_p = link_up;
1681         if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
1682                 err = 0;
1683         return err;
1684 }
1685
1686 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1687 {
1688         int err, link_up;
1689
1690         link_up = 0;
1691
1692         err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1693                         BCM8704_PMD_RCV_SIGDET);
1694         if (err < 0)
1695                 goto out;
1696         if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1697                 err = 0;
1698                 goto out;
1699         }
1700
1701         err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1702                         BCM8704_PCS_10G_R_STATUS);
1703         if (err < 0)
1704                 goto out;
1705         if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1706                 err = 0;
1707                 goto out;
1708         }
1709
1710         err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1711                         BCM8704_PHYXS_XGXS_LANE_STAT);
1712         if (err < 0)
1713                 goto out;
1714
1715         if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1716                     PHYXS_XGXS_LANE_STAT_MAGIC |
1717                     PHYXS_XGXS_LANE_STAT_LANE3 |
1718                     PHYXS_XGXS_LANE_STAT_LANE2 |
1719                     PHYXS_XGXS_LANE_STAT_LANE1 |
1720                     PHYXS_XGXS_LANE_STAT_LANE0)) {
1721                 err = 0;
1722                 goto out;
1723         }
1724
1725         link_up = 1;
1726         np->link_config.active_speed = SPEED_10000;
1727         np->link_config.active_duplex = DUPLEX_FULL;
1728         err = 0;
1729
1730 out:
1731         *link_up_p = link_up;
1732         return err;
1733 }
1734
1735 static int link_status_10g(struct niu *np, int *link_up_p)
1736 {
1737         unsigned long flags;
1738         int err = -EINVAL;
1739
1740         spin_lock_irqsave(&np->lock, flags);
1741
1742         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1743                 int phy_id;
1744
1745                 phy_id = phy_decode(np->parent->port_phy, np->port);
1746                 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1747
1748                 /* handle different phy types */
1749                 switch (phy_id & NIU_PHY_ID_MASK) {
1750                 case NIU_PHY_ID_MRVL88X2011:
1751                         err = link_status_10g_mrvl(np, link_up_p);
1752                         break;
1753
1754                 default: /* bcom 8704 */
1755                         err = link_status_10g_bcom(np, link_up_p);
1756                         break;
1757                 }
1758         }
1759
1760         spin_unlock_irqrestore(&np->lock, flags);
1761
1762         return err;
1763 }
1764
1765 static int niu_10g_phy_present(struct niu *np)
1766 {
1767         u64 sig, mask, val;
1768
1769         sig = nr64(ESR_INT_SIGNALS);
1770         switch (np->port) {
1771         case 0:
1772                 mask = ESR_INT_SIGNALS_P0_BITS;
1773                 val = (ESR_INT_SRDY0_P0 |
1774                        ESR_INT_DET0_P0 |
1775                        ESR_INT_XSRDY_P0 |
1776                        ESR_INT_XDP_P0_CH3 |
1777                        ESR_INT_XDP_P0_CH2 |
1778                        ESR_INT_XDP_P0_CH1 |
1779                        ESR_INT_XDP_P0_CH0);
1780                 break;
1781
1782         case 1:
1783                 mask = ESR_INT_SIGNALS_P1_BITS;
1784                 val = (ESR_INT_SRDY0_P1 |
1785                        ESR_INT_DET0_P1 |
1786                        ESR_INT_XSRDY_P1 |
1787                        ESR_INT_XDP_P1_CH3 |
1788                        ESR_INT_XDP_P1_CH2 |
1789                        ESR_INT_XDP_P1_CH1 |
1790                        ESR_INT_XDP_P1_CH0);
1791                 break;
1792
1793         default:
1794                 return 0;
1795         }
1796
1797         if ((sig & mask) != val)
1798                 return 0;
1799         return 1;
1800 }
1801
1802 static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
1803 {
1804         unsigned long flags;
1805         int err = 0;
1806         int phy_present;
1807         int phy_present_prev;
1808
1809         spin_lock_irqsave(&np->lock, flags);
1810
1811         if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1812                 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
1813                         1 : 0;
1814                 phy_present = niu_10g_phy_present(np);
1815                 if (phy_present != phy_present_prev) {
1816                         /* state change */
1817                         if (phy_present) {
1818                                 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
1819                                 if (np->phy_ops->xcvr_init)
1820                                         err = np->phy_ops->xcvr_init(np);
1821                                 if (err) {
1822                                         /* debounce */
1823                                         np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
1824                                 }
1825                         } else {
1826                                 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
1827                                 *link_up_p = 0;
1828                                 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
1829                                         np->dev->name);
1830                         }
1831                 }
1832                 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
1833                         err = link_status_10g_bcm8706(np, link_up_p);
1834         }
1835
1836         spin_unlock_irqrestore(&np->lock, flags);
1837
1838         return err;
1839 }
1840
1841 static int link_status_1g(struct niu *np, int *link_up_p)
1842 {
1843         struct niu_link_config *lp = &np->link_config;
1844         u16 current_speed, bmsr;
1845         unsigned long flags;
1846         u8 current_duplex;
1847         int err, link_up;
1848
1849         link_up = 0;
1850         current_speed = SPEED_INVALID;
1851         current_duplex = DUPLEX_INVALID;
1852
1853         spin_lock_irqsave(&np->lock, flags);
1854
1855         err = -EINVAL;
1856         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1857                 goto out;
1858
1859         err = mii_read(np, np->phy_addr, MII_BMSR);
1860         if (err < 0)
1861                 goto out;
1862
1863         bmsr = err;
1864         if (bmsr & BMSR_LSTATUS) {
1865                 u16 adv, lpa, common, estat;
1866
1867                 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1868                 if (err < 0)
1869                         goto out;
1870                 adv = err;
1871
1872                 err = mii_read(np, np->phy_addr, MII_LPA);
1873                 if (err < 0)
1874                         goto out;
1875                 lpa = err;
1876
1877                 common = adv & lpa;
1878
1879                 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1880                 if (err < 0)
1881                         goto out;
1882                 estat = err;
1883
1884                 link_up = 1;
1885                 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1886                         current_speed = SPEED_1000;
1887                         if (estat & ESTATUS_1000_TFULL)
1888                                 current_duplex = DUPLEX_FULL;
1889                         else
1890                                 current_duplex = DUPLEX_HALF;
1891                 } else {
1892                         if (common & ADVERTISE_100BASE4) {
1893                                 current_speed = SPEED_100;
1894                                 current_duplex = DUPLEX_HALF;
1895                         } else if (common & ADVERTISE_100FULL) {
1896                                 current_speed = SPEED_100;
1897                                 current_duplex = DUPLEX_FULL;
1898                         } else if (common & ADVERTISE_100HALF) {
1899                                 current_speed = SPEED_100;
1900                                 current_duplex = DUPLEX_HALF;
1901                         } else if (common & ADVERTISE_10FULL) {
1902                                 current_speed = SPEED_10;
1903                                 current_duplex = DUPLEX_FULL;
1904                         } else if (common & ADVERTISE_10HALF) {
1905                                 current_speed = SPEED_10;
1906                                 current_duplex = DUPLEX_HALF;
1907                         } else
1908                                 link_up = 0;
1909                 }
1910         }
1911         lp->active_speed = current_speed;
1912         lp->active_duplex = current_duplex;
1913         err = 0;
1914
1915 out:
1916         spin_unlock_irqrestore(&np->lock, flags);
1917
1918         *link_up_p = link_up;
1919         return err;
1920 }
1921
1922 static int niu_link_status(struct niu *np, int *link_up_p)
1923 {
1924         const struct niu_phy_ops *ops = np->phy_ops;
1925         int err;
1926
1927         err = 0;
1928         if (ops->link_status)
1929                 err = ops->link_status(np, link_up_p);
1930
1931         return err;
1932 }
1933
1934 static void niu_timer(unsigned long __opaque)
1935 {
1936         struct niu *np = (struct niu *) __opaque;
1937         unsigned long off;
1938         int err, link_up;
1939
1940         err = niu_link_status(np, &link_up);
1941         if (!err)
1942                 niu_link_status_common(np, link_up);
1943
1944         if (netif_carrier_ok(np->dev))
1945                 off = 5 * HZ;
1946         else
1947                 off = 1 * HZ;
1948         np->timer.expires = jiffies + off;
1949
1950         add_timer(&np->timer);
1951 }
1952
1953 static const struct niu_phy_ops phy_ops_10g_serdes = {
1954         .serdes_init            = serdes_init_10g_serdes,
1955         .link_status            = link_status_10g_serdes,
1956 };
1957
1958 static const struct niu_phy_ops phy_ops_1g_rgmii = {
1959         .xcvr_init              = xcvr_init_1g_rgmii,
1960         .link_status            = link_status_1g_rgmii,
1961 };
1962
1963 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1964         .serdes_init            = serdes_init_niu,
1965         .xcvr_init              = xcvr_init_10g,
1966         .link_status            = link_status_10g,
1967 };
1968
1969 static const struct niu_phy_ops phy_ops_10g_fiber = {
1970         .serdes_init            = serdes_init_10g,
1971         .xcvr_init              = xcvr_init_10g,
1972         .link_status            = link_status_10g,
1973 };
1974
1975 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
1976         .serdes_init            = serdes_init_10g,
1977         .xcvr_init              = xcvr_init_10g_bcm8706,
1978         .link_status            = link_status_10g_hotplug,
1979 };
1980
1981 static const struct niu_phy_ops phy_ops_10g_copper = {
1982         .serdes_init            = serdes_init_10g,
1983         .link_status            = link_status_10g, /* XXX */
1984 };
1985
1986 static const struct niu_phy_ops phy_ops_1g_fiber = {
1987         .serdes_init            = serdes_init_1g,
1988         .xcvr_init              = xcvr_init_1g,
1989         .link_status            = link_status_1g,
1990 };
1991
1992 static const struct niu_phy_ops phy_ops_1g_copper = {
1993         .xcvr_init              = xcvr_init_1g,
1994         .link_status            = link_status_1g,
1995 };
1996
1997 struct niu_phy_template {
1998         const struct niu_phy_ops        *ops;
1999         u32                             phy_addr_base;
2000 };
2001
2002 static const struct niu_phy_template phy_template_niu = {
2003         .ops            = &phy_ops_10g_fiber_niu,
2004         .phy_addr_base  = 16,
2005 };
2006
2007 static const struct niu_phy_template phy_template_10g_fiber = {
2008         .ops            = &phy_ops_10g_fiber,
2009         .phy_addr_base  = 8,
2010 };
2011
2012 static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2013         .ops            = &phy_ops_10g_fiber_hotplug,
2014         .phy_addr_base  = 8,
2015 };
2016
2017 static const struct niu_phy_template phy_template_10g_copper = {
2018         .ops            = &phy_ops_10g_copper,
2019         .phy_addr_base  = 10,
2020 };
2021
2022 static const struct niu_phy_template phy_template_1g_fiber = {
2023         .ops            = &phy_ops_1g_fiber,
2024         .phy_addr_base  = 0,
2025 };
2026
2027 static const struct niu_phy_template phy_template_1g_copper = {
2028         .ops            = &phy_ops_1g_copper,
2029         .phy_addr_base  = 0,
2030 };
2031
2032 static const struct niu_phy_template phy_template_1g_rgmii = {
2033         .ops            = &phy_ops_1g_rgmii,
2034         .phy_addr_base  = 0,
2035 };
2036
2037 static const struct niu_phy_template phy_template_10g_serdes = {
2038         .ops            = &phy_ops_10g_serdes,
2039         .phy_addr_base  = 0,
2040 };
2041
2042 static int niu_atca_port_num[4] = {
2043         0, 0,  11, 10
2044 };
2045
2046 static int serdes_init_10g_serdes(struct niu *np)
2047 {
2048         struct niu_link_config *lp = &np->link_config;
2049         unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2050         u64 ctrl_val, test_cfg_val, sig, mask, val;
2051         int err;
2052         u64 reset_val;
2053
2054         switch (np->port) {
2055         case 0:
2056                 reset_val =  ENET_SERDES_RESET_0;
2057                 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2058                 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2059                 pll_cfg = ENET_SERDES_0_PLL_CFG;
2060                 break;
2061         case 1:
2062                 reset_val =  ENET_SERDES_RESET_1;
2063                 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2064                 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2065                 pll_cfg = ENET_SERDES_1_PLL_CFG;
2066                 break;
2067
2068         default:
2069                 return -EINVAL;
2070         }
2071         ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2072                     ENET_SERDES_CTRL_SDET_1 |
2073                     ENET_SERDES_CTRL_SDET_2 |
2074                     ENET_SERDES_CTRL_SDET_3 |
2075                     (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2076                     (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2077                     (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2078                     (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2079                     (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2080                     (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2081                     (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2082                     (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2083         test_cfg_val = 0;
2084
2085         if (lp->loopback_mode == LOOPBACK_PHY) {
2086                 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2087                                   ENET_SERDES_TEST_MD_0_SHIFT) |
2088                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2089                                   ENET_SERDES_TEST_MD_1_SHIFT) |
2090                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2091                                   ENET_SERDES_TEST_MD_2_SHIFT) |
2092                                  (ENET_TEST_MD_PAD_LOOPBACK <<
2093                                   ENET_SERDES_TEST_MD_3_SHIFT));
2094         }
2095
2096         esr_reset(np);
2097         nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2098         nw64(ctrl_reg, ctrl_val);
2099         nw64(test_cfg_reg, test_cfg_val);
2100
2101         /* Initialize all 4 lanes of the SERDES.  */
2102         for (i = 0; i < 4; i++) {
2103                 u32 rxtx_ctrl, glue0;
2104
2105                 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2106                 if (err)
2107                         return err;
2108                 err = esr_read_glue0(np, i, &glue0);
2109                 if (err)
2110                         return err;
2111
2112                 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2113                 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2114                               (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2115
2116                 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2117                            ESR_GLUE_CTRL0_THCNT |
2118                            ESR_GLUE_CTRL0_BLTIME);
2119                 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2120                           (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2121                           (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2122                           (BLTIME_300_CYCLES <<
2123                            ESR_GLUE_CTRL0_BLTIME_SHIFT));
2124
2125                 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2126                 if (err)
2127                         return err;
2128                 err = esr_write_glue0(np, i, glue0);
2129                 if (err)
2130                         return err;
2131         }
2132
2133
2134         sig = nr64(ESR_INT_SIGNALS);
2135         switch (np->port) {
2136         case 0:
2137                 mask = ESR_INT_SIGNALS_P0_BITS;
2138                 val = (ESR_INT_SRDY0_P0 |
2139                        ESR_INT_DET0_P0 |
2140                        ESR_INT_XSRDY_P0 |
2141                        ESR_INT_XDP_P0_CH3 |
2142                        ESR_INT_XDP_P0_CH2 |
2143                        ESR_INT_XDP_P0_CH1 |
2144                        ESR_INT_XDP_P0_CH0);
2145                 break;
2146
2147         case 1:
2148                 mask = ESR_INT_SIGNALS_P1_BITS;
2149                 val = (ESR_INT_SRDY0_P1 |
2150                        ESR_INT_DET0_P1 |
2151                        ESR_INT_XSRDY_P1 |
2152                        ESR_INT_XDP_P1_CH3 |
2153                        ESR_INT_XDP_P1_CH2 |
2154                        ESR_INT_XDP_P1_CH1 |
2155                        ESR_INT_XDP_P1_CH0);
2156                 break;
2157
2158         default:
2159                 return -EINVAL;
2160         }
2161
2162         if ((sig & mask) != val) {
2163                 int err;
2164                 err = serdes_init_1g_serdes(np);
2165                 if (!err) {
2166                         np->flags &= ~NIU_FLAGS_10G;
2167                         np->mac_xcvr = MAC_XCVR_PCS;
2168                 }  else {
2169                         dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2170                          np->port);
2171                         return -ENODEV;
2172                 }
2173         }
2174
2175         return 0;
2176 }
2177
2178 static int niu_determine_phy_disposition(struct niu *np)
2179 {
2180         struct niu_parent *parent = np->parent;
2181         u8 plat_type = parent->plat_type;
2182         const struct niu_phy_template *tp;
2183         u32 phy_addr_off = 0;
2184
2185         if (plat_type == PLAT_TYPE_NIU) {
2186                 tp = &phy_template_niu;
2187                 phy_addr_off += np->port;
2188         } else {
2189                 switch (np->flags &
2190                         (NIU_FLAGS_10G |
2191                          NIU_FLAGS_FIBER |
2192                          NIU_FLAGS_XCVR_SERDES)) {
2193                 case 0:
2194                         /* 1G copper */
2195                         tp = &phy_template_1g_copper;
2196                         if (plat_type == PLAT_TYPE_VF_P0)
2197                                 phy_addr_off = 10;
2198                         else if (plat_type == PLAT_TYPE_VF_P1)
2199                                 phy_addr_off = 26;
2200
2201                         phy_addr_off += (np->port ^ 0x3);
2202                         break;
2203
2204                 case NIU_FLAGS_10G:
2205                         /* 10G copper */
2206                         tp = &phy_template_1g_copper;
2207                         break;
2208
2209                 case NIU_FLAGS_FIBER:
2210                         /* 1G fiber */
2211                         tp = &phy_template_1g_fiber;
2212                         break;
2213
2214                 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2215                         /* 10G fiber */
2216                         tp = &phy_template_10g_fiber;
2217                         if (plat_type == PLAT_TYPE_VF_P0 ||
2218                             plat_type == PLAT_TYPE_VF_P1)
2219                                 phy_addr_off = 8;
2220                         phy_addr_off += np->port;
2221                         if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2222                                 tp = &phy_template_10g_fiber_hotplug;
2223                                 if (np->port == 0)
2224                                         phy_addr_off = 8;
2225                                 if (np->port == 1)
2226                                         phy_addr_off = 12;
2227                         }
2228                         break;
2229
2230                 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2231                 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2232                 case NIU_FLAGS_XCVR_SERDES:
2233                         switch(np->port) {
2234                         case 0:
2235                         case 1:
2236                                 tp = &phy_template_10g_serdes;
2237                                 break;
2238                         case 2:
2239                         case 3:
2240                                 tp = &phy_template_1g_rgmii;
2241                                 break;
2242                         default:
2243                                 return -EINVAL;
2244                                 break;
2245                         }
2246                         phy_addr_off = niu_atca_port_num[np->port];
2247                         break;
2248
2249                 default:
2250                         return -EINVAL;
2251                 }
2252         }
2253
2254         np->phy_ops = tp->ops;
2255         np->phy_addr = tp->phy_addr_base + phy_addr_off;
2256
2257         return 0;
2258 }
2259
2260 static int niu_init_link(struct niu *np)
2261 {
2262         struct niu_parent *parent = np->parent;
2263         int err, ignore;
2264
2265         if (parent->plat_type == PLAT_TYPE_NIU) {
2266                 err = niu_xcvr_init(np);
2267                 if (err)
2268                         return err;
2269                 msleep(200);
2270         }
2271         err = niu_serdes_init(np);
2272         if (err)
2273                 return err;
2274         msleep(200);
2275         err = niu_xcvr_init(np);
2276         if (!err)
2277                 niu_link_status(np, &ignore);
2278         return 0;
2279 }
2280
2281 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2282 {
2283         u16 reg0 = addr[4] << 8 | addr[5];
2284         u16 reg1 = addr[2] << 8 | addr[3];
2285         u16 reg2 = addr[0] << 8 | addr[1];
2286
2287         if (np->flags & NIU_FLAGS_XMAC) {
2288                 nw64_mac(XMAC_ADDR0, reg0);
2289                 nw64_mac(XMAC_ADDR1, reg1);
2290                 nw64_mac(XMAC_ADDR2, reg2);
2291         } else {
2292                 nw64_mac(BMAC_ADDR0, reg0);
2293                 nw64_mac(BMAC_ADDR1, reg1);
2294                 nw64_mac(BMAC_ADDR2, reg2);
2295         }
2296 }
2297
2298 static int niu_num_alt_addr(struct niu *np)
2299 {
2300         if (np->flags & NIU_FLAGS_XMAC)
2301                 return XMAC_NUM_ALT_ADDR;
2302         else
2303                 return BMAC_NUM_ALT_ADDR;
2304 }
2305
2306 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2307 {
2308         u16 reg0 = addr[4] << 8 | addr[5];
2309         u16 reg1 = addr[2] << 8 | addr[3];
2310         u16 reg2 = addr[0] << 8 | addr[1];
2311
2312         if (index >= niu_num_alt_addr(np))
2313                 return -EINVAL;
2314
2315         if (np->flags & NIU_FLAGS_XMAC) {
2316                 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2317                 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2318                 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2319         } else {
2320                 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2321                 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2322                 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2323         }
2324
2325         return 0;
2326 }
2327
2328 static int niu_enable_alt_mac(struct niu *np, int index, int on)
2329 {
2330         unsigned long reg;
2331         u64 val, mask;
2332
2333         if (index >= niu_num_alt_addr(np))
2334                 return -EINVAL;
2335
2336         if (np->flags & NIU_FLAGS_XMAC) {
2337                 reg = XMAC_ADDR_CMPEN;
2338                 mask = 1 << index;
2339         } else {
2340                 reg = BMAC_ADDR_CMPEN;
2341                 mask = 1 << (index + 1);
2342         }
2343
2344         val = nr64_mac(reg);
2345         if (on)
2346                 val |= mask;
2347         else
2348                 val &= ~mask;
2349         nw64_mac(reg, val);
2350
2351         return 0;
2352 }
2353
2354 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2355                                    int num, int mac_pref)
2356 {
2357         u64 val = nr64_mac(reg);
2358         val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2359         val |= num;
2360         if (mac_pref)
2361                 val |= HOST_INFO_MPR;
2362         nw64_mac(reg, val);
2363 }
2364
2365 static int __set_rdc_table_num(struct niu *np,
2366                                int xmac_index, int bmac_index,
2367                                int rdc_table_num, int mac_pref)
2368 {
2369         unsigned long reg;
2370
2371         if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2372                 return -EINVAL;
2373         if (np->flags & NIU_FLAGS_XMAC)
2374                 reg = XMAC_HOST_INFO(xmac_index);
2375         else
2376                 reg = BMAC_HOST_INFO(bmac_index);
2377         __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2378         return 0;
2379 }
2380
2381 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2382                                          int mac_pref)
2383 {
2384         return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2385 }
2386
2387 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2388                                            int mac_pref)
2389 {
2390         return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2391 }
2392
2393 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2394                                      int table_num, int mac_pref)
2395 {
2396         if (idx >= niu_num_alt_addr(np))
2397                 return -EINVAL;
2398         return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2399 }
2400
2401 static u64 vlan_entry_set_parity(u64 reg_val)
2402 {
2403         u64 port01_mask;
2404         u64 port23_mask;
2405
2406         port01_mask = 0x00ff;
2407         port23_mask = 0xff00;
2408
2409         if (hweight64(reg_val & port01_mask) & 1)
2410                 reg_val |= ENET_VLAN_TBL_PARITY0;
2411         else
2412                 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2413
2414         if (hweight64(reg_val & port23_mask) & 1)
2415                 reg_val |= ENET_VLAN_TBL_PARITY1;
2416         else
2417                 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2418
2419         return reg_val;
2420 }
2421
2422 static void vlan_tbl_write(struct niu *np, unsigned long index,
2423                            int port, int vpr, int rdc_table)
2424 {
2425         u64 reg_val = nr64(ENET_VLAN_TBL(index));
2426
2427         reg_val &= ~((ENET_VLAN_TBL_VPR |
2428                       ENET_VLAN_TBL_VLANRDCTBLN) <<
2429                      ENET_VLAN_TBL_SHIFT(port));
2430         if (vpr)
2431                 reg_val |= (ENET_VLAN_TBL_VPR <<
2432                             ENET_VLAN_TBL_SHIFT(port));
2433         reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2434
2435         reg_val = vlan_entry_set_parity(reg_val);
2436
2437         nw64(ENET_VLAN_TBL(index), reg_val);
2438 }
2439
2440 static void vlan_tbl_clear(struct niu *np)
2441 {
2442         int i;
2443
2444         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2445                 nw64(ENET_VLAN_TBL(i), 0);
2446 }
2447
2448 static int tcam_wait_bit(struct niu *np, u64 bit)
2449 {
2450         int limit = 1000;
2451
2452         while (--limit > 0) {
2453                 if (nr64(TCAM_CTL) & bit)
2454                         break;
2455                 udelay(1);
2456         }
2457         if (limit < 0)
2458                 return -ENODEV;
2459
2460         return 0;
2461 }
2462
2463 static int tcam_flush(struct niu *np, int index)
2464 {
2465         nw64(TCAM_KEY_0, 0x00);
2466         nw64(TCAM_KEY_MASK_0, 0xff);
2467         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2468
2469         return tcam_wait_bit(np, TCAM_CTL_STAT);
2470 }
2471
2472 #if 0
2473 static int tcam_read(struct niu *np, int index,
2474                      u64 *key, u64 *mask)
2475 {
2476         int err;
2477
2478         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2479         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2480         if (!err) {
2481                 key[0] = nr64(TCAM_KEY_0);
2482                 key[1] = nr64(TCAM_KEY_1);
2483                 key[2] = nr64(TCAM_KEY_2);
2484                 key[3] = nr64(TCAM_KEY_3);
2485                 mask[0] = nr64(TCAM_KEY_MASK_0);
2486                 mask[1] = nr64(TCAM_KEY_MASK_1);
2487                 mask[2] = nr64(TCAM_KEY_MASK_2);
2488                 mask[3] = nr64(TCAM_KEY_MASK_3);
2489         }
2490         return err;
2491 }
2492 #endif
2493
2494 static int tcam_write(struct niu *np, int index,
2495                       u64 *key, u64 *mask)
2496 {
2497         nw64(TCAM_KEY_0, key[0]);
2498         nw64(TCAM_KEY_1, key[1]);
2499         nw64(TCAM_KEY_2, key[2]);
2500         nw64(TCAM_KEY_3, key[3]);
2501         nw64(TCAM_KEY_MASK_0, mask[0]);
2502         nw64(TCAM_KEY_MASK_1, mask[1]);
2503         nw64(TCAM_KEY_MASK_2, mask[2]);
2504         nw64(TCAM_KEY_MASK_3, mask[3]);
2505         nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2506
2507         return tcam_wait_bit(np, TCAM_CTL_STAT);
2508 }
2509
2510 #if 0
2511 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2512 {
2513         int err;
2514
2515         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2516         err = tcam_wait_bit(np, TCAM_CTL_STAT);
2517         if (!err)
2518                 *data = nr64(TCAM_KEY_1);
2519
2520         return err;
2521 }
2522 #endif
2523
2524 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2525 {
2526         nw64(TCAM_KEY_1, assoc_data);
2527         nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2528
2529         return tcam_wait_bit(np, TCAM_CTL_STAT);
2530 }
2531
2532 static void tcam_enable(struct niu *np, int on)
2533 {
2534         u64 val = nr64(FFLP_CFG_1);
2535
2536         if (on)
2537                 val &= ~FFLP_CFG_1_TCAM_DIS;
2538         else
2539                 val |= FFLP_CFG_1_TCAM_DIS;
2540         nw64(FFLP_CFG_1, val);
2541 }
2542
2543 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2544 {
2545         u64 val = nr64(FFLP_CFG_1);
2546
2547         val &= ~(FFLP_CFG_1_FFLPINITDONE |
2548                  FFLP_CFG_1_CAMLAT |
2549                  FFLP_CFG_1_CAMRATIO);
2550         val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2551         val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2552         nw64(FFLP_CFG_1, val);
2553
2554         val = nr64(FFLP_CFG_1);
2555         val |= FFLP_CFG_1_FFLPINITDONE;
2556         nw64(FFLP_CFG_1, val);
2557 }
2558
2559 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2560                                       int on)
2561 {
2562         unsigned long reg;
2563         u64 val;
2564
2565         if (class < CLASS_CODE_ETHERTYPE1 ||
2566             class > CLASS_CODE_ETHERTYPE2)
2567                 return -EINVAL;
2568
2569         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2570         val = nr64(reg);
2571         if (on)
2572                 val |= L2_CLS_VLD;
2573         else
2574                 val &= ~L2_CLS_VLD;
2575         nw64(reg, val);
2576
2577         return 0;
2578 }
2579
2580 #if 0
2581 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2582                                    u64 ether_type)
2583 {
2584         unsigned long reg;
2585         u64 val;
2586
2587         if (class < CLASS_CODE_ETHERTYPE1 ||
2588             class > CLASS_CODE_ETHERTYPE2 ||
2589             (ether_type & ~(u64)0xffff) != 0)
2590                 return -EINVAL;
2591
2592         reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2593         val = nr64(reg);
2594         val &= ~L2_CLS_ETYPE;
2595         val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2596         nw64(reg, val);
2597
2598         return 0;
2599 }
2600 #endif
2601
2602 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2603                                      int on)
2604 {
2605         unsigned long reg;
2606         u64 val;
2607
2608         if (class < CLASS_CODE_USER_PROG1 ||
2609             class > CLASS_CODE_USER_PROG4)
2610                 return -EINVAL;
2611
2612         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2613         val = nr64(reg);
2614         if (on)
2615                 val |= L3_CLS_VALID;
2616         else
2617                 val &= ~L3_CLS_VALID;
2618         nw64(reg, val);
2619
2620         return 0;
2621 }
2622
2623 #if 0
2624 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2625                                   int ipv6, u64 protocol_id,
2626                                   u64 tos_mask, u64 tos_val)
2627 {
2628         unsigned long reg;
2629         u64 val;
2630
2631         if (class < CLASS_CODE_USER_PROG1 ||
2632             class > CLASS_CODE_USER_PROG4 ||
2633             (protocol_id & ~(u64)0xff) != 0 ||
2634             (tos_mask & ~(u64)0xff) != 0 ||
2635             (tos_val & ~(u64)0xff) != 0)
2636                 return -EINVAL;
2637
2638         reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2639         val = nr64(reg);
2640         val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2641                  L3_CLS_TOSMASK | L3_CLS_TOS);
2642         if (ipv6)
2643                 val |= L3_CLS_IPVER;
2644         val |= (protocol_id << L3_CLS_PID_SHIFT);
2645         val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2646         val |= (tos_val << L3_CLS_TOS_SHIFT);
2647         nw64(reg, val);
2648
2649         return 0;
2650 }
2651 #endif
2652
2653 static int tcam_early_init(struct niu *np)
2654 {
2655         unsigned long i;
2656         int err;
2657
2658         tcam_enable(np, 0);
2659         tcam_set_lat_and_ratio(np,
2660                                DEFAULT_TCAM_LATENCY,
2661                                DEFAULT_TCAM_ACCESS_RATIO);
2662         for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2663                 err = tcam_user_eth_class_enable(np, i, 0);
2664                 if (err)
2665                         return err;
2666         }
2667         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2668                 err = tcam_user_ip_class_enable(np, i, 0);
2669                 if (err)
2670                         return err;
2671         }
2672
2673         return 0;
2674 }
2675
2676 static int tcam_flush_all(struct niu *np)
2677 {
2678         unsigned long i;
2679
2680         for (i = 0; i < np->parent->tcam_num_entries; i++) {
2681                 int err = tcam_flush(np, i);
2682                 if (err)
2683                         return err;
2684         }
2685         return 0;
2686 }
2687
2688 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
2689 {
2690         return ((u64)index | (num_entries == 1 ?
2691                               HASH_TBL_ADDR_AUTOINC : 0));
2692 }
2693
2694 #if 0
2695 static int hash_read(struct niu *np, unsigned long partition,
2696                      unsigned long index, unsigned long num_entries,
2697                      u64 *data)
2698 {
2699         u64 val = hash_addr_regval(index, num_entries);
2700         unsigned long i;
2701
2702         if (partition >= FCRAM_NUM_PARTITIONS ||
2703             index + num_entries > FCRAM_SIZE)
2704                 return -EINVAL;
2705
2706         nw64(HASH_TBL_ADDR(partition), val);
2707         for (i = 0; i < num_entries; i++)
2708                 data[i] = nr64(HASH_TBL_DATA(partition));
2709
2710         return 0;
2711 }
2712 #endif
2713
2714 static int hash_write(struct niu *np, unsigned long partition,
2715                       unsigned long index, unsigned long num_entries,
2716                       u64 *data)
2717 {
2718         u64 val = hash_addr_regval(index, num_entries);
2719         unsigned long i;
2720
2721         if (partition >= FCRAM_NUM_PARTITIONS ||
2722             index + (num_entries * 8) > FCRAM_SIZE)
2723                 return -EINVAL;
2724
2725         nw64(HASH_TBL_ADDR(partition), val);
2726         for (i = 0; i < num_entries; i++)
2727                 nw64(HASH_TBL_DATA(partition), data[i]);
2728
2729         return 0;
2730 }
2731
2732 static void fflp_reset(struct niu *np)
2733 {
2734         u64 val;
2735
2736         nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2737         udelay(10);
2738         nw64(FFLP_CFG_1, 0);
2739
2740         val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2741         nw64(FFLP_CFG_1, val);
2742 }
2743
2744 static void fflp_set_timings(struct niu *np)
2745 {
2746         u64 val = nr64(FFLP_CFG_1);
2747
2748         val &= ~FFLP_CFG_1_FFLPINITDONE;
2749         val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
2750         nw64(FFLP_CFG_1, val);
2751
2752         val = nr64(FFLP_CFG_1);
2753         val |= FFLP_CFG_1_FFLPINITDONE;
2754         nw64(FFLP_CFG_1, val);
2755
2756         val = nr64(FCRAM_REF_TMR);
2757         val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
2758         val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
2759         val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
2760         nw64(FCRAM_REF_TMR, val);
2761 }
2762
2763 static int fflp_set_partition(struct niu *np, u64 partition,
2764                               u64 mask, u64 base, int enable)
2765 {
2766         unsigned long reg;
2767         u64 val;
2768
2769         if (partition >= FCRAM_NUM_PARTITIONS ||
2770             (mask & ~(u64)0x1f) != 0 ||
2771             (base & ~(u64)0x1f) != 0)
2772                 return -EINVAL;
2773
2774         reg = FLW_PRT_SEL(partition);
2775
2776         val = nr64(reg);
2777         val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
2778         val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
2779         val |= (base << FLW_PRT_SEL_BASE_SHIFT);
2780         if (enable)
2781                 val |= FLW_PRT_SEL_EXT;
2782         nw64(reg, val);
2783
2784         return 0;
2785 }
2786
2787 static int fflp_disable_all_partitions(struct niu *np)
2788 {
2789         unsigned long i;
2790
2791         for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
2792                 int err = fflp_set_partition(np, 0, 0, 0, 0);
2793                 if (err)
2794                         return err;
2795         }
2796         return 0;
2797 }
2798
2799 static void fflp_llcsnap_enable(struct niu *np, int on)
2800 {
2801         u64 val = nr64(FFLP_CFG_1);
2802
2803         if (on)
2804                 val |= FFLP_CFG_1_LLCSNAP;
2805         else
2806                 val &= ~FFLP_CFG_1_LLCSNAP;
2807         nw64(FFLP_CFG_1, val);
2808 }
2809
2810 static void fflp_errors_enable(struct niu *np, int on)
2811 {
2812         u64 val = nr64(FFLP_CFG_1);
2813
2814         if (on)
2815                 val &= ~FFLP_CFG_1_ERRORDIS;
2816         else
2817                 val |= FFLP_CFG_1_ERRORDIS;
2818         nw64(FFLP_CFG_1, val);
2819 }
2820
2821 static int fflp_hash_clear(struct niu *np)
2822 {
2823         struct fcram_hash_ipv4 ent;
2824         unsigned long i;
2825
2826         /* IPV4 hash entry with valid bit clear, rest is don't care.  */
2827         memset(&ent, 0, sizeof(ent));
2828         ent.header = HASH_HEADER_EXT;
2829
2830         for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
2831                 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
2832                 if (err)
2833                         return err;
2834         }
2835         return 0;
2836 }
2837
2838 static int fflp_early_init(struct niu *np)
2839 {
2840         struct niu_parent *parent;
2841         unsigned long flags;
2842         int err;
2843
2844         niu_lock_parent(np, flags);
2845
2846         parent = np->parent;
2847         err = 0;
2848         if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
2849                 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
2850                        np->port);
2851                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2852                         fflp_reset(np);
2853                         fflp_set_timings(np);
2854                         err = fflp_disable_all_partitions(np);
2855                         if (err) {
2856                                 niudbg(PROBE, "fflp_disable_all_partitions "
2857                                        "failed, err=%d\n", err);
2858                                 goto out;
2859                         }
2860                 }
2861
2862                 err = tcam_early_init(np);
2863                 if (err) {
2864                         niudbg(PROBE, "tcam_early_init failed, err=%d\n",
2865                                err);
2866                         goto out;
2867                 }
2868                 fflp_llcsnap_enable(np, 1);
2869                 fflp_errors_enable(np, 0);
2870                 nw64(H1POLY, 0);
2871                 nw64(H2POLY, 0);
2872
2873                 err = tcam_flush_all(np);
2874                 if (err) {
2875                         niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
2876                                err);
2877                         goto out;
2878                 }
2879                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2880                         err = fflp_hash_clear(np);
2881                         if (err) {
2882                                 niudbg(PROBE, "fflp_hash_clear failed, "
2883                                        "err=%d\n", err);
2884                                 goto out;
2885                         }
2886                 }
2887
2888                 vlan_tbl_clear(np);
2889
2890                 niudbg(PROBE, "fflp_early_init: Success\n");
2891                 parent->flags |= PARENT_FLGS_CLS_HWINIT;
2892         }
2893 out:
2894         niu_unlock_parent(np, flags);
2895         return err;
2896 }
2897
2898 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
2899 {
2900         if (class_code < CLASS_CODE_USER_PROG1 ||
2901             class_code > CLASS_CODE_SCTP_IPV6)
2902                 return -EINVAL;
2903
2904         nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2905         return 0;
2906 }
2907
2908 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2909 {
2910         if (class_code < CLASS_CODE_USER_PROG1 ||
2911             class_code > CLASS_CODE_SCTP_IPV6)
2912                 return -EINVAL;
2913
2914         nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2915         return 0;
2916 }
2917
2918 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2919                               u32 offset, u32 size)
2920 {
2921         int i = skb_shinfo(skb)->nr_frags;
2922         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2923
2924         frag->page = page;
2925         frag->page_offset = offset;
2926         frag->size = size;
2927
2928         skb->len += size;
2929         skb->data_len += size;
2930         skb->truesize += size;
2931
2932         skb_shinfo(skb)->nr_frags = i + 1;
2933 }
2934
2935 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2936 {
2937         a >>= PAGE_SHIFT;
2938         a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2939
2940         return (a & (MAX_RBR_RING_SIZE - 1));
2941 }
2942
2943 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2944                                     struct page ***link)
2945 {
2946         unsigned int h = niu_hash_rxaddr(rp, addr);
2947         struct page *p, **pp;
2948
2949         addr &= PAGE_MASK;
2950         pp = &rp->rxhash[h];
2951         for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2952                 if (p->index == addr) {
2953                         *link = pp;
2954                         break;
2955                 }
2956         }
2957
2958         return p;
2959 }
2960
2961 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2962 {
2963         unsigned int h = niu_hash_rxaddr(rp, base);
2964
2965         page->index = base;
2966         page->mapping = (struct address_space *) rp->rxhash[h];
2967         rp->rxhash[h] = page;
2968 }
2969
2970 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2971                             gfp_t mask, int start_index)
2972 {
2973         struct page *page;
2974         u64 addr;
2975         int i;
2976
2977         page = alloc_page(mask);
2978         if (!page)
2979                 return -ENOMEM;
2980
2981         addr = np->ops->map_page(np->device, page, 0,
2982                                  PAGE_SIZE, DMA_FROM_DEVICE);
2983
2984         niu_hash_page(rp, page, addr);
2985         if (rp->rbr_blocks_per_page > 1)
2986                 atomic_add(rp->rbr_blocks_per_page - 1,
2987                            &compound_head(page)->_count);
2988
2989         for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2990                 __le32 *rbr = &rp->rbr[start_index + i];
2991
2992                 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2993                 addr += rp->rbr_block_size;
2994         }
2995
2996         return 0;
2997 }
2998
2999 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3000 {
3001         int index = rp->rbr_index;
3002
3003         rp->rbr_pending++;
3004         if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3005                 int err = niu_rbr_add_page(np, rp, mask, index);
3006
3007                 if (unlikely(err)) {
3008                         rp->rbr_pending--;
3009                         return;
3010                 }
3011
3012                 rp->rbr_index += rp->rbr_blocks_per_page;
3013                 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3014                 if (rp->rbr_index == rp->rbr_table_size)
3015                         rp->rbr_index = 0;
3016
3017                 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3018                         nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3019                         rp->rbr_pending = 0;
3020                 }
3021         }
3022 }
3023
3024 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3025 {
3026         unsigned int index = rp->rcr_index;
3027         int num_rcr = 0;
3028
3029         rp->rx_dropped++;
3030         while (1) {
3031                 struct page *page, **link;
3032                 u64 addr, val;
3033                 u32 rcr_size;
3034
3035                 num_rcr++;
3036
3037                 val = le64_to_cpup(&rp->rcr[index]);
3038                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3039                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3040                 page = niu_find_rxpage(rp, addr, &link);
3041
3042                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3043                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3044                 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3045                         *link = (struct page *) page->mapping;
3046                         np->ops->unmap_page(np->device, page->index,
3047                                             PAGE_SIZE, DMA_FROM_DEVICE);
3048                         page->index = 0;
3049                         page->mapping = NULL;
3050                         __free_page(page);
3051                         rp->rbr_refill_pending++;
3052                 }
3053
3054                 index = NEXT_RCR(rp, index);
3055                 if (!(val & RCR_ENTRY_MULTI))
3056                         break;
3057
3058         }
3059         rp->rcr_index = index;
3060
3061         return num_rcr;
3062 }
3063
3064 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3065 {
3066         unsigned int index = rp->rcr_index;
3067         struct sk_buff *skb;
3068         int len, num_rcr;
3069
3070         skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3071         if (unlikely(!skb))
3072                 return niu_rx_pkt_ignore(np, rp);
3073
3074         num_rcr = 0;
3075         while (1) {
3076                 struct page *page, **link;
3077                 u32 rcr_size, append_size;
3078                 u64 addr, val, off;
3079
3080                 num_rcr++;
3081
3082                 val = le64_to_cpup(&rp->rcr[index]);
3083
3084                 len = (val & RCR_ENTRY_L2_LEN) >>
3085                         RCR_ENTRY_L2_LEN_SHIFT;
3086                 len -= ETH_FCS_LEN;
3087
3088                 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3089                         RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3090                 page = niu_find_rxpage(rp, addr, &link);
3091
3092                 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3093                                          RCR_ENTRY_PKTBUFSZ_SHIFT];
3094
3095                 off = addr & ~PAGE_MASK;
3096                 append_size = rcr_size;
3097                 if (num_rcr == 1) {
3098                         int ptype;
3099
3100                         off += 2;
3101                         append_size -= 2;
3102
3103                         ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3104                         if ((ptype == RCR_PKT_TYPE_TCP ||
3105                              ptype == RCR_PKT_TYPE_UDP) &&
3106                             !(val & (RCR_ENTRY_NOPORT |
3107                                      RCR_ENTRY_ERROR)))
3108                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3109                         else
3110                                 skb->ip_summed = CHECKSUM_NONE;
3111                 }
3112                 if (!(val & RCR_ENTRY_MULTI))
3113                         append_size = len - skb->len;
3114
3115                 niu_rx_skb_append(skb, page, off, append_size);
3116                 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3117                         *link = (struct page *) page->mapping;
3118                         np->ops->unmap_page(np->device, page->index,
3119                                             PAGE_SIZE, DMA_FROM_DEVICE);
3120                         page->index = 0;
3121                         page->mapping = NULL;
3122                         rp->rbr_refill_pending++;
3123                 } else
3124                         get_page(page);
3125
3126                 index = NEXT_RCR(rp, index);
3127                 if (!(val & RCR_ENTRY_MULTI))
3128                         break;
3129
3130         }
3131         rp->rcr_index = index;
3132
3133         skb_reserve(skb, NET_IP_ALIGN);
3134         __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3135
3136         rp->rx_packets++;
3137         rp->rx_bytes += skb->len;
3138
3139         skb->protocol = eth_type_trans(skb, np->dev);
3140         netif_receive_skb(skb);
3141
3142         np->dev->last_rx = jiffies;
3143
3144         return num_rcr;
3145 }
3146
3147 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3148 {
3149         int blocks_per_page = rp->rbr_blocks_per_page;
3150         int err, index = rp->rbr_index;
3151
3152         err = 0;
3153         while (index < (rp->rbr_table_size - blocks_per_page)) {
3154                 err = niu_rbr_add_page(np, rp, mask, index);
3155                 if (err)
3156                         break;
3157
3158                 index += blocks_per_page;
3159         }
3160
3161         rp->rbr_index = index;
3162         return err;
3163 }
3164
3165 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3166 {
3167         int i;
3168
3169         for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3170                 struct page *page;
3171
3172                 page = rp->rxhash[i];
3173                 while (page) {
3174                         struct page *next = (struct page *) page->mapping;
3175                         u64 base = page->index;
3176
3177                         np->ops->unmap_page(np->device, base, PAGE_SIZE,
3178                                             DMA_FROM_DEVICE);
3179                         page->index = 0;
3180                         page->mapping = NULL;
3181
3182                         __free_page(page);
3183
3184                         page = next;
3185                 }
3186         }
3187
3188         for (i = 0; i < rp->rbr_table_size; i++)
3189                 rp->rbr[i] = cpu_to_le32(0);
3190         rp->rbr_index = 0;
3191 }
3192
3193 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3194 {
3195         struct tx_buff_info *tb = &rp->tx_buffs[idx];
3196         struct sk_buff *skb = tb->skb;
3197         struct tx_pkt_hdr *tp;
3198         u64 tx_flags;
3199         int i, len;
3200
3201         tp = (struct tx_pkt_hdr *) skb->data;
3202         tx_flags = le64_to_cpup(&tp->flags);
3203
3204         rp->tx_packets++;
3205         rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3206                          ((tx_flags & TXHDR_PAD) / 2));
3207
3208         len = skb_headlen(skb);
3209         np->ops->unmap_single(np->device, tb->mapping,
3210                               len, DMA_TO_DEVICE);
3211
3212         if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3213                 rp->mark_pending--;
3214
3215         tb->skb = NULL;
3216         do {
3217                 idx = NEXT_TX(rp, idx);
3218                 len -= MAX_TX_DESC_LEN;
3219         } while (len > 0);
3220
3221         for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3222                 tb = &rp->tx_buffs[idx];
3223                 BUG_ON(tb->skb != NULL);
3224                 np->ops->unmap_page(np->device, tb->mapping,
3225                                     skb_shinfo(skb)->frags[i].size,
3226                                     DMA_TO_DEVICE);
3227                 idx = NEXT_TX(rp, idx);
3228         }
3229
3230         dev_kfree_skb(skb);
3231
3232         return idx;
3233 }
3234
3235 #define NIU_TX_WAKEUP_THRESH(rp)                ((rp)->pending / 4)
3236
3237 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3238 {
3239         u16 pkt_cnt, tmp;
3240         int cons;
3241         u64 cs;
3242
3243         cs = rp->tx_cs;
3244         if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3245                 goto out;
3246
3247         tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3248         pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3249                 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3250
3251         rp->last_pkt_cnt = tmp;
3252
3253         cons = rp->cons;
3254
3255         niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3256                np->dev->name, pkt_cnt, cons);
3257
3258         while (pkt_cnt--)
3259                 cons = release_tx_packet(np, rp, cons);
3260
3261         rp->cons = cons;
3262         smp_mb();
3263
3264 out:
3265         if (unlikely(netif_queue_stopped(np->dev) &&
3266                      (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
3267                 netif_tx_lock(np->dev);
3268                 if (netif_queue_stopped(np->dev) &&
3269                     (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
3270                         netif_wake_queue(np->dev);
3271                 netif_tx_unlock(np->dev);
3272         }
3273 }
3274
3275 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3276 {
3277         int qlen, rcr_done = 0, work_done = 0;
3278         struct rxdma_mailbox *mbox = rp->mbox;
3279         u64 stat;
3280
3281 #if 1
3282         stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3283         qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3284 #else
3285         stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3286         qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3287 #endif
3288         mbox->rx_dma_ctl_stat = 0;
3289         mbox->rcrstat_a = 0;
3290
3291         niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3292                np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3293
3294         rcr_done = work_done = 0;
3295         qlen = min(qlen, budget);
3296         while (work_done < qlen) {
3297                 rcr_done += niu_process_rx_pkt(np, rp);
3298                 work_done++;
3299         }
3300
3301         if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3302                 unsigned int i;
3303
3304                 for (i = 0; i < rp->rbr_refill_pending; i++)
3305                         niu_rbr_refill(np, rp, GFP_ATOMIC);
3306                 rp->rbr_refill_pending = 0;
3307         }
3308
3309         stat = (RX_DMA_CTL_STAT_MEX |
3310                 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3311                 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3312
3313         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3314
3315         return work_done;
3316 }
3317
3318 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3319 {
3320         u64 v0 = lp->v0;
3321         u32 tx_vec = (v0 >> 32);
3322         u32 rx_vec = (v0 & 0xffffffff);
3323         int i, work_done = 0;
3324
3325         niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3326                np->dev->name, (unsigned long long) v0);
3327
3328         for (i = 0; i < np->num_tx_rings; i++) {
3329                 struct tx_ring_info *rp = &np->tx_rings[i];
3330                 if (tx_vec & (1 << rp->tx_channel))
3331                         niu_tx_work(np, rp);
3332                 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3333         }
3334
3335         for (i = 0; i < np->num_rx_rings; i++) {
3336                 struct rx_ring_info *rp = &np->rx_rings[i];
3337
3338                 if (rx_vec & (1 << rp->rx_channel)) {
3339                         int this_work_done;
3340
3341                         this_work_done = niu_rx_work(np, rp,
3342                                                      budget);
3343
3344                         budget -= this_work_done;
3345                         work_done += this_work_done;
3346                 }
3347                 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3348         }
3349
3350         return work_done;
3351 }
3352
3353 static int niu_poll(struct napi_struct *napi, int budget)
3354 {
3355         struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3356         struct niu *np = lp->np;
3357         int work_done;
3358
3359         work_done = niu_poll_core(np, lp, budget);
3360
3361         if (work_done < budget) {
3362                 netif_rx_complete(np->dev, napi);
3363                 niu_ldg_rearm(np, lp, 1);
3364         }
3365         return work_done;
3366 }
3367
3368 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3369                                   u64 stat)
3370 {
3371         dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3372                 np->dev->name, rp->rx_channel);
3373
3374         if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3375                 printk("RBR_TMOUT ");
3376         if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3377                 printk("RSP_CNT ");
3378         if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3379                 printk("BYTE_EN_BUS ");
3380         if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3381                 printk("RSP_DAT ");
3382         if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3383                 printk("RCR_ACK ");
3384         if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3385                 printk("RCR_SHA_PAR ");
3386         if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3387                 printk("RBR_PRE_PAR ");
3388         if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3389                 printk("CONFIG ");
3390         if (stat & RX_DMA_CTL_STAT_RCRINCON)
3391                 printk("RCRINCON ");
3392         if (stat & RX_DMA_CTL_STAT_RCRFULL)
3393                 printk("RCRFULL ");
3394         if (stat & RX_DMA_CTL_STAT_RBRFULL)
3395                 printk("RBRFULL ");
3396         if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3397                 printk("RBRLOGPAGE ");
3398         if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3399                 printk("CFIGLOGPAGE ");
3400         if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3401                 printk("DC_FIDO ");
3402
3403         printk(")\n");
3404 }
3405
3406 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3407 {
3408         u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3409         int err = 0;
3410
3411
3412         if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3413                     RX_DMA_CTL_STAT_PORT_FATAL))
3414                 err = -EINVAL;
3415
3416         if (err) {
3417                 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3418                         np->dev->name, rp->rx_channel,
3419                         (unsigned long long) stat);
3420
3421                 niu_log_rxchan_errors(np, rp, stat);
3422         }
3423
3424         nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3425              stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3426
3427         return err;
3428 }
3429
3430 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3431                                   u64 cs)
3432 {
3433         dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3434                 np->dev->name, rp->tx_channel);
3435
3436         if (cs & TX_CS_MBOX_ERR)
3437                 printk("MBOX ");
3438         if (cs & TX_CS_PKT_SIZE_ERR)
3439                 printk("PKT_SIZE ");
3440         if (cs & TX_CS_TX_RING_OFLOW)
3441                 printk("TX_RING_OFLOW ");
3442         if (cs & TX_CS_PREF_BUF_PAR_ERR)
3443                 printk("PREF_BUF_PAR ");
3444         if (cs & TX_CS_NACK_PREF)
3445                 printk("NACK_PREF ");
3446         if (cs & TX_CS_NACK_PKT_RD)
3447                 printk("NACK_PKT_RD ");
3448         if (cs & TX_CS_CONF_PART_ERR)
3449                 printk("CONF_PART ");
3450         if (cs & TX_CS_PKT_PRT_ERR)
3451                 printk("PKT_PTR ");
3452
3453         printk(")\n");
3454 }
3455
3456 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3457 {
3458         u64 cs, logh, logl;
3459
3460         cs = nr64(TX_CS(rp->tx_channel));
3461         logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3462         logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3463
3464         dev_err(np->device, PFX "%s: TX channel %u error, "
3465                 "cs[%llx] logh[%llx] logl[%llx]\n",
3466                 np->dev->name, rp->tx_channel,
3467                 (unsigned long long) cs,
3468                 (unsigned long long) logh,
3469                 (unsigned long long) logl);
3470
3471         niu_log_txchan_errors(np, rp, cs);
3472
3473         return -ENODEV;
3474 }
3475
3476 static int niu_mif_interrupt(struct niu *np)
3477 {
3478         u64 mif_status = nr64(MIF_STATUS);
3479         int phy_mdint = 0;
3480
3481         if (np->flags & NIU_FLAGS_XMAC) {
3482                 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3483
3484                 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3485                         phy_mdint = 1;
3486         }
3487
3488         dev_err(np->device, PFX "%s: MIF interrupt, "
3489                 "stat[%llx] phy_mdint(%d)\n",
3490                 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3491
3492         return -ENODEV;
3493 }
3494
3495 static void niu_xmac_interrupt(struct niu *np)
3496 {
3497         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3498         u64 val;
3499
3500         val = nr64_mac(XTXMAC_STATUS);
3501         if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3502                 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3503         if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3504                 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3505         if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3506                 mp->tx_fifo_errors++;
3507         if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3508                 mp->tx_overflow_errors++;
3509         if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3510                 mp->tx_max_pkt_size_errors++;
3511         if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3512                 mp->tx_underflow_errors++;
3513
3514         val = nr64_mac(XRXMAC_STATUS);
3515         if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3516                 mp->rx_local_faults++;
3517         if (val & XRXMAC_STATUS_RFLT_DET)
3518                 mp->rx_remote_faults++;
3519         if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3520                 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3521         if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3522                 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3523         if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3524                 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3525         if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3526                 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3527         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3528                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3529         if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3530                 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3531         if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3532                 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3533         if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3534                 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3535         if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3536                 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3537         if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3538                 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3539         if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3540                 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3541         if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3542                 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3543         if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3544                 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3545         if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3546                 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3547         if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3548                 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3549         if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3550                 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3551         if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3552                 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3553         if (val & XRXMAC_STATUS_RXUFLOW)
3554                 mp->rx_underflows++;
3555         if (val & XRXMAC_STATUS_RXOFLOW)
3556                 mp->rx_overflows++;
3557
3558         val = nr64_mac(XMAC_FC_STAT);
3559         if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3560                 mp->pause_off_state++;
3561         if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3562                 mp->pause_on_state++;
3563         if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3564                 mp->pause_received++;
3565 }
3566
3567 static void niu_bmac_interrupt(struct niu *np)
3568 {
3569         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3570         u64 val;
3571
3572         val = nr64_mac(BTXMAC_STATUS);
3573         if (val & BTXMAC_STATUS_UNDERRUN)
3574                 mp->tx_underflow_errors++;
3575         if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3576                 mp->tx_max_pkt_size_errors++;
3577         if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3578                 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3579         if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3580                 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3581
3582         val = nr64_mac(BRXMAC_STATUS);
3583         if (val & BRXMAC_STATUS_OVERFLOW)
3584                 mp->rx_overflows++;
3585         if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3586                 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3587         if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3588                 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3589         if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3590                 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3591         if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3592                 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3593
3594         val = nr64_mac(BMAC_CTRL_STATUS);
3595         if (val & BMAC_CTRL_STATUS_NOPAUSE)
3596                 mp->pause_off_state++;
3597         if (val & BMAC_CTRL_STATUS_PAUSE)
3598                 mp->pause_on_state++;
3599         if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
3600                 mp->pause_received++;
3601 }
3602
3603 static int niu_mac_interrupt(struct niu *np)
3604 {
3605         if (np->flags & NIU_FLAGS_XMAC)
3606                 niu_xmac_interrupt(np);
3607         else
3608                 niu_bmac_interrupt(np);
3609
3610         return 0;
3611 }
3612
3613 static void niu_log_device_error(struct niu *np, u64 stat)
3614 {
3615         dev_err(np->device, PFX "%s: Core device errors ( ",
3616                 np->dev->name);
3617
3618         if (stat & SYS_ERR_MASK_META2)
3619                 printk("META2 ");
3620         if (stat & SYS_ERR_MASK_META1)
3621                 printk("META1 ");
3622         if (stat & SYS_ERR_MASK_PEU)
3623                 printk("PEU ");
3624         if (stat & SYS_ERR_MASK_TXC)
3625                 printk("TXC ");
3626         if (stat & SYS_ERR_MASK_RDMC)
3627                 printk("RDMC ");
3628         if (stat & SYS_ERR_MASK_TDMC)
3629                 printk("TDMC ");
3630         if (stat & SYS_ERR_MASK_ZCP)
3631                 printk("ZCP ");
3632         if (stat & SYS_ERR_MASK_FFLP)
3633                 printk("FFLP ");
3634         if (stat & SYS_ERR_MASK_IPP)
3635                 printk("IPP ");
3636         if (stat & SYS_ERR_MASK_MAC)
3637                 printk("MAC ");
3638         if (stat & SYS_ERR_MASK_SMX)
3639                 printk("SMX ");
3640
3641         printk(")\n");
3642 }
3643
3644 static int niu_device_error(struct niu *np)
3645 {
3646         u64 stat = nr64(SYS_ERR_STAT);
3647
3648         dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
3649                 np->dev->name, (unsigned long long) stat);
3650
3651         niu_log_device_error(np, stat);
3652
3653         return -ENODEV;
3654 }
3655
3656 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
3657                               u64 v0, u64 v1, u64 v2)
3658 {
3659
3660         int i, err = 0;
3661
3662         lp->v0 = v0;
3663         lp->v1 = v1;
3664         lp->v2 = v2;
3665
3666         if (v1 & 0x00000000ffffffffULL) {
3667                 u32 rx_vec = (v1 & 0xffffffff);
3668
3669                 for (i = 0; i < np->num_rx_rings; i++) {
3670                         struct rx_ring_info *rp = &np->rx_rings[i];
3671
3672                         if (rx_vec & (1 << rp->rx_channel)) {
3673                                 int r = niu_rx_error(np, rp);
3674                                 if (r) {
3675                                         err = r;
3676                                 } else {
3677                                         if (!v0)
3678                                                 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3679                                                      RX_DMA_CTL_STAT_MEX);
3680                                 }
3681                         }
3682                 }
3683         }
3684         if (v1 & 0x7fffffff00000000ULL) {
3685                 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
3686
3687                 for (i = 0; i < np->num_tx_rings; i++) {
3688                         struct tx_ring_info *rp = &np->tx_rings[i];
3689
3690                         if (tx_vec & (1 << rp->tx_channel)) {
3691                                 int r = niu_tx_error(np, rp);
3692                                 if (r)
3693                                         err = r;
3694                         }
3695                 }
3696         }
3697         if ((v0 | v1) & 0x8000000000000000ULL) {
3698                 int r = niu_mif_interrupt(np);
3699                 if (r)
3700                         err = r;
3701         }
3702         if (v2) {
3703                 if (v2 & 0x01ef) {
3704                         int r = niu_mac_interrupt(np);
3705                         if (r)
3706                                 err = r;
3707                 }
3708                 if (v2 & 0x0210) {
3709                         int r = niu_device_error(np);
3710                         if (r)
3711                                 err = r;
3712                 }
3713         }
3714
3715         if (err)
3716                 niu_enable_interrupts(np, 0);
3717
3718         return err;
3719 }
3720
3721 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
3722                             int ldn)
3723 {
3724         struct rxdma_mailbox *mbox = rp->mbox;
3725         u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3726
3727         stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
3728                       RX_DMA_CTL_STAT_RCRTO);
3729         nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
3730
3731         niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
3732                np->dev->name, (unsigned long long) stat);
3733 }
3734
3735 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
3736                             int ldn)
3737 {
3738         rp->tx_cs = nr64(TX_CS(rp->tx_channel));
3739
3740         niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
3741                np->dev->name, (unsigned long long) rp->tx_cs);
3742 }
3743
3744 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
3745 {
3746         struct niu_parent *parent = np->parent;
3747         u32 rx_vec, tx_vec;
3748         int i;
3749
3750         tx_vec = (v0 >> 32);
3751         rx_vec = (v0 & 0xffffffff);
3752
3753         for (i = 0; i < np->num_rx_rings; i++) {
3754                 struct rx_ring_info *rp = &np->rx_rings[i];
3755                 int ldn = LDN_RXDMA(rp->rx_channel);
3756
3757                 if (parent->ldg_map[ldn] != ldg)
3758                         continue;
3759
3760                 nw64(LD_IM0(ldn), LD_IM0_MASK);
3761                 if (rx_vec & (1 << rp->rx_channel))
3762                         niu_rxchan_intr(np, rp, ldn);
3763         }
3764
3765         for (i = 0; i < np->num_tx_rings; i++) {
3766                 struct tx_ring_info *rp = &np->tx_rings[i];
3767                 int ldn = LDN_TXDMA(rp->tx_channel);
3768
3769                 if (parent->ldg_map[ldn] != ldg)
3770                         continue;
3771
3772                 nw64(LD_IM0(ldn), LD_IM0_MASK);
3773                 if (tx_vec & (1 << rp->tx_channel))
3774                         niu_txchan_intr(np, rp, ldn);
3775         }
3776 }
3777
3778 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
3779                               u64 v0, u64 v1, u64 v2)
3780 {
3781         if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
3782                 lp->v0 = v0;
3783                 lp->v1 = v1;
3784                 lp->v2 = v2;
3785                 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
3786                 __netif_rx_schedule(np->dev, &lp->napi);
3787         }
3788 }
3789
3790 static irqreturn_t niu_interrupt(int irq, void *dev_id)
3791 {
3792         struct niu_ldg *lp = dev_id;
3793         struct niu *np = lp->np;
3794         int ldg = lp->ldg_num;
3795         unsigned long flags;
3796         u64 v0, v1, v2;
3797
3798         if (netif_msg_intr(np))
3799                 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
3800                        lp, ldg);
3801
3802         spin_lock_irqsave(&np->lock, flags);
3803
3804         v0 = nr64(LDSV0(ldg));
3805         v1 = nr64(LDSV1(ldg));
3806         v2 = nr64(LDSV2(ldg));
3807
3808         if (netif_msg_intr(np))
3809                 printk("v0[%llx] v1[%llx] v2[%llx]\n",
3810                        (unsigned long long) v0,
3811                        (unsigned long long) v1,
3812                        (unsigned long long) v2);
3813
3814         if (unlikely(!v0 && !v1 && !v2)) {
3815                 spin_unlock_irqrestore(&np->lock, flags);
3816                 return IRQ_NONE;
3817         }
3818
3819         if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
3820                 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
3821                 if (err)
3822                         goto out;
3823         }
3824         if (likely(v0 & ~((u64)1 << LDN_MIF)))
3825                 niu_schedule_napi(np, lp, v0, v1, v2);
3826         else
3827                 niu_ldg_rearm(np, lp, 1);
3828 out:
3829         spin_unlock_irqrestore(&np->lock, flags);
3830
3831         return IRQ_HANDLED;
3832 }
3833
3834 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
3835 {
3836         if (rp->mbox) {
3837                 np->ops->free_coherent(np->device,
3838                                        sizeof(struct rxdma_mailbox),
3839                                        rp->mbox, rp->mbox_dma);
3840                 rp->mbox = NULL;
3841         }
3842         if (rp->rcr) {
3843                 np->ops->free_coherent(np->device,
3844                                        MAX_RCR_RING_SIZE * sizeof(__le64),
3845                                        rp->rcr, rp->rcr_dma);
3846                 rp->rcr = NULL;
3847                 rp->rcr_table_size = 0;
3848                 rp->rcr_index = 0;
3849         }
3850         if (rp->rbr) {
3851                 niu_rbr_free(np, rp);
3852
3853                 np->ops->free_coherent(np->device,
3854                                        MAX_RBR_RING_SIZE * sizeof(__le32),
3855                                        rp->rbr, rp->rbr_dma);
3856                 rp->rbr = NULL;
3857                 rp->rbr_table_size = 0;
3858                 rp->rbr_index = 0;
3859         }
3860         kfree(rp->rxhash);
3861         rp->rxhash = NULL;
3862 }
3863
3864 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
3865 {
3866         if (rp->mbox) {
3867                 np->ops->free_coherent(np->device,
3868                                        sizeof(struct txdma_mailbox),
3869                                        rp->mbox, rp->mbox_dma);
3870                 rp->mbox = NULL;
3871         }
3872         if (rp->descr) {
3873                 int i;
3874
3875                 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
3876                         if (rp->tx_buffs[i].skb)
3877                                 (void) release_tx_packet(np, rp, i);
3878                 }
3879
3880                 np->ops->free_coherent(np->device,
3881                                        MAX_TX_RING_SIZE * sizeof(__le64),
3882                                        rp->descr, rp->descr_dma);
3883                 rp->descr = NULL;
3884                 rp->pending = 0;
3885                 rp->prod = 0;
3886                 rp->cons = 0;
3887                 rp->wrap_bit = 0;
3888         }
3889 }
3890
3891 static void niu_free_channels(struct niu *np)
3892 {
3893         int i;
3894
3895         if (np->rx_rings) {
3896                 for (i = 0; i < np->num_rx_rings; i++) {
3897                         struct rx_ring_info *rp = &np->rx_rings[i];
3898
3899                         niu_free_rx_ring_info(np, rp);
3900                 }
3901                 kfree(np->rx_rings);
3902                 np->rx_rings = NULL;
3903                 np->num_rx_rings = 0;
3904         }
3905
3906         if (np->tx_rings) {
3907                 for (i = 0; i < np->num_tx_rings; i++) {
3908                         struct tx_ring_info *rp = &np->tx_rings[i];
3909
3910                         niu_free_tx_ring_info(np, rp);
3911                 }
3912                 kfree(np->tx_rings);
3913                 np->tx_rings = NULL;
3914                 np->num_tx_rings = 0;
3915         }
3916 }
3917
3918 static int niu_alloc_rx_ring_info(struct niu *np,
3919                                   struct rx_ring_info *rp)
3920 {
3921         BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3922
3923         rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3924                              GFP_KERNEL);
3925         if (!rp->rxhash)
3926                 return -ENOMEM;
3927
3928         rp->mbox = np->ops->alloc_coherent(np->device,
3929                                            sizeof(struct rxdma_mailbox),
3930                                            &rp->mbox_dma, GFP_KERNEL);
3931         if (!rp->mbox)
3932                 return -ENOMEM;
3933         if ((unsigned long)rp->mbox & (64UL - 1)) {
3934                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3935                         "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3936                 return -EINVAL;
3937         }
3938
3939         rp->rcr = np->ops->alloc_coherent(np->device,
3940                                           MAX_RCR_RING_SIZE * sizeof(__le64),
3941                                           &rp->rcr_dma, GFP_KERNEL);
3942         if (!rp->rcr)
3943                 return -ENOMEM;
3944         if ((unsigned long)rp->rcr & (64UL - 1)) {
3945                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3946                         "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3947                 return -EINVAL;
3948         }
3949         rp->rcr_table_size = MAX_RCR_RING_SIZE;
3950         rp->rcr_index = 0;
3951
3952         rp->rbr = np->ops->alloc_coherent(np->device,
3953                                           MAX_RBR_RING_SIZE * sizeof(__le32),
3954                                           &rp->rbr_dma, GFP_KERNEL);
3955         if (!rp->rbr)
3956                 return -ENOMEM;
3957         if ((unsigned long)rp->rbr & (64UL - 1)) {
3958                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3959                         "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3960                 return -EINVAL;
3961         }
3962         rp->rbr_table_size = MAX_RBR_RING_SIZE;
3963         rp->rbr_index = 0;
3964         rp->rbr_pending = 0;
3965
3966         return 0;
3967 }
3968
3969 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3970 {
3971         int mtu = np->dev->mtu;
3972
3973         /* These values are recommended by the HW designers for fair
3974          * utilization of DRR amongst the rings.
3975          */
3976         rp->max_burst = mtu + 32;
3977         if (rp->max_burst > 4096)
3978                 rp->max_burst = 4096;
3979 }
3980
3981 static int niu_alloc_tx_ring_info(struct niu *np,
3982                                   struct tx_ring_info *rp)
3983 {
3984         BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3985
3986         rp->mbox = np->ops->alloc_coherent(np->device,
3987                                            sizeof(struct txdma_mailbox),
3988                                            &rp->mbox_dma, GFP_KERNEL);
3989         if (!rp->mbox)
3990                 return -ENOMEM;
3991         if ((unsigned long)rp->mbox & (64UL - 1)) {
3992                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3993                         "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3994                 return -EINVAL;
3995         }
3996
3997         rp->descr = np->ops->alloc_coherent(np->device,
3998                                             MAX_TX_RING_SIZE * sizeof(__le64),
3999                                             &rp->descr_dma, GFP_KERNEL);
4000         if (!rp->descr)
4001                 return -ENOMEM;
4002         if ((unsigned long)rp->descr & (64UL - 1)) {
4003                 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4004                         "TXDMA descr table %p\n", np->dev->name, rp->descr);
4005                 return -EINVAL;
4006         }
4007
4008         rp->pending = MAX_TX_RING_SIZE;
4009         rp->prod = 0;
4010         rp->cons = 0;
4011         rp->wrap_bit = 0;
4012
4013         /* XXX make these configurable... XXX */
4014         rp->mark_freq = rp->pending / 4;
4015
4016         niu_set_max_burst(np, rp);
4017
4018         return 0;
4019 }
4020
4021 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4022 {
4023         u16 bss;
4024
4025         bss = min(PAGE_SHIFT, 15);
4026
4027         rp->rbr_block_size = 1 << bss;
4028         rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
4029
4030         rp->rbr_sizes[0] = 256;
4031         rp->rbr_sizes[1] = 1024;
4032         if (np->dev->mtu > ETH_DATA_LEN) {
4033                 switch (PAGE_SIZE) {
4034                 case 4 * 1024:
4035                         rp->rbr_sizes[2] = 4096;
4036                         break;
4037
4038                 default:
4039                         rp->rbr_sizes[2] = 8192;
4040                         break;
4041                 }
4042         } else {
4043                 rp->rbr_sizes[2] = 2048;
4044         }
4045         rp->rbr_sizes[3] = rp->rbr_block_size;
4046 }
4047
4048 static int niu_alloc_channels(struct niu *np)
4049 {
4050         struct niu_parent *parent = np->parent;
4051         int first_rx_channel, first_tx_channel;
4052         int i, port, err;
4053
4054         port = np->port;
4055         first_rx_channel = first_tx_channel = 0;
4056         for (i = 0; i < port; i++) {
4057                 first_rx_channel += parent->rxchan_per_port[i];
4058                 first_tx_channel += parent->txchan_per_port[i];
4059         }
4060
4061         np->num_rx_rings = parent->rxchan_per_port[port];
4062         np->num_tx_rings = parent->txchan_per_port[port];
4063
4064         np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4065                                GFP_KERNEL);
4066         err = -ENOMEM;
4067         if (!np->rx_rings)
4068                 goto out_err;
4069
4070         for (i = 0; i < np->num_rx_rings; i++) {
4071                 struct rx_ring_info *rp = &np->rx_rings[i];
4072
4073                 rp->np = np;
4074                 rp->rx_channel = first_rx_channel + i;
4075
4076                 err = niu_alloc_rx_ring_info(np, rp);
4077                 if (err)
4078                         goto out_err;
4079
4080                 niu_size_rbr(np, rp);
4081
4082                 /* XXX better defaults, configurable, etc... XXX */
4083                 rp->nonsyn_window = 64;
4084                 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4085                 rp->syn_window = 64;
4086                 rp->syn_threshold = rp->rcr_table_size - 64;
4087                 rp->rcr_pkt_threshold = 16;
4088                 rp->rcr_timeout = 8;
4089                 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4090                 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4091                         rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4092
4093                 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4094                 if (err)
4095                         return err;
4096         }
4097
4098         np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4099                                GFP_KERNEL);
4100         err = -ENOMEM;
4101         if (!np->tx_rings)
4102                 goto out_err;
4103
4104         for (i = 0; i < np->num_tx_rings; i++) {
4105                 struct tx_ring_info *rp = &np->tx_rings[i];
4106
4107                 rp->np = np;
4108                 rp->tx_channel = first_tx_channel + i;
4109
4110                 err = niu_alloc_tx_ring_info(np, rp);
4111                 if (err)
4112                         goto out_err;
4113         }
4114
4115         return 0;
4116
4117 out_err:
4118         niu_free_channels(np);
4119         return err;
4120 }
4121
4122 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4123 {
4124         int limit = 1000;
4125
4126         while (--limit > 0) {
4127                 u64 val = nr64(TX_CS(channel));
4128                 if (val & TX_CS_SNG_STATE)
4129                         return 0;
4130         }
4131         return -ENODEV;
4132 }
4133
4134 static int niu_tx_channel_stop(struct niu *np, int channel)
4135 {
4136         u64 val = nr64(TX_CS(channel));
4137
4138         val |= TX_CS_STOP_N_GO;
4139         nw64(TX_CS(channel), val);
4140
4141         return niu_tx_cs_sng_poll(np, channel);
4142 }
4143
4144 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4145 {
4146         int limit = 1000;
4147
4148         while (--limit > 0) {
4149                 u64 val = nr64(TX_CS(channel));
4150                 if (!(val & TX_CS_RST))
4151                         return 0;
4152         }
4153         return -ENODEV;
4154 }
4155
4156 static int niu_tx_channel_reset(struct niu *np, int channel)
4157 {
4158         u64 val = nr64(TX_CS(channel));
4159         int err;
4160
4161         val |= TX_CS_RST;
4162         nw64(TX_CS(channel), val);
4163
4164         err = niu_tx_cs_reset_poll(np, channel);
4165         if (!err)
4166                 nw64(TX_RING_KICK(channel), 0);
4167
4168         return err;
4169 }
4170
4171 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4172 {
4173         u64 val;
4174
4175         nw64(TX_LOG_MASK1(channel), 0);
4176         nw64(TX_LOG_VAL1(channel), 0);
4177         nw64(TX_LOG_MASK2(channel), 0);
4178         nw64(TX_LOG_VAL2(channel), 0);
4179         nw64(TX_LOG_PAGE_RELO1(channel), 0);
4180         nw64(TX_LOG_PAGE_RELO2(channel), 0);
4181         nw64(TX_LOG_PAGE_HDL(channel), 0);
4182
4183         val  = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4184         val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4185         nw64(TX_LOG_PAGE_VLD(channel), val);
4186
4187         /* XXX TXDMA 32bit mode? XXX */
4188
4189         return 0;
4190 }
4191
4192 static void niu_txc_enable_port(struct niu *np, int on)
4193 {
4194         unsigned long flags;
4195         u64 val, mask;
4196
4197         niu_lock_parent(np, flags);
4198         val = nr64(TXC_CONTROL);
4199         mask = (u64)1 << np->port;
4200         if (on) {
4201                 val |= TXC_CONTROL_ENABLE | mask;
4202         } else {
4203                 val &= ~mask;
4204                 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4205                         val &= ~TXC_CONTROL_ENABLE;
4206         }
4207         nw64(TXC_CONTROL, val);
4208         niu_unlock_parent(np, flags);
4209 }
4210
4211 static void niu_txc_set_imask(struct niu *np, u64 imask)
4212 {
4213         unsigned long flags;
4214         u64 val;
4215
4216         niu_lock_parent(np, flags);
4217         val = nr64(TXC_INT_MASK);
4218         val &= ~TXC_INT_MASK_VAL(np->port);
4219         val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4220         niu_unlock_parent(np, flags);
4221 }
4222
4223 static void niu_txc_port_dma_enable(struct niu *np, int on)
4224 {
4225         u64 val = 0;
4226
4227         if (on) {
4228                 int i;
4229
4230                 for (i = 0; i < np->num_tx_rings; i++)
4231                         val |= (1 << np->tx_rings[i].tx_channel);
4232         }
4233         nw64(TXC_PORT_DMA(np->port), val);
4234 }
4235
4236 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4237 {
4238         int err, channel = rp->tx_channel;
4239         u64 val, ring_len;
4240
4241         err = niu_tx_channel_stop(np, channel);
4242         if (err)
4243                 return err;
4244
4245         err = niu_tx_channel_reset(np, channel);
4246         if (err)
4247                 return err;
4248
4249         err = niu_tx_channel_lpage_init(np, channel);
4250         if (err)
4251                 return err;
4252
4253         nw64(TXC_DMA_MAX(channel), rp->max_burst);
4254         nw64(TX_ENT_MSK(channel), 0);
4255
4256         if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4257                               TX_RNG_CFIG_STADDR)) {
4258                 dev_err(np->device, PFX "%s: TX ring channel %d "
4259                         "DMA addr (%llx) is not aligned.\n",
4260                         np->dev->name, channel,
4261                         (unsigned long long) rp->descr_dma);
4262                 return -EINVAL;
4263         }
4264
4265         /* The length field in TX_RNG_CFIG is measured in 64-byte
4266          * blocks.  rp->pending is the number of TX descriptors in
4267          * our ring, 8 bytes each, thus we divide by 8 bytes more
4268          * to get the proper value the chip wants.
4269          */
4270         ring_len = (rp->pending / 8);
4271
4272         val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4273                rp->descr_dma);
4274         nw64(TX_RNG_CFIG(channel), val);
4275
4276         if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4277             ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4278                 dev_err(np->device, PFX "%s: TX ring channel %d "
4279                         "MBOX addr (%llx) is has illegal bits.\n",
4280                         np->dev->name, channel,
4281                         (unsigned long long) rp->mbox_dma);
4282                 return -EINVAL;
4283         }
4284         nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4285         nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4286
4287         nw64(TX_CS(channel), 0);
4288
4289         rp->last_pkt_cnt = 0;
4290
4291         return 0;
4292 }
4293
4294 static void niu_init_rdc_groups(struct niu *np)
4295 {
4296         struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4297         int i, first_table_num = tp->first_table_num;
4298
4299         for (i = 0; i < tp->num_tables; i++) {
4300                 struct rdc_table *tbl = &tp->tables[i];
4301                 int this_table = first_table_num + i;
4302                 int slot;
4303
4304                 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4305                         nw64(RDC_TBL(this_table, slot),
4306                              tbl->rxdma_channel[slot]);
4307         }
4308
4309         nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4310 }
4311
4312 static void niu_init_drr_weight(struct niu *np)
4313 {
4314         int type = phy_decode(np->parent->port_phy, np->port);
4315         u64 val;
4316
4317         switch (type) {
4318         case PORT_TYPE_10G:
4319                 val = PT_DRR_WEIGHT_DEFAULT_10G;
4320                 break;
4321
4322         case PORT_TYPE_1G:
4323         default:
4324                 val = PT_DRR_WEIGHT_DEFAULT_1G;
4325                 break;
4326         }
4327         nw64(PT_DRR_WT(np->port), val);
4328 }
4329
4330 static int niu_init_hostinfo(struct niu *np)
4331 {
4332         struct niu_parent *parent = np->parent;
4333         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4334         int i, err, num_alt = niu_num_alt_addr(np);
4335         int first_rdc_table = tp->first_table_num;
4336
4337         err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4338         if (err)
4339                 return err;
4340
4341         err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4342         if (err)
4343                 return err;
4344
4345         for (i = 0; i < num_alt; i++) {
4346                 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4347                 if (err)
4348                         return err;
4349         }
4350
4351         return 0;
4352 }
4353
4354 static int niu_rx_channel_reset(struct niu *np, int channel)
4355 {
4356         return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4357                                       RXDMA_CFIG1_RST, 1000, 10,
4358                                       "RXDMA_CFIG1");
4359 }
4360
4361 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4362 {
4363         u64 val;
4364
4365         nw64(RX_LOG_MASK1(channel), 0);
4366         nw64(RX_LOG_VAL1(channel), 0);
4367         nw64(RX_LOG_MASK2(channel), 0);
4368         nw64(RX_LOG_VAL2(channel), 0);
4369         nw64(RX_LOG_PAGE_RELO1(channel), 0);
4370         nw64(RX_LOG_PAGE_RELO2(channel), 0);
4371         nw64(RX_LOG_PAGE_HDL(channel), 0);
4372
4373         val  = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4374         val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4375         nw64(RX_LOG_PAGE_VLD(channel), val);
4376
4377         return 0;
4378 }
4379
4380 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4381 {
4382         u64 val;
4383
4384         val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4385                ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4386                ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4387                ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4388         nw64(RDC_RED_PARA(rp->rx_channel), val);
4389 }
4390
4391 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4392 {
4393         u64 val = 0;
4394
4395         switch (rp->rbr_block_size) {
4396         case 4 * 1024:
4397                 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4398                 break;
4399         case 8 * 1024:
4400                 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4401                 break;
4402         case 16 * 1024:
4403                 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4404                 break;
4405         case 32 * 1024:
4406                 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4407                 break;
4408         default:
4409                 return -EINVAL;
4410         }
4411         val |= RBR_CFIG_B_VLD2;
4412         switch (rp->rbr_sizes[2]) {
4413         case 2 * 1024:
4414                 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4415                 break;
4416         case 4 * 1024:
4417                 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4418                 break;
4419         case 8 * 1024:
4420                 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4421                 break;
4422         case 16 * 1024:
4423                 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4424                 break;
4425
4426         default:
4427                 return -EINVAL;
4428         }
4429         val |= RBR_CFIG_B_VLD1;
4430         switch (rp->rbr_sizes[1]) {
4431         case 1 * 1024:
4432                 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4433                 break;
4434         case 2 * 1024:
4435                 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4436                 break;
4437         case 4 * 1024:
4438                 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4439                 break;
4440         case 8 * 1024:
4441                 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4442                 break;
4443
4444         default:
4445                 return -EINVAL;
4446         }
4447         val |= RBR_CFIG_B_VLD0;
4448         switch (rp->rbr_sizes[0]) {
4449         case 256:
4450                 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4451                 break;
4452         case 512:
4453                 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4454                 break;
4455         case 1 * 1024:
4456                 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4457                 break;
4458         case 2 * 1024:
4459                 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4460                 break;
4461
4462         default:
4463                 return -EINVAL;
4464         }
4465
4466         *ret = val;
4467         return 0;
4468 }
4469
4470 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4471 {
4472         u64 val = nr64(RXDMA_CFIG1(channel));
4473         int limit;
4474
4475         if (on)
4476                 val |= RXDMA_CFIG1_EN;
4477         else
4478                 val &= ~RXDMA_CFIG1_EN;
4479         nw64(RXDMA_CFIG1(channel), val);
4480
4481         limit = 1000;
4482         while (--limit > 0) {
4483                 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4484                         break;
4485                 udelay(10);
4486         }
4487         if (limit <= 0)
4488                 return -ENODEV;
4489         return 0;
4490 }
4491
4492 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4493 {
4494         int err, channel = rp->rx_channel;
4495         u64 val;
4496
4497         err = niu_rx_channel_reset(np, channel);
4498         if (err)
4499                 return err;
4500
4501         err = niu_rx_channel_lpage_init(np, channel);
4502         if (err)
4503                 return err;
4504
4505         niu_rx_channel_wred_init(np, rp);
4506
4507         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4508         nw64(RX_DMA_CTL_STAT(channel),
4509              (RX_DMA_CTL_STAT_MEX |
4510               RX_DMA_CTL_STAT_RCRTHRES |
4511               RX_DMA_CTL_STAT_RCRTO |
4512               RX_DMA_CTL_STAT_RBR_EMPTY));
4513         nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4514         nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4515         nw64(RBR_CFIG_A(channel),
4516              ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4517              (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4518         err = niu_compute_rbr_cfig_b(rp, &val);
4519         if (err)
4520                 return err;
4521         nw64(RBR_CFIG_B(channel), val);
4522         nw64(RCRCFIG_A(channel),
4523              ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4524              (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4525         nw64(RCRCFIG_B(channel),
4526              ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4527              RCRCFIG_B_ENTOUT |
4528              ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4529
4530         err = niu_enable_rx_channel(np, channel, 1);
4531         if (err)
4532                 return err;
4533
4534         nw64(RBR_KICK(channel), rp->rbr_index);
4535
4536         val = nr64(RX_DMA_CTL_STAT(channel));
4537         val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4538         nw64(RX_DMA_CTL_STAT(channel), val);
4539
4540         return 0;
4541 }
4542
4543 static int niu_init_rx_channels(struct niu *np)
4544 {
4545         unsigned long flags;
4546         u64 seed = jiffies_64;
4547         int err, i;
4548
4549         niu_lock_parent(np, flags);
4550         nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4551         nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4552         niu_unlock_parent(np, flags);
4553
4554         /* XXX RXDMA 32bit mode? XXX */
4555
4556         niu_init_rdc_groups(np);
4557         niu_init_drr_weight(np);
4558
4559         err = niu_init_hostinfo(np);
4560         if (err)
4561                 return err;
4562
4563         for (i = 0; i < np->num_rx_rings; i++) {
4564                 struct rx_ring_info *rp = &np->rx_rings[i];
4565
4566                 err = niu_init_one_rx_channel(np, rp);
4567                 if (err)
4568                         return err;
4569         }
4570
4571         return 0;
4572 }
4573
4574 static int niu_set_ip_frag_rule(struct niu *np)
4575 {
4576         struct niu_parent *parent = np->parent;
4577         struct niu_classifier *cp = &np->clas;
4578         struct niu_tcam_entry *tp;
4579         int index, err;
4580
4581         /* XXX fix this allocation scheme XXX */
4582         index = cp->tcam_index;
4583         tp = &parent->tcam[index];
4584
4585         /* Note that the noport bit is the same in both ipv4 and
4586          * ipv6 format TCAM entries.
4587          */
4588         memset(tp, 0, sizeof(*tp));
4589         tp->key[1] = TCAM_V4KEY1_NOPORT;
4590         tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
4591         tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
4592                           ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
4593         err = tcam_write(np, index, tp->key, tp->key_mask);
4594         if (err)
4595                 return err;
4596         err = tcam_assoc_write(np, index, tp->assoc_data);
4597         if (err)
4598                 return err;
4599
4600         return 0;
4601 }
4602
4603 static int niu_init_classifier_hw(struct niu *np)
4604 {
4605         struct niu_parent *parent = np->parent;
4606         struct niu_classifier *cp = &np->clas;
4607         int i, err;
4608
4609         nw64(H1POLY, cp->h1_init);
4610         nw64(H2POLY, cp->h2_init);
4611
4612         err = niu_init_hostinfo(np);
4613         if (err)
4614                 return err;
4615
4616         for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
4617                 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
4618
4619                 vlan_tbl_write(np, i, np->port,
4620                                vp->vlan_pref, vp->rdc_num);
4621         }
4622
4623         for (i = 0; i < cp->num_alt_mac_mappings; i++) {
4624                 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
4625
4626                 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
4627                                                 ap->rdc_num, ap->mac_pref);
4628                 if (err)
4629                         return err;
4630         }
4631
4632         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
4633                 int index = i - CLASS_CODE_USER_PROG1;
4634
4635                 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
4636                 if (err)
4637                         return err;
4638                 err = niu_set_flow_key(np, i, parent->flow_key[index]);
4639                 if (err)
4640                         return err;
4641         }
4642
4643         err = niu_set_ip_frag_rule(np);
4644         if (err)
4645                 return err;
4646
4647         tcam_enable(np, 1);
4648
4649         return 0;
4650 }
4651
4652 static int niu_zcp_write(struct niu *np, int index, u64 *data)
4653 {
4654         nw64(ZCP_RAM_DATA0, data[0]);
4655         nw64(ZCP_RAM_DATA1, data[1]);
4656         nw64(ZCP_RAM_DATA2, data[2]);
4657         nw64(ZCP_RAM_DATA3, data[3]);
4658         nw64(ZCP_RAM_DATA4, data[4]);
4659         nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
4660         nw64(ZCP_RAM_ACC,
4661              (ZCP_RAM_ACC_WRITE |
4662               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4663               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4664
4665         return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4666                                    1000, 100);
4667 }
4668
4669 static int niu_zcp_read(struct niu *np, int index, u64 *data)
4670 {
4671         int err;
4672
4673         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4674                                   1000, 100);
4675         if (err) {
4676                 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
4677                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4678                         (unsigned long long) nr64(ZCP_RAM_ACC));
4679                 return err;
4680         }
4681
4682         nw64(ZCP_RAM_ACC,
4683              (ZCP_RAM_ACC_READ |
4684               (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4685               (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4686
4687         err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4688                                   1000, 100);
4689         if (err) {
4690                 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
4691                         "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4692                         (unsigned long long) nr64(ZCP_RAM_ACC));
4693                 return err;
4694         }
4695
4696         data[0] = nr64(ZCP_RAM_DATA0);
4697         data[1] = nr64(ZCP_RAM_DATA1);
4698         data[2] = nr64(ZCP_RAM_DATA2);
4699         data[3] = nr64(ZCP_RAM_DATA3);
4700         data[4] = nr64(ZCP_RAM_DATA4);
4701
4702         return 0;
4703 }
4704
4705 static void niu_zcp_cfifo_reset(struct niu *np)
4706 {
4707         u64 val = nr64(RESET_CFIFO);
4708
4709         val |= RESET_CFIFO_RST(np->port);
4710         nw64(RESET_CFIFO, val);
4711         udelay(10);
4712
4713         val &= ~RESET_CFIFO_RST(np->port);
4714         nw64(RESET_CFIFO, val);
4715 }
4716
4717 static int niu_init_zcp(struct niu *np)
4718 {
4719         u64 data[5], rbuf[5];
4720         int i, max, err;
4721
4722         if (np->parent->plat_type != PLAT_TYPE_NIU) {
4723                 if (np->port == 0 || np->port == 1)
4724                         max = ATLAS_P0_P1_CFIFO_ENTRIES;
4725                 else
4726                         max = ATLAS_P2_P3_CFIFO_ENTRIES;
4727         } else
4728                 max = NIU_CFIFO_ENTRIES;
4729
4730         data[0] = 0;
4731         data[1] = 0;
4732         data[2] = 0;
4733         data[3] = 0;
4734         data[4] = 0;
4735
4736         for (i = 0; i < max; i++) {
4737                 err = niu_zcp_write(np, i, data);
4738                 if (err)
4739                         return err;
4740                 err = niu_zcp_read(np, i, rbuf);
4741                 if (err)
4742                         return err;
4743         }
4744
4745         niu_zcp_cfifo_reset(np);
4746         nw64(CFIFO_ECC(np->port), 0);
4747         nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
4748         (void) nr64(ZCP_INT_STAT);
4749         nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
4750
4751         return 0;
4752 }
4753
4754 static void niu_ipp_write(struct niu *np, int index, u64 *data)
4755 {
4756         u64 val = nr64_ipp(IPP_CFIG);
4757
4758         nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
4759         nw64_ipp(IPP_DFIFO_WR_PTR, index);
4760         nw64_ipp(IPP_DFIFO_WR0, data[0]);
4761         nw64_ipp(IPP_DFIFO_WR1, data[1]);
4762         nw64_ipp(IPP_DFIFO_WR2, data[2]);
4763         nw64_ipp(IPP_DFIFO_WR3, data[3]);
4764         nw64_ipp(IPP_DFIFO_WR4, data[4]);
4765         nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
4766 }
4767
4768 static void niu_ipp_read(struct niu *np, int index, u64 *data)
4769 {
4770         nw64_ipp(IPP_DFIFO_RD_PTR, index);
4771         data[0] = nr64_ipp(IPP_DFIFO_RD0);
4772         data[1] = nr64_ipp(IPP_DFIFO_RD1);
4773         data[2] = nr64_ipp(IPP_DFIFO_RD2);
4774         data[3] = nr64_ipp(IPP_DFIFO_RD3);
4775         data[4] = nr64_ipp(IPP_DFIFO_RD4);
4776 }
4777
4778 static int niu_ipp_reset(struct niu *np)
4779 {
4780         return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
4781                                           1000, 100, "IPP_CFIG");
4782 }
4783
4784 static int niu_init_ipp(struct niu *np)
4785 {
4786         u64 data[5], rbuf[5], val;
4787         int i, max, err;
4788
4789         if (np->parent->plat_type != PLAT_TYPE_NIU) {
4790                 if (np->port == 0 || np->port == 1)
4791                         max = ATLAS_P0_P1_DFIFO_ENTRIES;
4792                 else
4793                         max = ATLAS_P2_P3_DFIFO_ENTRIES;
4794         } else
4795                 max = NIU_DFIFO_ENTRIES;
4796
4797         data[0] = 0;
4798         data[1] = 0;
4799         data[2] = 0;
4800         data[3] = 0;
4801         data[4] = 0;
4802
4803         for (i = 0; i < max; i++) {
4804                 niu_ipp_write(np, i, data);
4805                 niu_ipp_read(np, i, rbuf);
4806         }
4807
4808         (void) nr64_ipp(IPP_INT_STAT);
4809         (void) nr64_ipp(IPP_INT_STAT);
4810
4811         err = niu_ipp_reset(np);
4812         if (err)
4813                 return err;
4814
4815         (void) nr64_ipp(IPP_PKT_DIS);
4816         (void) nr64_ipp(IPP_BAD_CS_CNT);
4817         (void) nr64_ipp(IPP_ECC);
4818
4819         (void) nr64_ipp(IPP_INT_STAT);
4820
4821         nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
4822
4823         val = nr64_ipp(IPP_CFIG);
4824         val &= ~IPP_CFIG_IP_MAX_PKT;
4825         val |= (IPP_CFIG_IPP_ENABLE |
4826                 IPP_CFIG_DFIFO_ECC_EN |
4827                 IPP_CFIG_DROP_BAD_CRC |
4828                 IPP_CFIG_CKSUM_EN |
4829                 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
4830         nw64_ipp(IPP_CFIG, val);
4831
4832         return 0;
4833 }
4834
4835 static void niu_handle_led(struct niu *np, int status)
4836 {
4837         u64 val;
4838         val = nr64_mac(XMAC_CONFIG);
4839
4840         if ((np->flags & NIU_FLAGS_10G) != 0 &&
4841             (np->flags & NIU_FLAGS_FIBER) != 0) {
4842                 if (status) {
4843                         val |= XMAC_CONFIG_LED_POLARITY;
4844                         val &= ~XMAC_CONFIG_FORCE_LED_ON;
4845                 } else {
4846                         val |= XMAC_CONFIG_FORCE_LED_ON;
4847                         val &= ~XMAC_CONFIG_LED_POLARITY;
4848                 }
4849         }
4850
4851         nw64_mac(XMAC_CONFIG, val);
4852 }
4853
4854 static void niu_init_xif_xmac(struct niu *np)
4855 {
4856         struct niu_link_config *lp = &np->link_config;
4857         u64 val;
4858
4859         if (np->flags & NIU_FLAGS_XCVR_SERDES) {
4860                 val = nr64(MIF_CONFIG);
4861                 val |= MIF_CONFIG_ATCA_GE;
4862                 nw64(MIF_CONFIG, val);
4863         }
4864
4865         val = nr64_mac(XMAC_CONFIG);
4866         val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4867
4868         val |= XMAC_CONFIG_TX_OUTPUT_EN;
4869
4870         if (lp->loopback_mode == LOOPBACK_MAC) {
4871                 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4872                 val |= XMAC_CONFIG_LOOPBACK;
4873         } else {
4874                 val &= ~XMAC_CONFIG_LOOPBACK;
4875         }
4876
4877         if (np->flags & NIU_FLAGS_10G) {
4878                 val &= ~XMAC_CONFIG_LFS_DISABLE;
4879         } else {
4880                 val |= XMAC_CONFIG_LFS_DISABLE;
4881                 if (!(np->flags & NIU_FLAGS_FIBER) &&
4882                     !(np->flags & NIU_FLAGS_XCVR_SERDES))
4883                         val |= XMAC_CONFIG_1G_PCS_BYPASS;
4884                 else
4885                         val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
4886         }
4887
4888         val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4889
4890         if (lp->active_speed == SPEED_100)
4891                 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
4892         else
4893                 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
4894
4895         nw64_mac(XMAC_CONFIG, val);
4896
4897         val = nr64_mac(XMAC_CONFIG);
4898         val &= ~XMAC_CONFIG_MODE_MASK;
4899         if (np->flags & NIU_FLAGS_10G) {
4900                 val |= XMAC_CONFIG_MODE_XGMII;
4901         } else {
4902                 if (lp->active_speed == SPEED_100)
4903                         val |= XMAC_CONFIG_MODE_MII;
4904                 else
4905                         val |= XMAC_CONFIG_MODE_GMII;
4906         }
4907
4908         nw64_mac(XMAC_CONFIG, val);
4909 }
4910
4911 static void niu_init_xif_bmac(struct niu *np)
4912 {
4913         struct niu_link_config *lp = &np->link_config;
4914         u64 val;
4915
4916         val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
4917
4918         if (lp->loopback_mode == LOOPBACK_MAC)
4919                 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
4920         else
4921                 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
4922
4923         if (lp->active_speed == SPEED_1000)
4924                 val |= BMAC_XIF_CONFIG_GMII_MODE;
4925         else
4926                 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
4927
4928         val &= ~(BMAC_XIF_CONFIG_LINK_LED |
4929                  BMAC_XIF_CONFIG_LED_POLARITY);
4930
4931         if (!(np->flags & NIU_FLAGS_10G) &&
4932             !(np->flags & NIU_FLAGS_FIBER) &&
4933             lp->active_speed == SPEED_100)
4934                 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4935         else
4936                 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4937
4938         nw64_mac(BMAC_XIF_CONFIG, val);
4939 }
4940
4941 static void niu_init_xif(struct niu *np)
4942 {
4943         if (np->flags & NIU_FLAGS_XMAC)
4944                 niu_init_xif_xmac(np);
4945         else
4946                 niu_init_xif_bmac(np);
4947 }
4948
4949 static void niu_pcs_mii_reset(struct niu *np)
4950 {
4951         int limit = 1000;
4952         u64 val = nr64_pcs(PCS_MII_CTL);
4953         val |= PCS_MII_CTL_RST;
4954         nw64_pcs(PCS_MII_CTL, val);
4955         while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
4956                 udelay(100);
4957                 val = nr64_pcs(PCS_MII_CTL);
4958         }
4959 }
4960
4961 static void niu_xpcs_reset(struct niu *np)
4962 {
4963         int limit = 1000;
4964         u64 val = nr64_xpcs(XPCS_CONTROL1);
4965         val |= XPCS_CONTROL1_RESET;
4966         nw64_xpcs(XPCS_CONTROL1, val);
4967         while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
4968                 udelay(100);
4969                 val = nr64_xpcs(XPCS_CONTROL1);
4970         }
4971 }
4972
4973 static int niu_init_pcs(struct niu *np)
4974 {
4975         struct niu_link_config *lp = &np->link_config;
4976         u64 val;
4977
4978         switch (np->flags & (NIU_FLAGS_10G |
4979                              NIU_FLAGS_FIBER |
4980                              NIU_FLAGS_XCVR_SERDES)) {
4981         case NIU_FLAGS_FIBER:
4982                 /* 1G fiber */
4983                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4984                 nw64_pcs(PCS_DPATH_MODE, 0);
4985                 niu_pcs_mii_reset(np);
4986                 break;
4987
4988         case NIU_FLAGS_10G:
4989         case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
4990         case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
4991                 /* 10G SERDES */
4992                 if (!(np->flags & NIU_FLAGS_XMAC))
4993                         return -EINVAL;
4994
4995                 /* 10G copper or fiber */
4996                 val = nr64_mac(XMAC_CONFIG);
4997                 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4998                 nw64_mac(XMAC_CONFIG, val);
4999
5000                 niu_xpcs_reset(np);
5001
5002                 val = nr64_xpcs(XPCS_CONTROL1);
5003                 if (lp->loopback_mode == LOOPBACK_PHY)
5004                         val |= XPCS_CONTROL1_LOOPBACK;
5005                 else
5006                         val &= ~XPCS_CONTROL1_LOOPBACK;
5007                 nw64_xpcs(XPCS_CONTROL1, val);
5008
5009                 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5010                 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5011                 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5012                 break;
5013
5014
5015         case NIU_FLAGS_XCVR_SERDES:
5016                 /* 1G SERDES */
5017                 niu_pcs_mii_reset(np);
5018                 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5019                 nw64_pcs(PCS_DPATH_MODE, 0);
5020                 break;
5021
5022         case 0:
5023                 /* 1G copper */
5024         case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5025                 /* 1G RGMII FIBER */
5026                 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5027                 niu_pcs_mii_reset(np);
5028                 break;
5029
5030         default:
5031                 return -EINVAL;
5032         }
5033
5034         return 0;
5035 }
5036
5037 static int niu_reset_tx_xmac(struct niu *np)
5038 {
5039         return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5040                                           (XTXMAC_SW_RST_REG_RS |
5041                                            XTXMAC_SW_RST_SOFT_RST),
5042                                           1000, 100, "XTXMAC_SW_RST");
5043 }
5044
5045 static int niu_reset_tx_bmac(struct niu *np)
5046 {
5047         int limit;
5048
5049         nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5050         limit = 1000;
5051         while (--limit >= 0) {
5052                 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5053                         break;
5054                 udelay(100);
5055         }
5056         if (limit < 0) {
5057                 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5058                         "BTXMAC_SW_RST[%llx]\n",
5059                         np->port,
5060                         (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5061                 return -ENODEV;
5062         }
5063
5064         return 0;
5065 }
5066
5067 static int niu_reset_tx_mac(struct niu *np)
5068 {
5069         if (np->flags & NIU_FLAGS_XMAC)
5070                 return niu_reset_tx_xmac(np);
5071         else
5072                 return niu_reset_tx_bmac(np);
5073 }
5074
5075 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5076 {
5077         u64 val;
5078
5079         val = nr64_mac(XMAC_MIN);
5080         val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5081                  XMAC_MIN_RX_MIN_PKT_SIZE);
5082         val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5083         val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5084         nw64_mac(XMAC_MIN, val);
5085
5086         nw64_mac(XMAC_MAX, max);
5087
5088         nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5089
5090         val = nr64_mac(XMAC_IPG);
5091         if (np->flags & NIU_FLAGS_10G) {
5092                 val &= ~XMAC_IPG_IPG_XGMII;
5093                 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5094         } else {
5095                 val &= ~XMAC_IPG_IPG_MII_GMII;
5096                 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5097         }
5098         nw64_mac(XMAC_IPG, val);
5099
5100         val = nr64_mac(XMAC_CONFIG);
5101         val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5102                  XMAC_CONFIG_STRETCH_MODE |
5103                  XMAC_CONFIG_VAR_MIN_IPG_EN |
5104                  XMAC_CONFIG_TX_ENABLE);
5105         nw64_mac(XMAC_CONFIG, val);
5106
5107         nw64_mac(TXMAC_FRM_CNT, 0);
5108         nw64_mac(TXMAC_BYTE_CNT, 0);
5109 }
5110
5111 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5112 {
5113         u64 val;
5114
5115         nw64_mac(BMAC_MIN_FRAME, min);
5116         nw64_mac(BMAC_MAX_FRAME, max);
5117
5118         nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5119         nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5120         nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5121
5122         val = nr64_mac(BTXMAC_CONFIG);
5123         val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5124                  BTXMAC_CONFIG_ENABLE);
5125         nw64_mac(BTXMAC_CONFIG, val);
5126 }
5127
5128 static void niu_init_tx_mac(struct niu *np)
5129 {
5130         u64 min, max;
5131
5132         min = 64;
5133         if (np->dev->mtu > ETH_DATA_LEN)
5134                 max = 9216;
5135         else
5136                 max = 1522;
5137
5138         /* The XMAC_MIN register only accepts values for TX min which
5139          * have the low 3 bits cleared.
5140          */
5141         BUILD_BUG_ON(min & 0x7);
5142
5143         if (np->flags & NIU_FLAGS_XMAC)
5144                 niu_init_tx_xmac(np, min, max);
5145         else
5146                 niu_init_tx_bmac(np, min, max);
5147 }
5148
5149 static int niu_reset_rx_xmac(struct niu *np)
5150 {
5151         int limit;
5152
5153         nw64_mac(XRXMAC_SW_RST,
5154                  XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5155         limit = 1000;
5156         while (--limit >= 0) {
5157                 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5158                                                  XRXMAC_SW_RST_SOFT_RST)))
5159                     break;
5160                 udelay(100);
5161         }
5162         if (limit < 0) {
5163                 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5164                         "XRXMAC_SW_RST[%llx]\n",
5165                         np->port,
5166                         (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5167                 return -ENODEV;
5168         }
5169
5170         return 0;
5171 }
5172
5173 static int niu_reset_rx_bmac(struct niu *np)
5174 {
5175         int limit;
5176
5177         nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5178         limit = 1000;
5179         while (--limit >= 0) {
5180                 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5181                         break;
5182                 udelay(100);
5183         }
5184         if (limit < 0) {
5185                 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5186                         "BRXMAC_SW_RST[%llx]\n",
5187                         np->port,
5188                         (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5189                 return -ENODEV;
5190         }
5191
5192         return 0;
5193 }
5194
5195 static int niu_reset_rx_mac(struct niu *np)
5196 {
5197         if (np->flags & NIU_FLAGS_XMAC)
5198                 return niu_reset_rx_xmac(np);
5199         else
5200                 return niu_reset_rx_bmac(np);
5201 }
5202
5203 static void niu_init_rx_xmac(struct niu *np)
5204 {
5205         struct niu_parent *parent = np->parent;
5206         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5207         int first_rdc_table = tp->first_table_num;
5208         unsigned long i;
5209         u64 val;
5210
5211         nw64_mac(XMAC_ADD_FILT0, 0);
5212         nw64_mac(XMAC_ADD_FILT1, 0);
5213         nw64_mac(XMAC_ADD_FILT2, 0);
5214         nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5215         nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5216         for (i = 0; i < MAC_NUM_HASH; i++)
5217                 nw64_mac(XMAC_HASH_TBL(i), 0);
5218         nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5219         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5220         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5221
5222         val = nr64_mac(XMAC_CONFIG);
5223         val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5224                  XMAC_CONFIG_PROMISCUOUS |
5225                  XMAC_CONFIG_PROMISC_GROUP |
5226                  XMAC_CONFIG_ERR_CHK_DIS |
5227                  XMAC_CONFIG_RX_CRC_CHK_DIS |
5228                  XMAC_CONFIG_RESERVED_MULTICAST |
5229                  XMAC_CONFIG_RX_CODEV_CHK_DIS |
5230                  XMAC_CONFIG_ADDR_FILTER_EN |
5231                  XMAC_CONFIG_RCV_PAUSE_ENABLE |
5232                  XMAC_CONFIG_STRIP_CRC |
5233                  XMAC_CONFIG_PASS_FLOW_CTRL |
5234                  XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5235         val |= (XMAC_CONFIG_HASH_FILTER_EN);
5236         nw64_mac(XMAC_CONFIG, val);
5237
5238         nw64_mac(RXMAC_BT_CNT, 0);
5239         nw64_mac(RXMAC_BC_FRM_CNT, 0);
5240         nw64_mac(RXMAC_MC_FRM_CNT, 0);
5241         nw64_mac(RXMAC_FRAG_CNT, 0);
5242         nw64_mac(RXMAC_HIST_CNT1, 0);
5243         nw64_mac(RXMAC_HIST_CNT2, 0);
5244         nw64_mac(RXMAC_HIST_CNT3, 0);
5245         nw64_mac(RXMAC_HIST_CNT4, 0);
5246         nw64_mac(RXMAC_HIST_CNT5, 0);
5247         nw64_mac(RXMAC_HIST_CNT6, 0);
5248         nw64_mac(RXMAC_HIST_CNT7, 0);
5249         nw64_mac(RXMAC_MPSZER_CNT, 0);
5250         nw64_mac(RXMAC_CRC_ER_CNT, 0);
5251         nw64_mac(RXMAC_CD_VIO_CNT, 0);
5252         nw64_mac(LINK_FAULT_CNT, 0);
5253 }
5254
5255 static void niu_init_rx_bmac(struct niu *np)
5256 {
5257         struct niu_parent *parent = np->parent;
5258         struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5259         int first_rdc_table = tp->first_table_num;
5260         unsigned long i;
5261         u64 val;
5262
5263         nw64_mac(BMAC_ADD_FILT0, 0);
5264         nw64_mac(BMAC_ADD_FILT1, 0);
5265         nw64_mac(BMAC_ADD_FILT2, 0);
5266         nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5267         nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5268         for (i = 0; i < MAC_NUM_HASH; i++)
5269                 nw64_mac(BMAC_HASH_TBL(i), 0);
5270         niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5271         niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5272         nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5273
5274         val = nr64_mac(BRXMAC_CONFIG);
5275         val &= ~(BRXMAC_CONFIG_ENABLE |
5276                  BRXMAC_CONFIG_STRIP_PAD |
5277                  BRXMAC_CONFIG_STRIP_FCS |
5278                  BRXMAC_CONFIG_PROMISC |
5279                  BRXMAC_CONFIG_PROMISC_GRP |
5280                  BRXMAC_CONFIG_ADDR_FILT_EN |
5281                  BRXMAC_CONFIG_DISCARD_DIS);
5282         val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5283         nw64_mac(BRXMAC_CONFIG, val);
5284
5285         val = nr64_mac(BMAC_ADDR_CMPEN);
5286         val |= BMAC_ADDR_CMPEN_EN0;
5287         nw64_mac(BMAC_ADDR_CMPEN, val);
5288 }
5289
5290 static void niu_init_rx_mac(struct niu *np)
5291 {
5292         niu_set_primary_mac(np, np->dev->dev_addr);
5293
5294         if (np->flags & NIU_FLAGS_XMAC)
5295                 niu_init_rx_xmac(np);
5296         else
5297                 niu_init_rx_bmac(np);
5298 }
5299
5300 static void niu_enable_tx_xmac(struct niu *np, int on)
5301 {
5302         u64 val = nr64_mac(XMAC_CONFIG);
5303
5304         if (on)
5305                 val |= XMAC_CONFIG_TX_ENABLE;
5306         else
5307                 val &= ~XMAC_CONFIG_TX_ENABLE;
5308         nw64_mac(XMAC_CONFIG, val);
5309 }
5310
5311 static void niu_enable_tx_bmac(struct niu *np, int on)
5312 {
5313         u64 val = nr64_mac(BTXMAC_CONFIG);
5314
5315         if (on)
5316                 val |= BTXMAC_CONFIG_ENABLE;
5317         else
5318                 val &= ~BTXMAC_CONFIG_ENABLE;
5319         nw64_mac(BTXMAC_CONFIG, val);
5320 }
5321
5322 static void niu_enable_tx_mac(struct niu *np, int on)
5323 {
5324         if (np->flags & NIU_FLAGS_XMAC)
5325                 niu_enable_tx_xmac(np, on);
5326         else
5327                 niu_enable_tx_bmac(np, on);
5328 }
5329
5330 static void niu_enable_rx_xmac(struct niu *np, int on)
5331 {
5332         u64 val = nr64_mac(XMAC_CONFIG);
5333
5334         val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5335                  XMAC_CONFIG_PROMISCUOUS);
5336
5337         if (np->flags & NIU_FLAGS_MCAST)
5338                 val |= XMAC_CONFIG_HASH_FILTER_EN;
5339         if (np->flags & NIU_FLAGS_PROMISC)
5340                 val |= XMAC_CONFIG_PROMISCUOUS;
5341
5342         if (on)
5343                 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5344         else
5345                 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5346         nw64_mac(XMAC_CONFIG, val);
5347 }
5348
5349 static void niu_enable_rx_bmac(struct niu *np, int on)
5350 {
5351         u64 val = nr64_mac(BRXMAC_CONFIG);
5352
5353         val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5354                  BRXMAC_CONFIG_PROMISC);
5355
5356         if (np->flags & NIU_FLAGS_MCAST)
5357                 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5358         if (np->flags & NIU_FLAGS_PROMISC)
5359                 val |= BRXMAC_CONFIG_PROMISC;
5360
5361         if (on)
5362                 val |= BRXMAC_CONFIG_ENABLE;
5363         else
5364                 val &= ~BRXMAC_CONFIG_ENABLE;
5365         nw64_mac(BRXMAC_CONFIG, val);
5366 }
5367
5368 static void niu_enable_rx_mac(struct niu *np, int on)
5369 {
5370         if (np->flags & NIU_FLAGS_XMAC)
5371                 niu_enable_rx_xmac(np, on);
5372         else
5373                 niu_enable_rx_bmac(np, on);
5374 }
5375
5376 static int niu_init_mac(struct niu *np)
5377 {
5378         int err;
5379
5380         niu_init_xif(np);
5381         err = niu_init_pcs(np);
5382         if (err)
5383                 return err;
5384
5385         err = niu_reset_tx_mac(np);
5386         if (err)
5387                 return err;
5388         niu_init_tx_mac(np);
5389         err = niu_reset_rx_mac(np);
5390         if (err)
5391                 return err;
5392         niu_init_rx_mac(np);
5393
5394         /* This looks hookey but the RX MAC reset we just did will
5395          * undo some of the state we setup in niu_init_tx_mac() so we
5396          * have to call it again.  In particular, the RX MAC reset will
5397          * set the XMAC_MAX register back to it's default value.
5398          */
5399         niu_init_tx_mac(np);
5400         niu_enable_tx_mac(np, 1);
5401
5402         niu_enable_rx_mac(np, 1);
5403
5404         return 0;
5405 }
5406
5407 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5408 {
5409         (void) niu_tx_channel_stop(np, rp->tx_channel);
5410 }
5411
5412 static void niu_stop_tx_channels(struct niu *np)
5413 {
5414         int i;
5415
5416         for (i = 0; i < np->num_tx_rings; i++) {
5417                 struct tx_ring_info *rp = &np->tx_rings[i];
5418
5419                 niu_stop_one_tx_channel(np, rp);
5420         }
5421 }
5422
5423 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5424 {
5425         (void) niu_tx_channel_reset(np, rp->tx_channel);
5426 }
5427
5428 static void niu_reset_tx_channels(struct niu *np)
5429 {
5430         int i;
5431
5432         for (i = 0; i < np->num_tx_rings; i++) {
5433                 struct tx_ring_info *rp = &np->tx_rings[i];
5434
5435                 niu_reset_one_tx_channel(np, rp);
5436         }
5437 }
5438
5439 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5440 {
5441         (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5442 }
5443
5444 static void niu_stop_rx_channels(struct niu *np)
5445 {
5446         int i;
5447
5448         for (i = 0; i < np->num_rx_rings; i++) {
5449                 struct rx_ring_info *rp = &np->rx_rings[i];
5450
5451                 niu_stop_one_rx_channel(np, rp);
5452         }
5453 }
5454
5455 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5456 {
5457         int channel = rp->rx_channel;
5458
5459         (void) niu_rx_channel_reset(np, channel);
5460         nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5461         nw64(RX_DMA_CTL_STAT(channel), 0);
5462         (void) niu_enable_rx_channel(np, channel, 0);
5463 }
5464
5465 static void niu_reset_rx_channels(struct niu *np)
5466 {
5467         int i;
5468
5469         for (i = 0; i < np->num_rx_rings; i++) {
5470                 struct rx_ring_info *rp = &np->rx_rings[i];
5471
5472                 niu_reset_one_rx_channel(np, rp);
5473         }
5474 }
5475
5476 static void niu_disable_ipp(struct niu *np)
5477 {
5478         u64 rd, wr, val;
5479         int limit;
5480
5481         rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5482         wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5483         limit = 100;
5484         while (--limit >= 0 && (rd != wr)) {
5485                 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5486                 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5487         }
5488         if (limit < 0 &&
5489             (rd != 0 && wr != 1)) {
5490                 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5491                         "rd_ptr[%llx] wr_ptr[%llx]\n",
5492                         np->dev->name,
5493                         (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5494                         (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5495         }
5496
5497         val = nr64_ipp(IPP_CFIG);
5498         val &= ~(IPP_CFIG_IPP_ENABLE |
5499                  IPP_CFIG_DFIFO_ECC_EN |
5500                  IPP_CFIG_DROP_BAD_CRC |
5501                  IPP_CFIG_CKSUM_EN);
5502         nw64_ipp(IPP_CFIG, val);
5503
5504         (void) niu_ipp_reset(np);
5505 }
5506
5507 static int niu_init_hw(struct niu *np)
5508 {
5509         int i, err;
5510
5511         niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5512         niu_txc_enable_port(np, 1);
5513         niu_txc_port_dma_enable(np, 1);
5514         niu_txc_set_imask(np, 0);
5515
5516         niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5517         for (i = 0; i < np->num_tx_rings; i++) {
5518                 struct tx_ring_info *rp = &np->tx_rings[i];
5519
5520                 err = niu_init_one_tx_channel(np, rp);
5521                 if (err)
5522                         return err;
5523         }
5524
5525         niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5526         err = niu_init_rx_channels(np);
5527         if (err)
5528                 goto out_uninit_tx_channels;
5529
5530         niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5531         err = niu_init_classifier_hw(np);
5532         if (err)
5533                 goto out_uninit_rx_channels;
5534
5535         niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5536         err = niu_init_zcp(np);
5537         if (err)
5538                 goto out_uninit_rx_channels;
5539
5540         niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5541         err = niu_init_ipp(np);
5542         if (err)
5543                 goto out_uninit_rx_channels;
5544
5545         niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5546         err = niu_init_mac(np);
5547         if (err)
5548                 goto out_uninit_ipp;
5549
5550         return 0;
5551
5552 out_uninit_ipp:
5553         niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5554         niu_disable_ipp(np);
5555
5556 out_uninit_rx_channels:
5557         niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5558         niu_stop_rx_channels(np);
5559         niu_reset_rx_channels(np);
5560
5561 out_uninit_tx_channels:
5562         niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5563         niu_stop_tx_channels(np);
5564         niu_reset_tx_channels(np);
5565
5566         return err;
5567 }
5568
5569 static void niu_stop_hw(struct niu *np)
5570 {
5571         niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5572         niu_enable_interrupts(np, 0);
5573
5574         niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5575         niu_enable_rx_mac(np, 0);
5576
5577         niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5578         niu_disable_ipp(np);
5579
5580         niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
5581         niu_stop_tx_channels(np);
5582
5583         niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
5584         niu_stop_rx_channels(np);
5585
5586         niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
5587         niu_reset_tx_channels(np);
5588
5589         niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
5590         niu_reset_rx_channels(np);
5591 }
5592
5593 static int niu_request_irq(struct niu *np)
5594 {
5595         int i, j, err;
5596
5597         err = 0;
5598         for (i = 0; i < np->num_ldg; i++) {
5599                 struct niu_ldg *lp = &np->ldg[i];
5600
5601                 err = request_irq(lp->irq, niu_interrupt,
5602                                   IRQF_SHARED | IRQF_SAMPLE_RANDOM,
5603                                   np->dev->name, lp);
5604                 if (err)
5605                         goto out_free_irqs;
5606
5607         }
5608
5609         return 0;
5610
5611 out_free_irqs:
5612         for (j = 0; j < i; j++) {
5613                 struct niu_ldg *lp = &np->ldg[j];
5614
5615                 free_irq(lp->irq, lp);
5616         }
5617         return err;
5618 }
5619
5620 static void niu_free_irq(struct niu *np)
5621 {
5622         int i;
5623
5624         for (i = 0; i < np->num_ldg; i++) {
5625                 struct niu_ldg *lp = &np->ldg[i];
5626
5627                 free_irq(lp->irq, lp);
5628         }
5629 }
5630
5631 static void niu_enable_napi(struct niu *np)
5632 {
5633         int i;
5634
5635         for (i = 0; i < np->num_ldg; i++)
5636                 napi_enable(&np->ldg[i].napi);
5637 }
5638
5639 static void niu_disable_napi(struct niu *np)
5640 {
5641         int i;
5642
5643         for (i = 0; i < np->num_ldg; i++)
5644                 napi_disable(&np->ldg[i].napi);
5645 }
5646
5647 static int niu_open(struct net_device *dev)
5648 {
5649         struct niu *np = netdev_priv(dev);
5650         int err;
5651
5652         netif_carrier_off(dev);
5653
5654         err = niu_alloc_channels(np);
5655         if (err)
5656                 goto out_err;
5657
5658         err = niu_enable_interrupts(np, 0);
5659         if (err)
5660                 goto out_free_channels;
5661
5662         err = niu_request_irq(np);
5663         if (err)
5664                 goto out_free_channels;
5665
5666         niu_enable_napi(np);
5667
5668         spin_lock_irq(&np->lock);
5669
5670         err = niu_init_hw(np);
5671         if (!err) {
5672                 init_timer(&np->timer);
5673                 np->timer.expires = jiffies + HZ;
5674                 np->timer.data = (unsigned long) np;
5675                 np->timer.function = niu_timer;
5676
5677                 err = niu_enable_interrupts(np, 1);
5678                 if (err)
5679                         niu_stop_hw(np);
5680         }
5681
5682         spin_unlock_irq(&np->lock);
5683
5684         if (err) {
5685                 niu_disable_napi(np);
5686                 goto out_free_irq;
5687         }
5688
5689         netif_start_queue(dev);
5690
5691         if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5692                 netif_carrier_on(dev);
5693
5694         add_timer(&np->timer);
5695
5696         return 0;
5697
5698 out_free_irq:
5699         niu_free_irq(np);
5700
5701 out_free_channels:
5702         niu_free_channels(np);
5703
5704 out_err:
5705         return err;
5706 }
5707
5708 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
5709 {
5710         cancel_work_sync(&np->reset_task);
5711
5712         niu_disable_napi(np);
5713         netif_stop_queue(dev);
5714
5715         del_timer_sync(&np->timer);
5716
5717         spin_lock_irq(&np->lock);
5718
5719         niu_stop_hw(np);
5720
5721         spin_unlock_irq(&np->lock);
5722 }
5723
5724 static int niu_close(struct net_device *dev)
5725 {
5726         struct niu *np = netdev_priv(dev);
5727
5728         niu_full_shutdown(np, dev);
5729
5730         niu_free_irq(np);
5731
5732         niu_free_channels(np);
5733
5734         niu_handle_led(np, 0);
5735
5736         return 0;
5737 }
5738
5739 static void niu_sync_xmac_stats(struct niu *np)
5740 {
5741         struct niu_xmac_stats *mp = &np->mac_stats.xmac;
5742
5743         mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
5744         mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
5745
5746         mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
5747         mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
5748         mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
5749         mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
5750         mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
5751         mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
5752         mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
5753         mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
5754         mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
5755         mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
5756         mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
5757         mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
5758         mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
5759         mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
5760         mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
5761         mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
5762 }
5763
5764 static void niu_sync_bmac_stats(struct niu *np)
5765 {
5766         struct niu_bmac_stats *mp = &np->mac_stats.bmac;
5767
5768         mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
5769         mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
5770
5771         mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
5772         mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5773         mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5774         mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
5775 }
5776
5777 static void niu_sync_mac_stats(struct niu *np)
5778 {
5779         if (np->flags & NIU_FLAGS_XMAC)
5780                 niu_sync_xmac_stats(np);
5781         else
5782                 niu_sync_bmac_stats(np);
5783 }
5784
5785 static void niu_get_rx_stats(struct niu *np)
5786 {
5787         unsigned long pkts, dropped, errors, bytes;
5788         int i;
5789
5790         pkts = dropped = errors = bytes = 0;
5791         for (i = 0; i < np->num_rx_rings; i++) {
5792                 struct rx_ring_info *rp = &np->rx_rings[i];
5793
5794                 pkts += rp->rx_packets;
5795                 bytes += rp->rx_bytes;
5796                 dropped += rp->rx_dropped;
5797                 errors += rp->rx_errors;
5798         }
5799         np->net_stats.rx_packets = pkts;
5800         np->net_stats.rx_bytes = bytes;
5801         np->net_stats.rx_dropped = dropped;
5802         np->net_stats.rx_errors = errors;
5803 }
5804
5805 static void niu_get_tx_stats(struct niu *np)
5806 {
5807         unsigned long pkts, errors, bytes;
5808         int i;
5809
5810         pkts = errors = bytes = 0;
5811         for (i = 0; i < np->num_tx_rings; i++) {
5812                 struct tx_ring_info *rp = &np->tx_rings[i];
5813
5814                 pkts += rp->tx_packets;
5815                 bytes += rp->tx_bytes;
5816                 errors += rp->tx_errors;
5817         }
5818         np->net_stats.tx_packets = pkts;
5819         np->net_stats.tx_bytes = bytes;
5820         np->net_stats.tx_errors = errors;
5821 }
5822
5823 static struct net_device_stats *niu_get_stats(struct net_device *dev)
5824 {
5825         struct niu *np = netdev_priv(dev);
5826
5827         niu_get_rx_stats(np);
5828         niu_get_tx_stats(np);
5829
5830         return &np->net_stats;
5831 }
5832
5833 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
5834 {
5835         int i;
5836
5837         for (i = 0; i < 16; i++)
5838                 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
5839 }
5840
5841 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
5842 {
5843         int i;
5844
5845         for (i = 0; i < 16; i++)
5846                 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
5847 }
5848
5849 static void niu_load_hash(struct niu *np, u16 *hash)
5850 {
5851         if (np->flags & NIU_FLAGS_XMAC)
5852                 niu_load_hash_xmac(np, hash);
5853         else
5854                 niu_load_hash_bmac(np, hash);
5855 }
5856
5857 static void niu_set_rx_mode(struct net_device *dev)
5858 {
5859         struct niu *np = netdev_priv(dev);
5860         int i, alt_cnt, err;
5861         struct dev_addr_list *addr;
5862         unsigned long flags;
5863         u16 hash[16] = { 0, };
5864
5865         spin_lock_irqsave(&np->lock, flags);
5866         niu_enable_rx_mac(np, 0);
5867
5868         np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
5869         if (dev->flags & IFF_PROMISC)
5870                 np->flags |= NIU_FLAGS_PROMISC;
5871         if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
5872                 np->flags |= NIU_FLAGS_MCAST;
5873
5874         alt_cnt = dev->uc_count;
5875         if (alt_cnt > niu_num_alt_addr(np)) {
5876                 alt_cnt = 0;
5877                 np->flags |= NIU_FLAGS_PROMISC;
5878         }
5879
5880         if (alt_cnt) {
5881                 int index = 0;
5882
5883                 for (addr = dev->uc_list; addr; addr = addr->next) {
5884                         err = niu_set_alt_mac(np, index,
5885                                               addr->da_addr);
5886                         if (err)
5887                                 printk(KERN_WARNING PFX "%s: Error %d "
5888                                        "adding alt mac %d\n",
5889                                        dev->name, err, index);
5890                         err = niu_enable_alt_mac(np, index, 1);
5891                         if (err)
5892                                 printk(KERN_WARNING PFX "%s: Error %d "
5893                                        "enabling alt mac %d\n",
5894                                        dev->name, err, index);
5895
5896                         index++;
5897                 }
5898         } else {
5899                 int alt_start;
5900                 if (np->flags & NIU_FLAGS_XMAC)
5901                         alt_start = 0;
5902                 else
5903                         alt_start = 1;
5904                 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
5905                         err = niu_enable_alt_mac(np, i, 0);
5906                         if (err)
5907                                 printk(KERN_WARNING PFX "%s: Error %d "
5908                                        "disabling alt mac %d\n",
5909                                        dev->name, err, i);
5910                 }
5911         }
5912         if (dev->flags & IFF_ALLMULTI) {
5913                 for (i = 0; i < 16; i++)
5914                         hash[i] = 0xffff;
5915         } else if (dev->mc_count > 0) {
5916                 for (addr = dev->mc_list; addr; addr = addr->next) {
5917                         u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
5918
5919                         crc >>= 24;
5920                         hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
5921                 }
5922         }
5923
5924         if (np->flags & NIU_FLAGS_MCAST)
5925                 niu_load_hash(np, hash);
5926
5927         niu_enable_rx_mac(np, 1);
5928         spin_unlock_irqrestore(&np->lock, flags);
5929 }
5930
5931 static int niu_set_mac_addr(struct net_device *dev, void *p)
5932 {
5933         struct niu *np = netdev_priv(dev);
5934         struct sockaddr *addr = p;
5935         unsigned long flags;
5936
5937         if (!is_valid_ether_addr(addr->sa_data))
5938                 return -EINVAL;
5939
5940         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
5941
5942         if (!netif_running(dev))
5943                 return 0;
5944
5945         spin_lock_irqsave(&np->lock, flags);
5946         niu_enable_rx_mac(np, 0);
5947         niu_set_primary_mac(np, dev->dev_addr);
5948         niu_enable_rx_mac(np, 1);
5949         spin_unlock_irqrestore(&np->lock, flags);
5950
5951         return 0;
5952 }
5953
5954 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5955 {
5956         return -EOPNOTSUPP;
5957 }
5958
5959 static void niu_netif_stop(struct niu *np)
5960 {
5961         np->dev->trans_start = jiffies; /* prevent tx timeout */
5962
5963         niu_disable_napi(np);
5964
5965         netif_tx_disable(np->dev);
5966 }
5967
5968 static void niu_netif_start(struct niu *np)
5969 {
5970         /* NOTE: unconditional netif_wake_queue is only appropriate
5971          * so long as all callers are assured to have free tx slots
5972          * (such as after niu_init_hw).
5973          */
5974         netif_wake_queue(np->dev);
5975
5976         niu_enable_napi(np);
5977
5978         niu_enable_interrupts(np, 1);
5979 }
5980
5981 static void niu_reset_task(struct work_struct *work)
5982 {
5983         struct niu *np = container_of(work, struct niu, reset_task);
5984         unsigned long flags;
5985         int err;
5986
5987         spin_lock_irqsave(&np->lock, flags);
5988         if (!netif_running(np->dev)) {
5989                 spin_unlock_irqrestore(&np->lock, flags);
5990                 return;
5991         }
5992
5993         spin_unlock_irqrestore(&np->lock, flags);
5994
5995         del_timer_sync(&np->timer);
5996
5997         niu_netif_stop(np);
5998
5999         spin_lock_irqsave(&np->lock, flags);
6000
6001         niu_stop_hw(np);
6002
6003         err = niu_init_hw(np);
6004         if (!err) {
6005                 np->timer.expires = jiffies + HZ;
6006                 add_timer(&np->timer);
6007                 niu_netif_start(np);
6008         }
6009
6010         spin_unlock_irqrestore(&np->lock, flags);
6011 }
6012
6013 static void niu_tx_timeout(struct net_device *dev)
6014 {
6015         struct niu *np = netdev_priv(dev);
6016
6017         dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6018                 dev->name);
6019
6020         schedule_work(&np->reset_task);
6021 }
6022
6023 static void niu_set_txd(struct tx_ring_info *rp, int index,
6024                         u64 mapping, u64 len, u64 mark,
6025                         u64 n_frags)
6026 {
6027         __le64 *desc = &rp->descr[index];
6028
6029         *desc = cpu_to_le64(mark |
6030                             (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6031                             (len << TX_DESC_TR_LEN_SHIFT) |
6032                             (mapping & TX_DESC_SAD));
6033 }
6034
6035 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6036                                 u64 pad_bytes, u64 len)
6037 {
6038         u16 eth_proto, eth_proto_inner;
6039         u64 csum_bits, l3off, ihl, ret;
6040         u8 ip_proto;
6041         int ipv6;
6042
6043         eth_proto = be16_to_cpu(ehdr->h_proto);
6044         eth_proto_inner = eth_proto;
6045         if (eth_proto == ETH_P_8021Q) {
6046                 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6047                 __be16 val = vp->h_vlan_encapsulated_proto;
6048
6049                 eth_proto_inner = be16_to_cpu(val);
6050         }
6051
6052         ipv6 = ihl = 0;
6053         switch (skb->protocol) {
6054         case __constant_htons(ETH_P_IP):
6055                 ip_proto = ip_hdr(skb)->protocol;
6056                 ihl = ip_hdr(skb)->ihl;
6057                 break;
6058         case __constant_htons(ETH_P_IPV6):
6059                 ip_proto = ipv6_hdr(skb)->nexthdr;
6060                 ihl = (40 >> 2);
6061                 ipv6 = 1;
6062                 break;
6063         default:
6064                 ip_proto = ihl = 0;
6065                 break;
6066         }
6067
6068         csum_bits = TXHDR_CSUM_NONE;
6069         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6070                 u64 start, stuff;
6071
6072                 csum_bits = (ip_proto == IPPROTO_TCP ?
6073                              TXHDR_CSUM_TCP :
6074                              (ip_proto == IPPROTO_UDP ?
6075                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6076
6077                 start = skb_transport_offset(skb) -
6078                         (pad_bytes + sizeof(struct tx_pkt_hdr));
6079                 stuff = start + skb->csum_offset;
6080
6081                 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6082                 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6083         }
6084
6085         l3off = skb_network_offset(skb) -
6086                 (pad_bytes + sizeof(struct tx_pkt_hdr));
6087
6088         ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6089                (len << TXHDR_LEN_SHIFT) |
6090                ((l3off / 2) << TXHDR_L3START_SHIFT) |
6091                (ihl << TXHDR_IHL_SHIFT) |
6092                ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6093                ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6094                (ipv6 ? TXHDR_IP_VER : 0) |
6095                csum_bits);
6096
6097         return ret;
6098 }
6099
6100 static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
6101 {
6102         return &np->tx_rings[0];
6103 }
6104
6105 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6106 {
6107         struct niu *np = netdev_priv(dev);
6108         unsigned long align, headroom;
6109         struct tx_ring_info *rp;
6110         struct tx_pkt_hdr *tp;
6111         unsigned int len, nfg;
6112         struct ethhdr *ehdr;
6113         int prod, i, tlen;
6114         u64 mapping, mrk;
6115
6116         rp = tx_ring_select(np, skb);
6117
6118         if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
6119                 netif_stop_queue(dev);
6120                 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6121                         "queue awake!\n", dev->name);
6122                 rp->tx_errors++;
6123                 return NETDEV_TX_BUSY;
6124         }
6125
6126         if (skb->len < ETH_ZLEN) {
6127                 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6128
6129                 if (skb_pad(skb, pad_bytes))
6130                         goto out;
6131                 skb_put(skb, pad_bytes);
6132         }
6133
6134         len = sizeof(struct tx_pkt_hdr) + 15;
6135         if (skb_headroom(skb) < len) {
6136                 struct sk_buff *skb_new;
6137
6138                 skb_new = skb_realloc_headroom(skb, len);
6139                 if (!skb_new) {
6140                         rp->tx_errors++;
6141                         goto out_drop;
6142                 }
6143                 kfree_skb(skb);
6144                 skb = skb_new;
6145         } else
6146                 skb_orphan(skb);
6147
6148         align = ((unsigned long) skb->data & (16 - 1));
6149         headroom = align + sizeof(struct tx_pkt_hdr);
6150
6151         ehdr = (struct ethhdr *) skb->data;
6152         tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6153
6154         len = skb->len - sizeof(struct tx_pkt_hdr);
6155         tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6156         tp->resv = 0;
6157
6158         len = skb_headlen(skb);
6159         mapping = np->ops->map_single(np->device, skb->data,
6160                                       len, DMA_TO_DEVICE);
6161
6162         prod = rp->prod;
6163
6164         rp->tx_buffs[prod].skb = skb;
6165         rp->tx_buffs[prod].mapping = mapping;
6166
6167         mrk = TX_DESC_SOP;
6168         if (++rp->mark_counter == rp->mark_freq) {
6169                 rp->mark_counter = 0;
6170                 mrk |= TX_DESC_MARK;
6171                 rp->mark_pending++;
6172         }
6173
6174         tlen = len;
6175         nfg = skb_shinfo(skb)->nr_frags;
6176         while (tlen > 0) {
6177                 tlen -= MAX_TX_DESC_LEN;
6178                 nfg++;
6179         }
6180
6181         while (len > 0) {
6182                 unsigned int this_len = len;
6183
6184                 if (this_len > MAX_TX_DESC_LEN)
6185                         this_len = MAX_TX_DESC_LEN;
6186
6187                 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6188                 mrk = nfg = 0;
6189
6190                 prod = NEXT_TX(rp, prod);
6191                 mapping += this_len;
6192                 len -= this_len;
6193         }
6194
6195         for (i = 0; i <  skb_shinfo(skb)->nr_frags; i++) {
6196                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6197
6198                 len = frag->size;
6199                 mapping = np->ops->map_page(np->device, frag->page,
6200                                             frag->page_offset, len,
6201                                             DMA_TO_DEVICE);
6202
6203                 rp->tx_buffs[prod].skb = NULL;
6204                 rp->tx_buffs[prod].mapping = mapping;
6205
6206                 niu_set_txd(rp, prod, mapping, len, 0, 0);
6207
6208                 prod = NEXT_TX(rp, prod);
6209         }
6210
6211         if (prod < rp->prod)
6212                 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6213         rp->prod = prod;
6214
6215         nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6216
6217         if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
6218                 netif_stop_queue(dev);
6219                 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
6220                         netif_wake_queue(dev);
6221         }
6222
6223         dev->trans_start = jiffies;
6224
6225 out:
6226         return NETDEV_TX_OK;
6227
6228 out_drop:
6229         rp->tx_errors++;
6230         kfree_skb(skb);
6231         goto out;
6232 }
6233
6234 static int niu_change_mtu(struct net_device *dev, int new_mtu)
6235 {
6236         struct niu *np = netdev_priv(dev);
6237         int err, orig_jumbo, new_jumbo;
6238
6239         if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6240                 return -EINVAL;
6241
6242         orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6243         new_jumbo = (new_mtu > ETH_DATA_LEN);
6244
6245         dev->mtu = new_mtu;
6246
6247         if (!netif_running(dev) ||
6248             (orig_jumbo == new_jumbo))
6249                 return 0;
6250
6251         niu_full_shutdown(np, dev);
6252
6253         niu_free_channels(np);
6254
6255         niu_enable_napi(np);
6256
6257         err = niu_alloc_channels(np);
6258         if (err)
6259                 return err;
6260
6261         spin_lock_irq(&np->lock);
6262
6263         err = niu_init_hw(np);
6264         if (!err) {
6265                 init_timer(&np->timer);
6266                 np->timer.expires = jiffies + HZ;
6267                 np->timer.data = (unsigned long) np;
6268                 np->timer.function = niu_timer;
6269
6270                 err = niu_enable_interrupts(np, 1);
6271                 if (err)
6272                         niu_stop_hw(np);
6273         }
6274
6275         spin_unlock_irq(&np->lock);
6276
6277         if (!err) {
6278                 netif_start_queue(dev);
6279                 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6280                         netif_carrier_on(dev);
6281
6282                 add_timer(&np->timer);
6283         }
6284
6285         return err;
6286 }
6287
6288 static void niu_get_drvinfo(struct net_device *dev,
6289                             struct ethtool_drvinfo *info)
6290 {
6291         struct niu *np = netdev_priv(dev);
6292         struct niu_vpd *vpd = &np->vpd;
6293
6294         strcpy(info->driver, DRV_MODULE_NAME);
6295         strcpy(info->version, DRV_MODULE_VERSION);
6296         sprintf(info->fw_version, "%d.%d",
6297                 vpd->fcode_major, vpd->fcode_minor);
6298         if (np->parent->plat_type != PLAT_TYPE_NIU)
6299                 strcpy(info->bus_info, pci_name(np->pdev));
6300 }
6301
6302 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6303 {
6304         struct niu *np = netdev_priv(dev);
6305         struct niu_link_config *lp;
6306
6307         lp = &np->link_config;
6308
6309         memset(cmd, 0, sizeof(*cmd));
6310         cmd->phy_address = np->phy_addr;
6311         cmd->supported = lp->supported;
6312         cmd->advertising = lp->advertising;
6313         cmd->autoneg = lp->autoneg;
6314         cmd->speed = lp->active_speed;
6315         cmd->duplex = lp->active_duplex;
6316
6317         return 0;
6318 }
6319
6320 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6321 {
6322         return -EINVAL;
6323 }
6324
6325 static u32 niu_get_msglevel(struct net_device *dev)
6326 {
6327         struct niu *np = netdev_priv(dev);
6328         return np->msg_enable;
6329 }
6330
6331 static void niu_set_msglevel(struct net_device *dev, u32 value)
6332 {
6333         struct niu *np = netdev_priv(dev);
6334         np->msg_enable = value;
6335 }
6336
6337 static int niu_get_eeprom_len(struct net_device *dev)
6338 {
6339         struct niu *np = netdev_priv(dev);
6340
6341         return np->eeprom_len;
6342 }
6343
6344 static int niu_get_eeprom(struct net_device *dev,
6345                           struct ethtool_eeprom *eeprom, u8 *data)
6346 {
6347         struct niu *np = netdev_priv(dev);
6348         u32 offset, len, val;
6349
6350         offset = eeprom->offset;
6351         len = eeprom->len;
6352
6353         if (offset + len < offset)
6354                 return -EINVAL;
6355         if (offset >= np->eeprom_len)
6356                 return -EINVAL;
6357         if (offset + len > np->eeprom_len)
6358                 len = eeprom->len = np->eeprom_len - offset;
6359
6360         if (offset & 3) {
6361                 u32 b_offset, b_count;
6362
6363                 b_offset = offset & 3;
6364                 b_count = 4 - b_offset;
6365                 if (b_count > len)
6366                         b_count = len;
6367
6368                 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6369                 memcpy(data, ((char *)&val) + b_offset, b_count);
6370                 data += b_count;
6371                 len -= b_count;
6372                 offset += b_count;
6373         }
6374         while (len >= 4) {
6375                 val = nr64(ESPC_NCR(offset / 4));
6376                 memcpy(data, &val, 4);
6377                 data += 4;
6378                 len -= 4;
6379                 offset += 4;
6380         }
6381         if (len) {
6382                 val = nr64(ESPC_NCR(offset / 4));
6383                 memcpy(data, &val, len);
6384         }
6385         return 0;
6386 }
6387
6388 static const struct {
6389         const char string[ETH_GSTRING_LEN];
6390 } niu_xmac_stat_keys[] = {
6391         { "tx_frames" },
6392         { "tx_bytes" },
6393         { "tx_fifo_errors" },
6394         { "tx_overflow_errors" },
6395         { "tx_max_pkt_size_errors" },
6396         { "tx_underflow_errors" },
6397         { "rx_local_faults" },
6398         { "rx_remote_faults" },
6399         { "rx_link_faults" },
6400         { "rx_align_errors" },
6401         { "rx_frags" },
6402         { "rx_mcasts" },
6403         { "rx_bcasts" },
6404         { "rx_hist_cnt1" },
6405         { "rx_hist_cnt2" },
6406         { "rx_hist_cnt3" },
6407         { "rx_hist_cnt4" },
6408         { "rx_hist_cnt5" },
6409         { "rx_hist_cnt6" },
6410         { "rx_hist_cnt7" },
6411         { "rx_octets" },
6412         { "rx_code_violations" },
6413         { "rx_len_errors" },
6414         { "rx_crc_errors" },
6415         { "rx_underflows" },
6416         { "rx_overflows" },
6417         { "pause_off_state" },
6418         { "pause_on_state" },
6419         { "pause_received" },
6420 };
6421
6422 #define NUM_XMAC_STAT_KEYS      ARRAY_SIZE(niu_xmac_stat_keys)
6423
6424 static const struct {
6425         const char string[ETH_GSTRING_LEN];
6426 } niu_bmac_stat_keys[] = {
6427         { "tx_underflow_errors" },
6428         { "tx_max_pkt_size_errors" },
6429         { "tx_bytes" },
6430         { "tx_frames" },
6431         { "rx_overflows" },
6432         { "rx_frames" },
6433         { "rx_align_errors" },
6434         { "rx_crc_errors" },
6435         { "rx_len_errors" },
6436         { "pause_off_state" },
6437         { "pause_on_state" },
6438         { "pause_received" },
6439 };
6440
6441 #define NUM_BMAC_STAT_KEYS      ARRAY_SIZE(niu_bmac_stat_keys)
6442
6443 static const struct {
6444         const char string[ETH_GSTRING_LEN];
6445 } niu_rxchan_stat_keys[] = {
6446         { "rx_channel" },
6447         { "rx_packets" },
6448         { "rx_bytes" },
6449         { "rx_dropped" },
6450         { "rx_errors" },
6451 };
6452
6453 #define NUM_RXCHAN_STAT_KEYS    ARRAY_SIZE(niu_rxchan_stat_keys)
6454
6455 static const struct {
6456         const char string[ETH_GSTRING_LEN];
6457 } niu_txchan_stat_keys[] = {
6458         { "tx_channel" },
6459         { "tx_packets" },
6460         { "tx_bytes" },
6461         { "tx_errors" },
6462 };
6463
6464 #define NUM_TXCHAN_STAT_KEYS    ARRAY_SIZE(niu_txchan_stat_keys)
6465
6466 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
6467 {
6468         struct niu *np = netdev_priv(dev);
6469         int i;
6470
6471         if (stringset != ETH_SS_STATS)
6472                 return;
6473
6474         if (np->flags & NIU_FLAGS_XMAC) {
6475                 memcpy(data, niu_xmac_stat_keys,
6476                        sizeof(niu_xmac_stat_keys));
6477                 data += sizeof(niu_xmac_stat_keys);
6478         } else {
6479                 memcpy(data, niu_bmac_stat_keys,
6480                        sizeof(niu_bmac_stat_keys));
6481                 data += sizeof(niu_bmac_stat_keys);
6482         }
6483         for (i = 0; i < np->num_rx_rings; i++) {
6484                 memcpy(data, niu_rxchan_stat_keys,
6485                        sizeof(niu_rxchan_stat_keys));
6486                 data += sizeof(niu_rxchan_stat_keys);
6487         }
6488         for (i = 0; i < np->num_tx_rings; i++) {
6489                 memcpy(data, niu_txchan_stat_keys,
6490                        sizeof(niu_txchan_stat_keys));
6491                 data += sizeof(niu_txchan_stat_keys);
6492         }
6493 }
6494
6495 static int niu_get_stats_count(struct net_device *dev)
6496 {
6497         struct niu *np = netdev_priv(dev);
6498
6499         return ((np->flags & NIU_FLAGS_XMAC ?
6500                  NUM_XMAC_STAT_KEYS :
6501                  NUM_BMAC_STAT_KEYS) +
6502                 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
6503                 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
6504 }
6505
6506 static void niu_get_ethtool_stats(struct net_device *dev,
6507                                   struct ethtool_stats *stats, u64 *data)
6508 {
6509         struct niu *np = netdev_priv(dev);
6510         int i;
6511
6512         niu_sync_mac_stats(np);
6513         if (np->flags & NIU_FLAGS_XMAC) {
6514                 memcpy(data, &np->mac_stats.xmac,
6515                        sizeof(struct niu_xmac_stats));
6516                 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
6517         } else {
6518                 memcpy(data, &np->mac_stats.bmac,
6519                        sizeof(struct niu_bmac_stats));
6520                 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
6521         }
6522         for (i = 0; i < np->num_rx_rings; i++) {
6523                 struct rx_ring_info *rp = &np->rx_rings[i];
6524
6525                 data[0] = rp->rx_channel;
6526                 data[1] = rp->rx_packets;
6527                 data[2] = rp->rx_bytes;
6528                 data[3] = rp->rx_dropped;
6529                 data[4] = rp->rx_errors;
6530                 data += 5;
6531         }
6532         for (i = 0; i < np->num_tx_rings; i++) {
6533                 struct tx_ring_info *rp = &np->tx_rings[i];
6534
6535                 data[0] = rp->tx_channel;
6536                 data[1] = rp->tx_packets;
6537                 data[2] = rp->tx_bytes;
6538                 data[3] = rp->tx_errors;
6539                 data += 4;
6540         }
6541 }
6542
6543 static u64 niu_led_state_save(struct niu *np)
6544 {
6545         if (np->flags & NIU_FLAGS_XMAC)
6546                 return nr64_mac(XMAC_CONFIG);
6547         else
6548                 return nr64_mac(BMAC_XIF_CONFIG);
6549 }
6550
6551 static void niu_led_state_restore(struct niu *np, u64 val)
6552 {
6553         if (np->flags & NIU_FLAGS_XMAC)
6554                 nw64_mac(XMAC_CONFIG, val);
6555         else
6556                 nw64_mac(BMAC_XIF_CONFIG, val);
6557 }
6558
6559 static void niu_force_led(struct niu *np, int on)
6560 {
6561         u64 val, reg, bit;
6562
6563         if (np->flags & NIU_FLAGS_XMAC) {
6564                 reg = XMAC_CONFIG;
6565                 bit = XMAC_CONFIG_FORCE_LED_ON;
6566         } else {
6567                 reg = BMAC_XIF_CONFIG;
6568                 bit = BMAC_XIF_CONFIG_LINK_LED;
6569         }
6570
6571         val = nr64_mac(reg);
6572         if (on)
6573                 val |= bit;
6574         else
6575                 val &= ~bit;
6576         nw64_mac(reg, val);
6577 }
6578
6579 static int niu_phys_id(struct net_device *dev, u32 data)
6580 {
6581         struct niu *np = netdev_priv(dev);
6582         u64 orig_led_state;
6583         int i;
6584
6585         if (!netif_running(dev))
6586                 return -EAGAIN;
6587
6588         if (data == 0)
6589                 data = 2;
6590
6591         orig_led_state = niu_led_state_save(np);
6592         for (i = 0; i < (data * 2); i++) {
6593                 int on = ((i % 2) == 0);
6594
6595                 niu_force_led(np, on);
6596
6597                 if (msleep_interruptible(500))
6598                         break;
6599         }
6600         niu_led_state_restore(np, orig_led_state);
6601
6602         return 0;
6603 }
6604
6605 static const struct ethtool_ops niu_ethtool_ops = {
6606         .get_drvinfo            = niu_get_drvinfo,
6607         .get_link               = ethtool_op_get_link,
6608         .get_msglevel           = niu_get_msglevel,
6609         .set_msglevel           = niu_set_msglevel,
6610         .get_eeprom_len         = niu_get_eeprom_len,
6611         .get_eeprom             = niu_get_eeprom,
6612         .get_settings           = niu_get_settings,
6613         .set_settings           = niu_set_settings,
6614         .get_strings            = niu_get_strings,
6615         .get_stats_count        = niu_get_stats_count,
6616         .get_ethtool_stats      = niu_get_ethtool_stats,
6617         .phys_id                = niu_phys_id,
6618 };
6619
6620 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
6621                               int ldg, int ldn)
6622 {
6623         if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
6624                 return -EINVAL;
6625         if (ldn < 0 || ldn > LDN_MAX)
6626                 return -EINVAL;
6627
6628         parent->ldg_map[ldn] = ldg;
6629
6630         if (np->parent->plat_type == PLAT_TYPE_NIU) {
6631                 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
6632                  * the firmware, and we're not supposed to change them.
6633                  * Validate the mapping, because if it's wrong we probably
6634                  * won't get any interrupts and that's painful to debug.
6635                  */
6636                 if (nr64(LDG_NUM(ldn)) != ldg) {
6637                         dev_err(np->device, PFX "Port %u, mis-matched "
6638                                 "LDG assignment "
6639                                 "for ldn %d, should be %d is %llu\n",
6640                                 np->port, ldn, ldg,
6641                                 (unsigned long long) nr64(LDG_NUM(ldn)));
6642                         return -EINVAL;
6643                 }
6644         } else
6645                 nw64(LDG_NUM(ldn), ldg);
6646
6647         return 0;
6648 }
6649
6650 static int niu_set_ldg_timer_res(struct niu *np, int res)
6651 {
6652         if (res < 0 || res > LDG_TIMER_RES_VAL)
6653                 return -EINVAL;
6654
6655
6656         nw64(LDG_TIMER_RES, res);
6657
6658         return 0;
6659 }
6660
6661 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
6662 {
6663         if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
6664             (func < 0 || func > 3) ||
6665             (vector < 0 || vector > 0x1f))
6666                 return -EINVAL;
6667
6668         nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
6669
6670         return 0;
6671 }
6672
6673 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
6674 {
6675         u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
6676                                  (addr << ESPC_PIO_STAT_ADDR_SHIFT));
6677         int limit;
6678
6679         if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
6680                 return -EINVAL;
6681
6682         frame = frame_base;
6683         nw64(ESPC_PIO_STAT, frame);
6684         limit = 64;
6685         do {
6686                 udelay(5);
6687                 frame = nr64(ESPC_PIO_STAT);
6688                 if (frame & ESPC_PIO_STAT_READ_END)
6689                         break;
6690         } while (limit--);
6691         if (!(frame & ESPC_PIO_STAT_READ_END)) {
6692                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
6693                         (unsigned long long) frame);
6694                 return -ENODEV;
6695         }
6696
6697         frame = frame_base;
6698         nw64(ESPC_PIO_STAT, frame);
6699         limit = 64;
6700         do {
6701                 udelay(5);
6702                 frame = nr64(ESPC_PIO_STAT);
6703                 if (frame & ESPC_PIO_STAT_READ_END)
6704                         break;
6705         } while (limit--);
6706         if (!(frame & ESPC_PIO_STAT_READ_END)) {
6707                 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
6708                         (unsigned long long) frame);
6709                 return -ENODEV;
6710         }
6711
6712         frame = nr64(ESPC_PIO_STAT);
6713         return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
6714 }
6715
6716 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
6717 {
6718         int err = niu_pci_eeprom_read(np, off);
6719         u16 val;
6720
6721         if (err < 0)
6722                 return err;
6723         val = (err << 8);
6724         err = niu_pci_eeprom_read(np, off + 1);
6725         if (err < 0)
6726                 return err;
6727         val |= (err & 0xff);
6728
6729         return val;
6730 }
6731
6732 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
6733 {
6734         int err = niu_pci_eeprom_read(np, off);
6735         u16 val;
6736
6737         if (err < 0)
6738                 return err;
6739
6740         val = (err & 0xff);
6741         err = niu_pci_eeprom_read(np, off + 1);
6742         if (err < 0)
6743                 return err;
6744
6745         val |= (err & 0xff) << 8;
6746
6747         return val;
6748 }
6749
6750 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
6751                                               u32 off,
6752                                               char *namebuf,
6753                                               int namebuf_len)
6754 {
6755         int i;
6756
6757         for (i = 0; i < namebuf_len; i++) {
6758                 int err = niu_pci_eeprom_read(np, off + i);
6759                 if (err < 0)
6760                         return err;
6761                 *namebuf++ = err;
6762                 if (!err)
6763                         break;
6764         }
6765         if (i >= namebuf_len)
6766                 return -EINVAL;
6767
6768         return i + 1;
6769 }
6770
6771 static void __devinit niu_vpd_parse_version(struct niu *np)
6772 {
6773         struct niu_vpd *vpd = &np->vpd;
6774         int len = strlen(vpd->version) + 1;
6775         const char *s = vpd->version;
6776         int i;
6777
6778         for (i = 0; i < len - 5; i++) {
6779                 if (!strncmp(s + i, "FCode ", 5))
6780                         break;
6781         }
6782         if (i >= len - 5)
6783                 return;
6784
6785         s += i + 5;
6786         sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
6787
6788         niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
6789                vpd->fcode_major, vpd->fcode_minor);
6790         if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
6791             (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
6792              vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
6793                 np->flags |= NIU_FLAGS_VPD_VALID;
6794 }
6795
6796 /* ESPC_PIO_EN_ENABLE must be set */
6797 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
6798                                             u32 start, u32 end)
6799 {
6800         unsigned int found_mask = 0;
6801 #define FOUND_MASK_MODEL        0x00000001
6802 #define FOUND_MASK_BMODEL       0x00000002
6803 #define FOUND_MASK_VERS         0x00000004
6804 #define FOUND_MASK_MAC          0x00000008
6805 #define FOUND_MASK_NMAC         0x00000010
6806 #define FOUND_MASK_PHY          0x00000020
6807 #define FOUND_MASK_ALL          0x0000003f
6808
6809         niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
6810                start, end);
6811         while (start < end) {
6812                 int len, err, instance, type, prop_len;
6813                 char namebuf[64];
6814                 u8 *prop_buf;
6815                 int max_len;
6816
6817                 if (found_mask == FOUND_MASK_ALL) {
6818                         niu_vpd_parse_version(np);
6819                         return 1;
6820                 }
6821
6822                 err = niu_pci_eeprom_read(np, start + 2);
6823                 if (err < 0)
6824                         return err;
6825                 len = err;
6826                 start += 3;
6827
6828                 instance = niu_pci_eeprom_read(np, start);
6829                 type = niu_pci_eeprom_read(np, start + 3);
6830                 prop_len = niu_pci_eeprom_read(np, start + 4);
6831                 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
6832                 if (err < 0)
6833                         return err;
6834
6835                 prop_buf = NULL;
6836                 max_len = 0;
6837                 if (!strcmp(namebuf, "model")) {
6838                         prop_buf = np->vpd.model;
6839                         max_len = NIU_VPD_MODEL_MAX;
6840                         found_mask |= FOUND_MASK_MODEL;
6841                 } else if (!strcmp(namebuf, "board-model")) {
6842                         prop_buf = np->vpd.board_model;
6843                         max_len = NIU_VPD_BD_MODEL_MAX;
6844                         found_mask |= FOUND_MASK_BMODEL;
6845                 } else if (!strcmp(namebuf, "version")) {
6846                         prop_buf = np->vpd.version;
6847                         max_len = NIU_VPD_VERSION_MAX;
6848                         found_mask |= FOUND_MASK_VERS;
6849                 } else if (!strcmp(namebuf, "local-mac-address")) {
6850                         prop_buf = np->vpd.local_mac;
6851                         max_len = ETH_ALEN;
6852                         found_mask |= FOUND_MASK_MAC;
6853                 } else if (!strcmp(namebuf, "num-mac-addresses")) {
6854                         prop_buf = &np->vpd.mac_num;
6855                         max_len = 1;
6856                         found_mask |= FOUND_MASK_NMAC;
6857                 } else if (!strcmp(namebuf, "phy-type")) {
6858                         prop_buf = np->vpd.phy_type;
6859                         max_len = NIU_VPD_PHY_TYPE_MAX;
6860                         found_mask |= FOUND_MASK_PHY;
6861                 }
6862
6863                 if (max_len && prop_len > max_len) {
6864                         dev_err(np->device, PFX "Property '%s' length (%d) is "
6865                                 "too long.\n", namebuf, prop_len);
6866                         return -EINVAL;
6867                 }
6868
6869                 if (prop_buf) {
6870                         u32 off = start + 5 + err;
6871                         int i;
6872
6873                         niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
6874                                "len[%d]\n", namebuf, prop_len);
6875                         for (i = 0; i < prop_len; i++)
6876                                 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
6877                 }
6878
6879                 start += len;
6880         }
6881
6882         return 0;
6883 }
6884
6885 /* ESPC_PIO_EN_ENABLE must be set */
6886 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
6887 {
6888         u32 offset;
6889         int err;
6890
6891         err = niu_pci_eeprom_read16_swp(np, start + 1);
6892         if (err < 0)
6893                 return;
6894
6895         offset = err + 3;
6896
6897         while (start + offset < ESPC_EEPROM_SIZE) {
6898                 u32 here = start + offset;
6899                 u32 end;
6900
6901                 err = niu_pci_eeprom_read(np, here);
6902                 if (err != 0x90)
6903                         return;
6904
6905                 err = niu_pci_eeprom_read16_swp(np, here + 1);
6906                 if (err < 0)
6907                         return;
6908
6909                 here = start + offset + 3;
6910                 end = start + offset + err;
6911
6912                 offset += err;
6913
6914                 err = niu_pci_vpd_scan_props(np, here, end);
6915                 if (err < 0 || err == 1)
6916                         return;
6917         }
6918 }
6919
6920 /* ESPC_PIO_EN_ENABLE must be set */
6921 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
6922 {
6923         u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
6924         int err;
6925
6926         while (start < end) {
6927                 ret = start;
6928
6929                 /* ROM header signature?  */
6930                 err = niu_pci_eeprom_read16(np, start +  0);
6931                 if (err != 0x55aa)
6932                         return 0;
6933
6934                 /* Apply offset to PCI data structure.  */
6935                 err = niu_pci_eeprom_read16(np, start + 23);
6936                 if (err < 0)
6937                         return 0;
6938                 start += err;
6939
6940                 /* Check for "PCIR" signature.  */
6941                 err = niu_pci_eeprom_read16(np, start +  0);
6942                 if (err != 0x5043)
6943                         return 0;
6944                 err = niu_pci_eeprom_read16(np, start +  2);
6945                 if (err != 0x4952)
6946                         return 0;
6947
6948                 /* Check for OBP image type.  */
6949                 err = niu_pci_eeprom_read(np, start + 20);
6950                 if (err < 0)
6951                         return 0;
6952                 if (err != 0x01) {
6953                         err = niu_pci_eeprom_read(np, ret + 2);
6954                         if (err < 0)
6955                                 return 0;
6956
6957                         start = ret + (err * 512);
6958                         continue;
6959                 }
6960
6961                 err = niu_pci_eeprom_read16_swp(np, start + 8);
6962                 if (err < 0)
6963                         return err;
6964                 ret += err;
6965
6966                 err = niu_pci_eeprom_read(np, ret + 0);
6967                 if (err != 0x82)
6968                         return 0;
6969
6970                 return ret;
6971         }
6972
6973         return 0;
6974 }
6975
6976 static int __devinit niu_phy_type_prop_decode(struct niu *np,
6977                                               const char *phy_prop)
6978 {
6979         if (!strcmp(phy_prop, "mif")) {
6980                 /* 1G copper, MII */
6981                 np->flags &= ~(NIU_FLAGS_FIBER |
6982                                NIU_FLAGS_10G);
6983                 np->mac_xcvr = MAC_XCVR_MII;
6984         } else if (!strcmp(phy_prop, "xgf")) {
6985                 /* 10G fiber, XPCS */
6986                 np->flags |= (NIU_FLAGS_10G |
6987                               NIU_FLAGS_FIBER);
6988                 np->mac_xcvr = MAC_XCVR_XPCS;
6989         } else if (!strcmp(phy_prop, "pcs")) {
6990                 /* 1G fiber, PCS */
6991                 np->flags &= ~NIU_FLAGS_10G;
6992                 np->flags |= NIU_FLAGS_FIBER;
6993                 np->mac_xcvr = MAC_XCVR_PCS;
6994         } else if (!strcmp(phy_prop, "xgc")) {
6995                 /* 10G copper, XPCS */
6996                 np->flags |= NIU_FLAGS_10G;
6997                 np->flags &= ~NIU_FLAGS_FIBER;
6998                 np->mac_xcvr = MAC_XCVR_XPCS;
6999         } else {
7000                 return -EINVAL;
7001         }
7002         return 0;
7003 }
7004
7005 static int niu_pci_vpd_get_nports(struct niu *np)
7006 {
7007         int ports = 0;
7008
7009         if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
7010             (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
7011             (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
7012             (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
7013             (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7014                 ports = 4;
7015         } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
7016                    (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
7017                    (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
7018                    (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7019                 ports = 2;
7020         }
7021
7022         return ports;
7023 }
7024
7025 static void __devinit niu_pci_vpd_validate(struct niu *np)
7026 {
7027         struct net_device *dev = np->dev;
7028         struct niu_vpd *vpd = &np->vpd;
7029         u8 val8;
7030
7031         if (!is_valid_ether_addr(&vpd->local_mac[0])) {
7032                 dev_err(np->device, PFX "VPD MAC invalid, "
7033                         "falling back to SPROM.\n");
7034
7035                 np->flags &= ~NIU_FLAGS_VPD_VALID;
7036                 return;
7037         }
7038
7039         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7040             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
7041                 np->flags |= NIU_FLAGS_10G;
7042                 np->flags &= ~NIU_FLAGS_FIBER;
7043                 np->flags |= NIU_FLAGS_XCVR_SERDES;
7044                 np->mac_xcvr = MAC_XCVR_PCS;
7045                 if (np->port > 1) {
7046                         np->flags |= NIU_FLAGS_FIBER;
7047                         np->flags &= ~NIU_FLAGS_10G;
7048                 }
7049                 if (np->flags & NIU_FLAGS_10G)
7050                          np->mac_xcvr = MAC_XCVR_XPCS;
7051         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
7052                 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
7053                               NIU_FLAGS_HOTPLUG_PHY);
7054         } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7055                 dev_err(np->device, PFX "Illegal phy string [%s].\n",
7056                         np->vpd.phy_type);
7057                 dev_err(np->device, PFX "Falling back to SPROM.\n");
7058                 np->flags &= ~NIU_FLAGS_VPD_VALID;
7059                 return;
7060         }
7061
7062         memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
7063
7064         val8 = dev->perm_addr[5];
7065         dev->perm_addr[5] += np->port;
7066         if (dev->perm_addr[5] < val8)
7067                 dev->perm_addr[4]++;
7068
7069         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7070 }
7071
7072 static int __devinit niu_pci_probe_sprom(struct niu *np)
7073 {
7074         struct net_device *dev = np->dev;
7075         int len, i;
7076         u64 val, sum;
7077         u8 val8;
7078
7079         val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
7080         val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
7081         len = val / 4;
7082
7083         np->eeprom_len = len;
7084
7085         niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
7086
7087         sum = 0;
7088         for (i = 0; i < len; i++) {
7089                 val = nr64(ESPC_NCR(i));
7090                 sum += (val >>  0) & 0xff;
7091                 sum += (val >>  8) & 0xff;
7092                 sum += (val >> 16) & 0xff;
7093                 sum += (val >> 24) & 0xff;
7094         }
7095         niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
7096         if ((sum & 0xff) != 0xab) {
7097                 dev_err(np->device, PFX "Bad SPROM checksum "
7098                         "(%x, should be 0xab)\n", (int) (sum & 0xff));
7099                 return -EINVAL;
7100         }
7101
7102         val = nr64(ESPC_PHY_TYPE);
7103         switch (np->port) {
7104         case 0:
7105                 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
7106                         ESPC_PHY_TYPE_PORT0_SHIFT;
7107                 break;
7108         case 1:
7109                 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
7110                         ESPC_PHY_TYPE_PORT1_SHIFT;
7111                 break;
7112         case 2:
7113                 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
7114                         ESPC_PHY_TYPE_PORT2_SHIFT;
7115                 break;
7116         case 3:
7117                 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
7118                         ESPC_PHY_TYPE_PORT3_SHIFT;
7119                 break;
7120         default:
7121                 dev_err(np->device, PFX "Bogus port number %u\n",
7122                         np->port);
7123                 return -EINVAL;
7124         }
7125         niudbg(PROBE, "SPROM: PHY type %x\n", val8);
7126
7127         switch (val8) {
7128         case ESPC_PHY_TYPE_1G_COPPER:
7129                 /* 1G copper, MII */
7130                 np->flags &= ~(NIU_FLAGS_FIBER |
7131                                NIU_FLAGS_10G);
7132                 np->mac_xcvr = MAC_XCVR_MII;
7133                 break;
7134
7135         case ESPC_PHY_TYPE_1G_FIBER:
7136                 /* 1G fiber, PCS */
7137                 np->flags &= ~NIU_FLAGS_10G;
7138                 np->flags |= NIU_FLAGS_FIBER;
7139                 np->mac_xcvr = MAC_XCVR_PCS;
7140                 break;
7141
7142         case ESPC_PHY_TYPE_10G_COPPER:
7143                 /* 10G copper, XPCS */
7144                 np->flags |= NIU_FLAGS_10G;
7145                 np->flags &= ~NIU_FLAGS_FIBER;
7146                 np->mac_xcvr = MAC_XCVR_XPCS;
7147                 break;
7148
7149         case ESPC_PHY_TYPE_10G_FIBER:
7150                 /* 10G fiber, XPCS */
7151                 np->flags |= (NIU_FLAGS_10G |
7152                               NIU_FLAGS_FIBER);
7153                 np->mac_xcvr = MAC_XCVR_XPCS;
7154                 break;
7155
7156         default:
7157                 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
7158                 return -EINVAL;
7159         }
7160
7161         val = nr64(ESPC_MAC_ADDR0);
7162         niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
7163                (unsigned long long) val);
7164         dev->perm_addr[0] = (val >>  0) & 0xff;
7165         dev->perm_addr[1] = (val >>  8) & 0xff;
7166         dev->perm_addr[2] = (val >> 16) & 0xff;
7167         dev->perm_addr[3] = (val >> 24) & 0xff;
7168
7169         val = nr64(ESPC_MAC_ADDR1);
7170         niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
7171                (unsigned long long) val);
7172         dev->perm_addr[4] = (val >>  0) & 0xff;
7173         dev->perm_addr[5] = (val >>  8) & 0xff;
7174
7175         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7176                 dev_err(np->device, PFX "SPROM MAC address invalid\n");
7177                 dev_err(np->device, PFX "[ \n");
7178                 for (i = 0; i < 6; i++)
7179                         printk("%02x ", dev->perm_addr[i]);
7180                 printk("]\n");
7181                 return -EINVAL;
7182         }
7183
7184         val8 = dev->perm_addr[5];
7185         dev->perm_addr[5] += np->port;
7186         if (dev->perm_addr[5] < val8)
7187                 dev->perm_addr[4]++;
7188
7189         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7190
7191         val = nr64(ESPC_MOD_STR_LEN);
7192         niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
7193                (unsigned long long) val);
7194         if (val >= 8 * 4)
7195                 return -EINVAL;
7196
7197         for (i = 0; i < val; i += 4) {
7198                 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
7199
7200                 np->vpd.model[i + 3] = (tmp >>  0) & 0xff;
7201                 np->vpd.model[i + 2] = (tmp >>  8) & 0xff;
7202                 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
7203                 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
7204         }
7205         np->vpd.model[val] = '\0';
7206
7207         val = nr64(ESPC_BD_MOD_STR_LEN);
7208         niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7209                (unsigned long long) val);
7210         if (val >= 4 * 4)
7211                 return -EINVAL;
7212
7213         for (i = 0; i < val; i += 4) {
7214                 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
7215
7216                 np->vpd.board_model[i + 3] = (tmp >>  0) & 0xff;
7217                 np->vpd.board_model[i + 2] = (tmp >>  8) & 0xff;
7218                 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
7219                 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
7220         }
7221         np->vpd.board_model[val] = '\0';
7222
7223         np->vpd.mac_num =
7224                 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7225         niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7226                np->vpd.mac_num);
7227
7228         return 0;
7229 }
7230
7231 static int __devinit niu_get_and_validate_port(struct niu *np)
7232 {
7233         struct niu_parent *parent = np->parent;
7234
7235         if (np->port <= 1)
7236                 np->flags |= NIU_FLAGS_XMAC;
7237
7238         if (!parent->num_ports) {
7239                 if (parent->plat_type == PLAT_TYPE_NIU) {
7240                         parent->num_ports = 2;
7241                 } else {
7242                         parent->num_ports = niu_pci_vpd_get_nports(np);
7243                         if (!parent->num_ports) {
7244                                 /* Fall back to SPROM as last resort.
7245                                  * This will fail on most cards.
7246                                  */
7247                                 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7248                                         ESPC_NUM_PORTS_MACS_VAL;
7249
7250                                 /* All of the current probing methods fail on
7251                                  * Maramba on-board parts.
7252                                  */
7253                                 if (!parent->num_ports)
7254                                         parent->num_ports = 4;
7255                         }
7256                 }
7257         }
7258
7259         niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7260                np->port, parent->num_ports);
7261         if (np->port >= parent->num_ports)
7262                 return -ENODEV;
7263
7264         return 0;
7265 }
7266
7267 static int __devinit phy_record(struct niu_parent *parent,
7268                                 struct phy_probe_info *p,
7269                                 int dev_id_1, int dev_id_2, u8 phy_port,
7270                                 int type)
7271 {
7272         u32 id = (dev_id_1 << 16) | dev_id_2;
7273         u8 idx;
7274
7275         if (dev_id_1 < 0 || dev_id_2 < 0)
7276                 return 0;
7277         if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
7278                 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
7279                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
7280                     ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
7281                         return 0;
7282         } else {
7283                 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7284                         return 0;
7285         }
7286
7287         pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7288                 parent->index, id,
7289                 (type == PHY_TYPE_PMA_PMD ?
7290                  "PMA/PMD" :
7291                  (type == PHY_TYPE_PCS ?
7292                   "PCS" : "MII")),
7293                 phy_port);
7294
7295         if (p->cur[type] >= NIU_MAX_PORTS) {
7296                 printk(KERN_ERR PFX "Too many PHY ports.\n");
7297                 return -EINVAL;
7298         }
7299         idx = p->cur[type];
7300         p->phy_id[type][idx] = id;
7301         p->phy_port[type][idx] = phy_port;
7302         p->cur[type] = idx + 1;
7303         return 0;
7304 }
7305
7306 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7307 {
7308         int i;
7309
7310         for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
7311                 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
7312                         return 1;
7313         }
7314         for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
7315                 if (p->phy_port[PHY_TYPE_PCS][i] == port)
7316                         return 1;
7317         }
7318
7319         return 0;
7320 }
7321
7322 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
7323 {
7324         int port, cnt;
7325
7326         cnt = 0;
7327         *lowest = 32;
7328         for (port = 8; port < 32; port++) {
7329                 if (port_has_10g(p, port)) {
7330                         if (!cnt)
7331                                 *lowest = port;
7332                         cnt++;
7333                 }
7334         }
7335
7336         return cnt;
7337 }
7338
7339 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
7340 {
7341         *lowest = 32;
7342         if (p->cur[PHY_TYPE_MII])
7343                 *lowest = p->phy_port[PHY_TYPE_MII][0];
7344
7345         return p->cur[PHY_TYPE_MII];
7346 }
7347
7348 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
7349 {
7350         int num_ports = parent->num_ports;
7351         int i;
7352
7353         for (i = 0; i < num_ports; i++) {
7354                 parent->rxchan_per_port[i] = (16 / num_ports);
7355                 parent->txchan_per_port[i] = (16 / num_ports);
7356
7357                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7358                         "[%u TX chans]\n",
7359                         parent->index, i,
7360                         parent->rxchan_per_port[i],
7361                         parent->txchan_per_port[i]);
7362         }
7363 }
7364
7365 static void __devinit niu_divide_channels(struct niu_parent *parent,
7366                                           int num_10g, int num_1g)
7367 {
7368         int num_ports = parent->num_ports;
7369         int rx_chans_per_10g, rx_chans_per_1g;
7370         int tx_chans_per_10g, tx_chans_per_1g;
7371         int i, tot_rx, tot_tx;
7372
7373         if (!num_10g || !num_1g) {
7374                 rx_chans_per_10g = rx_chans_per_1g =
7375                         (NIU_NUM_RXCHAN / num_ports);
7376                 tx_chans_per_10g = tx_chans_per_1g =
7377                         (NIU_NUM_TXCHAN / num_ports);
7378         } else {
7379                 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
7380                 rx_chans_per_10g = (NIU_NUM_RXCHAN -
7381                                     (rx_chans_per_1g * num_1g)) /
7382                         num_10g;
7383
7384                 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
7385                 tx_chans_per_10g = (NIU_NUM_TXCHAN -
7386                                     (tx_chans_per_1g * num_1g)) /
7387                         num_10g;
7388         }
7389
7390         tot_rx = tot_tx = 0;
7391         for (i = 0; i < num_ports; i++) {
7392                 int type = phy_decode(parent->port_phy, i);
7393
7394                 if (type == PORT_TYPE_10G) {
7395                         parent->rxchan_per_port[i] = rx_chans_per_10g;
7396                         parent->txchan_per_port[i] = tx_chans_per_10g;
7397                 } else {
7398                         parent->rxchan_per_port[i] = rx_chans_per_1g;
7399                         parent->txchan_per_port[i] = tx_chans_per_1g;
7400                 }
7401                 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7402                         "[%u TX chans]\n",
7403                         parent->index, i,
7404                         parent->rxchan_per_port[i],
7405                         parent->txchan_per_port[i]);
7406                 tot_rx += parent->rxchan_per_port[i];
7407                 tot_tx += parent->txchan_per_port[i];
7408         }
7409
7410         if (tot_rx > NIU_NUM_RXCHAN) {
7411                 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
7412                        "resetting to one per port.\n",
7413                        parent->index, tot_rx);
7414                 for (i = 0; i < num_ports; i++)
7415                         parent->rxchan_per_port[i] = 1;
7416         }
7417         if (tot_tx > NIU_NUM_TXCHAN) {
7418                 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
7419                        "resetting to one per port.\n",
7420                        parent->index, tot_tx);
7421                 for (i = 0; i < num_ports; i++)
7422                         parent->txchan_per_port[i] = 1;
7423         }
7424         if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
7425                 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
7426                        "RX[%d] TX[%d]\n",
7427                        parent->index, tot_rx, tot_tx);
7428         }
7429 }
7430
7431 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
7432                                             int num_10g, int num_1g)
7433 {
7434         int i, num_ports = parent->num_ports;
7435         int rdc_group, rdc_groups_per_port;
7436         int rdc_channel_base;
7437
7438         rdc_group = 0;
7439         rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
7440
7441         rdc_channel_base = 0;
7442
7443         for (i = 0; i < num_ports; i++) {
7444                 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
7445                 int grp, num_channels = parent->rxchan_per_port[i];
7446                 int this_channel_offset;
7447
7448                 tp->first_table_num = rdc_group;
7449                 tp->num_tables = rdc_groups_per_port;
7450                 this_channel_offset = 0;
7451                 for (grp = 0; grp < tp->num_tables; grp++) {
7452                         struct rdc_table *rt = &tp->tables[grp];
7453                         int slot;
7454
7455                         pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
7456                                 parent->index, i, tp->first_table_num + grp);
7457                         for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
7458                                 rt->rxdma_channel[slot] =
7459                                         rdc_channel_base + this_channel_offset;
7460
7461                                 printk("%d ", rt->rxdma_channel[slot]);
7462
7463                                 if (++this_channel_offset == num_channels)
7464                                         this_channel_offset = 0;
7465                         }
7466                         printk("]\n");
7467                 }
7468
7469                 parent->rdc_default[i] = rdc_channel_base;
7470
7471                 rdc_channel_base += num_channels;
7472                 rdc_group += rdc_groups_per_port;
7473         }
7474 }
7475
7476 static int __devinit fill_phy_probe_info(struct niu *np,
7477                                          struct niu_parent *parent,
7478                                          struct phy_probe_info *info)
7479 {
7480         unsigned long flags;
7481         int port, err;
7482
7483         memset(info, 0, sizeof(*info));
7484
7485         /* Port 0 to 7 are reserved for onboard Serdes, probe the rest.  */
7486         niu_lock_parent(np, flags);
7487         err = 0;
7488         for (port = 8; port < 32; port++) {
7489                 int dev_id_1, dev_id_2;
7490
7491                 dev_id_1 = mdio_read(np, port,
7492                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
7493                 dev_id_2 = mdio_read(np, port,
7494                                      NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
7495                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7496                                  PHY_TYPE_PMA_PMD);
7497                 if (err)
7498                         break;
7499                 dev_id_1 = mdio_read(np, port,
7500                                      NIU_PCS_DEV_ADDR, MII_PHYSID1);
7501                 dev_id_2 = mdio_read(np, port,
7502                                      NIU_PCS_DEV_ADDR, MII_PHYSID2);
7503                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7504                                  PHY_TYPE_PCS);
7505                 if (err)
7506                         break;
7507                 dev_id_1 = mii_read(np, port, MII_PHYSID1);
7508                 dev_id_2 = mii_read(np, port, MII_PHYSID2);
7509                 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
7510                                  PHY_TYPE_MII);
7511                 if (err)
7512                         break;
7513         }
7514         niu_unlock_parent(np, flags);
7515
7516         return err;
7517 }
7518
7519 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
7520 {
7521         struct phy_probe_info *info = &parent->phy_probe_info;
7522         int lowest_10g, lowest_1g;
7523         int num_10g, num_1g;
7524         u32 val;
7525         int err;
7526
7527         if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7528             !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
7529                 num_10g = 0;
7530                 num_1g = 2;
7531                 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
7532                 parent->num_ports = 4;
7533                 val = (phy_encode(PORT_TYPE_1G, 0) |
7534                        phy_encode(PORT_TYPE_1G, 1) |
7535                        phy_encode(PORT_TYPE_1G, 2) |
7536                        phy_encode(PORT_TYPE_1G, 3));
7537         } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
7538                 num_10g = 2;
7539                 num_1g = 0;
7540                 parent->num_ports = 2;
7541                 val = (phy_encode(PORT_TYPE_10G, 0) |
7542                        phy_encode(PORT_TYPE_10G, 1));
7543         } else {
7544                 err = fill_phy_probe_info(np, parent, info);
7545                 if (err)
7546                         return err;
7547
7548                 num_10g = count_10g_ports(info, &lowest_10g);
7549                 num_1g = count_1g_ports(info, &lowest_1g);
7550
7551                 switch ((num_10g << 4) | num_1g) {
7552                 case 0x24:
7553                         if (lowest_1g == 10)
7554                                 parent->plat_type = PLAT_TYPE_VF_P0;
7555                         else if (lowest_1g == 26)
7556                                 parent->plat_type = PLAT_TYPE_VF_P1;
7557                         else
7558                                 goto unknown_vg_1g_port;
7559
7560                         /* fallthru */
7561                 case 0x22:
7562                         val = (phy_encode(PORT_TYPE_10G, 0) |
7563                                phy_encode(PORT_TYPE_10G, 1) |
7564                                phy_encode(PORT_TYPE_1G, 2) |
7565                                phy_encode(PORT_TYPE_1G, 3));
7566                         break;
7567
7568                 case 0x20:
7569                         val = (phy_encode(PORT_TYPE_10G, 0) |
7570                                phy_encode(PORT_TYPE_10G, 1));
7571                         break;
7572
7573                 case 0x10:
7574                         val = phy_encode(PORT_TYPE_10G, np->port);
7575                         break;
7576
7577                 case 0x14:
7578                         if (lowest_1g == 10)
7579                                 parent->plat_type = PLAT_TYPE_VF_P0;
7580                         else if (lowest_1g == 26)
7581                                 parent->plat_type = PLAT_TYPE_VF_P1;
7582                         else
7583                                 goto unknown_vg_1g_port;
7584
7585                         /* fallthru */
7586                 case 0x13:
7587                         if ((lowest_10g & 0x7) == 0)
7588                                 val = (phy_encode(PORT_TYPE_10G, 0) |
7589                                        phy_encode(PORT_TYPE_1G, 1) |
7590                                        phy_encode(PORT_TYPE_1G, 2) |
7591                                        phy_encode(PORT_TYPE_1G, 3));
7592                         else
7593                                 val = (phy_encode(PORT_TYPE_1G, 0) |
7594                                        phy_encode(PORT_TYPE_10G, 1) |
7595                                        phy_encode(PORT_TYPE_1G, 2) |
7596                                        phy_encode(PORT_TYPE_1G, 3));
7597                         break;
7598
7599                 case 0x04:
7600                         if (lowest_1g == 10)
7601                                 parent->plat_type = PLAT_TYPE_VF_P0;
7602                         else if (lowest_1g == 26)
7603                                 parent->plat_type = PLAT_TYPE_VF_P1;
7604                         else
7605                                 goto unknown_vg_1g_port;
7606
7607                         val = (phy_encode(PORT_TYPE_1G, 0) |
7608                                phy_encode(PORT_TYPE_1G, 1) |
7609                                phy_encode(PORT_TYPE_1G, 2) |
7610                                phy_encode(PORT_TYPE_1G, 3));
7611                         break;
7612
7613                 default:
7614                         printk(KERN_ERR PFX "Unsupported port config "
7615                                "10G[%d] 1G[%d]\n",
7616                                num_10g, num_1g);
7617                         return -EINVAL;
7618                 }
7619         }
7620
7621         parent->port_phy = val;
7622
7623         if (parent->plat_type == PLAT_TYPE_NIU)
7624                 niu_n2_divide_channels(parent);
7625         else
7626                 niu_divide_channels(parent, num_10g, num_1g);
7627
7628         niu_divide_rdc_groups(parent, num_10g, num_1g);
7629
7630         return 0;
7631
7632 unknown_vg_1g_port:
7633         printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
7634                lowest_1g);
7635         return -EINVAL;
7636 }
7637
7638 static int __devinit niu_probe_ports(struct niu *np)
7639 {
7640         struct niu_parent *parent = np->parent;
7641         int err, i;
7642
7643         niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
7644                parent->port_phy);
7645
7646         if (parent->port_phy == PORT_PHY_UNKNOWN) {
7647                 err = walk_phys(np, parent);
7648                 if (err)
7649                         return err;
7650
7651                 niu_set_ldg_timer_res(np, 2);
7652                 for (i = 0; i <= LDN_MAX; i++)
7653                         niu_ldn_irq_enable(np, i, 0);
7654         }
7655
7656         if (parent->port_phy == PORT_PHY_INVALID)
7657                 return -EINVAL;
7658
7659         return 0;
7660 }
7661
7662 static int __devinit niu_classifier_swstate_init(struct niu *np)
7663 {
7664         struct niu_classifier *cp = &np->clas;
7665
7666         niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
7667                np->parent->tcam_num_entries);
7668
7669         cp->tcam_index = (u16) np->port;
7670         cp->h1_init = 0xffffffff;
7671         cp->h2_init = 0xffff;
7672
7673         return fflp_early_init(np);
7674 }
7675
7676 static void __devinit niu_link_config_init(struct niu *np)
7677 {
7678         struct niu_link_config *lp = &np->link_config;
7679
7680         lp->advertising = (ADVERTISED_10baseT_Half |
7681                            ADVERTISED_10baseT_Full |
7682                            ADVERTISED_100baseT_Half |
7683                            ADVERTISED_100baseT_Full |
7684                            ADVERTISED_1000baseT_Half |
7685                            ADVERTISED_1000baseT_Full |
7686                            ADVERTISED_10000baseT_Full |
7687                            ADVERTISED_Autoneg);
7688         lp->speed = lp->active_speed = SPEED_INVALID;
7689         lp->duplex = lp->active_duplex = DUPLEX_INVALID;
7690 #if 0
7691         lp->loopback_mode = LOOPBACK_MAC;
7692         lp->active_speed = SPEED_10000;
7693         lp->active_duplex = DUPLEX_FULL;
7694 #else
7695         lp->loopback_mode = LOOPBACK_DISABLED;
7696 #endif
7697 }
7698
7699 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
7700 {
7701         switch (np->port) {
7702         case 0:
7703                 np->mac_regs = np->regs + XMAC_PORT0_OFF;
7704                 np->ipp_off  = 0x00000;
7705                 np->pcs_off  = 0x04000;
7706                 np->xpcs_off = 0x02000;
7707                 break;
7708
7709         case 1:
7710                 np->mac_regs = np->regs + XMAC_PORT1_OFF;
7711                 np->ipp_off  = 0x08000;
7712                 np->pcs_off  = 0x0a000;
7713                 np->xpcs_off = 0x08000;
7714                 break;
7715
7716         case 2:
7717                 np->mac_regs = np->regs + BMAC_PORT2_OFF;
7718                 np->ipp_off  = 0x04000;
7719                 np->pcs_off  = 0x0e000;
7720                 np->xpcs_off = ~0UL;
7721                 break;
7722
7723         case 3:
7724                 np->mac_regs = np->regs + BMAC_PORT3_OFF;
7725                 np->ipp_off  = 0x0c000;
7726                 np->pcs_off  = 0x12000;
7727                 np->xpcs_off = ~0UL;
7728                 break;
7729
7730         default:
7731                 dev_err(np->device, PFX "Port %u is invalid, cannot "
7732                         "compute MAC block offset.\n", np->port);
7733                 return -EINVAL;
7734         }
7735
7736         return 0;
7737 }
7738
7739 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
7740 {
7741         struct msix_entry msi_vec[NIU_NUM_LDG];
7742         struct niu_parent *parent = np->parent;
7743         struct pci_dev *pdev = np->pdev;
7744         int i, num_irqs, err;
7745         u8 first_ldg;
7746
7747         first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
7748         for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
7749                 ldg_num_map[i] = first_ldg + i;
7750
7751         num_irqs = (parent->rxchan_per_port[np->port] +
7752                     parent->txchan_per_port[np->port] +
7753                     (np->port == 0 ? 3 : 1));
7754         BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
7755
7756 retry:
7757         for (i = 0; i < num_irqs; i++) {
7758                 msi_vec[i].vector = 0;
7759                 msi_vec[i].entry = i;
7760         }
7761
7762         err = pci_enable_msix(pdev, msi_vec, num_irqs);
7763         if (err < 0) {
7764                 np->flags &= ~NIU_FLAGS_MSIX;
7765                 return;
7766         }
7767         if (err > 0) {
7768                 num_irqs = err;
7769                 goto retry;
7770         }
7771
7772         np->flags |= NIU_FLAGS_MSIX;
7773         for (i = 0; i < num_irqs; i++)
7774                 np->ldg[i].irq = msi_vec[i].vector;
7775         np->num_ldg = num_irqs;
7776 }
7777
7778 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
7779 {
7780 #ifdef CONFIG_SPARC64
7781         struct of_device *op = np->op;
7782         const u32 *int_prop;
7783         int i;
7784
7785         int_prop = of_get_property(op->node, "interrupts", NULL);
7786         if (!int_prop)
7787                 return -ENODEV;
7788
7789         for (i = 0; i < op->num_irqs; i++) {
7790                 ldg_num_map[i] = int_prop[i];
7791                 np->ldg[i].irq = op->irqs[i];
7792         }
7793
7794         np->num_ldg = op->num_irqs;
7795
7796         return 0;
7797 #else
7798         return -EINVAL;
7799 #endif
7800 }
7801
7802 static int __devinit niu_ldg_init(struct niu *np)
7803 {
7804         struct niu_parent *parent = np->parent;
7805         u8 ldg_num_map[NIU_NUM_LDG];
7806         int first_chan, num_chan;
7807         int i, err, ldg_rotor;
7808         u8 port;
7809
7810         np->num_ldg = 1;
7811         np->ldg[0].irq = np->dev->irq;
7812         if (parent->plat_type == PLAT_TYPE_NIU) {
7813                 err = niu_n2_irq_init(np, ldg_num_map);
7814                 if (err)
7815                         return err;
7816         } else
7817                 niu_try_msix(np, ldg_num_map);
7818
7819         port = np->port;
7820         for (i = 0; i < np->num_ldg; i++) {
7821                 struct niu_ldg *lp = &np->ldg[i];
7822
7823                 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
7824
7825                 lp->np = np;
7826                 lp->ldg_num = ldg_num_map[i];
7827                 lp->timer = 2; /* XXX */
7828
7829                 /* On N2 NIU the firmware has setup the SID mappings so they go
7830                  * to the correct values that will route the LDG to the proper
7831                  * interrupt in the NCU interrupt table.
7832                  */
7833                 if (np->parent->plat_type != PLAT_TYPE_NIU) {
7834                         err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
7835                         if (err)
7836                                 return err;
7837                 }
7838         }
7839
7840         /* We adopt the LDG assignment ordering used by the N2 NIU
7841          * 'interrupt' properties because that simplifies a lot of
7842          * things.  This ordering is:
7843          *
7844          *      MAC
7845          *      MIF     (if port zero)
7846          *      SYSERR  (if port zero)
7847          *      RX channels
7848          *      TX channels
7849          */
7850
7851         ldg_rotor = 0;
7852
7853         err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
7854                                   LDN_MAC(port));
7855         if (err)
7856                 return err;
7857
7858         ldg_rotor++;
7859         if (ldg_rotor == np->num_ldg)
7860                 ldg_rotor = 0;
7861
7862         if (port == 0) {
7863                 err = niu_ldg_assign_ldn(np, parent,
7864                                          ldg_num_map[ldg_rotor],
7865                                          LDN_MIF);
7866                 if (err)
7867                         return err;
7868
7869                 ldg_rotor++;
7870                 if (ldg_rotor == np->num_ldg)
7871                         ldg_rotor = 0;
7872
7873                 err = niu_ldg_assign_ldn(np, parent,
7874                                          ldg_num_map[ldg_rotor],
7875                                          LDN_DEVICE_ERROR);
7876                 if (err)
7877                         return err;
7878
7879                 ldg_rotor++;
7880                 if (ldg_rotor == np->num_ldg)
7881                         ldg_rotor = 0;
7882
7883         }
7884
7885         first_chan = 0;
7886         for (i = 0; i < port; i++)
7887                 first_chan += parent->rxchan_per_port[port];
7888         num_chan = parent->rxchan_per_port[port];
7889
7890         for (i = first_chan; i < (first_chan + num_chan); i++) {
7891                 err = niu_ldg_assign_ldn(np, parent,
7892                                          ldg_num_map[ldg_rotor],
7893                                          LDN_RXDMA(i));
7894                 if (err)
7895                         return err;
7896                 ldg_rotor++;
7897                 if (ldg_rotor == np->num_ldg)
7898                         ldg_rotor = 0;
7899         }
7900
7901         first_chan = 0;
7902         for (i = 0; i < port; i++)
7903                 first_chan += parent->txchan_per_port[port];
7904         num_chan = parent->txchan_per_port[port];
7905         for (i = first_chan; i < (first_chan + num_chan); i++) {
7906                 err = niu_ldg_assign_ldn(np, parent,
7907                                          ldg_num_map[ldg_rotor],
7908                                          LDN_TXDMA(i));
7909                 if (err)
7910                         return err;
7911                 ldg_rotor++;
7912                 if (ldg_rotor == np->num_ldg)
7913                         ldg_rotor = 0;
7914         }
7915
7916         return 0;
7917 }
7918
7919 static void __devexit niu_ldg_free(struct niu *np)
7920 {
7921         if (np->flags & NIU_FLAGS_MSIX)
7922                 pci_disable_msix(np->pdev);
7923 }
7924
7925 static int __devinit niu_get_of_props(struct niu *np)
7926 {
7927 #ifdef CONFIG_SPARC64
7928         struct net_device *dev = np->dev;
7929         struct device_node *dp;
7930         const char *phy_type;
7931         const u8 *mac_addr;
7932         const char *model;
7933         int prop_len;
7934
7935         if (np->parent->plat_type == PLAT_TYPE_NIU)
7936                 dp = np->op->node;
7937         else
7938                 dp = pci_device_to_OF_node(np->pdev);
7939
7940         phy_type = of_get_property(dp, "phy-type", &prop_len);
7941         if (!phy_type) {
7942                 dev_err(np->device, PFX "%s: OF node lacks "
7943                         "phy-type property\n",
7944                         dp->full_name);
7945                 return -EINVAL;
7946         }
7947
7948         if (!strcmp(phy_type, "none"))
7949                 return -ENODEV;
7950
7951         strcpy(np->vpd.phy_type, phy_type);
7952
7953         if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7954                 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
7955                         dp->full_name, np->vpd.phy_type);
7956                 return -EINVAL;
7957         }
7958
7959         mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
7960         if (!mac_addr) {
7961                 dev_err(np->device, PFX "%s: OF node lacks "
7962                         "local-mac-address property\n",
7963                         dp->full_name);
7964                 return -EINVAL;
7965         }
7966         if (prop_len != dev->addr_len) {
7967                 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
7968                         "is wrong.\n",
7969                         dp->full_name, prop_len);
7970         }
7971         memcpy(dev->perm_addr, mac_addr, dev->addr_len);
7972         if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7973                 int i;
7974
7975                 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
7976                         dp->full_name);
7977                 dev_err(np->device, PFX "%s: [ \n",
7978                         dp->full_name);
7979                 for (i = 0; i < 6; i++)
7980                         printk("%02x ", dev->perm_addr[i]);
7981                 printk("]\n");
7982                 return -EINVAL;
7983         }
7984
7985         memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7986
7987         model = of_get_property(dp, "model", &prop_len);
7988
7989         if (model)
7990                 strcpy(np->vpd.model, model);
7991
7992         return 0;
7993 #else
7994         return -EINVAL;
7995 #endif
7996 }
7997
7998 static int __devinit niu_get_invariants(struct niu *np)
7999 {
8000         int err, have_props;
8001         u32 offset;
8002
8003         err = niu_get_of_props(np);
8004         if (err == -ENODEV)
8005                 return err;
8006
8007         have_props = !err;
8008
8009         err = niu_init_mac_ipp_pcs_base(np);
8010         if (err)
8011                 return err;
8012
8013         if (have_props) {
8014                 err = niu_get_and_validate_port(np);
8015                 if (err)
8016                         return err;
8017
8018         } else  {
8019                 if (np->parent->plat_type == PLAT_TYPE_NIU)
8020                         return -EINVAL;
8021
8022                 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
8023                 offset = niu_pci_vpd_offset(np);
8024                 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
8025                        offset);
8026                 if (offset)
8027                         niu_pci_vpd_fetch(np, offset);
8028                 nw64(ESPC_PIO_EN, 0);
8029
8030                 if (np->flags & NIU_FLAGS_VPD_VALID) {
8031                         niu_pci_vpd_validate(np);
8032                         err = niu_get_and_validate_port(np);
8033                         if (err)
8034                                 return err;
8035                 }
8036
8037                 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
8038                         err = niu_get_and_validate_port(np);
8039                         if (err)
8040                                 return err;
8041                         err = niu_pci_probe_sprom(np);
8042                         if (err)
8043                                 return err;
8044                 }
8045         }
8046
8047         err = niu_probe_ports(np);
8048         if (err)
8049                 return err;
8050
8051         niu_ldg_init(np);
8052
8053         niu_classifier_swstate_init(np);
8054         niu_link_config_init(np);
8055
8056         err = niu_determine_phy_disposition(np);
8057         if (!err)
8058                 err = niu_init_link(np);
8059
8060         return err;
8061 }
8062
8063 static LIST_HEAD(niu_parent_list);
8064 static DEFINE_MUTEX(niu_parent_lock);
8065 static int niu_parent_index;
8066
8067 static ssize_t show_port_phy(struct device *dev,
8068                              struct device_attribute *attr, char *buf)
8069 {
8070         struct platform_device *plat_dev = to_platform_device(dev);
8071         struct niu_parent *p = plat_dev->dev.platform_data;
8072         u32 port_phy = p->port_phy;
8073         char *orig_buf = buf;
8074         int i;
8075
8076         if (port_phy == PORT_PHY_UNKNOWN ||
8077             port_phy == PORT_PHY_INVALID)
8078                 return 0;
8079
8080         for (i = 0; i < p->num_ports; i++) {
8081                 const char *type_str;
8082                 int type;
8083
8084                 type = phy_decode(port_phy, i);
8085                 if (type == PORT_TYPE_10G)
8086                         type_str = "10G";
8087                 else
8088                         type_str = "1G";
8089                 buf += sprintf(buf,
8090                                (i == 0) ? "%s" : " %s",
8091                                type_str);
8092         }
8093         buf += sprintf(buf, "\n");
8094         return buf - orig_buf;
8095 }
8096
8097 static ssize_t show_plat_type(struct device *dev,
8098                               struct device_attribute *attr, char *buf)
8099 {
8100         struct platform_device *plat_dev = to_platform_device(dev);
8101         struct niu_parent *p = plat_dev->dev.platform_data;
8102         const char *type_str;
8103
8104         switch (p->plat_type) {
8105         case PLAT_TYPE_ATLAS:
8106                 type_str = "atlas";
8107                 break;
8108         case PLAT_TYPE_NIU:
8109                 type_str = "niu";
8110                 break;
8111         case PLAT_TYPE_VF_P0:
8112                 type_str = "vf_p0";
8113                 break;
8114         case PLAT_TYPE_VF_P1:
8115                 type_str = "vf_p1";
8116                 break;
8117         default:
8118                 type_str = "unknown";
8119                 break;
8120         }
8121
8122         return sprintf(buf, "%s\n", type_str);
8123 }
8124
8125 static ssize_t __show_chan_per_port(struct device *dev,
8126                                     struct device_attribute *attr, char *buf,
8127                                     int rx)
8128 {
8129         struct platform_device *plat_dev = to_platform_device(dev);
8130         struct niu_parent *p = plat_dev->dev.platform_data;
8131         char *orig_buf = buf;
8132         u8 *arr;
8133         int i;
8134
8135         arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
8136
8137         for (i = 0; i < p->num_ports; i++) {
8138                 buf += sprintf(buf,
8139                                (i == 0) ? "%d" : " %d",
8140                                arr[i]);
8141         }
8142         buf += sprintf(buf, "\n");
8143
8144         return buf - orig_buf;
8145 }
8146
8147 static ssize_t show_rxchan_per_port(struct device *dev,
8148                                     struct device_attribute *attr, char *buf)
8149 {
8150         return __show_chan_per_port(dev, attr, buf, 1);
8151 }
8152
8153 static ssize_t show_txchan_per_port(struct device *dev,
8154                                     struct device_attribute *attr, char *buf)
8155 {
8156         return __show_chan_per_port(dev, attr, buf, 1);
8157 }
8158
8159 static ssize_t show_num_ports(struct device *dev,
8160                               struct device_attribute *attr, char *buf)
8161 {
8162         struct platform_device *plat_dev = to_platform_device(dev);
8163         struct niu_parent *p = plat_dev->dev.platform_data;
8164
8165         return sprintf(buf, "%d\n", p->num_ports);
8166 }
8167
8168 static struct device_attribute niu_parent_attributes[] = {
8169         __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
8170         __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
8171         __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
8172         __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
8173         __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
8174         {}
8175 };
8176
8177 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
8178                                                     union niu_parent_id *id,
8179                                                     u8 ptype)
8180 {
8181         struct platform_device *plat_dev;
8182         struct niu_parent *p;
8183         int i;
8184
8185         niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
8186
8187         plat_dev = platform_device_register_simple("niu", niu_parent_index,
8188                                                    NULL, 0);
8189         if (!plat_dev)
8190                 return NULL;
8191
8192         for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
8193                 int err = device_create_file(&plat_dev->dev,
8194                                              &niu_parent_attributes[i]);
8195                 if (err)
8196                         goto fail_unregister;
8197         }
8198
8199         p = kzalloc(sizeof(*p), GFP_KERNEL);
8200         if (!p)
8201                 goto fail_unregister;
8202
8203         p->index = niu_parent_index++;
8204
8205         plat_dev->dev.platform_data = p;
8206         p->plat_dev = plat_dev;
8207
8208         memcpy(&p->id, id, sizeof(*id));
8209         p->plat_type = ptype;
8210         INIT_LIST_HEAD(&p->list);
8211         atomic_set(&p->refcnt, 0);
8212         list_add(&p->list, &niu_parent_list);
8213         spin_lock_init(&p->lock);
8214
8215         p->rxdma_clock_divider = 7500;
8216
8217         p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
8218         if (p->plat_type == PLAT_TYPE_NIU)
8219                 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
8220
8221         for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
8222                 int index = i - CLASS_CODE_USER_PROG1;
8223
8224                 p->tcam_key[index] = TCAM_KEY_TSEL;
8225                 p->flow_key[index] = (FLOW_KEY_IPSA |
8226                                       FLOW_KEY_IPDA |
8227                                       FLOW_KEY_PROTO |
8228                                       (FLOW_KEY_L4_BYTE12 <<
8229                                        FLOW_KEY_L4_0_SHIFT) |
8230                                       (FLOW_KEY_L4_BYTE12 <<
8231                                        FLOW_KEY_L4_1_SHIFT));
8232         }
8233
8234         for (i = 0; i < LDN_MAX + 1; i++)
8235                 p->ldg_map[i] = LDG_INVALID;
8236
8237         return p;
8238
8239 fail_unregister:
8240         platform_device_unregister(plat_dev);
8241         return NULL;
8242 }
8243
8244 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8245                                                     union niu_parent_id *id,
8246                                                     u8 ptype)
8247 {
8248         struct niu_parent *p, *tmp;
8249         int port = np->port;
8250
8251         niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8252                ptype, port);
8253
8254         mutex_lock(&niu_parent_lock);
8255         p = NULL;
8256         list_for_each_entry(tmp, &niu_parent_list, list) {
8257                 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8258                         p = tmp;
8259                         break;
8260                 }
8261         }
8262         if (!p)
8263                 p = niu_new_parent(np, id, ptype);
8264
8265         if (p) {
8266                 char port_name[6];
8267                 int err;
8268
8269                 sprintf(port_name, "port%d", port);
8270                 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8271                                         &np->device->kobj,
8272                                         port_name);
8273                 if (!err) {
8274                         p->ports[port] = np;
8275                         atomic_inc(&p->refcnt);
8276                 }
8277         }
8278         mutex_unlock(&niu_parent_lock);
8279
8280         return p;
8281 }
8282
8283 static void niu_put_parent(struct niu *np)
8284 {
8285         struct niu_parent *p = np->parent;
8286         u8 port = np->port;
8287         char port_name[6];
8288
8289         BUG_ON(!p || p->ports[port] != np);
8290
8291         niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8292
8293         sprintf(port_name, "port%d", port);
8294
8295         mutex_lock(&niu_parent_lock);
8296
8297         sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
8298
8299         p->ports[port] = NULL;
8300         np->parent = NULL;
8301
8302         if (atomic_dec_and_test(&p->refcnt)) {
8303                 list_del(&p->list);
8304                 platform_device_unregister(p->plat_dev);
8305         }
8306
8307         mutex_unlock(&niu_parent_lock);
8308 }
8309
8310 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
8311                                     u64 *handle, gfp_t flag)
8312 {
8313         dma_addr_t dh;
8314         void *ret;
8315
8316         ret = dma_alloc_coherent(dev, size, &dh, flag);
8317         if (ret)
8318                 *handle = dh;
8319         return ret;
8320 }
8321
8322 static void niu_pci_free_coherent(struct device *dev, size_t size,
8323                                   void *cpu_addr, u64 handle)
8324 {
8325         dma_free_coherent(dev, size, cpu_addr, handle);
8326 }
8327
8328 static u64 niu_pci_map_page(struct device *dev, struct page *page,
8329                             unsigned long offset, size_t size,
8330                             enum dma_data_direction direction)
8331 {
8332         return dma_map_page(dev, page, offset, size, direction);
8333 }
8334
8335 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
8336                                size_t size, enum dma_data_direction direction)
8337 {
8338         return dma_unmap_page(dev, dma_address, size, direction);
8339 }
8340
8341 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
8342                               size_t size,
8343                               enum dma_data_direction direction)
8344 {
8345         return dma_map_single(dev, cpu_addr, size, direction);
8346 }
8347
8348 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
8349                                  size_t size,
8350                                  enum dma_data_direction direction)
8351 {
8352         dma_unmap_single(dev, dma_address, size, direction);
8353 }
8354
8355 static const struct niu_ops niu_pci_ops = {
8356         .alloc_coherent = niu_pci_alloc_coherent,
8357         .free_coherent  = niu_pci_free_coherent,
8358         .map_page       = niu_pci_map_page,
8359         .unmap_page     = niu_pci_unmap_page,
8360         .map_single     = niu_pci_map_single,
8361         .unmap_single   = niu_pci_unmap_single,
8362 };
8363
8364 static void __devinit niu_driver_version(void)
8365 {
8366         static int niu_version_printed;
8367
8368         if (niu_version_printed++ == 0)
8369                 pr_info("%s", version);
8370 }
8371
8372 static struct net_device * __devinit niu_alloc_and_init(
8373         struct device *gen_dev, struct pci_dev *pdev,
8374         struct of_device *op, const struct niu_ops *ops,
8375         u8 port)
8376 {
8377         struct net_device *dev = alloc_etherdev(sizeof(struct niu));
8378         struct niu *np;
8379
8380         if (!dev) {
8381                 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8382                 return NULL;
8383         }
8384
8385         SET_NETDEV_DEV(dev, gen_dev);
8386
8387         np = netdev_priv(dev);
8388         np->dev = dev;
8389         np->pdev = pdev;
8390         np->op = op;
8391         np->device = gen_dev;
8392         np->ops = ops;
8393
8394         np->msg_enable = niu_debug;
8395
8396         spin_lock_init(&np->lock);
8397         INIT_WORK(&np->reset_task, niu_reset_task);
8398
8399         np->port = port;
8400
8401         return dev;
8402 }
8403
8404 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
8405 {
8406         dev->open = niu_open;
8407         dev->stop = niu_close;
8408         dev->get_stats = niu_get_stats;
8409         dev->set_multicast_list = niu_set_rx_mode;
8410         dev->set_mac_address = niu_set_mac_addr;
8411         dev->do_ioctl = niu_ioctl;
8412         dev->tx_timeout = niu_tx_timeout;
8413         dev->hard_start_xmit = niu_start_xmit;
8414         dev->ethtool_ops = &niu_ethtool_ops;
8415         dev->watchdog_timeo = NIU_TX_TIMEOUT;
8416         dev->change_mtu = niu_change_mtu;
8417 }
8418
8419 static void __devinit niu_device_announce(struct niu *np)
8420 {
8421         struct net_device *dev = np->dev;
8422         DECLARE_MAC_BUF(mac);
8423
8424         pr_info("%s: NIU Ethernet %s\n",
8425                 dev->name, print_mac(mac, dev->dev_addr));
8426
8427         if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
8428                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8429                                 dev->name,
8430                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8431                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8432                                 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
8433                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8434                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8435                                 np->vpd.phy_type);
8436         } else {
8437                 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
8438                                 dev->name,
8439                                 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
8440                                 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
8441                                 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
8442                                 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
8443                                  (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
8444                                 np->vpd.phy_type);
8445         }
8446 }
8447
8448 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
8449                                       const struct pci_device_id *ent)
8450 {
8451         unsigned long niureg_base, niureg_len;
8452         union niu_parent_id parent_id;
8453         struct net_device *dev;
8454         struct niu *np;
8455         int err, pos;
8456         u64 dma_mask;
8457         u16 val16;
8458
8459         niu_driver_version();
8460
8461         err = pci_enable_device(pdev);
8462         if (err) {
8463                 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
8464                         "aborting.\n");
8465                 return err;
8466         }
8467
8468         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
8469             !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
8470                 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
8471                         "base addresses, aborting.\n");
8472                 err = -ENODEV;
8473                 goto err_out_disable_pdev;
8474         }
8475
8476         err = pci_request_regions(pdev, DRV_MODULE_NAME);
8477         if (err) {
8478                 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
8479                         "aborting.\n");
8480                 goto err_out_disable_pdev;
8481         }
8482
8483         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
8484         if (pos <= 0) {
8485                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
8486                         "aborting.\n");
8487                 goto err_out_free_res;
8488         }
8489
8490         dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
8491                                  &niu_pci_ops, PCI_FUNC(pdev->devfn));
8492         if (!dev) {
8493                 err = -ENOMEM;
8494                 goto err_out_free_res;
8495         }
8496         np = netdev_priv(dev);
8497
8498         memset(&parent_id, 0, sizeof(parent_id));
8499         parent_id.pci.domain = pci_domain_nr(pdev->bus);
8500         parent_id.pci.bus = pdev->bus->number;
8501         parent_id.pci.device = PCI_SLOT(pdev->devfn);
8502
8503         np->parent = niu_get_parent(np, &parent_id,
8504                                     PLAT_TYPE_ATLAS);
8505         if (!np->parent) {
8506                 err = -ENOMEM;
8507                 goto err_out_free_dev;
8508         }
8509
8510         pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
8511         val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
8512         val16 |= (PCI_EXP_DEVCTL_CERE |
8513                   PCI_EXP_DEVCTL_NFERE |
8514                   PCI_EXP_DEVCTL_FERE |
8515                   PCI_EXP_DEVCTL_URRE |
8516                   PCI_EXP_DEVCTL_RELAX_EN);
8517         pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
8518
8519         dma_mask = DMA_44BIT_MASK;
8520         err = pci_set_dma_mask(pdev, dma_mask);
8521         if (!err) {
8522                 dev->features |= NETIF_F_HIGHDMA;
8523                 err = pci_set_consistent_dma_mask(pdev, dma_mask);
8524                 if (err) {
8525                         dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
8526                                 "DMA for consistent allocations, "
8527                                 "aborting.\n");
8528                         goto err_out_release_parent;
8529                 }
8530         }
8531         if (err || dma_mask == DMA_32BIT_MASK) {
8532                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
8533                 if (err) {
8534                         dev_err(&pdev->dev, PFX "No usable DMA configuration, "
8535                                 "aborting.\n");
8536                         goto err_out_release_parent;
8537                 }
8538         }
8539
8540         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
8541
8542         niureg_base = pci_resource_start(pdev, 0);
8543         niureg_len = pci_resource_len(pdev, 0);
8544
8545         np->regs = ioremap_nocache(niureg_base, niureg_len);
8546         if (!np->regs) {
8547                 dev_err(&pdev->dev, PFX "Cannot map device registers, "
8548                         "aborting.\n");
8549                 err = -ENOMEM;
8550                 goto err_out_release_parent;
8551         }
8552
8553         pci_set_master(pdev);
8554         pci_save_state(pdev);
8555
8556         dev->irq = pdev->irq;
8557
8558         niu_assign_netdev_ops(dev);
8559
8560         err = niu_get_invariants(np);
8561         if (err) {
8562                 if (err != -ENODEV)
8563                         dev_err(&pdev->dev, PFX "Problem fetching invariants "
8564                                 "of chip, aborting.\n");
8565                 goto err_out_iounmap;
8566         }
8567
8568         err = register_netdev(dev);
8569         if (err) {
8570                 dev_err(&pdev->dev, PFX "Cannot register net device, "
8571                         "aborting.\n");
8572                 goto err_out_iounmap;
8573         }
8574
8575         pci_set_drvdata(pdev, dev);
8576
8577         niu_device_announce(np);
8578
8579         return 0;
8580
8581 err_out_iounmap:
8582         if (np->regs) {
8583                 iounmap(np->regs);
8584                 np->regs = NULL;
8585         }
8586
8587 err_out_release_parent:
8588         niu_put_parent(np);
8589
8590 err_out_free_dev:
8591         free_netdev(dev);
8592
8593 err_out_free_res:
8594         pci_release_regions(pdev);
8595
8596 err_out_disable_pdev:
8597         pci_disable_device(pdev);
8598         pci_set_drvdata(pdev, NULL);
8599
8600         return err;
8601 }
8602
8603 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
8604 {
8605         struct net_device *dev = pci_get_drvdata(pdev);
8606
8607         if (dev) {
8608                 struct niu *np = netdev_priv(dev);
8609
8610                 unregister_netdev(dev);
8611                 if (np->regs) {
8612                         iounmap(np->regs);
8613                         np->regs = NULL;
8614                 }
8615
8616                 niu_ldg_free(np);
8617
8618                 niu_put_parent(np);
8619
8620                 free_netdev(dev);
8621                 pci_release_regions(pdev);
8622                 pci_disable_device(pdev);
8623                 pci_set_drvdata(pdev, NULL);
8624         }
8625 }
8626
8627 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
8628 {
8629         struct net_device *dev = pci_get_drvdata(pdev);
8630         struct niu *np = netdev_priv(dev);
8631         unsigned long flags;
8632
8633         if (!netif_running(dev))
8634                 return 0;
8635
8636         flush_scheduled_work();
8637         niu_netif_stop(np);
8638
8639         del_timer_sync(&np->timer);
8640
8641         spin_lock_irqsave(&np->lock, flags);
8642         niu_enable_interrupts(np, 0);
8643         spin_unlock_irqrestore(&np->lock, flags);
8644
8645         netif_device_detach(dev);
8646
8647         spin_lock_irqsave(&np->lock, flags);
8648         niu_stop_hw(np);
8649         spin_unlock_irqrestore(&np->lock, flags);
8650
8651         pci_save_state(pdev);
8652
8653         return 0;
8654 }
8655
8656 static int niu_resume(struct pci_dev *pdev)
8657 {
8658         struct net_device *dev = pci_get_drvdata(pdev);
8659         struct niu *np = netdev_priv(dev);
8660         unsigned long flags;
8661         int err;
8662
8663         if (!netif_running(dev))
8664                 return 0;
8665
8666         pci_restore_state(pdev);
8667
8668         netif_device_attach(dev);
8669
8670         spin_lock_irqsave(&np->lock, flags);
8671
8672         err = niu_init_hw(np);
8673         if (!err) {
8674                 np->timer.expires = jiffies + HZ;
8675                 add_timer(&np->timer);
8676                 niu_netif_start(np);
8677         }
8678
8679         spin_unlock_irqrestore(&np->lock, flags);
8680
8681         return err;
8682 }
8683
8684 static struct pci_driver niu_pci_driver = {
8685         .name           = DRV_MODULE_NAME,
8686         .id_table       = niu_pci_tbl,
8687         .probe          = niu_pci_init_one,
8688         .remove         = __devexit_p(niu_pci_remove_one),
8689         .suspend        = niu_suspend,
8690         .resume         = niu_resume,
8691 };
8692
8693 #ifdef CONFIG_SPARC64
8694 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
8695                                      u64 *dma_addr, gfp_t flag)
8696 {
8697         unsigned long order = get_order(size);
8698         unsigned long page = __get_free_pages(flag, order);
8699
8700         if (page == 0UL)
8701                 return NULL;
8702         memset((char *)page, 0, PAGE_SIZE << order);
8703         *dma_addr = __pa(page);
8704
8705         return (void *) page;
8706 }
8707
8708 static void niu_phys_free_coherent(struct device *dev, size_t size,
8709                                    void *cpu_addr, u64 handle)
8710 {
8711         unsigned long order = get_order(size);
8712
8713         free_pages((unsigned long) cpu_addr, order);
8714 }
8715
8716 static u64 niu_phys_map_page(struct device *dev, struct page *page,
8717                              unsigned long offset, size_t size,
8718                              enum dma_data_direction direction)
8719 {
8720         return page_to_phys(page) + offset;
8721 }
8722
8723 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
8724                                 size_t size, enum dma_data_direction direction)
8725 {
8726         /* Nothing to do.  */
8727 }
8728
8729 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
8730                                size_t size,
8731                                enum dma_data_direction direction)
8732 {
8733         return __pa(cpu_addr);
8734 }
8735
8736 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
8737                                   size_t size,
8738                                   enum dma_data_direction direction)
8739 {
8740         /* Nothing to do.  */
8741 }
8742
8743 static const struct niu_ops niu_phys_ops = {
8744         .alloc_coherent = niu_phys_alloc_coherent,
8745         .free_coherent  = niu_phys_free_coherent,
8746         .map_page       = niu_phys_map_page,
8747         .unmap_page     = niu_phys_unmap_page,
8748         .map_single     = niu_phys_map_single,
8749         .unmap_single   = niu_phys_unmap_single,
8750 };
8751
8752 static unsigned long res_size(struct resource *r)
8753 {
8754         return r->end - r->start + 1UL;
8755 }
8756
8757 static int __devinit niu_of_probe(struct of_device *op,
8758                                   const struct of_device_id *match)
8759 {
8760         union niu_parent_id parent_id;
8761         struct net_device *dev;
8762         struct niu *np;
8763         const u32 *reg;
8764         int err;
8765
8766         niu_driver_version();
8767
8768         reg = of_get_property(op->node, "reg", NULL);
8769         if (!reg) {
8770                 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
8771                         op->node->full_name);
8772                 return -ENODEV;
8773         }
8774
8775         dev = niu_alloc_and_init(&op->dev, NULL, op,
8776                                  &niu_phys_ops, reg[0] & 0x1);
8777         if (!dev) {
8778                 err = -ENOMEM;
8779                 goto err_out;
8780         }
8781         np = netdev_priv(dev);
8782
8783         memset(&parent_id, 0, sizeof(parent_id));
8784         parent_id.of = of_get_parent(op->node);
8785
8786         np->parent = niu_get_parent(np, &parent_id,
8787                                     PLAT_TYPE_NIU);
8788         if (!np->parent) {
8789                 err = -ENOMEM;
8790                 goto err_out_free_dev;
8791         }
8792
8793         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
8794
8795         np->regs = of_ioremap(&op->resource[1], 0,
8796                               res_size(&op->resource[1]),
8797                               "niu regs");
8798         if (!np->regs) {
8799                 dev_err(&op->dev, PFX "Cannot map device registers, "
8800                         "aborting.\n");
8801                 err = -ENOMEM;
8802                 goto err_out_release_parent;
8803         }
8804
8805         np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
8806                                     res_size(&op->resource[2]),
8807                                     "niu vregs-1");
8808         if (!np->vir_regs_1) {
8809                 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
8810                         "aborting.\n");
8811                 err = -ENOMEM;
8812                 goto err_out_iounmap;
8813         }
8814
8815         np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
8816                                     res_size(&op->resource[3]),
8817                                     "niu vregs-2");
8818         if (!np->vir_regs_2) {
8819                 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
8820                         "aborting.\n");
8821                 err = -ENOMEM;
8822                 goto err_out_iounmap;
8823         }
8824
8825         niu_assign_netdev_ops(dev);
8826
8827         err = niu_get_invariants(np);
8828         if (err) {
8829                 if (err != -ENODEV)
8830                         dev_err(&op->dev, PFX "Problem fetching invariants "
8831                                 "of chip, aborting.\n");
8832                 goto err_out_iounmap;
8833         }
8834
8835         err = register_netdev(dev);
8836         if (err) {
8837                 dev_err(&op->dev, PFX "Cannot register net device, "
8838                         "aborting.\n");
8839                 goto err_out_iounmap;
8840         }
8841
8842         dev_set_drvdata(&op->dev, dev);
8843
8844         niu_device_announce(np);
8845
8846         return 0;
8847
8848 err_out_iounmap:
8849         if (np->vir_regs_1) {
8850                 of_iounmap(&op->resource[2], np->vir_regs_1,
8851                            res_size(&op->resource[2]));
8852                 np->vir_regs_1 = NULL;
8853         }
8854
8855         if (np->vir_regs_2) {
8856                 of_iounmap(&op->resource[3], np->vir_regs_2,
8857                            res_size(&op->resource[3]));
8858                 np->vir_regs_2 = NULL;
8859         }
8860
8861         if (np->regs) {
8862                 of_iounmap(&op->resource[1], np->regs,
8863                            res_size(&op->resource[1]));
8864                 np->regs = NULL;
8865         }
8866
8867 err_out_release_parent:
8868         niu_put_parent(np);
8869
8870 err_out_free_dev:
8871         free_netdev(dev);
8872
8873 err_out:
8874         return err;
8875 }
8876
8877 static int __devexit niu_of_remove(struct of_device *op)
8878 {
8879         struct net_device *dev = dev_get_drvdata(&op->dev);
8880
8881         if (dev) {
8882                 struct niu *np = netdev_priv(dev);
8883
8884                 unregister_netdev(dev);
8885
8886                 if (np->vir_regs_1) {
8887                         of_iounmap(&op->resource[2], np->vir_regs_1,
8888                                    res_size(&op->resource[2]));
8889                         np->vir_regs_1 = NULL;
8890                 }
8891
8892                 if (np->vir_regs_2) {
8893                         of_iounmap(&op->resource[3], np->vir_regs_2,
8894                                    res_size(&op->resource[3]));
8895                         np->vir_regs_2 = NULL;
8896                 }
8897
8898                 if (np->regs) {
8899                         of_iounmap(&op->resource[1], np->regs,
8900                                    res_size(&op->resource[1]));
8901                         np->regs = NULL;
8902                 }
8903
8904                 niu_ldg_free(np);
8905
8906                 niu_put_parent(np);
8907
8908                 free_netdev(dev);
8909                 dev_set_drvdata(&op->dev, NULL);
8910         }
8911         return 0;
8912 }
8913
8914 static struct of_device_id niu_match[] = {
8915         {
8916                 .name = "network",
8917                 .compatible = "SUNW,niusl",
8918         },
8919         {},
8920 };
8921 MODULE_DEVICE_TABLE(of, niu_match);
8922
8923 static struct of_platform_driver niu_of_driver = {
8924         .name           = "niu",
8925         .match_table    = niu_match,
8926         .probe          = niu_of_probe,
8927         .remove         = __devexit_p(niu_of_remove),
8928 };
8929
8930 #endif /* CONFIG_SPARC64 */
8931
8932 static int __init niu_init(void)
8933 {
8934         int err = 0;
8935
8936         BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
8937
8938         niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
8939
8940 #ifdef CONFIG_SPARC64
8941         err = of_register_driver(&niu_of_driver, &of_bus_type);
8942 #endif
8943
8944         if (!err) {
8945                 err = pci_register_driver(&niu_pci_driver);
8946 #ifdef CONFIG_SPARC64
8947                 if (err)
8948                         of_unregister_driver(&niu_of_driver);
8949 #endif
8950         }
8951
8952         return err;
8953 }
8954
8955 static void __exit niu_exit(void)
8956 {
8957         pci_unregister_driver(&niu_pci_driver);
8958 #ifdef CONFIG_SPARC64
8959         of_unregister_driver(&niu_of_driver);
8960 #endif
8961 }
8962
8963 module_init(niu_init);
8964 module_exit(niu_exit);