git.oblomov.eu Git - linux-2.6/blob - arch/sparc/kernel/irq_64.c

   1 /* irq.c: UltraSparc IRQ handling/init/registry.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/sched.h>
  10 #include <linux/linkage.h>
  11 #include <linux/ptrace.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/signal.h>
  15 #include <linux/mm.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/slab.h>
  18 #include <linux/random.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/bootmem.h>
  24 #include <linux/irq.h>
  25
  26 #include <asm/ptrace.h>
  27 #include <asm/processor.h>
  28 #include <asm/atomic.h>
  29 #include <asm/system.h>
  30 #include <asm/irq.h>
  31 #include <asm/io.h>
  32 #include <asm/iommu.h>
  33 #include <asm/upa.h>
  34 #include <asm/oplib.h>
  35 #include <asm/prom.h>
  36 #include <asm/timer.h>
  37 #include <asm/smp.h>
  38 #include <asm/starfire.h>
  39 #include <asm/uaccess.h>
  40 #include <asm/cache.h>
  41 #include <asm/cpudata.h>
  42 #include <asm/auxio.h>
  43 #include <asm/head.h>
  44 #include <asm/hypervisor.h>
  45 #include <asm/cacheflush.h>
  46
  47 #include "entry.h"
  48 #include "cpumap.h"
  49
  50 #define NUM_IVECS       (IMAP_INR + 1)
  51
  52 struct ino_bucket *ivector_table;
  53 unsigned long ivector_table_pa;
  54
  55 /* On several sun4u processors, it is illegal to mix bypass and
  56  * non-bypass accesses.  Therefore we access all INO buckets
  57  * using bypass accesses only.
  58  */
  59 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  60 {
  61         unsigned long ret;
  62
  63         __asm__ __volatile__("ldxa      [%1] %2, %0"
  64                              : "=&r" (ret)
  65                              : "r" (bucket_pa +
  66                                     offsetof(struct ino_bucket,
  67                                              __irq_chain_pa)),
  68                                "i" (ASI_PHYS_USE_EC));
  69
  70         return ret;
  71 }
  72
  73 static void bucket_clear_chain_pa(unsigned long bucket_pa)
  74 {
  75         __asm__ __volatile__("stxa      %%g0, [%0] %1"
  76                              : /* no outputs */
  77                              : "r" (bucket_pa +
  78                                     offsetof(struct ino_bucket,
  79                                              __irq_chain_pa)),
  80                                "i" (ASI_PHYS_USE_EC));
  81 }
  82
  83 static unsigned int bucket_get_virt_irq(unsigned long bucket_pa)
  84 {
  85         unsigned int ret;
  86
  87         __asm__ __volatile__("lduwa     [%1] %2, %0"
  88                              : "=&r" (ret)
  89                              : "r" (bucket_pa +
  90                                     offsetof(struct ino_bucket,
  91                                              __virt_irq)),
  92                                "i" (ASI_PHYS_USE_EC));
  93
  94         return ret;
  95 }
  96
  97 static void bucket_set_virt_irq(unsigned long bucket_pa,
  98                                 unsigned int virt_irq)
  99 {
 100         __asm__ __volatile__("stwa      %0, [%1] %2"
 101                              : /* no outputs */
 102                              : "r" (virt_irq),
 103                                "r" (bucket_pa +
 104                                     offsetof(struct ino_bucket,
 105                                              __virt_irq)),
 106                                "i" (ASI_PHYS_USE_EC));
 107 }
 108
 109 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
 110
 111 static struct {
 112         unsigned int dev_handle;
 113         unsigned int dev_ino;
 114         unsigned int in_use;
 115 } virt_irq_table[NR_IRQS];
 116 static DEFINE_SPINLOCK(virt_irq_alloc_lock);
 117
 118 unsigned char virt_irq_alloc(unsigned int dev_handle,
 119                              unsigned int dev_ino)
 120 {
 121         unsigned long flags;
 122         unsigned char ent;
 123
 124         BUILD_BUG_ON(NR_IRQS >= 256);
 125
 126         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
 127
 128         for (ent = 1; ent < NR_IRQS; ent++) {
 129                 if (!virt_irq_table[ent].in_use)
 130                         break;
 131         }
 132         if (ent >= NR_IRQS) {
 133                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
 134                 ent = 0;
 135         } else {
 136                 virt_irq_table[ent].dev_handle = dev_handle;
 137                 virt_irq_table[ent].dev_ino = dev_ino;
 138                 virt_irq_table[ent].in_use = 1;
 139         }
 140
 141         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
 142
 143         return ent;
 144 }
 145
 146 #ifdef CONFIG_PCI_MSI
 147 void virt_irq_free(unsigned int virt_irq)
 148 {
 149         unsigned long flags;
 150
 151         if (virt_irq >= NR_IRQS)
 152                 return;
 153
 154         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
 155
 156         virt_irq_table[virt_irq].in_use = 0;
 157
 158         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
 159 }
 160 #endif
 161
 162 /*
 163  * /proc/interrupts printing:
 164  */
 165
 166 int show_interrupts(struct seq_file *p, void *v)
 167 {
 168         int i = *(loff_t *) v, j;
 169         struct irqaction * action;
 170         unsigned long flags;
 171
 172         if (i == 0) {
 173                 seq_printf(p, "           ");
 174                 for_each_online_cpu(j)
 175                         seq_printf(p, "CPU%d       ",j);
 176                 seq_putc(p, '\n');
 177         }
 178
 179         if (i < NR_IRQS) {
 180                 spin_lock_irqsave(&irq_desc[i].lock, flags);
 181                 action = irq_desc[i].action;
 182                 if (!action)
 183                         goto skip;
 184                 seq_printf(p, "%3d: ",i);
 185 #ifndef CONFIG_SMP
 186                 seq_printf(p, "%10u ", kstat_irqs(i));
 187 #else
 188                 for_each_online_cpu(j)
 189                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
 190 #endif
 191                 seq_printf(p, " %9s", irq_desc[i].chip->typename);
 192                 seq_printf(p, "  %s", action->name);
 193
 194                 for (action=action->next; action; action = action->next)
 195                         seq_printf(p, ", %s", action->name);
 196
 197                 seq_putc(p, '\n');
 198 skip:
 199                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 200         } else if (i == NR_IRQS) {
 201                 seq_printf(p, "NMI: ");
 202                 for_each_online_cpu(j)
 203                         seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
 204                 seq_printf(p, "     Non-maskable interrupts\n");
 205         }
 206         return 0;
 207 }
 208
 209 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 210 {
 211         unsigned int tid;
 212
 213         if (this_is_starfire) {
 214                 tid = starfire_translate(imap, cpuid);
 215                 tid <<= IMAP_TID_SHIFT;
 216                 tid &= IMAP_TID_UPA;
 217         } else {
 218                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 219                         unsigned long ver;
 220
 221                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 222                         if ((ver >> 32UL) == __JALAPENO_ID ||
 223                             (ver >> 32UL) == __SERRANO_ID) {
 224                                 tid = cpuid << IMAP_TID_SHIFT;
 225                                 tid &= IMAP_TID_JBUS;
 226                         } else {
 227                                 unsigned int a = cpuid & 0x1f;
 228                                 unsigned int n = (cpuid >> 5) & 0x1f;
 229
 230                                 tid = ((a << IMAP_AID_SHIFT) |
 231                                        (n << IMAP_NID_SHIFT));
 232                                 tid &= (IMAP_AID_SAFARI |
 233                                         IMAP_NID_SAFARI);;
 234                         }
 235                 } else {
 236                         tid = cpuid << IMAP_TID_SHIFT;
 237                         tid &= IMAP_TID_UPA;
 238                 }
 239         }
 240
 241         return tid;
 242 }
 243
 244 struct irq_handler_data {
 245         unsigned long   iclr;
 246         unsigned long   imap;
 247
 248         void            (*pre_handler)(unsigned int, void *, void *);
 249         void            *arg1;
 250         void            *arg2;
 251 };
 252
 253 #ifdef CONFIG_SMP
 254 static int irq_choose_cpu(unsigned int virt_irq)
 255 {
 256         cpumask_t mask;
 257         int cpuid;
 258
 259         cpumask_copy(&mask, irq_desc[virt_irq].affinity);
 260         if (cpus_equal(mask, cpu_online_map)) {
 261                 cpuid = map_to_cpu(virt_irq);
 262         } else {
 263                 cpumask_t tmp;
 264
 265                 cpus_and(tmp, cpu_online_map, mask);
 266                 cpuid = cpus_empty(tmp) ? map_to_cpu(virt_irq) : first_cpu(tmp);
 267         }
 268
 269         return cpuid;
 270 }
 271 #else
 272 static int irq_choose_cpu(unsigned int virt_irq)
 273 {
 274         return real_hard_smp_processor_id();
 275 }
 276 #endif
 277
 278 static void sun4u_irq_enable(unsigned int virt_irq)
 279 {
 280         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 281
 282         if (likely(data)) {
 283                 unsigned long cpuid, imap, val;
 284                 unsigned int tid;
 285
 286                 cpuid = irq_choose_cpu(virt_irq);
 287                 imap = data->imap;
 288
 289                 tid = sun4u_compute_tid(imap, cpuid);
 290
 291                 val = upa_readq(imap);
 292                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 293                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 294                 val |= tid | IMAP_VALID;
 295                 upa_writeq(val, imap);
 296                 upa_writeq(ICLR_IDLE, data->iclr);
 297         }
 298 }
 299
 300 static int sun4u_set_affinity(unsigned int virt_irq,
 301                                const struct cpumask *mask)
 302 {
 303         sun4u_irq_enable(virt_irq);
 304
 305         return 0;
 306 }
 307
 308 /* Don't do anything.  The desc->status check for IRQ_DISABLED in
 309  * handler_irq() will skip the handler call and that will leave the
 310  * interrupt in the sent state.  The next ->enable() call will hit the
 311  * ICLR register to reset the state machine.
 312  *
 313  * This scheme is necessary, instead of clearing the Valid bit in the
 314  * IMAP register, to handle the case of IMAP registers being shared by
 315  * multiple INOs (and thus ICLR registers).  Since we use a different
 316  * virtual IRQ for each shared IMAP instance, the generic code thinks
 317  * there is only one user so it prematurely calls ->disable() on
 318  * free_irq().
 319  *
 320  * We have to provide an explicit ->disable() method instead of using
 321  * NULL to get the default.  The reason is that if the generic code
 322  * sees that, it also hooks up a default ->shutdown method which
 323  * invokes ->mask() which we do not want.  See irq_chip_set_defaults().
 324  */
 325 static void sun4u_irq_disable(unsigned int virt_irq)
 326 {
 327 }
 328
 329 static void sun4u_irq_eoi(unsigned int virt_irq)
 330 {
 331         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 332         struct irq_desc *desc = irq_desc + virt_irq;
 333
 334         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 335                 return;
 336
 337         if (likely(data))
 338                 upa_writeq(ICLR_IDLE, data->iclr);
 339 }
 340
 341 static void sun4v_irq_enable(unsigned int virt_irq)
 342 {
 343         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 344         unsigned long cpuid = irq_choose_cpu(virt_irq);
 345         int err;
 346
 347         err = sun4v_intr_settarget(ino, cpuid);
 348         if (err != HV_EOK)
 349                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 350                        "err(%d)\n", ino, cpuid, err);
 351         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 352         if (err != HV_EOK)
 353                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 354                        "err(%d)\n", ino, err);
 355         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 356         if (err != HV_EOK)
 357                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
 358                        ino, err);
 359 }
 360
 361 static int sun4v_set_affinity(unsigned int virt_irq,
 362                                const struct cpumask *mask)
 363 {
 364         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 365         unsigned long cpuid = irq_choose_cpu(virt_irq);
 366         int err;
 367
 368         err = sun4v_intr_settarget(ino, cpuid);
 369         if (err != HV_EOK)
 370                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 371                        "err(%d)\n", ino, cpuid, err);
 372
 373         return 0;
 374 }
 375
 376 static void sun4v_irq_disable(unsigned int virt_irq)
 377 {
 378         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 379         int err;
 380
 381         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 382         if (err != HV_EOK)
 383                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
 384                        "err(%d)\n", ino, err);
 385 }
 386
 387 static void sun4v_irq_eoi(unsigned int virt_irq)
 388 {
 389         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 390         struct irq_desc *desc = irq_desc + virt_irq;
 391         int err;
 392
 393         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 394                 return;
 395
 396         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 397         if (err != HV_EOK)
 398                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 399                        "err(%d)\n", ino, err);
 400 }
 401
 402 static void sun4v_virq_enable(unsigned int virt_irq)
 403 {
 404         unsigned long cpuid, dev_handle, dev_ino;
 405         int err;
 406
 407         cpuid = irq_choose_cpu(virt_irq);
 408
 409         dev_handle = virt_irq_table[virt_irq].dev_handle;
 410         dev_ino = virt_irq_table[virt_irq].dev_ino;
 411
 412         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 413         if (err != HV_EOK)
 414                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 415                        "err(%d)\n",
 416                        dev_handle, dev_ino, cpuid, err);
 417         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 418                                     HV_INTR_STATE_IDLE);
 419         if (err != HV_EOK)
 420                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 421                        "HV_INTR_STATE_IDLE): err(%d)\n",
 422                        dev_handle, dev_ino, err);
 423         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 424                                     HV_INTR_ENABLED);
 425         if (err != HV_EOK)
 426                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 427                        "HV_INTR_ENABLED): err(%d)\n",
 428                        dev_handle, dev_ino, err);
 429 }
 430
 431 static int sun4v_virt_set_affinity(unsigned int virt_irq,
 432                                     const struct cpumask *mask)
 433 {
 434         unsigned long cpuid, dev_handle, dev_ino;
 435         int err;
 436
 437         cpuid = irq_choose_cpu(virt_irq);
 438
 439         dev_handle = virt_irq_table[virt_irq].dev_handle;
 440         dev_ino = virt_irq_table[virt_irq].dev_ino;
 441
 442         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 443         if (err != HV_EOK)
 444                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 445                        "err(%d)\n",
 446                        dev_handle, dev_ino, cpuid, err);
 447
 448         return 0;
 449 }
 450
 451 static void sun4v_virq_disable(unsigned int virt_irq)
 452 {
 453         unsigned long dev_handle, dev_ino;
 454         int err;
 455
 456         dev_handle = virt_irq_table[virt_irq].dev_handle;
 457         dev_ino = virt_irq_table[virt_irq].dev_ino;
 458
 459         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 460                                     HV_INTR_DISABLED);
 461         if (err != HV_EOK)
 462                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 463                        "HV_INTR_DISABLED): err(%d)\n",
 464                        dev_handle, dev_ino, err);
 465 }
 466
 467 static void sun4v_virq_eoi(unsigned int virt_irq)
 468 {
 469         struct irq_desc *desc = irq_desc + virt_irq;
 470         unsigned long dev_handle, dev_ino;
 471         int err;
 472
 473         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 474                 return;
 475
 476         dev_handle = virt_irq_table[virt_irq].dev_handle;
 477         dev_ino = virt_irq_table[virt_irq].dev_ino;
 478
 479         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 480                                     HV_INTR_STATE_IDLE);
 481         if (err != HV_EOK)
 482                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 483                        "HV_INTR_STATE_IDLE): err(%d)\n",
 484                        dev_handle, dev_ino, err);
 485 }
 486
 487 static struct irq_chip sun4u_irq = {
 488         .typename       = "sun4u",
 489         .enable         = sun4u_irq_enable,
 490         .disable        = sun4u_irq_disable,
 491         .eoi            = sun4u_irq_eoi,
 492         .set_affinity   = sun4u_set_affinity,
 493 };
 494
 495 static struct irq_chip sun4v_irq = {
 496         .typename       = "sun4v",
 497         .enable         = sun4v_irq_enable,
 498         .disable        = sun4v_irq_disable,
 499         .eoi            = sun4v_irq_eoi,
 500         .set_affinity   = sun4v_set_affinity,
 501 };
 502
 503 static struct irq_chip sun4v_virq = {
 504         .typename       = "vsun4v",
 505         .enable         = sun4v_virq_enable,
 506         .disable        = sun4v_virq_disable,
 507         .eoi            = sun4v_virq_eoi,
 508         .set_affinity   = sun4v_virt_set_affinity,
 509 };
 510
 511 static void pre_flow_handler(unsigned int virt_irq,
 512                                       struct irq_desc *desc)
 513 {
 514         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 515         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 516
 517         data->pre_handler(ino, data->arg1, data->arg2);
 518
 519         handle_fasteoi_irq(virt_irq, desc);
 520 }
 521
 522 void irq_install_pre_handler(int virt_irq,
 523                              void (*func)(unsigned int, void *, void *),
 524                              void *arg1, void *arg2)
 525 {
 526         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 527         struct irq_desc *desc = irq_desc + virt_irq;
 528
 529         data->pre_handler = func;
 530         data->arg1 = arg1;
 531         data->arg2 = arg2;
 532
 533         desc->handle_irq = pre_flow_handler;
 534 }
 535
 536 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 537 {
 538         struct ino_bucket *bucket;
 539         struct irq_handler_data *data;
 540         unsigned int virt_irq;
 541         int ino;
 542
 543         BUG_ON(tlb_type == hypervisor);
 544
 545         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 546         bucket = &ivector_table[ino];
 547         virt_irq = bucket_get_virt_irq(__pa(bucket));
 548         if (!virt_irq) {
 549                 virt_irq = virt_irq_alloc(0, ino);
 550                 bucket_set_virt_irq(__pa(bucket), virt_irq);
 551                 set_irq_chip_and_handler_name(virt_irq,
 552                                               &sun4u_irq,
 553                                               handle_fasteoi_irq,
 554                                               "IVEC");
 555         }
 556
 557         data = get_irq_chip_data(virt_irq);
 558         if (unlikely(data))
 559                 goto out;
 560
 561         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 562         if (unlikely(!data)) {
 563                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 564                 prom_halt();
 565         }
 566         set_irq_chip_data(virt_irq, data);
 567
 568         data->imap  = imap;
 569         data->iclr  = iclr;
 570
 571 out:
 572         return virt_irq;
 573 }
 574
 575 static unsigned int sun4v_build_common(unsigned long sysino,
 576                                        struct irq_chip *chip)
 577 {
 578         struct ino_bucket *bucket;
 579         struct irq_handler_data *data;
 580         unsigned int virt_irq;
 581
 582         BUG_ON(tlb_type != hypervisor);
 583
 584         bucket = &ivector_table[sysino];
 585         virt_irq = bucket_get_virt_irq(__pa(bucket));
 586         if (!virt_irq) {
 587                 virt_irq = virt_irq_alloc(0, sysino);
 588                 bucket_set_virt_irq(__pa(bucket), virt_irq);
 589                 set_irq_chip_and_handler_name(virt_irq, chip,
 590                                               handle_fasteoi_irq,
 591                                               "IVEC");
 592         }
 593
 594         data = get_irq_chip_data(virt_irq);
 595         if (unlikely(data))
 596                 goto out;
 597
 598         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 599         if (unlikely(!data)) {
 600                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 601                 prom_halt();
 602         }
 603         set_irq_chip_data(virt_irq, data);
 604
 605         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 606          * is done by hypervisor calls on sun4v platforms, not by direct
 607          * register accesses.
 608          */
 609         data->imap = ~0UL;
 610         data->iclr = ~0UL;
 611
 612 out:
 613         return virt_irq;
 614 }
 615
 616 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 617 {
 618         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
 619
 620         return sun4v_build_common(sysino, &sun4v_irq);
 621 }
 622
 623 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
 624 {
 625         struct irq_handler_data *data;
 626         unsigned long hv_err, cookie;
 627         struct ino_bucket *bucket;
 628         struct irq_desc *desc;
 629         unsigned int virt_irq;
 630
 631         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
 632         if (unlikely(!bucket))
 633                 return 0;
 634         __flush_dcache_range((unsigned long) bucket,
 635                              ((unsigned long) bucket +
 636                               sizeof(struct ino_bucket)));
 637
 638         virt_irq = virt_irq_alloc(devhandle, devino);
 639         bucket_set_virt_irq(__pa(bucket), virt_irq);
 640
 641         set_irq_chip_and_handler_name(virt_irq, &sun4v_virq,
 642                                       handle_fasteoi_irq,
 643                                       "IVEC");
 644
 645         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 646         if (unlikely(!data))
 647                 return 0;
 648
 649         /* In order to make the LDC channel startup sequence easier,
 650          * especially wrt. locking, we do not let request_irq() enable
 651          * the interrupt.
 652          */
 653         desc = irq_desc + virt_irq;
 654         desc->status |= IRQ_NOAUTOEN;
 655
 656         set_irq_chip_data(virt_irq, data);
 657
 658         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 659          * is done by hypervisor calls on sun4v platforms, not by direct
 660          * register accesses.
 661          */
 662         data->imap = ~0UL;
 663         data->iclr = ~0UL;
 664
 665         cookie = ~__pa(bucket);
 666         hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
 667         if (hv_err) {
 668                 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
 669                             "err=%lu\n", devhandle, devino, hv_err);
 670                 prom_halt();
 671         }
 672
 673         return virt_irq;
 674 }
 675
 676 void ack_bad_irq(unsigned int virt_irq)
 677 {
 678         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 679
 680         if (!ino)
 681                 ino = 0xdeadbeef;
 682
 683         printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
 684                ino, virt_irq);
 685 }
 686
 687 void *hardirq_stack[NR_CPUS];
 688 void *softirq_stack[NR_CPUS];
 689
 690 static __attribute__((always_inline)) void *set_hardirq_stack(void)
 691 {
 692         void *orig_sp, *sp = hardirq_stack[smp_processor_id()];
 693
 694         __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp));
 695         if (orig_sp < sp ||
 696             orig_sp > (sp + THREAD_SIZE)) {
 697                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 698                 __asm__ __volatile__("mov %0, %%sp" : : "r" (sp));
 699         }
 700
 701         return orig_sp;
 702 }
 703 static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp)
 704 {
 705         __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp));
 706 }
 707
 708 void handler_irq(int irq, struct pt_regs *regs)
 709 {
 710         unsigned long pstate, bucket_pa;
 711         struct pt_regs *old_regs;
 712         void *orig_sp;
 713
 714         clear_softint(1 << irq);
 715
 716         old_regs = set_irq_regs(regs);
 717         irq_enter();
 718
 719         /* Grab an atomic snapshot of the pending IVECs.  */
 720         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
 721                              "wrpr      %0, %3, %%pstate\n\t"
 722                              "ldx       [%2], %1\n\t"
 723                              "stx       %%g0, [%2]\n\t"
 724                              "wrpr      %0, 0x0, %%pstate\n\t"
 725                              : "=&r" (pstate), "=&r" (bucket_pa)
 726                              : "r" (irq_work_pa(smp_processor_id())),
 727                                "i" (PSTATE_IE)
 728                              : "memory");
 729
 730         orig_sp = set_hardirq_stack();
 731
 732         while (bucket_pa) {
 733                 struct irq_desc *desc;
 734                 unsigned long next_pa;
 735                 unsigned int virt_irq;
 736
 737                 next_pa = bucket_get_chain_pa(bucket_pa);
 738                 virt_irq = bucket_get_virt_irq(bucket_pa);
 739                 bucket_clear_chain_pa(bucket_pa);
 740
 741                 desc = irq_desc + virt_irq;
 742
 743                 if (!(desc->status & IRQ_DISABLED))
 744                         desc->handle_irq(virt_irq, desc);
 745
 746                 bucket_pa = next_pa;
 747         }
 748
 749         restore_hardirq_stack(orig_sp);
 750
 751         irq_exit();
 752         set_irq_regs(old_regs);
 753 }
 754
 755 void do_softirq(void)
 756 {
 757         unsigned long flags;
 758
 759         if (in_interrupt())
 760                 return;
 761
 762         local_irq_save(flags);
 763
 764         if (local_softirq_pending()) {
 765                 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
 766
 767                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 768
 769                 __asm__ __volatile__("mov %%sp, %0\n\t"
 770                                      "mov %1, %%sp"
 771                                      : "=&r" (orig_sp)
 772                                      : "r" (sp));
 773                 __do_softirq();
 774                 __asm__ __volatile__("mov %0, %%sp"
 775                                      : : "r" (orig_sp));
 776         }
 777
 778         local_irq_restore(flags);
 779 }
 780
 781 #ifdef CONFIG_HOTPLUG_CPU
 782 void fixup_irqs(void)
 783 {
 784         unsigned int irq;
 785
 786         for (irq = 0; irq < NR_IRQS; irq++) {
 787                 unsigned long flags;
 788
 789                 spin_lock_irqsave(&irq_desc[irq].lock, flags);
 790                 if (irq_desc[irq].action &&
 791                     !(irq_desc[irq].status & IRQ_PER_CPU)) {
 792                         if (irq_desc[irq].chip->set_affinity)
 793                                 irq_desc[irq].chip->set_affinity(irq,
 794                                         irq_desc[irq].affinity);
 795                 }
 796                 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
 797         }
 798
 799         tick_ops->disable_irq();
 800 }
 801 #endif
 802
 803 struct sun5_timer {
 804         u64     count0;
 805         u64     limit0;
 806         u64     count1;
 807         u64     limit1;
 808 };
 809
 810 static struct sun5_timer *prom_timers;
 811 static u64 prom_limit0, prom_limit1;
 812
 813 static void map_prom_timers(void)
 814 {
 815         struct device_node *dp;
 816         const unsigned int *addr;
 817
 818         /* PROM timer node hangs out in the top level of device siblings... */
 819         dp = of_find_node_by_path("/");
 820         dp = dp->child;
 821         while (dp) {
 822                 if (!strcmp(dp->name, "counter-timer"))
 823                         break;
 824                 dp = dp->sibling;
 825         }
 826
 827         /* Assume if node is not present, PROM uses different tick mechanism
 828          * which we should not care about.
 829          */
 830         if (!dp) {
 831                 prom_timers = (struct sun5_timer *) 0;
 832                 return;
 833         }
 834
 835         /* If PROM is really using this, it must be mapped by him. */
 836         addr = of_get_property(dp, "address", NULL);
 837         if (!addr) {
 838                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 839                 prom_timers = (struct sun5_timer *) 0;
 840                 return;
 841         }
 842         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 843 }
 844
 845 static void kill_prom_timer(void)
 846 {
 847         if (!prom_timers)
 848                 return;
 849
 850         /* Save them away for later. */
 851         prom_limit0 = prom_timers->limit0;
 852         prom_limit1 = prom_timers->limit1;
 853
 854         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 855          * We turn both off here just to be paranoid.
 856          */
 857         prom_timers->limit0 = 0;
 858         prom_timers->limit1 = 0;
 859
 860         /* Wheee, eat the interrupt packet too... */
 861         __asm__ __volatile__(
 862 "       mov     0x40, %%g2\n"
 863 "       ldxa    [%%g0] %0, %%g1\n"
 864 "       ldxa    [%%g2] %1, %%g1\n"
 865 "       stxa    %%g0, [%%g0] %0\n"
 866 "       membar  #Sync\n"
 867         : /* no outputs */
 868         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 869         : "g1", "g2");
 870 }
 871
 872 void notrace init_irqwork_curcpu(void)
 873 {
 874         int cpu = hard_smp_processor_id();
 875
 876         trap_block[cpu].irq_worklist_pa = 0UL;
 877 }
 878
 879 /* Please be very careful with register_one_mondo() and
 880  * sun4v_register_mondo_queues().
 881  *
 882  * On SMP this gets invoked from the CPU trampoline before
 883  * the cpu has fully taken over the trap table from OBP,
 884  * and it's kernel stack + %g6 thread register state is
 885  * not fully cooked yet.
 886  *
 887  * Therefore you cannot make any OBP calls, not even prom_printf,
 888  * from these two routines.
 889  */
 890 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
 891 {
 892         unsigned long num_entries = (qmask + 1) / 64;
 893         unsigned long status;
 894
 895         status = sun4v_cpu_qconf(type, paddr, num_entries);
 896         if (status != HV_EOK) {
 897                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 898                             "err %lu\n", type, paddr, num_entries, status);
 899                 prom_halt();
 900         }
 901 }
 902
 903 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
 904 {
 905         struct trap_per_cpu *tb = &trap_block[this_cpu];
 906
 907         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
 908                            tb->cpu_mondo_qmask);
 909         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
 910                            tb->dev_mondo_qmask);
 911         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
 912                            tb->resum_qmask);
 913         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
 914                            tb->nonresum_qmask);
 915 }
 916
 917 static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask)
 918 {
 919         unsigned long size = PAGE_ALIGN(qmask + 1);
 920         void *p = __alloc_bootmem(size, size, 0);
 921         if (!p) {
 922                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
 923                 prom_halt();
 924         }
 925
 926         *pa_ptr = __pa(p);
 927 }
 928
 929 static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask)
 930 {
 931         unsigned long size = PAGE_ALIGN(qmask + 1);
 932         void *p = __alloc_bootmem(size, size, 0);
 933
 934         if (!p) {
 935                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
 936                 prom_halt();
 937         }
 938
 939         *pa_ptr = __pa(p);
 940 }
 941
 942 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
 943 {
 944 #ifdef CONFIG_SMP
 945         void *page;
 946
 947         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 948
 949         page = alloc_bootmem_pages(PAGE_SIZE);
 950         if (!page) {
 951                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 952                 prom_halt();
 953         }
 954
 955         tb->cpu_mondo_block_pa = __pa(page);
 956         tb->cpu_list_pa = __pa(page + 64);
 957 #endif
 958 }
 959
 960 /* Allocate mondo and error queues for all possible cpus.  */
 961 static void __init sun4v_init_mondo_queues(void)
 962 {
 963         int cpu;
 964
 965         for_each_possible_cpu(cpu) {
 966                 struct trap_per_cpu *tb = &trap_block[cpu];
 967
 968                 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
 969                 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
 970                 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask);
 971                 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask);
 972                 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
 973                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
 974                                tb->nonresum_qmask);
 975         }
 976 }
 977
 978 static void __init init_send_mondo_info(void)
 979 {
 980         int cpu;
 981
 982         for_each_possible_cpu(cpu) {
 983                 struct trap_per_cpu *tb = &trap_block[cpu];
 984
 985                 init_cpu_send_mondo_info(tb);
 986         }
 987 }
 988
 989 static struct irqaction timer_irq_action = {
 990         .name = "timer",
 991 };
 992
 993 /* Only invoked on boot processor. */
 994 void __init init_IRQ(void)
 995 {
 996         unsigned long size;
 997
 998         map_prom_timers();
 999         kill_prom_timer();
1000
1001         size = sizeof(struct ino_bucket) * NUM_IVECS;
1002         ivector_table = alloc_bootmem(size);
1003         if (!ivector_table) {
1004                 prom_printf("Fatal error, cannot allocate ivector_table\n");
1005                 prom_halt();
1006         }
1007         __flush_dcache_range((unsigned long) ivector_table,
1008                              ((unsigned long) ivector_table) + size);
1009
1010         ivector_table_pa = __pa(ivector_table);
1011
1012         if (tlb_type == hypervisor)
1013                 sun4v_init_mondo_queues();
1014
1015         init_send_mondo_info();
1016
1017         if (tlb_type == hypervisor) {
1018                 /* Load up the boot cpu's entries.  */
1019                 sun4v_register_mondo_queues(hard_smp_processor_id());
1020         }
1021
1022         /* We need to clear any IRQ's pending in the soft interrupt
1023          * registers, a spurious one could be left around from the
1024          * PROM timer which we just disabled.
1025          */
1026         clear_softint(get_softint());
1027
1028         /* Now that ivector table is initialized, it is safe
1029          * to receive IRQ vector traps.  We will normally take
1030          * one or two right now, in case some device PROM used
1031          * to boot us wants to speak to us.  We just ignore them.
1032          */
1033         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1034                              "or        %%g1, %0, %%g1\n\t"
1035                              "wrpr      %%g1, 0x0, %%pstate"
1036                              : /* No outputs */
1037                              : "i" (PSTATE_IE)
1038                              : "g1");
1039
1040         irq_desc[0].action = &timer_irq_action;
1041 }