2 STB0899 Multistandard Frontend driver
3 Copyright (C) Manu Abraham (abraham.manu@gmail.com)
5 Copyright (C) ST Microelectronics
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include "stb0899_drv.h"
23 #include "stb0899_priv.h"
24 #include "stb0899_reg.h"
28 * float division with integer
30 static long BinaryFloatDiv(long n1, long n2, int precision)
35 while (i <= precision) {
40 result = result * 2 + 1;
53 static u32 stb0899_calc_srate(u32 master_clk, u8 *sfr)
57 mclk = master_clk / 4096L; /* MasterClock * 10 / 2^20 */
58 tmp = (((u32) sfr[0] << 12) + ((u32) sfr[1] << 4)) / 16;
62 tmp2 = ((u32) sfr[2] * mclk) / 256;
70 * Get the current symbol rate
72 u32 stb0899_get_srate(struct stb0899_state *state)
74 struct stb0899_internal *internal = &state->internal;
77 stb0899_read_regs(state, STB0899_SFRH, sfr, 3);
79 return stb0899_calc_srate(internal->master_clk, sfr);
84 * Set symbol frequency
85 * MasterClock: master clock frequency (hz)
86 * SymbolRate: symbol rate (bauds)
87 * return symbol frequency
89 static u32 stb0899_set_srate(struct stb0899_state *state, u32 master_clk, u32 srate)
91 u32 tmp, tmp_up, srate_up;
95 dprintk(state->verbose, FE_DEBUG, 1, "-->");
97 * in order to have the maximum precision, the symbol rate entered into
98 * the chip is computed as the closest value of the "true value".
99 * In this purpose, the symbol rate value is rounded (1 is added on the bit
102 // srate_up += (srate_up * 3) / 100;
104 tmp = BinaryFloatDiv(srate, master_clk, 20);
105 // tmp_up = BinaryFloatDiv(srate_up, master_clk, 20);
107 // sfr_up[0] = (tmp_up >> 12) & 0xff;
108 // sfr_up[1] = (tmp_up >> 4) & 0xff;
109 // sfr_up[2] = tmp_up & 0x0f;
111 sfr[0] = (tmp >> 12) & 0xff;
112 sfr[1] = (tmp >> 4) & 0xff;
115 // stb0899_write_regs(state, STB0899_SFRUPH, sfr_up, 3);
116 stb0899_write_regs(state, STB0899_SFRH, sfr, 3);
122 * stb0899_calc_loop_time
123 * Compute the amount of time needed by the timing loop to lock
124 * SymbolRate: Symbol rate
125 * return: timing loop time constant (ms)
127 static long stb0899_calc_loop_time(long srate)
130 return (100000 / (srate / 1000));
136 * stb0899_calc_derot_time
137 * Compute the amount of time needed by the derotator to lock
138 * SymbolRate: Symbol rate
139 * return: derotator time constant (ms)
141 static long stb0899_calc_derot_time(long srate)
144 return (100000 / (srate / 1000));
151 * Compute the width of the carrier
152 * return: width of carrier (kHz or Mhz)
154 long stb0899_carr_width(struct stb0899_state *state)
156 struct stb0899_internal *internal = &state->internal;
158 return (internal->srate + (internal->srate * internal->rolloff) / 100);
162 * stb0899_first_subrange
163 * Compute the first subrange of the search
165 static void stb0899_first_subrange(struct stb0899_state *state)
167 struct stb0899_internal *internal = &state->internal;
168 struct stb0899_params *params = &state->params;
169 struct stb0899_config *config = state->config;
174 if (config->tuner_get_bandwidth) {
175 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
176 range = bandwidth - stb0899_carr_width(state) / 2;
180 internal->sub_range = MIN(internal->srch_range, range);
182 internal->sub_range = 0;
184 internal->freq = params->freq;
185 internal->tuner_offst = 0L;
186 internal->sub_dir = 1;
191 * check for timing lock
192 * internal.Ttiming: time to wait for loop lock
194 static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state)
196 struct stb0899_internal *internal = &state->internal;
201 msleep(internal->t_timing);
203 reg = stb0899_read_reg(state, STB0899_RTF);
204 STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0xf2);
205 stb0899_write_reg(state, STB0899_RTF, reg);
206 reg = stb0899_read_reg(state, STB0899_TLIR);
207 lock = STB0899_GETFIELD(TLIR_TMG_LOCK_IND, reg);
208 timing = stb0899_read_reg(state, STB0899_RTF);
211 if ((lock > 48) && (ABS(timing) >= 110)) {
212 internal->status = ANALOGCARRIER;
213 dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !");
215 internal->status = TIMINGOK;
216 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK !");
219 internal->status = NOTIMING;
220 dprintk(state->verbose, FE_DEBUG, 1, "-->NO TIMING !");
222 return internal->status;
227 * perform a fs/2 zig-zag to find timing
229 static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state)
231 struct stb0899_internal *internal = &state->internal;
232 struct stb0899_params *params = &state->params;
234 short int derot_step, derot_freq = 0, derot_limit, next_loop = 3;
238 internal->status = NOTIMING;
240 /* timing loop computation & symbol rate optimisation */
241 derot_limit = (internal->sub_range / 2L) / internal->mclk;
242 derot_step = (params->srate / 2L) / internal->mclk;
244 while ((stb0899_check_tmg(state) != TIMINGOK) && next_loop) {
246 derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */
248 if (ABS(derot_freq) > derot_limit)
252 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
253 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
254 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
256 internal->direction = -internal->direction; /* Change zigzag direction */
259 if (internal->status == TIMINGOK) {
260 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
261 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
262 dprintk(state->verbose, FE_DEBUG, 1, "------->TIMING OK ! Derot Freq = %d", internal->derot_freq);
265 return internal->status;
269 * stb0899_check_carrier
270 * Check for carrier found
272 static enum stb0899_status stb0899_check_carrier(struct stb0899_state *state)
274 struct stb0899_internal *internal = &state->internal;
277 msleep(internal->t_derot); /* wait for derotator ok */
279 reg = stb0899_read_reg(state, STB0899_CFD);
280 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
281 stb0899_write_reg(state, STB0899_CFD, reg);
283 reg = stb0899_read_reg(state, STB0899_DSTATUS);
284 dprintk(state->verbose, FE_DEBUG, 1, "--------------------> STB0899_DSTATUS=[0x%02x]", reg);
285 if (STB0899_GETFIELD(CARRIER_FOUND, reg)) {
286 internal->status = CARRIEROK;
287 dprintk(state->verbose, FE_DEBUG, 1, "-------------> CARRIEROK !");
289 internal->status = NOCARRIER;
290 dprintk(state->verbose, FE_DEBUG, 1, "-------------> NOCARRIER !");
293 return internal->status;
297 * stb0899_search_carrier
298 * Search for a QPSK carrier with the derotator
300 static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state)
302 struct stb0899_internal *internal = &state->internal;
304 short int derot_freq = 0, last_derot_freq = 0, derot_limit, next_loop = 3;
309 internal->status = NOCARRIER;
310 derot_limit = (internal->sub_range / 2L) / internal->mclk;
311 derot_freq = internal->derot_freq;
313 reg = stb0899_read_reg(state, STB0899_CFD);
314 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
315 stb0899_write_reg(state, STB0899_CFD, reg);
318 dprintk(state->verbose, FE_DEBUG, 1, "Derot Freq=%d, mclk=%d", derot_freq, internal->mclk);
319 if (stb0899_check_carrier(state) == NOCARRIER) {
321 last_derot_freq = derot_freq;
322 derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */
324 if(ABS(derot_freq) > derot_limit)
328 reg = stb0899_read_reg(state, STB0899_CFD);
329 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
330 stb0899_write_reg(state, STB0899_CFD, reg);
332 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
333 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
334 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
338 internal->direction = -internal->direction; /* Change zigzag direction */
339 } while ((internal->status != CARRIEROK) && next_loop);
341 if (internal->status == CARRIEROK) {
342 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
343 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
344 dprintk(state->verbose, FE_DEBUG, 1, "----> CARRIER OK !, Derot Freq=%d", internal->derot_freq);
346 internal->derot_freq = last_derot_freq;
349 return internal->status;
354 * Check for data found
356 static enum stb0899_status stb0899_check_data(struct stb0899_state *state)
358 struct stb0899_internal *internal = &state->internal;
359 struct stb0899_params *params = &state->params;
361 int lock = 0, index = 0, dataTime = 500, loop;
364 internal->status = NODATA;
367 reg = stb0899_read_reg(state, STB0899_TSTRES);
368 STB0899_SETFIELD_VAL(FRESACS, reg, 1);
369 stb0899_write_reg(state, STB0899_TSTRES, reg);
371 reg = stb0899_read_reg(state, STB0899_TSTRES);
372 STB0899_SETFIELD_VAL(FRESACS, reg, 0);
373 stb0899_write_reg(state, STB0899_TSTRES, reg);
375 if (params->srate <= 2000000)
377 else if (params->srate <= 5000000)
379 else if (params->srate <= 15000000)
384 stb0899_write_reg(state, STB0899_DSTATUS2, 0x00); /* force search loop */
386 /* WARNING! VIT LOCKED has to be tested before VIT_END_LOOOP */
387 reg = stb0899_read_reg(state, STB0899_VSTATUS);
388 lock = STB0899_GETFIELD(VSTATUS_LOCKEDVIT, reg);
389 loop = STB0899_GETFIELD(VSTATUS_END_LOOPVIT, reg);
391 if (lock || loop || (index > dataTime))
396 if (lock) { /* DATA LOCK indicator */
397 internal->status = DATAOK;
398 dprintk(state->verbose, FE_DEBUG, 1, "-----------------> DATA OK !");
401 return internal->status;
405 * stb0899_search_data
406 * Search for a QPSK carrier with the derotator
408 static enum stb0899_status stb0899_search_data(struct stb0899_state *state)
410 short int derot_freq, derot_step, derot_limit, next_loop = 3;
415 struct stb0899_internal *internal = &state->internal;
416 struct stb0899_params *params = &state->params;
418 derot_step = (params->srate / 4L) / internal->mclk;
419 derot_limit = (internal->sub_range / 2L) / internal->mclk;
420 derot_freq = internal->derot_freq;
423 if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) {
425 derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */
426 if (ABS(derot_freq) > derot_limit)
430 dprintk(state->verbose, FE_DEBUG, 1, "Derot freq=%d, mclk=%d", derot_freq, internal->mclk);
431 reg = stb0899_read_reg(state, STB0899_CFD);
432 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
433 stb0899_write_reg(state, STB0899_CFD, reg);
435 STB0899_SETFIELD_VAL(CFRM, cfr[0], MSB(state->config->inversion * derot_freq));
436 STB0899_SETFIELD_VAL(CFRL, cfr[1], LSB(state->config->inversion * derot_freq));
437 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* derotator frequency */
439 stb0899_check_carrier(state);
443 internal->direction = -internal->direction; /* change zig zag direction */
444 } while ((internal->status != DATAOK) && next_loop);
446 if (internal->status == DATAOK) {
447 stb0899_read_regs(state, STB0899_CFRM, cfr, 2); /* get derotator frequency */
448 internal->derot_freq = state->config->inversion * MAKEWORD16(cfr[0], cfr[1]);
449 dprintk(state->verbose, FE_DEBUG, 1, "------> DATAOK ! Derot Freq=%d", internal->derot_freq);
452 return internal->status;
456 * stb0899_check_range
457 * check if the found frequency is in the correct range
459 static enum stb0899_status stb0899_check_range(struct stb0899_state *state)
461 struct stb0899_internal *internal = &state->internal;
462 struct stb0899_params *params = &state->params;
464 int range_offst, tp_freq;
466 range_offst = internal->srch_range / 2000;
467 tp_freq = internal->freq + (internal->derot_freq * internal->mclk) / 1000;
469 if ((tp_freq >= params->freq - range_offst) && (tp_freq <= params->freq + range_offst)) {
470 internal->status = RANGEOK;
471 dprintk(state->verbose, FE_DEBUG, 1, "----> RANGEOK !");
473 internal->status = OUTOFRANGE;
474 dprintk(state->verbose, FE_DEBUG, 1, "----> OUT OF RANGE !");
477 return internal->status;
482 * Compute the next subrange of the search
484 static void next_sub_range(struct stb0899_state *state)
486 struct stb0899_internal *internal = &state->internal;
487 struct stb0899_params *params = &state->params;
491 if (internal->sub_dir > 0) {
492 old_sub_range = internal->sub_range;
493 internal->sub_range = MIN((internal->srch_range / 2) -
494 (internal->tuner_offst + internal->sub_range / 2),
495 internal->sub_range);
497 if (internal->sub_range < 0)
498 internal->sub_range = 0;
500 internal->tuner_offst += (old_sub_range + internal->sub_range) / 2;
503 internal->freq = params->freq + (internal->sub_dir * internal->tuner_offst) / 1000;
504 internal->sub_dir = -internal->sub_dir;
509 * Search for a signal, timing, carrier and data for a
510 * given frequency in a given range
512 enum stb0899_status stb0899_dvbs_algo(struct stb0899_state *state)
514 struct stb0899_params *params = &state->params;
515 struct stb0899_internal *internal = &state->internal;
516 struct stb0899_config *config = state->config;
524 /* BETA values rated @ 99MHz */
525 s32 betaTab[5][4] = {
527 { 37, 34, 32, 31 }, /* QPSK 1/2 */
528 { 37, 35, 33, 31 }, /* QPSK 2/3 */
529 { 37, 35, 33, 31 }, /* QPSK 3/4 */
530 { 37, 36, 33, 32 }, /* QPSK 5/6 */
531 { 37, 36, 33, 32 } /* QPSK 7/8 */
534 internal->direction = 1;
536 stb0899_set_srate(state, internal->master_clk, params->srate);
537 /* Carrier loop optimization versus symbol rate for acquisition*/
538 if (params->srate <= 5000000) {
539 stb0899_write_reg(state, STB0899_ACLC, 0x89);
540 bclc = stb0899_read_reg(state, STB0899_BCLC);
541 STB0899_SETFIELD_VAL(BETA, bclc, 0x1c);
542 stb0899_write_reg(state, STB0899_BCLC, bclc);
544 } else if (params->srate <= 15000000) {
545 stb0899_write_reg(state, STB0899_ACLC, 0xc9);
546 bclc = stb0899_read_reg(state, STB0899_BCLC);
547 STB0899_SETFIELD_VAL(BETA, bclc, 0x22);
548 stb0899_write_reg(state, STB0899_BCLC, bclc);
550 } else if(params->srate <= 25000000) {
551 stb0899_write_reg(state, STB0899_ACLC, 0x89);
552 bclc = stb0899_read_reg(state, STB0899_BCLC);
553 STB0899_SETFIELD_VAL(BETA, bclc, 0x27);
554 stb0899_write_reg(state, STB0899_BCLC, bclc);
557 stb0899_write_reg(state, STB0899_ACLC, 0xc8);
558 bclc = stb0899_read_reg(state, STB0899_BCLC);
559 STB0899_SETFIELD_VAL(BETA, bclc, 0x29);
560 stb0899_write_reg(state, STB0899_BCLC, bclc);
564 dprintk(state->verbose, FE_DEBUG, 1, "Set the timing loop to acquisition");
565 /* Set the timing loop to acquisition */
566 stb0899_write_reg(state, STB0899_RTC, 0x46);
567 stb0899_write_reg(state, STB0899_CFD, 0xee);
570 * Do not read any status variables while acquisition,
571 * If any needed, read before the acquisition starts
572 * querying status while acquiring causes the
573 * acquisition to go bad and hence no locks.
575 dprintk(state->verbose, FE_DEBUG, 1, "Derot Percent=%d Srate=%d mclk=%d",
576 internal->derot_percent, params->srate, internal->mclk);
578 /* Initial calculations */
579 internal->derot_step = internal->derot_percent * (params->srate / 1000L) / internal->mclk; /* DerotStep/1000 * Fsymbol */
580 internal->t_timing = stb0899_calc_loop_time(params->srate);
581 internal->t_derot = stb0899_calc_derot_time(params->srate);
582 internal->t_data = 500;
584 dprintk(state->verbose, FE_DEBUG, 1, "RESET stream merger");
585 /* RESET Stream merger */
586 reg = stb0899_read_reg(state, STB0899_TSTRES);
587 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
588 stb0899_write_reg(state, STB0899_TSTRES, reg);
591 * Set KDIVIDER to an intermediate value between
592 * 1/2 and 7/8 for acquisition
594 reg = stb0899_read_reg(state, STB0899_DEMAPVIT);
595 STB0899_SETFIELD_VAL(DEMAPVIT_KDIVIDER, reg, 60);
596 stb0899_write_reg(state, STB0899_DEMAPVIT, reg);
598 stb0899_write_reg(state, STB0899_EQON, 0x01); /* Equalizer OFF while acquiring */
599 stb0899_write_reg(state, STB0899_VITSYNC, 0x19);
601 stb0899_first_subrange(state);
603 /* Initialisations */
605 stb0899_write_regs(state, STB0899_CFRM, cfr, 2); /* RESET derotator frequency */
607 reg = stb0899_read_reg(state, STB0899_RTF);
608 STB0899_SETFIELD_VAL(RTF_TIMING_LOOP_FREQ, reg, 0);
609 stb0899_write_reg(state, STB0899_RTF, reg);
610 reg = stb0899_read_reg(state, STB0899_CFD);
611 STB0899_SETFIELD_VAL(CFD_ON, reg, 1);
612 stb0899_write_reg(state, STB0899_CFD, reg);
614 internal->derot_freq = 0;
615 internal->status = NOAGC1;
617 /* Move tuner to frequency */
618 dprintk(state->verbose, FE_DEBUG, 1, "Tuner set frequency");
619 if (state->config->tuner_set_frequency)
620 state->config->tuner_set_frequency(&state->frontend, internal->freq);
622 if (state->config->tuner_get_frequency)
623 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
625 msleep(internal->t_agc1 + internal->t_agc2 + internal->t_timing); /* AGC1, AGC2 and timing loop */
626 dprintk(state->verbose, FE_DEBUG, 1, "current derot freq=%d", internal->derot_freq);
627 internal->status = AGC1OK;
629 /* There is signal in the band */
630 if (config->tuner_get_bandwidth)
631 config->tuner_get_bandwidth(&state->frontend, &bandwidth);
632 if (params->srate <= bandwidth / 2)
633 stb0899_search_tmg(state); /* For low rates (SCPC) */
635 stb0899_check_tmg(state); /* For high rates (MCPC) */
637 if (internal->status == TIMINGOK) {
638 dprintk(state->verbose, FE_DEBUG, 1,
639 "TIMING OK ! Derot freq=%d, mclk=%d",
640 internal->derot_freq, internal->mclk);
642 if (stb0899_search_carrier(state) == CARRIEROK) { /* Search for carrier */
643 dprintk(state->verbose, FE_DEBUG, 1,
644 "CARRIER OK ! Derot freq=%d, mclk=%d",
645 internal->derot_freq, internal->mclk);
647 if (stb0899_search_data(state) == DATAOK) { /* Check for data */
648 dprintk(state->verbose, FE_DEBUG, 1,
649 "DATA OK ! Derot freq=%d, mclk=%d",
650 internal->derot_freq, internal->mclk);
652 if (stb0899_check_range(state) == RANGEOK) {
653 dprintk(state->verbose, FE_DEBUG, 1,
654 "RANGE OK ! derot freq=%d, mclk=%d",
655 internal->derot_freq, internal->mclk);
657 internal->freq = params->freq + ((internal->derot_freq * internal->mclk) / 1000);
658 reg = stb0899_read_reg(state, STB0899_PLPARM);
659 internal->fecrate = STB0899_GETFIELD(VITCURPUN, reg);
660 dprintk(state->verbose, FE_DEBUG, 1,
661 "freq=%d, internal resultant freq=%d",
662 params->freq, internal->freq);
664 dprintk(state->verbose, FE_DEBUG, 1,
665 "internal puncture rate=%d",
671 if (internal->status != RANGEOK)
672 next_sub_range(state);
674 } while (internal->sub_range && internal->status != RANGEOK);
676 /* Set the timing loop to tracking */
677 stb0899_write_reg(state, STB0899_RTC, 0x33);
678 stb0899_write_reg(state, STB0899_CFD, 0xf7);
679 /* if locked and range ok, set Kdiv */
680 if (internal->status == RANGEOK) {
681 dprintk(state->verbose, FE_DEBUG, 1, "Locked & Range OK !");
682 stb0899_write_reg(state, STB0899_EQON, 0x41); /* Equalizer OFF while acquiring */
683 stb0899_write_reg(state, STB0899_VITSYNC, 0x39); /* SN to b'11 for acquisition */
686 * Carrier loop optimization versus
687 * symbol Rate/Puncture Rate for Tracking
689 reg = stb0899_read_reg(state, STB0899_BCLC);
690 switch (internal->fecrate) {
691 case STB0899_FEC_1_2: /* 13 */
692 stb0899_write_reg(state, STB0899_DEMAPVIT, 0x1a);
693 STB0899_SETFIELD_VAL(BETA, reg, betaTab[0][clnI]);
694 stb0899_write_reg(state, STB0899_BCLC, reg);
696 case STB0899_FEC_2_3: /* 18 */
697 stb0899_write_reg(state, STB0899_DEMAPVIT, 44);
698 STB0899_SETFIELD_VAL(BETA, reg, betaTab[1][clnI]);
699 stb0899_write_reg(state, STB0899_BCLC, reg);
701 case STB0899_FEC_3_4: /* 21 */
702 stb0899_write_reg(state, STB0899_DEMAPVIT, 60);
703 STB0899_SETFIELD_VAL(BETA, reg, betaTab[2][clnI]);
704 stb0899_write_reg(state, STB0899_BCLC, reg);
706 case STB0899_FEC_5_6: /* 24 */
707 stb0899_write_reg(state, STB0899_DEMAPVIT, 75);
708 STB0899_SETFIELD_VAL(BETA, reg, betaTab[3][clnI]);
709 stb0899_write_reg(state, STB0899_BCLC, reg);
711 case STB0899_FEC_6_7: /* 25 */
712 stb0899_write_reg(state, STB0899_DEMAPVIT, 88);
713 stb0899_write_reg(state, STB0899_ACLC, 0x88);
714 stb0899_write_reg(state, STB0899_BCLC, 0x9a);
716 case STB0899_FEC_7_8: /* 26 */
717 stb0899_write_reg(state, STB0899_DEMAPVIT, 94);
718 STB0899_SETFIELD_VAL(BETA, reg, betaTab[4][clnI]);
719 stb0899_write_reg(state, STB0899_BCLC, reg);
722 dprintk(state->verbose, FE_DEBUG, 1, "Unsupported Puncture Rate");
725 /* release stream merger RESET */
726 reg = stb0899_read_reg(state, STB0899_TSTRES);
727 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
728 stb0899_write_reg(state, STB0899_TSTRES, reg);
730 /* disable carrier detector */
731 reg = stb0899_read_reg(state, STB0899_CFD);
732 STB0899_SETFIELD_VAL(CFD_ON, reg, 0);
733 stb0899_write_reg(state, STB0899_CFD, reg);
735 stb0899_read_regs(state, STB0899_EQUAI1, eq_const, 10);
738 return internal->status;
742 * stb0899_dvbs2_config_uwp
743 * Configure UWP state machine
745 static void stb0899_dvbs2_config_uwp(struct stb0899_state *state)
747 struct stb0899_internal *internal = &state->internal;
748 struct stb0899_config *config = state->config;
749 u32 uwp1, uwp2, uwp3, reg;
751 uwp1 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL1);
752 uwp2 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL2);
753 uwp3 = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_CNTRL3);
755 STB0899_SETFIELD_VAL(UWP_ESN0_AVE, uwp1, config->esno_ave);
756 STB0899_SETFIELD_VAL(UWP_ESN0_QUANT, uwp1, config->esno_quant);
757 STB0899_SETFIELD_VAL(UWP_TH_SOF, uwp1, config->uwp_threshold_sof);
759 STB0899_SETFIELD_VAL(FE_COARSE_TRK, uwp2, internal->av_frame_coarse);
760 STB0899_SETFIELD_VAL(FE_FINE_TRK, uwp2, internal->av_frame_fine);
761 STB0899_SETFIELD_VAL(UWP_MISS_TH, uwp2, config->miss_threshold);
763 STB0899_SETFIELD_VAL(UWP_TH_ACQ, uwp3, config->uwp_threshold_acq);
764 STB0899_SETFIELD_VAL(UWP_TH_TRACK, uwp3, config->uwp_threshold_track);
766 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL1, STB0899_OFF0_UWP_CNTRL1, uwp1);
767 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL2, STB0899_OFF0_UWP_CNTRL2, uwp2);
768 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_UWP_CNTRL3, STB0899_OFF0_UWP_CNTRL3, uwp3);
770 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, SOF_SRCH_TO);
771 STB0899_SETFIELD_VAL(SOF_SEARCH_TIMEOUT, reg, config->sof_search_timeout);
772 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_SOF_SRCH_TO, STB0899_OFF0_SOF_SRCH_TO, reg);
776 * stb0899_dvbs2_config_csm_auto
777 * Set CSM to AUTO mode
779 static void stb0899_dvbs2_config_csm_auto(struct stb0899_state *state)
783 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
784 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, reg, 1);
785 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, reg);
788 long Log2Int(int number)
793 while ((1 << i) <= ABS(number))
803 * stb0899_dvbs2_calc_srate
804 * compute BTR_NOM_FREQ for the symbol rate
806 static u32 stb0899_dvbs2_calc_srate(struct stb0899_state *state)
808 struct stb0899_internal *internal = &state->internal;
809 struct stb0899_config *config = state->config;
811 u32 dec_ratio, dec_rate, decim, remain, intval, btr_nom_freq;
812 u32 master_clk, srate;
814 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
815 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
816 dec_rate = Log2Int(dec_ratio);
817 decim = 1 << dec_rate;
818 master_clk = internal->master_clk / 1000;
819 srate = internal->srate / 1000;
822 intval = (decim * (1 << (config->btr_nco_bits - 1))) / master_clk;
823 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
825 intval = (1 << (config->btr_nco_bits - 1)) / (master_clk / 100) * decim / 100;
826 remain = (decim * (1 << (config->btr_nco_bits - 1))) % master_clk;
828 btr_nom_freq = (intval * srate) + ((remain * srate) / master_clk);
834 * stb0899_dvbs2_calc_dev
835 * compute the correction to be applied to symbol rate
837 static u32 stb0899_dvbs2_calc_dev(struct stb0899_state *state)
839 struct stb0899_internal *internal = &state->internal;
840 u32 dec_ratio, correction, master_clk, srate;
842 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
843 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
845 master_clk = internal->master_clk / 1000; /* for integer Caculation*/
846 srate = internal->srate / 1000; /* for integer Caculation*/
847 correction = (512 * master_clk) / (2 * dec_ratio * srate);
853 * stb0899_dvbs2_set_srate
854 * Set DVBS2 symbol rate
856 static void stb0899_dvbs2_set_srate(struct stb0899_state *state)
858 struct stb0899_internal *internal = &state->internal;
860 u32 dec_ratio, dec_rate, win_sel, decim, f_sym, btr_nom_freq;
861 u32 correction, freq_adj, band_lim, decim_cntrl, reg;
864 /*set decimation to 1*/
865 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
866 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
867 dec_rate = Log2Int(dec_ratio);
871 win_sel = dec_rate - 4;
873 decim = (1 << dec_rate);
874 /* (FSamp/Fsymbol *100) for integer Caculation */
875 f_sym = internal->master_clk / ((decim * internal->srate) / 1000);
877 if (f_sym <= 2250) /* don't band limit signal going into btr block*/
880 band_lim = 0; /* band limit signal going into btr block*/
882 decim_cntrl = ((win_sel << 3) & 0x18) + ((band_lim << 5) & 0x20) + (dec_rate & 0x7);
883 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DECIM_CNTRL, STB0899_OFF0_DECIM_CNTRL, decim_cntrl);
887 else if (f_sym <= 4250)
892 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ANTI_ALIAS_SEL, STB0899_OFF0_ANTI_ALIAS_SEL, anti_alias);
893 btr_nom_freq = stb0899_dvbs2_calc_srate(state);
894 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_NOM_FREQ, STB0899_OFF0_BTR_NOM_FREQ, btr_nom_freq);
896 correction = stb0899_dvbs2_calc_dev(state);
897 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
898 STB0899_SETFIELD_VAL(BTR_FREQ_CORR, reg, correction);
899 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
901 /* scale UWP+CSM frequency to sample rate*/
902 freq_adj = internal->srate / (internal->master_clk / 4096);
903 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_FREQ_ADJ_SCALE, STB0899_OFF0_FREQ_ADJ_SCALE, freq_adj);
907 * stb0899_dvbs2_set_btr_loopbw
908 * set bit timing loop bandwidth as a percentage of the symbol rate
910 static void stb0899_dvbs2_set_btr_loopbw(struct stb0899_state *state)
912 struct stb0899_internal *internal = &state->internal;
913 struct stb0899_config *config = state->config;
915 u32 sym_peak = 23, zeta = 707, loopbw_percent = 60;
916 s32 dec_ratio, dec_rate, k_btr1_rshft, k_btr1, k_btr0_rshft;
917 s32 k_btr0, k_btr2_rshft, k_direct_shift, k_indirect_shift;
918 u32 decim, K, wn, k_direct, k_indirect;
921 dec_ratio = (internal->master_clk * 2) / (5 * internal->srate);
922 dec_ratio = (dec_ratio == 0) ? 1 : dec_ratio;
923 dec_rate = Log2Int(dec_ratio);
924 decim = (1 << dec_rate);
927 K = (1 << config->btr_nco_bits) / (internal->master_clk / 1000);
928 K *= (internal->srate / 1000000) * decim; /*k=k 10^-8*/
932 wn = (4 * zeta * zeta) + 1000000;
933 wn = (2 * (loopbw_percent * 1000) * 40 * zeta) /wn; /*wn =wn 10^-8*/
935 k_indirect = (wn * wn) / K;
936 k_indirect = k_indirect; /*kindirect = kindirect 10^-6*/
937 k_direct = (2 * wn * zeta) / K; /*kDirect = kDirect 10^-2*/
940 k_direct_shift = Log2Int(k_direct) - Log2Int(10000) - 2;
941 k_btr1_rshft = (-1 * k_direct_shift) + config->btr_gain_shift_offset;
942 k_btr1 = k_direct / (1 << k_direct_shift);
945 k_indirect_shift = Log2Int(k_indirect + 15) - 20 /*- 2*/;
946 k_btr0_rshft = (-1 * k_indirect_shift) + config->btr_gain_shift_offset;
947 k_btr0 = k_indirect * (1 << (-k_indirect_shift));
951 if (k_btr0_rshft > 15) {
952 k_btr2_rshft = k_btr0_rshft - 15;
955 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_LOOP_GAIN);
956 STB0899_SETFIELD_VAL(KBTR0_RSHFT, reg, k_btr0_rshft);
957 STB0899_SETFIELD_VAL(KBTR0, reg, k_btr0);
958 STB0899_SETFIELD_VAL(KBTR1_RSHFT, reg, k_btr1_rshft);
959 STB0899_SETFIELD_VAL(KBTR1, reg, k_btr1);
960 STB0899_SETFIELD_VAL(KBTR2_RSHFT, reg, k_btr2_rshft);
961 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, reg);
963 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_LOOP_GAIN, STB0899_OFF0_BTR_LOOP_GAIN, 0xc4c4f);
967 * stb0899_dvbs2_set_carr_freq
968 * set nominal frequency for carrier search
970 static void stb0899_dvbs2_set_carr_freq(struct stb0899_state *state, s32 carr_freq, u32 master_clk)
972 struct stb0899_config *config = state->config;
976 crl_nom_freq = (1 << config->crl_nco_bits) / master_clk;
977 crl_nom_freq *= carr_freq;
978 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
979 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, crl_nom_freq);
980 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
984 * stb0899_dvbs2_init_calc
985 * Initialize DVBS2 UWP, CSM, carrier and timing loops
987 static void stb0899_dvbs2_init_calc(struct stb0899_state *state)
989 struct stb0899_internal *internal = &state->internal;
990 s32 steps, step_size;
993 /* config uwp and csm */
994 stb0899_dvbs2_config_uwp(state);
995 stb0899_dvbs2_config_csm_auto(state);
998 stb0899_dvbs2_set_srate(state);
999 stb0899_dvbs2_set_btr_loopbw(state);
1001 if (internal->srate / 1000000 >= 15)
1002 step_size = (1 << 17) / 5;
1003 else if (internal->srate / 1000000 >= 10)
1004 step_size = (1 << 17) / 7;
1005 else if (internal->srate / 1000000 >= 5)
1006 step_size = (1 << 17) / 10;
1008 step_size = (1 << 17) / 4;
1010 range = internal->srch_range / 1000000;
1011 steps = (10 * range * (1 << 17)) / (step_size * (internal->srate / 1000000));
1012 steps = (steps + 6) / 10;
1013 steps = (steps == 0) ? 1 : steps;
1015 stb0899_dvbs2_set_carr_freq(state, internal->center_freq -
1016 (internal->step_size * (internal->srate / 20000000)),
1017 (internal->master_clk) / 1000000);
1019 stb0899_dvbs2_set_carr_freq(state, internal->center_freq, (internal->master_clk) / 1000000);
1021 /*Set Carrier Search params (zigzag, num steps and freq step size*/
1022 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, ACQ_CNTRL2);
1023 STB0899_SETFIELD_VAL(ZIGZAG, reg, 1);
1024 STB0899_SETFIELD_VAL(NUM_STEPS, reg, steps);
1025 STB0899_SETFIELD_VAL(FREQ_STEPSIZE, reg, step_size);
1026 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQ_CNTRL2, STB0899_OFF0_ACQ_CNTRL2, reg);
1030 * stb0899_dvbs2_btr_init
1031 * initialize the timing loop
1033 static void stb0899_dvbs2_btr_init(struct stb0899_state *state)
1037 /* set enable BTR loopback */
1038 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_CNTRL);
1039 STB0899_SETFIELD_VAL(INTRP_PHS_SENSE, reg, 1);
1040 STB0899_SETFIELD_VAL(BTR_ERR_ENA, reg, 1);
1041 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_CNTRL, STB0899_OFF0_BTR_CNTRL, reg);
1043 /* fix btr freq accum at 0 */
1044 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x10000000);
1045 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_FREQ_INIT, STB0899_OFF0_BTR_FREQ_INIT, 0x00000000);
1047 /* fix btr freq accum at 0 */
1048 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x10000000);
1049 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_BTR_PHS_INIT, STB0899_OFF0_BTR_PHS_INIT, 0x00000000);
1053 * stb0899_dvbs2_reacquire
1054 * trigger a DVB-S2 acquisition
1056 static void stb0899_dvbs2_reacquire(struct stb0899_state *state)
1060 /* demod soft reset */
1061 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 1);
1062 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1064 /*Reset Timing Loop */
1065 stb0899_dvbs2_btr_init(state);
1067 /* reset Carrier loop */
1068 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, (1 << 30));
1069 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_FREQ_INIT, STB0899_OFF0_CRL_FREQ_INIT, 0);
1070 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_LOOP_GAIN, STB0899_OFF0_CRL_LOOP_GAIN, 0);
1071 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, (1 << 30));
1072 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_PHS_INIT, STB0899_OFF0_CRL_PHS_INIT, 0);
1074 /*release demod soft reset */
1076 STB0899_SETFIELD_VAL(DVBS2_RESET, reg, 0);
1077 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_RESET_CNTRL, STB0899_OFF0_RESET_CNTRL, reg);
1079 /* start acquisition process */
1080 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_ACQUIRE_TRIG, STB0899_OFF0_ACQUIRE_TRIG, 1);
1081 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_LOCK_LOST, STB0899_OFF0_LOCK_LOST, 0);
1083 /* equalizer Init */
1084 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 1);
1086 /*Start equilizer */
1087 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQUALIZER_INIT, STB0899_OFF0_EQUALIZER_INIT, 0);
1089 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1090 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0);
1091 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 0);
1092 STB0899_SETFIELD_VAL(EQ_DELAY, reg, 0x05);
1093 STB0899_SETFIELD_VAL(EQ_ADAPT_MODE, reg, 0x01);
1094 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1096 /* RESET Packet delineator */
1097 stb0899_write_reg(state, STB0899_PDELCTRL, 0x4a);
1101 * stb0899_dvbs2_get_dmd_status
1102 * get DVB-S2 Demod LOCK status
1104 static enum stb0899_status stb0899_dvbs2_get_dmd_status(struct stb0899_state *state, int timeout)
1106 int time = -10, lock = 0, uwp, csm;
1110 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STATUS);
1111 dprintk(state->verbose, FE_DEBUG, 1, "DMD_STATUS=[0x%02x]", reg);
1112 if (STB0899_GETFIELD(IF_AGC_LOCK, reg))
1113 dprintk(state->verbose, FE_DEBUG, 1, "------------->IF AGC LOCKED !");
1114 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_STAT2);
1115 dprintk(state->verbose, FE_DEBUG, 1, "----------->DMD STAT2=[0x%02x]", reg);
1116 uwp = STB0899_GETFIELD(UWP_LOCK, reg);
1117 csm = STB0899_GETFIELD(CSM_LOCK, reg);
1124 } while ((!lock) && (time <= timeout));
1127 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 LOCK !");
1128 return DVBS2_DEMOD_LOCK;
1130 return DVBS2_DEMOD_NOLOCK;
1135 * stb0899_dvbs2_get_data_lock
1138 static int stb0899_dvbs2_get_data_lock(struct stb0899_state *state, int timeout)
1140 int time = 0, lock = 0;
1143 while ((!lock) && (time < timeout)) {
1144 reg = stb0899_read_reg(state, STB0899_CFGPDELSTATUS1);
1145 dprintk(state->verbose, FE_DEBUG, 1, "---------> CFGPDELSTATUS=[0x%02x]", reg);
1146 lock = STB0899_GETFIELD(CFGPDELSTATUS_LOCK, reg);
1154 * stb0899_dvbs2_get_fec_status
1155 * get DVB-S2 FEC LOCK status
1157 static enum stb0899_status stb0899_dvbs2_get_fec_status(struct stb0899_state *state, int timeout)
1159 int time = 0, Locked;
1162 Locked = stb0899_dvbs2_get_data_lock(state, 1);
1166 } while ((!Locked) && (time < timeout));
1169 dprintk(state->verbose, FE_DEBUG, 1, "---------->DVB-S2 FEC LOCK !");
1170 return DVBS2_FEC_LOCK;
1172 return DVBS2_FEC_NOLOCK;
1178 * stb0899_dvbs2_init_csm
1179 * set parameters for manual mode
1181 static void stb0899_dvbs2_init_csm(struct stb0899_state *state, int pilots, enum stb0899_modcod modcod)
1183 struct stb0899_internal *internal = &state->internal;
1185 s32 dvt_tbl = 1, two_pass = 0, agc_gain = 6, agc_shift = 0, loop_shift = 0, phs_diff_thr = 0x80;
1186 s32 gamma_acq, gamma_rho_acq, gamma_trk, gamma_rho_trk, lock_count_thr;
1187 u32 csm1, csm2, csm3, csm4;
1189 if (((internal->master_clk / internal->srate) <= 4) && (modcod <= 11) && (pilots == 1)) {
1191 case STB0899_QPSK_12:
1193 gamma_rho_acq = 2700;
1195 gamma_rho_trk = 180;
1198 case STB0899_QPSK_35:
1200 gamma_rho_acq = 7182;
1202 gamma_rho_trk = 308;
1205 case STB0899_QPSK_23:
1207 gamma_rho_acq = 9408;
1209 gamma_rho_trk = 476;
1212 case STB0899_QPSK_34:
1214 gamma_rho_acq = 16642;
1216 gamma_rho_trk = 646;
1219 case STB0899_QPSK_45:
1221 gamma_rho_acq = 17119;
1223 gamma_rho_trk = 880;
1226 case STB0899_QPSK_56:
1228 gamma_rho_acq = 19250;
1230 gamma_rho_trk = 989;
1233 case STB0899_QPSK_89:
1235 gamma_rho_acq = 24240;
1237 gamma_rho_trk = 1176;
1240 case STB0899_QPSK_910:
1242 gamma_rho_acq = 29634;
1244 gamma_rho_trk = 1176;
1249 gamma_rho_acq = 29634;
1251 gamma_rho_trk = 1176;
1256 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1257 STB0899_SETFIELD_VAL(CSM_AUTO_PARAM, csm1, 0);
1258 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1260 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1261 csm2 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL2);
1262 csm3 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL3);
1263 csm4 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL4);
1265 STB0899_SETFIELD_VAL(CSM_DVT_TABLE, csm1, dvt_tbl);
1266 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, two_pass);
1267 STB0899_SETFIELD_VAL(CSM_AGC_GAIN, csm1, agc_gain);
1268 STB0899_SETFIELD_VAL(CSM_AGC_SHIFT, csm1, agc_shift);
1269 STB0899_SETFIELD_VAL(FE_LOOP_SHIFT, csm1, loop_shift);
1270 STB0899_SETFIELD_VAL(CSM_GAMMA_ACQ, csm2, gamma_acq);
1271 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOACQ, csm2, gamma_rho_acq);
1272 STB0899_SETFIELD_VAL(CSM_GAMMA_TRACK, csm3, gamma_trk);
1273 STB0899_SETFIELD_VAL(CSM_GAMMA_RHOTRACK, csm3, gamma_rho_trk);
1274 STB0899_SETFIELD_VAL(CSM_LOCKCOUNT_THRESH, csm4, lock_count_thr);
1275 STB0899_SETFIELD_VAL(CSM_PHASEDIFF_THRESH, csm4, phs_diff_thr);
1277 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1278 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL2, STB0899_OFF0_CSM_CNTRL2, csm2);
1279 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL3, STB0899_OFF0_CSM_CNTRL3, csm3);
1280 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL4, STB0899_OFF0_CSM_CNTRL4, csm4);
1285 * stb0899_dvbs2_get_srate
1286 * get DVB-S2 Symbol Rate
1288 static u32 stb0899_dvbs2_get_srate(struct stb0899_state *state)
1290 struct stb0899_internal *internal = &state->internal;
1291 struct stb0899_config *config = state->config;
1293 u32 bTrNomFreq, srate, decimRate, intval1, intval2, reg;
1294 int div1, div2, rem1, rem2;
1296 div1 = config->btr_nco_bits / 2;
1297 div2 = config->btr_nco_bits - div1 - 1;
1299 bTrNomFreq = STB0899_READ_S2REG(STB0899_S2DEMOD, BTR_NOM_FREQ);
1301 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DECIM_CNTRL);
1302 decimRate = STB0899_GETFIELD(DECIM_RATE, reg);
1303 decimRate = (1 << decimRate);
1305 intval1 = internal->master_clk / (1 << div1);
1306 intval2 = bTrNomFreq / (1 << div2);
1308 rem1 = internal->master_clk % (1 << div1);
1309 rem2 = bTrNomFreq % (1 << div2);
1310 /* only for integer calculation */
1311 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1));
1312 srate /= decimRate; /*symbrate = (btrnomfreq_register_val*MasterClock)/2^(27+decim_rate_field) */
1318 * stb0899_dvbs2_algo
1319 * Search for signal, timing, carrier and data for a given
1320 * frequency in a given range
1322 enum stb0899_status stb0899_dvbs2_algo(struct stb0899_state *state)
1324 struct stb0899_internal *internal = &state->internal;
1325 enum stb0899_modcod modcod;
1327 s32 offsetfreq, searchTime, FecLockTime, pilots, iqSpectrum;
1331 if (internal->srate <= 2000000) {
1332 searchTime = 5000; /* 5000 ms max time to lock UWP and CSM, SYMB <= 2Mbs */
1333 FecLockTime = 350; /* 350 ms max time to lock FEC, SYMB <= 2Mbs */
1334 } else if (internal->srate <= 5000000) {
1335 searchTime = 2500; /* 2500 ms max time to lock UWP and CSM, 2Mbs < SYMB <= 5Mbs */
1336 FecLockTime = 170; /* 170 ms max time to lock FEC, 2Mbs< SYMB <= 5Mbs */
1337 } else if (internal->srate <= 10000000) {
1338 searchTime = 1500; /* 1500 ms max time to lock UWP and CSM, 5Mbs <SYMB <= 10Mbs */
1339 FecLockTime = 80; /* 80 ms max time to lock FEC, 5Mbs< SYMB <= 10Mbs */
1340 } else if (internal->srate <= 15000000) {
1341 searchTime = 500; /* 500 ms max time to lock UWP and CSM, 10Mbs <SYMB <= 15Mbs */
1342 FecLockTime = 50; /* 50 ms max time to lock FEC, 10Mbs< SYMB <= 15Mbs */
1343 } else if (internal->srate <= 20000000) {
1344 searchTime = 300; /* 300 ms max time to lock UWP and CSM, 15Mbs < SYMB <= 20Mbs */
1345 FecLockTime = 30; /* 50 ms max time to lock FEC, 15Mbs< SYMB <= 20Mbs */
1346 } else if (internal->srate <= 25000000) {
1347 searchTime = 250; /* 250 ms max time to lock UWP and CSM, 20 Mbs < SYMB <= 25Mbs */
1348 FecLockTime = 25; /* 25 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1350 searchTime = 150; /* 150 ms max time to lock UWP and CSM, SYMB > 25Mbs */
1351 FecLockTime = 20; /* 20 ms max time to lock FEC, 20Mbs< SYMB <= 25Mbs */
1354 /* Maintain Stream Merger in reset during acquisition */
1355 reg = stb0899_read_reg(state, STB0899_TSTRES);
1356 STB0899_SETFIELD_VAL(FRESRS, reg, 1);
1357 stb0899_write_reg(state, STB0899_TSTRES, reg);
1359 /* Move tuner to frequency */
1360 if (state->config->tuner_set_frequency)
1361 state->config->tuner_set_frequency(&state->frontend, internal->freq);
1362 if (state->config->tuner_get_frequency)
1363 state->config->tuner_get_frequency(&state->frontend, &internal->freq);
1365 /* Set IF AGC to acquisition */
1366 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1367 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 4);
1368 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 32);
1369 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1371 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1372 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 0);
1373 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1375 /* Initialisation */
1376 stb0899_dvbs2_init_calc(state);
1378 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1379 switch (internal->inversion) {
1381 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 0);
1384 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1386 case IQ_SWAP_AUTO: /* use last successful search first */
1387 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, 1);
1390 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1391 stb0899_dvbs2_reacquire(state);
1393 /* Wait for demod lock (UWP and CSM) */
1394 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1396 if (internal->status == DVBS2_DEMOD_LOCK) {
1397 dprintk(state->verbose, FE_DEBUG, 1, "------------> DVB-S2 DEMOD LOCK !");
1399 /* Demod Locked, check FEC status */
1400 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1402 /*If false lock (UWP and CSM Locked but no FEC) try 3 time max*/
1403 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1404 /* Read the frequency offset*/
1405 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1407 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1408 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1409 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1410 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1411 stb0899_dvbs2_reacquire(state);
1412 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1417 if (internal->status != DVBS2_FEC_LOCK) {
1418 if (internal->inversion == IQ_SWAP_AUTO) {
1419 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1420 iqSpectrum = STB0899_GETFIELD(SPECTRUM_INVERT, reg);
1421 /* IQ Spectrum Inversion */
1422 STB0899_SETFIELD_VAL(SPECTRUM_INVERT, reg, !iqSpectrum);
1423 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_DMD_CNTRL2, STB0899_OFF0_DMD_CNTRL2, reg);
1424 /* start acquistion process */
1425 stb0899_dvbs2_reacquire(state);
1427 /* Wait for demod lock (UWP and CSM) */
1428 internal->status = stb0899_dvbs2_get_dmd_status(state, searchTime);
1429 if (internal->status == DVBS2_DEMOD_LOCK) {
1431 /* Demod Locked, check FEC */
1432 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1433 /*try thrice for false locks, (UWP and CSM Locked but no FEC) */
1434 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1435 /* Read the frequency offset*/
1436 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1438 /* Set the Nominal frequency to the found frequency offset for the next reacquire*/
1439 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_NOM_FREQ);
1440 STB0899_SETFIELD_VAL(CRL_NOM_FREQ, reg, offsetfreq);
1441 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CRL_NOM_FREQ, STB0899_OFF0_CRL_NOM_FREQ, reg);
1443 stb0899_dvbs2_reacquire(state);
1444 internal->status = stb0899_dvbs2_get_fec_status(state, searchTime);
1449 if (pParams->DVBS2State == FE_DVBS2_FEC_LOCKED)
1450 pParams->IQLocked = !iqSpectrum;
1454 if (internal->status == DVBS2_FEC_LOCK) {
1455 dprintk(state->verbose, FE_DEBUG, 1, "----------------> DVB-S2 FEC Lock !");
1456 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1457 modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1458 pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1460 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1461 (INRANGE(STB0899_QPSK_23, modcod, STB0899_QPSK_910)) &&
1464 stb0899_dvbs2_init_csm(state, pilots, modcod);
1465 /* Wait for UWP,CSM and data LOCK 20ms max */
1466 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1469 while ((internal->status != DVBS2_FEC_LOCK) && (i < 3)) {
1470 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1471 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 1);
1472 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1473 csm1 = STB0899_READ_S2REG(STB0899_S2DEMOD, CSM_CNTRL1);
1474 STB0899_SETFIELD_VAL(CSM_TWO_PASS, csm1, 0);
1475 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_CSM_CNTRL1, STB0899_OFF0_CSM_CNTRL1, csm1);
1477 internal->status = stb0899_dvbs2_get_fec_status(state, FecLockTime);
1482 if ((((10 * internal->master_clk) / (internal->srate / 10)) <= 410) &&
1483 (INRANGE(STB0899_QPSK_12, modcod, STB0899_QPSK_35)) &&
1486 /* Equalizer Disable update */
1487 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1488 STB0899_SETFIELD_VAL(EQ_DISABLE_UPDATE, reg, 1);
1489 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1492 /* slow down the Equalizer once locked */
1493 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, EQ_CNTRL);
1494 STB0899_SETFIELD_VAL(EQ_SHIFT, reg, 0x02);
1495 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_EQ_CNTRL, STB0899_OFF0_EQ_CNTRL, reg);
1497 /* Store signal parameters */
1498 offsetfreq = STB0899_READ_S2REG(STB0899_S2DEMOD, CRL_FREQ);
1500 offsetfreq = offsetfreq / ((1 << 30) / 1000);
1501 offsetfreq *= (internal->master_clk / 1000000);
1502 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, DMD_CNTRL2);
1503 if (STB0899_GETFIELD(SPECTRUM_INVERT, reg))
1506 internal->freq = internal->freq - offsetfreq;
1507 internal->srate = stb0899_dvbs2_get_srate(state);
1509 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, UWP_STAT2);
1510 internal->modcod = STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 2;
1511 internal->pilots = STB0899_GETFIELD(UWP_DECODE_MOD, reg) & 0x01;
1512 internal->frame_length = (STB0899_GETFIELD(UWP_DECODE_MOD, reg) >> 1) & 0x01;
1514 /* Set IF AGC to tracking */
1515 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL);
1516 STB0899_SETFIELD_VAL(IF_LOOP_GAIN, reg, 3);
1518 /* if QPSK 1/2,QPSK 3/5 or QPSK 2/3 set IF AGC reference to 16 otherwise 32*/
1519 if (INRANGE(STB0899_QPSK_12, internal->modcod, STB0899_QPSK_23))
1520 STB0899_SETFIELD_VAL(IF_AGC_REF, reg, 16);
1522 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL, STB0899_OFF0_IF_AGC_CNTRL, reg);
1524 reg = STB0899_READ_S2REG(STB0899_S2DEMOD, IF_AGC_CNTRL2);
1525 STB0899_SETFIELD_VAL(IF_AGC_DUMP_PER, reg, 7);
1526 stb0899_write_s2reg(state, STB0899_S2DEMOD, STB0899_BASE_IF_AGC_CNTRL2, STB0899_OFF0_IF_AGC_CNTRL2, reg);
1529 /* Release Stream Merger Reset */
1530 reg = stb0899_read_reg(state, STB0899_TSTRES);
1531 STB0899_SETFIELD_VAL(FRESRS, reg, 0);
1532 stb0899_write_reg(state, STB0899_TSTRES, reg);
1534 return internal->status;