2 * Derived from arch/powerpc/kernel/iommu.c
4 * Copyright (C) IBM Corporation, 2006
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <linux/pci_ids.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <asm/proto.h>
39 #include <asm/calgary.h>
41 #include <asm/pci-direct.h>
42 #include <asm/system.h>
46 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
47 #define PCI_VENDOR_DEVICE_ID_CALGARY \
48 (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
50 /* we need these for register space address calculation */
51 #define START_ADDRESS 0xfe000000
52 #define CHASSIS_BASE 0
53 #define ONE_BASED_CHASSIS_NUM 1
55 /* register offsets inside the host bridge space */
56 #define CALGARY_CONFIG_REG 0x0108
57 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
58 #define PHB_PLSSR_OFFSET 0x0120
59 #define PHB_CONFIG_RW_OFFSET 0x0160
60 #define PHB_IOBASE_BAR_LOW 0x0170
61 #define PHB_IOBASE_BAR_HIGH 0x0180
62 #define PHB_MEM_1_LOW 0x0190
63 #define PHB_MEM_1_HIGH 0x01A0
64 #define PHB_IO_ADDR_SIZE 0x01B0
65 #define PHB_MEM_1_SIZE 0x01C0
66 #define PHB_MEM_ST_OFFSET 0x01D0
67 #define PHB_AER_OFFSET 0x0200
68 #define PHB_CONFIG_0_HIGH 0x0220
69 #define PHB_CONFIG_0_LOW 0x0230
70 #define PHB_CONFIG_0_END 0x0240
71 #define PHB_MEM_2_LOW 0x02B0
72 #define PHB_MEM_2_HIGH 0x02C0
73 #define PHB_MEM_2_SIZE_HIGH 0x02D0
74 #define PHB_MEM_2_SIZE_LOW 0x02E0
75 #define PHB_DOSHOLE_OFFSET 0x08E0
78 #define PHB_TCE_ENABLE 0x20000000
79 #define PHB_SLOT_DISABLE 0x1C000000
80 #define PHB_DAC_DISABLE 0x01000000
81 #define PHB_MEM2_ENABLE 0x00400000
82 #define PHB_MCSR_ENABLE 0x00100000
83 /* TAR (Table Address Register) */
84 #define TAR_SW_BITS 0x0000ffffffff800fUL
85 #define TAR_VALID 0x0000000000000008UL
86 /* CSR (Channel/DMA Status Register) */
87 #define CSR_AGENT_MASK 0xffe0ffff
88 /* CCR (Calgary Configuration Register) */
89 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
91 #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
92 #define MAX_NUM_CHASSIS 8 /* max number of chassis */
93 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
94 #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
95 #define PHBS_PER_CALGARY 4
97 /* register offsets in Calgary's internal register space */
98 static const unsigned long tar_offsets[] = {
105 static const unsigned long split_queue_offsets[] = {
106 0x4870 /* SPLIT QUEUE 0 */,
107 0x5870 /* SPLIT QUEUE 1 */,
108 0x6870 /* SPLIT QUEUE 2 */,
109 0x7870 /* SPLIT QUEUE 3 */
112 static const unsigned long phb_offsets[] = {
119 /* PHB debug registers */
121 static const unsigned long phb_debug_offsets[] = {
122 0x4000 /* PHB 0 DEBUG */,
123 0x5000 /* PHB 1 DEBUG */,
124 0x6000 /* PHB 2 DEBUG */,
125 0x7000 /* PHB 3 DEBUG */
129 * STUFF register for each debug PHB,
130 * byte 1 = start bus number, byte 2 = end bus number
133 #define PHB_DEBUG_STUFF_OFFSET 0x0020
135 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
136 static int translate_empty_slots __read_mostly = 0;
137 static int calgary_detected __read_mostly = 0;
139 static struct rio_table_hdr *rio_table_hdr __initdata;
140 static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
141 static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
143 struct calgary_bus_info {
145 unsigned char translation_disabled;
150 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
152 static void tce_cache_blast(struct iommu_table *tbl);
154 /* enable this to stress test the chip's TCE cache */
155 #ifdef CONFIG_IOMMU_DEBUG
156 int debugging __read_mostly = 1;
158 static inline unsigned long verify_bit_range(unsigned long* bitmap,
159 int expected, unsigned long start, unsigned long end)
161 unsigned long idx = start;
163 BUG_ON(start >= end);
166 if (!!test_bit(idx, bitmap) != expected)
171 /* all bits have the expected value */
174 #else /* debugging is disabled */
175 int debugging __read_mostly = 0;
177 static inline unsigned long verify_bit_range(unsigned long* bitmap,
178 int expected, unsigned long start, unsigned long end)
182 #endif /* CONFIG_IOMMU_DEBUG */
184 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
188 npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
189 npages >>= PAGE_SHIFT;
194 static inline int translate_phb(struct pci_dev* dev)
196 int disabled = bus_info[dev->bus->number].translation_disabled;
200 static void iommu_range_reserve(struct iommu_table *tbl,
201 unsigned long start_addr, unsigned int npages)
205 unsigned long badbit;
207 index = start_addr >> PAGE_SHIFT;
209 /* bail out if we're asked to reserve a region we don't cover */
210 if (index >= tbl->it_size)
213 end = index + npages;
214 if (end > tbl->it_size) /* don't go off the table */
217 badbit = verify_bit_range(tbl->it_map, 0, index, end);
218 if (badbit != ~0UL) {
219 if (printk_ratelimit())
220 printk(KERN_ERR "Calgary: entry already allocated at "
221 "0x%lx tbl %p dma 0x%lx npages %u\n",
222 badbit, tbl, start_addr, npages);
225 set_bit_string(tbl->it_map, index, npages);
228 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
231 unsigned long offset;
235 offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
236 tbl->it_size, npages);
237 if (offset == ~0UL) {
238 tce_cache_blast(tbl);
239 offset = find_next_zero_string(tbl->it_map, 0,
240 tbl->it_size, npages);
241 if (offset == ~0UL) {
242 printk(KERN_WARNING "Calgary: IOMMU full.\n");
243 if (panic_on_overflow)
244 panic("Calgary: fix the allocator.\n");
246 return bad_dma_address;
250 set_bit_string(tbl->it_map, offset, npages);
251 tbl->it_hint = offset + npages;
252 BUG_ON(tbl->it_hint > tbl->it_size);
257 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
258 unsigned int npages, int direction)
260 unsigned long entry, flags;
261 dma_addr_t ret = bad_dma_address;
263 spin_lock_irqsave(&tbl->it_lock, flags);
265 entry = iommu_range_alloc(tbl, npages);
267 if (unlikely(entry == bad_dma_address))
270 /* set the return dma address */
271 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
273 /* put the TCEs in the HW table */
274 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
277 spin_unlock_irqrestore(&tbl->it_lock, flags);
282 spin_unlock_irqrestore(&tbl->it_lock, flags);
283 printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
284 "iommu %p\n", npages, tbl);
285 return bad_dma_address;
288 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
292 unsigned long badbit;
294 entry = dma_addr >> PAGE_SHIFT;
296 BUG_ON(entry + npages > tbl->it_size);
298 tce_free(tbl, entry, npages);
300 badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
301 if (badbit != ~0UL) {
302 if (printk_ratelimit())
303 printk(KERN_ERR "Calgary: bit is off at 0x%lx "
304 "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
305 badbit, tbl, dma_addr, entry, npages);
308 __clear_bit_string(tbl->it_map, entry, npages);
311 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
316 spin_lock_irqsave(&tbl->it_lock, flags);
318 __iommu_free(tbl, dma_addr, npages);
320 spin_unlock_irqrestore(&tbl->it_lock, flags);
323 static void __calgary_unmap_sg(struct iommu_table *tbl,
324 struct scatterlist *sglist, int nelems, int direction)
328 dma_addr_t dma = sglist->dma_address;
329 unsigned int dmalen = sglist->dma_length;
334 npages = num_dma_pages(dma, dmalen);
335 __iommu_free(tbl, dma, npages);
340 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
341 int nelems, int direction)
344 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
346 if (!translate_phb(to_pci_dev(dev)))
349 spin_lock_irqsave(&tbl->it_lock, flags);
351 __calgary_unmap_sg(tbl, sglist, nelems, direction);
353 spin_unlock_irqrestore(&tbl->it_lock, flags);
356 static int calgary_nontranslate_map_sg(struct device* dev,
357 struct scatterlist *sg, int nelems, int direction)
361 for (i = 0; i < nelems; i++ ) {
362 struct scatterlist *s = &sg[i];
364 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
365 s->dma_length = s->length;
370 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
371 int nelems, int direction)
373 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
380 if (!translate_phb(to_pci_dev(dev)))
381 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
383 spin_lock_irqsave(&tbl->it_lock, flags);
385 for (i = 0; i < nelems; i++ ) {
386 struct scatterlist *s = &sg[i];
389 vaddr = (unsigned long)page_address(s->page) + s->offset;
390 npages = num_dma_pages(vaddr, s->length);
392 entry = iommu_range_alloc(tbl, npages);
393 if (entry == bad_dma_address) {
394 /* makes sure unmap knows to stop */
399 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
401 /* insert into HW table */
402 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
405 s->dma_length = s->length;
408 spin_unlock_irqrestore(&tbl->it_lock, flags);
412 __calgary_unmap_sg(tbl, sg, nelems, direction);
413 for (i = 0; i < nelems; i++) {
414 sg[i].dma_address = bad_dma_address;
415 sg[i].dma_length = 0;
417 spin_unlock_irqrestore(&tbl->it_lock, flags);
421 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
422 size_t size, int direction)
424 dma_addr_t dma_handle = bad_dma_address;
427 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
429 uaddr = (unsigned long)vaddr;
430 npages = num_dma_pages(uaddr, size);
432 if (translate_phb(to_pci_dev(dev)))
433 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
435 dma_handle = virt_to_bus(vaddr);
440 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
441 size_t size, int direction)
443 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
446 if (!translate_phb(to_pci_dev(dev)))
449 npages = num_dma_pages(dma_handle, size);
450 iommu_free(tbl, dma_handle, npages);
453 void* calgary_alloc_coherent(struct device *dev, size_t size,
454 dma_addr_t *dma_handle, gfp_t flag)
458 unsigned int npages, order;
459 struct iommu_table *tbl;
461 tbl = to_pci_dev(dev)->bus->self->sysdata;
463 size = PAGE_ALIGN(size); /* size rounded up to full pages */
464 npages = size >> PAGE_SHIFT;
465 order = get_order(size);
467 /* alloc enough pages (and possibly more) */
468 ret = (void *)__get_free_pages(flag, order);
471 memset(ret, 0, size);
473 if (translate_phb(to_pci_dev(dev))) {
474 /* set up tces to cover the allocated range */
475 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
476 if (mapping == bad_dma_address)
479 *dma_handle = mapping;
480 } else /* non translated slot */
481 *dma_handle = virt_to_bus(ret);
486 free_pages((unsigned long)ret, get_order(size));
492 static struct dma_mapping_ops calgary_dma_ops = {
493 .alloc_coherent = calgary_alloc_coherent,
494 .map_single = calgary_map_single,
495 .unmap_single = calgary_unmap_single,
496 .map_sg = calgary_map_sg,
497 .unmap_sg = calgary_unmap_sg,
500 static inline void __iomem * busno_to_bbar(unsigned char num)
502 return bus_info[num].bbar;
505 static inline int busno_to_phbid(unsigned char num)
507 return bus_info[num].phbid;
510 static inline unsigned long split_queue_offset(unsigned char num)
512 size_t idx = busno_to_phbid(num);
514 return split_queue_offsets[idx];
517 static inline unsigned long tar_offset(unsigned char num)
519 size_t idx = busno_to_phbid(num);
521 return tar_offsets[idx];
524 static inline unsigned long phb_offset(unsigned char num)
526 size_t idx = busno_to_phbid(num);
528 return phb_offsets[idx];
531 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
533 unsigned long target = ((unsigned long)bar) | offset;
534 return (void __iomem*)target;
537 static void tce_cache_blast(struct iommu_table *tbl)
542 void __iomem *bbar = tbl->bbar;
543 void __iomem *target;
545 /* disable arbitration on the bus */
546 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
550 /* read plssr to ensure it got there */
551 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
554 /* poll split queues until all DMA activity is done */
555 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
559 } while ((val & 0xff) != 0xff && i < 100);
561 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
562 "continuing anyway\n");
564 /* invalidate TCE cache */
565 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
566 writeq(tbl->tar_val, target);
568 /* enable arbitration */
569 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
571 (void)readl(target); /* flush */
574 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
577 unsigned int numpages;
579 limit = limit | 0xfffff;
582 numpages = ((limit - start) >> PAGE_SHIFT);
583 iommu_range_reserve(dev->sysdata, start, numpages);
586 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
588 void __iomem *target;
589 u64 low, high, sizelow;
591 struct iommu_table *tbl = dev->sysdata;
592 unsigned char busnum = dev->bus->number;
593 void __iomem *bbar = tbl->bbar;
595 /* peripheral MEM_1 region */
596 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
597 low = be32_to_cpu(readl(target));
598 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
599 high = be32_to_cpu(readl(target));
600 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
601 sizelow = be32_to_cpu(readl(target));
603 start = (high << 32) | low;
606 calgary_reserve_mem_region(dev, start, limit);
609 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
611 void __iomem *target;
613 u64 low, high, sizelow, sizehigh;
615 struct iommu_table *tbl = dev->sysdata;
616 unsigned char busnum = dev->bus->number;
617 void __iomem *bbar = tbl->bbar;
620 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
621 val32 = be32_to_cpu(readl(target));
622 if (!(val32 & PHB_MEM2_ENABLE))
625 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
626 low = be32_to_cpu(readl(target));
627 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
628 high = be32_to_cpu(readl(target));
629 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
630 sizelow = be32_to_cpu(readl(target));
631 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
632 sizehigh = be32_to_cpu(readl(target));
634 start = (high << 32) | low;
635 limit = (sizehigh << 32) | sizelow;
637 calgary_reserve_mem_region(dev, start, limit);
641 * some regions of the IO address space do not get translated, so we
642 * must not give devices IO addresses in those regions. The regions
643 * are the 640KB-1MB region and the two PCI peripheral memory holes.
644 * Reserve all of them in the IOMMU bitmap to avoid giving them out
647 static void __init calgary_reserve_regions(struct pci_dev *dev)
651 unsigned char busnum;
653 struct iommu_table *tbl = dev->sysdata;
656 busnum = dev->bus->number;
658 /* reserve bad_dma_address in case it's a legal address */
659 iommu_range_reserve(tbl, bad_dma_address, 1);
661 /* avoid the BIOS/VGA first 640KB-1MB region */
662 start = (640 * 1024);
663 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
664 iommu_range_reserve(tbl, start, npages);
666 /* reserve the two PCI peripheral memory regions in IO space */
667 calgary_reserve_peripheral_mem_1(dev);
668 calgary_reserve_peripheral_mem_2(dev);
671 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
675 void __iomem *target;
677 struct iommu_table *tbl;
679 /* build TCE tables for each PHB */
680 ret = build_tce_table(dev, bbar);
685 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
686 tce_free(tbl, 0, tbl->it_size);
688 calgary_reserve_regions(dev);
690 /* set TARs for each PHB */
691 target = calgary_reg(bbar, tar_offset(dev->bus->number));
692 val64 = be64_to_cpu(readq(target));
694 /* zero out all TAR bits under sw control */
695 val64 &= ~TAR_SW_BITS;
698 table_phys = (u64)__pa(tbl->it_base);
701 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
702 val64 |= (u64) specified_table_size;
704 tbl->tar_val = cpu_to_be64(val64);
705 writeq(tbl->tar_val, target);
706 readq(target); /* flush */
711 static void __init calgary_free_bus(struct pci_dev *dev)
714 struct iommu_table *tbl = dev->sysdata;
715 void __iomem *target;
716 unsigned int bitmapsz;
718 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
719 val64 = be64_to_cpu(readq(target));
720 val64 &= ~TAR_SW_BITS;
721 writeq(cpu_to_be64(val64), target);
722 readq(target); /* flush */
724 bitmapsz = tbl->it_size / BITS_PER_BYTE;
725 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
731 /* Can't free bootmem allocated memory after system is up :-( */
732 bus_info[dev->bus->number].tce_space = NULL;
735 static void calgary_watchdog(unsigned long data)
737 struct pci_dev *dev = (struct pci_dev *)data;
738 struct iommu_table *tbl = dev->sysdata;
739 void __iomem *bbar = tbl->bbar;
741 void __iomem *target;
743 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
744 val32 = be32_to_cpu(readl(target));
746 /* If no error, the agent ID in the CSR is not valid */
747 if (val32 & CSR_AGENT_MASK) {
748 printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, "
749 "CSR = %#x\n", dev->bus->number, val32);
752 /* Disable bus that caused the error */
753 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
754 PHB_CONFIG_RW_OFFSET);
755 val32 = be32_to_cpu(readl(target));
756 val32 |= PHB_SLOT_DISABLE;
757 writel(cpu_to_be32(val32), target);
758 readl(target); /* flush */
760 /* Reset the timer */
761 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
765 static void __init calgary_increase_split_completion_timeout(void __iomem *bbar,
766 unsigned char busnum)
769 void __iomem *target;
770 unsigned int phb_shift = ~0; /* silence gcc */
773 switch (busno_to_phbid(busnum)) {
774 case 0: phb_shift = (63 - 19);
776 case 1: phb_shift = (63 - 23);
778 case 2: phb_shift = (63 - 27);
780 case 3: phb_shift = (63 - 35);
783 BUG_ON(busno_to_phbid(busnum));
786 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
787 val64 = be64_to_cpu(readq(target));
789 /* zero out this PHB's timer bits */
790 mask = ~(0xFUL << phb_shift);
792 val64 |= (CCR_2SEC_TIMEOUT << phb_shift);
793 writeq(cpu_to_be64(val64), target);
794 readq(target); /* flush */
797 static void __init calgary_enable_translation(struct pci_dev *dev)
800 unsigned char busnum;
801 void __iomem *target;
803 struct iommu_table *tbl;
805 busnum = dev->bus->number;
809 /* enable TCE in PHB Config Register */
810 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
811 val32 = be32_to_cpu(readl(target));
812 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
814 printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum);
815 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
818 writel(cpu_to_be32(val32), target);
819 readl(target); /* flush */
822 * Give split completion a longer timeout on bus 1 for aic94xx
823 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
826 calgary_increase_split_completion_timeout(bbar, busnum);
828 init_timer(&tbl->watchdog_timer);
829 tbl->watchdog_timer.function = &calgary_watchdog;
830 tbl->watchdog_timer.data = (unsigned long)dev;
831 mod_timer(&tbl->watchdog_timer, jiffies);
834 static void __init calgary_disable_translation(struct pci_dev *dev)
837 unsigned char busnum;
838 void __iomem *target;
840 struct iommu_table *tbl;
842 busnum = dev->bus->number;
846 /* disable TCE in PHB Config Register */
847 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
848 val32 = be32_to_cpu(readl(target));
849 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
851 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
852 writel(cpu_to_be32(val32), target);
853 readl(target); /* flush */
855 del_timer_sync(&tbl->watchdog_timer);
858 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
862 dev->bus->self = dev;
865 static int __init calgary_init_one(struct pci_dev *dev)
870 BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
872 bbar = busno_to_bbar(dev->bus->number);
873 ret = calgary_setup_tar(dev, bbar);
878 dev->bus->self = dev;
879 calgary_enable_translation(dev);
887 static int __init calgary_locate_bbars(void)
890 int rioidx, phb, bus;
892 void __iomem *target;
893 unsigned long offset;
894 u8 start_bus, end_bus;
898 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
899 struct rio_detail *rio = rio_devs[rioidx];
901 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
904 /* map entire 1MB of Calgary config space */
905 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
909 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
910 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
911 target = calgary_reg(bbar, offset);
913 val = be32_to_cpu(readl(target));
914 start_bus = (u8)((val & 0x00FF0000) >> 16);
915 end_bus = (u8)((val & 0x0000FF00) >> 8);
916 for (bus = start_bus; bus <= end_bus; bus++) {
917 bus_info[bus].bbar = bbar;
918 bus_info[bus].phbid = phb;
926 /* scan bus_info and iounmap any bbars we previously ioremap'd */
927 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
928 if (bus_info[bus].bbar)
929 iounmap(bus_info[bus].bbar);
934 static int __init calgary_init(void)
937 struct pci_dev *dev = NULL;
939 ret = calgary_locate_bbars();
944 dev = pci_get_device(PCI_VENDOR_ID_IBM,
945 PCI_DEVICE_ID_IBM_CALGARY,
949 if (!translate_phb(dev)) {
950 calgary_init_one_nontraslated(dev);
953 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
956 ret = calgary_init_one(dev);
965 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
966 PCI_DEVICE_ID_IBM_CALGARY,
970 if (!translate_phb(dev)) {
974 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
977 calgary_disable_translation(dev);
978 calgary_free_bus(dev);
979 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
985 static inline int __init determine_tce_table_size(u64 ram)
989 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
990 return specified_table_size;
993 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
994 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
995 * larger table size has twice as many entries, so shift the
996 * max ram address by 13 to divide by 8K and then look at the
997 * order of the result to choose between 0-7.
999 ret = get_order(ram >> 13);
1000 if (ret > TCE_TABLE_SIZE_8M)
1001 ret = TCE_TABLE_SIZE_8M;
1006 static int __init build_detail_arrays(void)
1009 int i, scal_detail_size, rio_detail_size;
1011 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1013 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1014 "but system has %d nodes.\n",
1015 MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1019 switch (rio_table_hdr->version){
1021 scal_detail_size = 11;
1022 rio_detail_size = 13;
1025 scal_detail_size = 12;
1026 rio_detail_size = 15;
1030 "Calgary: Invalid Rio Grande Table Version: %d\n",
1031 rio_table_hdr->version);
1035 ptr = ((unsigned long)rio_table_hdr) + 3;
1036 for (i = 0; i < rio_table_hdr->num_scal_dev;
1037 i++, ptr += scal_detail_size)
1038 scal_devs[i] = (struct scal_detail *)ptr;
1040 for (i = 0; i < rio_table_hdr->num_rio_dev;
1041 i++, ptr += rio_detail_size)
1042 rio_devs[i] = (struct rio_detail *)ptr;
1047 void __init detect_calgary(void)
1052 int calgary_found = 0;
1058 * if the user specified iommu=off or iommu=soft or we found
1059 * another HW IOMMU already, bail out.
1061 if (swiotlb || no_iommu || iommu_detected)
1064 if (!early_pci_allowed())
1067 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1069 rio_table_hdr = NULL;
1072 /* The block id is stored in the 2nd word */
1073 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1074 /* set the pointer past the offset & block id */
1075 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1078 /* The next offset is stored in the 1st word. 0 means no more */
1079 offset = *((unsigned short *)(ptr + offset));
1081 if (!rio_table_hdr) {
1082 printk(KERN_ERR "Calgary: Unable to locate "
1083 "Rio Grande Table in EBDA - bailing!\n");
1087 ret = build_detail_arrays();
1089 printk(KERN_ERR "Calgary: build_detail_arrays ret %d\n", ret);
1093 specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1095 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1097 struct calgary_bus_info *info = &bus_info[bus];
1099 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
1102 if (info->translation_disabled)
1106 * Scan the slots of the PCI bus to see if there is a device present.
1107 * The parent bus will be the zero-ith device, so start at 1.
1109 for (dev = 1; dev < 8; dev++) {
1110 val = read_pci_config(bus, dev, 0, 0);
1111 if (val != 0xffffffff || translate_empty_slots) {
1112 tbl = alloc_tce_table();
1115 info->tce_space = tbl;
1122 if (calgary_found) {
1124 calgary_detected = 1;
1125 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1126 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1127 "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1128 debugging ? "enabled" : "disabled");
1133 for (--bus; bus >= 0; --bus) {
1134 struct calgary_bus_info *info = &bus_info[bus];
1136 if (info->tce_space)
1137 free_tce_table(info->tce_space);
1141 int __init calgary_iommu_init(void)
1145 if (no_iommu || swiotlb)
1148 if (!calgary_detected)
1151 /* ok, we're trying to use Calgary - let's roll */
1152 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1154 ret = calgary_init();
1156 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1157 "falling back to no_iommu\n", ret);
1158 if (end_pfn > MAX_DMA32_PFN)
1159 printk(KERN_ERR "WARNING more than 4GB of memory, "
1160 "32bit PCI may malfunction.\n");
1165 dma_ops = &calgary_dma_ops;
1170 static int __init calgary_parse_options(char *p)
1172 unsigned int bridge;
1177 if (!strncmp(p, "64k", 3))
1178 specified_table_size = TCE_TABLE_SIZE_64K;
1179 else if (!strncmp(p, "128k", 4))
1180 specified_table_size = TCE_TABLE_SIZE_128K;
1181 else if (!strncmp(p, "256k", 4))
1182 specified_table_size = TCE_TABLE_SIZE_256K;
1183 else if (!strncmp(p, "512k", 4))
1184 specified_table_size = TCE_TABLE_SIZE_512K;
1185 else if (!strncmp(p, "1M", 2))
1186 specified_table_size = TCE_TABLE_SIZE_1M;
1187 else if (!strncmp(p, "2M", 2))
1188 specified_table_size = TCE_TABLE_SIZE_2M;
1189 else if (!strncmp(p, "4M", 2))
1190 specified_table_size = TCE_TABLE_SIZE_4M;
1191 else if (!strncmp(p, "8M", 2))
1192 specified_table_size = TCE_TABLE_SIZE_8M;
1194 len = strlen("translate_empty_slots");
1195 if (!strncmp(p, "translate_empty_slots", len))
1196 translate_empty_slots = 1;
1198 len = strlen("disable");
1199 if (!strncmp(p, "disable", len)) {
1205 bridge = simple_strtol(p, &endp, 0);
1209 if (bridge < MAX_PHB_BUS_NUM) {
1210 printk(KERN_INFO "Calgary: disabling "
1211 "translation for PHB %#x\n", bridge);
1212 bus_info[bridge].translation_disabled = 1;
1216 p = strpbrk(p, ",");
1224 __setup("calgary=", calgary_parse_options);