git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Allow hardware encryption to be disabled.
  42  */
  43 static int modparam_nohwcrypt = 0;
  44 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  45 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  46
  47 /*
  48  * Register access.
  49  * BBP and RF register require indirect register access,
  50  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  51  * These indirect registers work with busy bits,
  52  * and we will try maximal REGISTER_BUSY_COUNT times to access
  53  * the register while taking a REGISTER_BUSY_DELAY us delay
  54  * between each attampt. When the busy bit is still set at that time,
  55  * the access attempt is considered to have failed,
  56  * and we will print an error.
  57  */
  58 #define WAIT_FOR_BBP(__dev, __reg) \
  59         rt2x00pci_regbusy_read((__dev), PHY_CSR3, PHY_CSR3_BUSY, (__reg))
  60 #define WAIT_FOR_RF(__dev, __reg) \
  61         rt2x00pci_regbusy_read((__dev), PHY_CSR4, PHY_CSR4_BUSY, (__reg))
  62 #define WAIT_FOR_MCU(__dev, __reg) \
  63         rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  64                                H2M_MAILBOX_CSR_OWNER, (__reg))
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         mutex_lock(&rt2x00dev->csr_mutex);
  72
  73         /*
  74          * Wait until the BBP becomes available, afterwards we
  75          * can safely write the new data into the register.
  76          */
  77         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  78                 reg = 0;
  79                 rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  80                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  81                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  82                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  83
  84                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  85         }
  86
  87         mutex_unlock(&rt2x00dev->csr_mutex);
  88 }
  89
  90 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  91                              const unsigned int word, u8 *value)
  92 {
  93         u32 reg;
  94
  95         mutex_lock(&rt2x00dev->csr_mutex);
  96
  97         /*
  98          * Wait until the BBP becomes available, afterwards we
  99          * can safely write the read request into the register.
 100          * After the data has been written, we wait until hardware
 101          * returns the correct value, if at any time the register
 102          * doesn't become available in time, reg will be 0xffffffff
 103          * which means we return 0xff to the caller.
 104          */
 105         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 106                 reg = 0;
 107                 rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 108                 rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 109                 rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 110
 111                 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 112
 113                 WAIT_FOR_BBP(rt2x00dev, &reg);
 114         }
 115
 116         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 117
 118         mutex_unlock(&rt2x00dev->csr_mutex);
 119 }
 120
 121 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 122                              const unsigned int word, const u32 value)
 123 {
 124         u32 reg;
 125
 126         if (!word)
 127                 return;
 128
 129         mutex_lock(&rt2x00dev->csr_mutex);
 130
 131         /*
 132          * Wait until the RF becomes available, afterwards we
 133          * can safely write the new data into the register.
 134          */
 135         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 136                 reg = 0;
 137                 rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 138                 rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 139                 rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 140                 rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 141
 142                 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 143                 rt2x00_rf_write(rt2x00dev, word, value);
 144         }
 145
 146         mutex_unlock(&rt2x00dev->csr_mutex);
 147 }
 148
 149 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 150                                 const u8 command, const u8 token,
 151                                 const u8 arg0, const u8 arg1)
 152 {
 153         u32 reg;
 154
 155         mutex_lock(&rt2x00dev->csr_mutex);
 156
 157         /*
 158          * Wait until the MCU becomes available, afterwards we
 159          * can safely write the new data into the register.
 160          */
 161         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 162                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 163                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 164                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 165                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 166                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 167
 168                 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 169                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 170                 rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 171                 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 172         }
 173
 174         mutex_unlock(&rt2x00dev->csr_mutex);
 175
 176 }
 177
 178 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 179 {
 180         struct rt2x00_dev *rt2x00dev = eeprom->data;
 181         u32 reg;
 182
 183         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 184
 185         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 186         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 187         eeprom->reg_data_clock =
 188             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 189         eeprom->reg_chip_select =
 190             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 191 }
 192
 193 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg = 0;
 197
 198         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 199         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 200         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 201                            !!eeprom->reg_data_clock);
 202         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 203                            !!eeprom->reg_chip_select);
 204
 205         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 206 }
 207
 208 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 209 static const struct rt2x00debug rt61pci_rt2x00debug = {
 210         .owner  = THIS_MODULE,
 211         .csr    = {
 212                 .read           = rt2x00pci_register_read,
 213                 .write          = rt2x00pci_register_write,
 214                 .flags          = RT2X00DEBUGFS_OFFSET,
 215                 .word_base      = CSR_REG_BASE,
 216                 .word_size      = sizeof(u32),
 217                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 218         },
 219         .eeprom = {
 220                 .read           = rt2x00_eeprom_read,
 221                 .write          = rt2x00_eeprom_write,
 222                 .word_base      = EEPROM_BASE,
 223                 .word_size      = sizeof(u16),
 224                 .word_count     = EEPROM_SIZE / sizeof(u16),
 225         },
 226         .bbp    = {
 227                 .read           = rt61pci_bbp_read,
 228                 .write          = rt61pci_bbp_write,
 229                 .word_base      = BBP_BASE,
 230                 .word_size      = sizeof(u8),
 231                 .word_count     = BBP_SIZE / sizeof(u8),
 232         },
 233         .rf     = {
 234                 .read           = rt2x00_rf_read,
 235                 .write          = rt61pci_rf_write,
 236                 .word_base      = RF_BASE,
 237                 .word_size      = sizeof(u32),
 238                 .word_count     = RF_SIZE / sizeof(u32),
 239         },
 240 };
 241 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 242
 243 #ifdef CONFIG_RT2X00_LIB_RFKILL
 244 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 245 {
 246         u32 reg;
 247
 248         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 249         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 250 }
 251 #else
 252 #define rt61pci_rfkill_poll     NULL
 253 #endif /* CONFIG_RT2X00_LIB_RFKILL */
 254
 255 #ifdef CONFIG_RT2X00_LIB_LEDS
 256 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 257                                    enum led_brightness brightness)
 258 {
 259         struct rt2x00_led *led =
 260             container_of(led_cdev, struct rt2x00_led, led_dev);
 261         unsigned int enabled = brightness != LED_OFF;
 262         unsigned int a_mode =
 263             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 264         unsigned int bg_mode =
 265             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 266
 267         if (led->type == LED_TYPE_RADIO) {
 268                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 269                                    MCU_LEDCS_RADIO_STATUS, enabled);
 270
 271                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 272                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 273                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 274         } else if (led->type == LED_TYPE_ASSOC) {
 275                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 276                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 277                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 278                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 279
 280                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 281                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 282                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 283         } else if (led->type == LED_TYPE_QUALITY) {
 284                 /*
 285                  * The brightness is divided into 6 levels (0 - 5),
 286                  * this means we need to convert the brightness
 287                  * argument into the matching level within that range.
 288                  */
 289                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 290                                     brightness / (LED_FULL / 6), 0);
 291         }
 292 }
 293
 294 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 295                              unsigned long *delay_on,
 296                              unsigned long *delay_off)
 297 {
 298         struct rt2x00_led *led =
 299             container_of(led_cdev, struct rt2x00_led, led_dev);
 300         u32 reg;
 301
 302         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 303         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 304         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 305         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 306
 307         return 0;
 308 }
 309
 310 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev,
 311                              struct rt2x00_led *led,
 312                              enum led_type type)
 313 {
 314         led->rt2x00dev = rt2x00dev;
 315         led->type = type;
 316         led->led_dev.brightness_set = rt61pci_brightness_set;
 317         led->led_dev.blink_set = rt61pci_blink_set;
 318         led->flags = LED_INITIALIZED;
 319 }
 320 #endif /* CONFIG_RT2X00_LIB_LEDS */
 321
 322 /*
 323  * Configuration handlers.
 324  */
 325 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 326                                      struct rt2x00lib_crypto *crypto,
 327                                      struct ieee80211_key_conf *key)
 328 {
 329         struct hw_key_entry key_entry;
 330         struct rt2x00_field32 field;
 331         u32 mask;
 332         u32 reg;
 333
 334         if (crypto->cmd == SET_KEY) {
 335                 /*
 336                  * rt2x00lib can't determine the correct free
 337                  * key_idx for shared keys. We have 1 register
 338                  * with key valid bits. The goal is simple, read
 339                  * the register, if that is full we have no slots
 340                  * left.
 341                  * Note that each BSS is allowed to have up to 4
 342                  * shared keys, so put a mask over the allowed
 343                  * entries.
 344                  */
 345                 mask = (0xf << crypto->bssidx);
 346
 347                 rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 348                 reg &= mask;
 349
 350                 if (reg && reg == mask)
 351                         return -ENOSPC;
 352
 353                 key->hw_key_idx += reg ? ffz(reg) : 0;
 354
 355                 /*
 356                  * Upload key to hardware
 357                  */
 358                 memcpy(key_entry.key, crypto->key,
 359                        sizeof(key_entry.key));
 360                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 361                        sizeof(key_entry.tx_mic));
 362                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 363                        sizeof(key_entry.rx_mic));
 364
 365                 reg = SHARED_KEY_ENTRY(key->hw_key_idx);
 366                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 367                                               &key_entry, sizeof(key_entry));
 368
 369                 /*
 370                  * The cipher types are stored over 2 registers.
 371                  * bssidx 0 and 1 keys are stored in SEC_CSR1 and
 372                  * bssidx 1 and 2 keys are stored in SEC_CSR5.
 373                  * Using the correct defines correctly will cause overhead,
 374                  * so just calculate the correct offset.
 375                  */
 376                 if (key->hw_key_idx < 8) {
 377                         field.bit_offset = (3 * key->hw_key_idx);
 378                         field.bit_mask = 0x7 << field.bit_offset;
 379
 380                         rt2x00pci_register_read(rt2x00dev, SEC_CSR1, &reg);
 381                         rt2x00_set_field32(&reg, field, crypto->cipher);
 382                         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, reg);
 383                 } else {
 384                         field.bit_offset = (3 * (key->hw_key_idx - 8));
 385                         field.bit_mask = 0x7 << field.bit_offset;
 386
 387                         rt2x00pci_register_read(rt2x00dev, SEC_CSR5, &reg);
 388                         rt2x00_set_field32(&reg, field, crypto->cipher);
 389                         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, reg);
 390                 }
 391
 392                 /*
 393                  * The driver does not support the IV/EIV generation
 394                  * in hardware. However it doesn't support the IV/EIV
 395                  * inside the ieee80211 frame either, but requires it
 396                  * to be provided seperately for the descriptor.
 397                  * rt2x00lib will cut the IV/EIV data out of all frames
 398                  * given to us by mac80211, but we must tell mac80211
 399                  * to generate the IV/EIV data.
 400                  */
 401                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 402         }
 403
 404         /*
 405          * SEC_CSR0 contains only single-bit fields to indicate
 406          * a particular key is valid. Because using the FIELD32()
 407          * defines directly will cause a lot of overhead we use
 408          * a calculation to determine the correct bit directly.
 409          */
 410         mask = 1 << key->hw_key_idx;
 411
 412         rt2x00pci_register_read(rt2x00dev, SEC_CSR0, &reg);
 413         if (crypto->cmd == SET_KEY)
 414                 reg |= mask;
 415         else if (crypto->cmd == DISABLE_KEY)
 416                 reg &= ~mask;
 417         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, reg);
 418
 419         return 0;
 420 }
 421
 422 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 423                                        struct rt2x00lib_crypto *crypto,
 424                                        struct ieee80211_key_conf *key)
 425 {
 426         struct hw_pairwise_ta_entry addr_entry;
 427         struct hw_key_entry key_entry;
 428         u32 mask;
 429         u32 reg;
 430
 431         if (crypto->cmd == SET_KEY) {
 432                 /*
 433                  * rt2x00lib can't determine the correct free
 434                  * key_idx for pairwise keys. We have 2 registers
 435                  * with key valid bits. The goal is simple, read
 436                  * the first register, if that is full move to
 437                  * the next register.
 438                  * When both registers are full, we drop the key,
 439                  * otherwise we use the first invalid entry.
 440                  */
 441                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 442                 if (reg && reg == ~0) {
 443                         key->hw_key_idx = 32;
 444                         rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 445                         if (reg && reg == ~0)
 446                                 return -ENOSPC;
 447                 }
 448
 449                 key->hw_key_idx += reg ? ffz(reg) : 0;
 450
 451                 /*
 452                  * Upload key to hardware
 453                  */
 454                 memcpy(key_entry.key, crypto->key,
 455                        sizeof(key_entry.key));
 456                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 457                        sizeof(key_entry.tx_mic));
 458                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 459                        sizeof(key_entry.rx_mic));
 460
 461                 memset(&addr_entry, 0, sizeof(addr_entry));
 462                 memcpy(&addr_entry, crypto->address, ETH_ALEN);
 463                 addr_entry.cipher = crypto->cipher;
 464
 465                 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 466                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 467                                               &key_entry, sizeof(key_entry));
 468
 469                 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx);
 470                 rt2x00pci_register_multiwrite(rt2x00dev, reg,
 471                                               &addr_entry, sizeof(addr_entry));
 472
 473                 /*
 474                  * Enable pairwise lookup table for given BSS idx,
 475                  * without this received frames will not be decrypted
 476                  * by the hardware.
 477                  */
 478                 rt2x00pci_register_read(rt2x00dev, SEC_CSR4, &reg);
 479                 reg |= (1 << crypto->bssidx);
 480                 rt2x00pci_register_write(rt2x00dev, SEC_CSR4, reg);
 481
 482                 /*
 483                  * The driver does not support the IV/EIV generation
 484                  * in hardware. However it doesn't support the IV/EIV
 485                  * inside the ieee80211 frame either, but requires it
 486                  * to be provided seperately for the descriptor.
 487                  * rt2x00lib will cut the IV/EIV data out of all frames
 488                  * given to us by mac80211, but we must tell mac80211
 489                  * to generate the IV/EIV data.
 490                  */
 491                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
 492         }
 493
 494         /*
 495          * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate
 496          * a particular key is valid. Because using the FIELD32()
 497          * defines directly will cause a lot of overhead we use
 498          * a calculation to determine the correct bit directly.
 499          */
 500         if (key->hw_key_idx < 32) {
 501                 mask = 1 << key->hw_key_idx;
 502
 503                 rt2x00pci_register_read(rt2x00dev, SEC_CSR2, &reg);
 504                 if (crypto->cmd == SET_KEY)
 505                         reg |= mask;
 506                 else if (crypto->cmd == DISABLE_KEY)
 507                         reg &= ~mask;
 508                 rt2x00pci_register_write(rt2x00dev, SEC_CSR2, reg);
 509         } else {
 510                 mask = 1 << (key->hw_key_idx - 32);
 511
 512                 rt2x00pci_register_read(rt2x00dev, SEC_CSR3, &reg);
 513                 if (crypto->cmd == SET_KEY)
 514                         reg |= mask;
 515                 else if (crypto->cmd == DISABLE_KEY)
 516                         reg &= ~mask;
 517                 rt2x00pci_register_write(rt2x00dev, SEC_CSR3, reg);
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 524                                   const unsigned int filter_flags)
 525 {
 526         u32 reg;
 527
 528         /*
 529          * Start configuration steps.
 530          * Note that the version error will always be dropped
 531          * and broadcast frames will always be accepted since
 532          * there is no filter for it at this time.
 533          */
 534         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 535         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 536                            !(filter_flags & FIF_FCSFAIL));
 537         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 538                            !(filter_flags & FIF_PLCPFAIL));
 539         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 540                            !(filter_flags & FIF_CONTROL));
 541         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 542                            !(filter_flags & FIF_PROMISC_IN_BSS));
 543         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 544                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 545                            !rt2x00dev->intf_ap_count);
 546         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 547         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 548                            !(filter_flags & FIF_ALLMULTI));
 549         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 550         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 551                            !(filter_flags & FIF_CONTROL));
 552         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 553 }
 554
 555 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 556                                 struct rt2x00_intf *intf,
 557                                 struct rt2x00intf_conf *conf,
 558                                 const unsigned int flags)
 559 {
 560         unsigned int beacon_base;
 561         u32 reg;
 562
 563         if (flags & CONFIG_UPDATE_TYPE) {
 564                 /*
 565                  * Clear current synchronisation setup.
 566                  * For the Beacon base registers we only need to clear
 567                  * the first byte since that byte contains the VALID and OWNER
 568                  * bits which (when set to 0) will invalidate the entire beacon.
 569                  */
 570                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 571                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 572
 573                 /*
 574                  * Enable synchronisation.
 575                  */
 576                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 577                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 578                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 579                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 580                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 581         }
 582
 583         if (flags & CONFIG_UPDATE_MAC) {
 584                 reg = le32_to_cpu(conf->mac[1]);
 585                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 586                 conf->mac[1] = cpu_to_le32(reg);
 587
 588                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 589                                               conf->mac, sizeof(conf->mac));
 590         }
 591
 592         if (flags & CONFIG_UPDATE_BSSID) {
 593                 reg = le32_to_cpu(conf->bssid[1]);
 594                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 595                 conf->bssid[1] = cpu_to_le32(reg);
 596
 597                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 598                                               conf->bssid, sizeof(conf->bssid));
 599         }
 600 }
 601
 602 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 603                                struct rt2x00lib_erp *erp)
 604 {
 605         u32 reg;
 606
 607         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 608         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 609         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 610
 611         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 612         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 613                            !!erp->short_preamble);
 614         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 615
 616         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, erp->basic_rates);
 617
 618         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 619         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, erp->slot_time);
 620         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 621
 622         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 623         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, erp->sifs);
 624         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 625         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, erp->eifs);
 626         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 627 }
 628
 629 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 630                                       struct antenna_setup *ant)
 631 {
 632         u8 r3;
 633         u8 r4;
 634         u8 r77;
 635
 636         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 637         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 638         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 639
 640         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 641                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 642
 643         /*
 644          * Configure the RX antenna.
 645          */
 646         switch (ant->rx) {
 647         case ANTENNA_HW_DIVERSITY:
 648                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 649                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 650                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 651                 break;
 652         case ANTENNA_A:
 653                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 654                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 655                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 656                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 657                 else
 658                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 659                 break;
 660         case ANTENNA_B:
 661         default:
 662                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 663                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 664                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 665                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 666                 else
 667                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 668                 break;
 669         }
 670
 671         rt61pci_bbp_write(rt2x00dev, 77, r77);
 672         rt61pci_bbp_write(rt2x00dev, 3, r3);
 673         rt61pci_bbp_write(rt2x00dev, 4, r4);
 674 }
 675
 676 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 677                                       struct antenna_setup *ant)
 678 {
 679         u8 r3;
 680         u8 r4;
 681         u8 r77;
 682
 683         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 684         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 685         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 686
 687         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 688                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 689         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 690                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 691
 692         /*
 693          * Configure the RX antenna.
 694          */
 695         switch (ant->rx) {
 696         case ANTENNA_HW_DIVERSITY:
 697                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 698                 break;
 699         case ANTENNA_A:
 700                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 701                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 702                 break;
 703         case ANTENNA_B:
 704         default:
 705                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 706                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 707                 break;
 708         }
 709
 710         rt61pci_bbp_write(rt2x00dev, 77, r77);
 711         rt61pci_bbp_write(rt2x00dev, 3, r3);
 712         rt61pci_bbp_write(rt2x00dev, 4, r4);
 713 }
 714
 715 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 716                                            const int p1, const int p2)
 717 {
 718         u32 reg;
 719
 720         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 721
 722         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 723         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 724
 725         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 726         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 727
 728         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 729 }
 730
 731 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 732                                         struct antenna_setup *ant)
 733 {
 734         u8 r3;
 735         u8 r4;
 736         u8 r77;
 737
 738         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 739         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 740         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 741
 742         /*
 743          * Configure the RX antenna.
 744          */
 745         switch (ant->rx) {
 746         case ANTENNA_A:
 747                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 748                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 749                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 750                 break;
 751         case ANTENNA_HW_DIVERSITY:
 752                 /*
 753                  * FIXME: Antenna selection for the rf 2529 is very confusing
 754                  * in the legacy driver. Just default to antenna B until the
 755                  * legacy code can be properly translated into rt2x00 code.
 756                  */
 757         case ANTENNA_B:
 758         default:
 759                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 760                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 761                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 762                 break;
 763         }
 764
 765         rt61pci_bbp_write(rt2x00dev, 77, r77);
 766         rt61pci_bbp_write(rt2x00dev, 3, r3);
 767         rt61pci_bbp_write(rt2x00dev, 4, r4);
 768 }
 769
 770 struct antenna_sel {
 771         u8 word;
 772         /*
 773          * value[0] -> non-LNA
 774          * value[1] -> LNA
 775          */
 776         u8 value[2];
 777 };
 778
 779 static const struct antenna_sel antenna_sel_a[] = {
 780         { 96,  { 0x58, 0x78 } },
 781         { 104, { 0x38, 0x48 } },
 782         { 75,  { 0xfe, 0x80 } },
 783         { 86,  { 0xfe, 0x80 } },
 784         { 88,  { 0xfe, 0x80 } },
 785         { 35,  { 0x60, 0x60 } },
 786         { 97,  { 0x58, 0x58 } },
 787         { 98,  { 0x58, 0x58 } },
 788 };
 789
 790 static const struct antenna_sel antenna_sel_bg[] = {
 791         { 96,  { 0x48, 0x68 } },
 792         { 104, { 0x2c, 0x3c } },
 793         { 75,  { 0xfe, 0x80 } },
 794         { 86,  { 0xfe, 0x80 } },
 795         { 88,  { 0xfe, 0x80 } },
 796         { 35,  { 0x50, 0x50 } },
 797         { 97,  { 0x48, 0x48 } },
 798         { 98,  { 0x48, 0x48 } },
 799 };
 800
 801 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev,
 802                                struct antenna_setup *ant)
 803 {
 804         const struct antenna_sel *sel;
 805         unsigned int lna;
 806         unsigned int i;
 807         u32 reg;
 808
 809         /*
 810          * We should never come here because rt2x00lib is supposed
 811          * to catch this and send us the correct antenna explicitely.
 812          */
 813         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 814                ant->tx == ANTENNA_SW_DIVERSITY);
 815
 816         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 817                 sel = antenna_sel_a;
 818                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 819         } else {
 820                 sel = antenna_sel_bg;
 821                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 822         }
 823
 824         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 825                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 826
 827         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 828
 829         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 830                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 831         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 832                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 833
 834         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 835
 836         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 837             rt2x00_rf(&rt2x00dev->chip, RF5325))
 838                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 839         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 840                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 841         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 842                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 843                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 844                 else
 845                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 846         }
 847 }
 848
 849 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 850                                     struct rt2x00lib_conf *libconf)
 851 {
 852         u16 eeprom;
 853         short lna_gain = 0;
 854
 855         if (libconf->conf->channel->band == IEEE80211_BAND_2GHZ) {
 856                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
 857                         lna_gain += 14;
 858
 859                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
 860                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
 861         } else {
 862                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
 863                         lna_gain += 14;
 864
 865                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
 866                 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
 867         }
 868
 869         rt2x00dev->lna_gain = lna_gain;
 870 }
 871
 872 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 873                                    struct rf_channel *rf, const int txpower)
 874 {
 875         u8 r3;
 876         u8 r94;
 877         u8 smart;
 878
 879         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 880         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 881
 882         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 883                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 884
 885         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 886         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 887         rt61pci_bbp_write(rt2x00dev, 3, r3);
 888
 889         r94 = 6;
 890         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 891                 r94 += txpower - MAX_TXPOWER;
 892         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 893                 r94 += txpower;
 894         rt61pci_bbp_write(rt2x00dev, 94, r94);
 895
 896         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 897         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 898         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 899         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 900
 901         udelay(200);
 902
 903         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 904         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 905         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 906         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 907
 908         udelay(200);
 909
 910         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 911         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 912         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 913         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 914
 915         msleep(1);
 916 }
 917
 918 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 919                                    const int txpower)
 920 {
 921         struct rf_channel rf;
 922
 923         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 924         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 925         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 926         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 927
 928         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 929 }
 930
 931 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
 932                                     struct rt2x00lib_conf *libconf)
 933 {
 934         u32 reg;
 935
 936         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 937         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT,
 938                            libconf->conf->long_frame_max_tx_count);
 939         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT,
 940                            libconf->conf->short_frame_max_tx_count);
 941         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 942 }
 943
 944 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 945                                     struct rt2x00lib_conf *libconf)
 946 {
 947         u32 reg;
 948
 949         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 950         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 951         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 952
 953         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 954         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 955         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 956
 957         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 958         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 959                            libconf->conf->beacon_int * 16);
 960         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 961 }
 962
 963 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev,
 964                                 struct rt2x00lib_conf *libconf)
 965 {
 966         enum dev_state state =
 967             (libconf->conf->flags & IEEE80211_CONF_PS) ?
 968                 STATE_SLEEP : STATE_AWAKE;
 969         u32 reg;
 970
 971         if (state == STATE_SLEEP) {
 972                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 973                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN,
 974                                    libconf->conf->beacon_int - 10);
 975                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP,
 976                                    libconf->conf->listen_interval - 1);
 977                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 5);
 978
 979                 /* We must first disable autowake before it can be enabled */
 980                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 981                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 982
 983                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 1);
 984                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 985
 986                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000005);
 987                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c);
 988                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060);
 989
 990                 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
 991         } else {
 992                 rt2x00pci_register_read(rt2x00dev, MAC_CSR11, &reg);
 993                 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
 994                 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
 995                 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
 996                 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
 997                 rt2x00pci_register_write(rt2x00dev, MAC_CSR11, reg);
 998
 999                 rt2x00pci_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007);
1000                 rt2x00pci_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018);
1001                 rt2x00pci_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020);
1002
1003                 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1004         }
1005 }
1006
1007 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
1008                            struct rt2x00lib_conf *libconf,
1009                            const unsigned int flags)
1010 {
1011         /* Always recalculate LNA gain before changing configuration */
1012         rt61pci_config_lna_gain(rt2x00dev, libconf);
1013
1014         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1015                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
1016                                        libconf->conf->power_level);
1017         if ((flags & IEEE80211_CONF_CHANGE_POWER) &&
1018             !(flags & IEEE80211_CONF_CHANGE_CHANNEL))
1019                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1020         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1021                 rt61pci_config_retry_limit(rt2x00dev, libconf);
1022         if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
1023                 rt61pci_config_duration(rt2x00dev, libconf);
1024         if (flags & IEEE80211_CONF_CHANGE_PS)
1025                 rt61pci_config_ps(rt2x00dev, libconf);
1026 }
1027
1028 /*
1029  * Link tuning
1030  */
1031 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
1032                                struct link_qual *qual)
1033 {
1034         u32 reg;
1035
1036         /*
1037          * Update FCS error count from register.
1038          */
1039         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1040         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
1041
1042         /*
1043          * Update False CCA count from register.
1044          */
1045         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1046         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
1047 }
1048
1049 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev, u8 vgc_level)
1050 {
1051         if (rt2x00dev->link.vgc_level != vgc_level) {
1052                 rt61pci_bbp_write(rt2x00dev, 17, vgc_level);
1053                 rt2x00dev->link.vgc_level = vgc_level;
1054                 rt2x00dev->link.vgc_level_reg = vgc_level;
1055         }
1056 }
1057
1058 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
1059 {
1060         rt61pci_set_vgc(rt2x00dev, 0x20);
1061 }
1062
1063 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
1064 {
1065         struct link *link = &rt2x00dev->link;
1066         int rssi = rt2x00_get_link_rssi(link);
1067         u8 up_bound;
1068         u8 low_bound;
1069
1070         /*
1071          * Determine r17 bounds.
1072          */
1073         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1074                 low_bound = 0x28;
1075                 up_bound = 0x48;
1076                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1077                         low_bound += 0x10;
1078                         up_bound += 0x10;
1079                 }
1080         } else {
1081                 low_bound = 0x20;
1082                 up_bound = 0x40;
1083                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
1084                         low_bound += 0x10;
1085                         up_bound += 0x10;
1086                 }
1087         }
1088
1089         /*
1090          * If we are not associated, we should go straight to the
1091          * dynamic CCA tuning.
1092          */
1093         if (!rt2x00dev->intf_associated)
1094                 goto dynamic_cca_tune;
1095
1096         /*
1097          * Special big-R17 for very short distance
1098          */
1099         if (rssi >= -35) {
1100                 rt61pci_set_vgc(rt2x00dev, 0x60);
1101                 return;
1102         }
1103
1104         /*
1105          * Special big-R17 for short distance
1106          */
1107         if (rssi >= -58) {
1108                 rt61pci_set_vgc(rt2x00dev, up_bound);
1109                 return;
1110         }
1111
1112         /*
1113          * Special big-R17 for middle-short distance
1114          */
1115         if (rssi >= -66) {
1116                 rt61pci_set_vgc(rt2x00dev, low_bound + 0x10);
1117                 return;
1118         }
1119
1120         /*
1121          * Special mid-R17 for middle distance
1122          */
1123         if (rssi >= -74) {
1124                 rt61pci_set_vgc(rt2x00dev, low_bound + 0x08);
1125                 return;
1126         }
1127
1128         /*
1129          * Special case: Change up_bound based on the rssi.
1130          * Lower up_bound when rssi is weaker then -74 dBm.
1131          */
1132         up_bound -= 2 * (-74 - rssi);
1133         if (low_bound > up_bound)
1134                 up_bound = low_bound;
1135
1136         if (link->vgc_level > up_bound) {
1137                 rt61pci_set_vgc(rt2x00dev, up_bound);
1138                 return;
1139         }
1140
1141 dynamic_cca_tune:
1142
1143         /*
1144          * r17 does not yet exceed upper limit, continue and base
1145          * the r17 tuning on the false CCA count.
1146          */
1147         if ((link->qual.false_cca > 512) && (link->vgc_level < up_bound))
1148                 rt61pci_set_vgc(rt2x00dev, ++link->vgc_level);
1149         else if ((link->qual.false_cca < 100) && (link->vgc_level > low_bound))
1150                 rt61pci_set_vgc(rt2x00dev, --link->vgc_level);
1151 }
1152
1153 /*
1154  * Firmware functions
1155  */
1156 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1157 {
1158         char *fw_name;
1159
1160         switch (rt2x00dev->chip.rt) {
1161         case RT2561:
1162                 fw_name = FIRMWARE_RT2561;
1163                 break;
1164         case RT2561s:
1165                 fw_name = FIRMWARE_RT2561s;
1166                 break;
1167         case RT2661:
1168                 fw_name = FIRMWARE_RT2661;
1169                 break;
1170         default:
1171                 fw_name = NULL;
1172                 break;
1173         }
1174
1175         return fw_name;
1176 }
1177
1178 static u16 rt61pci_get_firmware_crc(const void *data, const size_t len)
1179 {
1180         u16 crc;
1181
1182         /*
1183          * Use the crc itu-t algorithm.
1184          * The last 2 bytes in the firmware array are the crc checksum itself,
1185          * this means that we should never pass those 2 bytes to the crc
1186          * algorithm.
1187          */
1188         crc = crc_itu_t(0, data, len - 2);
1189         crc = crc_itu_t_byte(crc, 0);
1190         crc = crc_itu_t_byte(crc, 0);
1191
1192         return crc;
1193 }
1194
1195 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, const void *data,
1196                                  const size_t len)
1197 {
1198         int i;
1199         u32 reg;
1200
1201         /*
1202          * Wait for stable hardware.
1203          */
1204         for (i = 0; i < 100; i++) {
1205                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1206                 if (reg)
1207                         break;
1208                 msleep(1);
1209         }
1210
1211         if (!reg) {
1212                 ERROR(rt2x00dev, "Unstable hardware.\n");
1213                 return -EBUSY;
1214         }
1215
1216         /*
1217          * Prepare MCU and mailbox for firmware loading.
1218          */
1219         reg = 0;
1220         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1221         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1222         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1223         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1224         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1225
1226         /*
1227          * Write firmware to device.
1228          */
1229         reg = 0;
1230         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
1231         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
1232         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1233
1234         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1235                                       data, len);
1236
1237         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
1238         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1239
1240         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
1241         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1242
1243         for (i = 0; i < 100; i++) {
1244                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
1245                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1246                         break;
1247                 msleep(1);
1248         }
1249
1250         if (i == 100) {
1251                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1252                 return -EBUSY;
1253         }
1254
1255         /*
1256          * Hardware needs another millisecond before it is ready.
1257          */
1258         msleep(1);
1259
1260         /*
1261          * Reset MAC and BBP registers.
1262          */
1263         reg = 0;
1264         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1265         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1266         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1267
1268         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1269         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1270         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1271         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1272
1273         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1274         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1275         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1276
1277         return 0;
1278 }
1279
1280 /*
1281  * Initialization functions.
1282  */
1283 static bool rt61pci_get_entry_state(struct queue_entry *entry)
1284 {
1285         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1286         u32 word;
1287
1288         if (entry->queue->qid == QID_RX) {
1289                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1290
1291                 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
1292         } else {
1293                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1294
1295                 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1296                         rt2x00_get_field32(word, TXD_W0_VALID));
1297         }
1298 }
1299
1300 static void rt61pci_clear_entry(struct queue_entry *entry)
1301 {
1302         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1303         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1304         u32 word;
1305
1306         if (entry->queue->qid == QID_RX) {
1307                 rt2x00_desc_read(entry_priv->desc, 5, &word);
1308                 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1309                                    skbdesc->skb_dma);
1310                 rt2x00_desc_write(entry_priv->desc, 5, word);
1311
1312                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1313                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1314                 rt2x00_desc_write(entry_priv->desc, 0, word);
1315         } else {
1316                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1317                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1318                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1319                 rt2x00_desc_write(entry_priv->desc, 0, word);
1320         }
1321 }
1322
1323 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1324 {
1325         struct queue_entry_priv_pci *entry_priv;
1326         u32 reg;
1327
1328         /*
1329          * Initialize registers.
1330          */
1331         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1332         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1333                            rt2x00dev->tx[0].limit);
1334         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1335                            rt2x00dev->tx[1].limit);
1336         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1337                            rt2x00dev->tx[2].limit);
1338         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1339                            rt2x00dev->tx[3].limit);
1340         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1341
1342         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1343         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1344                            rt2x00dev->tx[0].desc_size / 4);
1345         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1346
1347         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1348         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1349         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1350                            entry_priv->desc_dma);
1351         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1352
1353         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1354         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1355         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1356                            entry_priv->desc_dma);
1357         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1358
1359         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1360         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1361         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1362                            entry_priv->desc_dma);
1363         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1364
1365         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1366         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1367         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1368                            entry_priv->desc_dma);
1369         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1370
1371         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1372         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1373         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1374                            rt2x00dev->rx->desc_size / 4);
1375         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1376         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1377
1378         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1379         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1380         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1381                            entry_priv->desc_dma);
1382         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1383
1384         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1385         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1386         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1387         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1388         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1389         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1390
1391         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1392         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1393         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1394         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1395         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1396         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1397
1398         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1399         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1400         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1401
1402         return 0;
1403 }
1404
1405 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1406 {
1407         u32 reg;
1408
1409         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1410         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1411         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1412         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1413         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1414
1415         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1416         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1417         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1418         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1419         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1420         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1421         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1422         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1423         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1424         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1425
1426         /*
1427          * CCK TXD BBP registers
1428          */
1429         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1430         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1431         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1432         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1433         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1434         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1435         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1436         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1437         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1438         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1439
1440         /*
1441          * OFDM TXD BBP registers
1442          */
1443         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1444         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1445         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1446         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1447         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1448         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1449         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1450         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1451
1452         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1453         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1454         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1455         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1456         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1457         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1458
1459         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1460         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1461         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1462         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1463         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1464         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1465
1466         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1467         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL, 0);
1468         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1469         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, 0);
1470         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1471         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1472         rt2x00_set_field32(&reg, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0);
1473         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1474
1475         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1476
1477         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1478
1479         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1480         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1481         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1482
1483         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1484
1485         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1486                 return -EBUSY;
1487
1488         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1489
1490         /*
1491          * Invalidate all Shared Keys (SEC_CSR0),
1492          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1493          */
1494         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1495         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1496         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1497
1498         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1499         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1500         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1501         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1502
1503         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1504
1505         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1506
1507         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1508
1509         /*
1510          * Clear all beacons
1511          * For the Beacon base registers we only need to clear
1512          * the first byte since that byte contains the VALID and OWNER
1513          * bits which (when set to 0) will invalidate the entire beacon.
1514          */
1515         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1516         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1517         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1518         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1519
1520         /*
1521          * We must clear the error counters.
1522          * These registers are cleared on read,
1523          * so we may pass a useless variable to store the value.
1524          */
1525         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1526         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1527         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1528
1529         /*
1530          * Reset MAC and BBP registers.
1531          */
1532         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1533         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1534         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1535         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1536
1537         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1538         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1539         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1540         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1541
1542         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1543         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1544         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1545
1546         return 0;
1547 }
1548
1549 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1550 {
1551         unsigned int i;
1552         u8 value;
1553
1554         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1555                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1556                 if ((value != 0xff) && (value != 0x00))
1557                         return 0;
1558                 udelay(REGISTER_BUSY_DELAY);
1559         }
1560
1561         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1562         return -EACCES;
1563 }
1564
1565 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1566 {
1567         unsigned int i;
1568         u16 eeprom;
1569         u8 reg_id;
1570         u8 value;
1571
1572         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1573                 return -EACCES;
1574
1575         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1576         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1577         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1578         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1579         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1580         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1581         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1582         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1583         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1584         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1585         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1586         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1587         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1588         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1589         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1590         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1591         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1592         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1593         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1594         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1595         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1596         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1597         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1598         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1599
1600         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1601                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1602
1603                 if (eeprom != 0xffff && eeprom != 0x0000) {
1604                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1605                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1606                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1607                 }
1608         }
1609
1610         return 0;
1611 }
1612
1613 /*
1614  * Device state switch handlers.
1615  */
1616 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1617                               enum dev_state state)
1618 {
1619         u32 reg;
1620
1621         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1622         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1623                            (state == STATE_RADIO_RX_OFF) ||
1624                            (state == STATE_RADIO_RX_OFF_LINK));
1625         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1626 }
1627
1628 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1629                                enum dev_state state)
1630 {
1631         int mask = (state == STATE_RADIO_IRQ_OFF);
1632         u32 reg;
1633
1634         /*
1635          * When interrupts are being enabled, the interrupt registers
1636          * should clear the register to assure a clean state.
1637          */
1638         if (state == STATE_RADIO_IRQ_ON) {
1639                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1640                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1641
1642                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1643                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1644         }
1645
1646         /*
1647          * Only toggle the interrupts bits we are going to use.
1648          * Non-checked interrupt bits are disabled by default.
1649          */
1650         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1651         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1652         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1653         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1654         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1655         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1656
1657         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1658         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1659         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1660         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1661         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1662         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1663         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1664         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1665         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1666         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1667 }
1668
1669 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1670 {
1671         u32 reg;
1672
1673         /*
1674          * Initialize all registers.
1675          */
1676         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1677                      rt61pci_init_registers(rt2x00dev) ||
1678                      rt61pci_init_bbp(rt2x00dev)))
1679                 return -EIO;
1680
1681         /*
1682          * Enable RX.
1683          */
1684         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1685         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1686         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1687
1688         return 0;
1689 }
1690
1691 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1692 {
1693         u32 reg;
1694
1695         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1696
1697         /*
1698          * Disable synchronisation.
1699          */
1700         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1701
1702         /*
1703          * Cancel RX and TX.
1704          */
1705         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1706         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1707         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1708         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1709         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1710         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1711 }
1712
1713 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1714 {
1715         u32 reg;
1716         unsigned int i;
1717         char put_to_sleep;
1718
1719         put_to_sleep = (state != STATE_AWAKE);
1720
1721         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1722         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1723         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1724         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1725
1726         /*
1727          * Device is not guaranteed to be in the requested state yet.
1728          * We must wait until the register indicates that the
1729          * device has entered the correct state.
1730          */
1731         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1732                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1733                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1734                 if (state == !put_to_sleep)
1735                         return 0;
1736                 msleep(10);
1737         }
1738
1739         return -EBUSY;
1740 }
1741
1742 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1743                                     enum dev_state state)
1744 {
1745         int retval = 0;
1746
1747         switch (state) {
1748         case STATE_RADIO_ON:
1749                 retval = rt61pci_enable_radio(rt2x00dev);
1750                 break;
1751         case STATE_RADIO_OFF:
1752                 rt61pci_disable_radio(rt2x00dev);
1753                 break;
1754         case STATE_RADIO_RX_ON:
1755         case STATE_RADIO_RX_ON_LINK:
1756         case STATE_RADIO_RX_OFF:
1757         case STATE_RADIO_RX_OFF_LINK:
1758                 rt61pci_toggle_rx(rt2x00dev, state);
1759                 break;
1760         case STATE_RADIO_IRQ_ON:
1761         case STATE_RADIO_IRQ_OFF:
1762                 rt61pci_toggle_irq(rt2x00dev, state);
1763                 break;
1764         case STATE_DEEP_SLEEP:
1765         case STATE_SLEEP:
1766         case STATE_STANDBY:
1767         case STATE_AWAKE:
1768                 retval = rt61pci_set_state(rt2x00dev, state);
1769                 break;
1770         default:
1771                 retval = -ENOTSUPP;
1772                 break;
1773         }
1774
1775         if (unlikely(retval))
1776                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1777                       state, retval);
1778
1779         return retval;
1780 }
1781
1782 /*
1783  * TX descriptor initialization
1784  */
1785 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1786                                   struct sk_buff *skb,
1787                                   struct txentry_desc *txdesc)
1788 {
1789         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1790         __le32 *txd = skbdesc->desc;
1791         u32 word;
1792
1793         /*
1794          * Start writing the descriptor words.
1795          */
1796         rt2x00_desc_read(txd, 1, &word);
1797         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1798         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1799         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1800         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1801         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1802         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
1803                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1804         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1805         rt2x00_desc_write(txd, 1, word);
1806
1807         rt2x00_desc_read(txd, 2, &word);
1808         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1809         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1810         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1811         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1812         rt2x00_desc_write(txd, 2, word);
1813
1814         if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1815                 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]);
1816                 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1817         }
1818
1819         rt2x00_desc_read(txd, 5, &word);
1820         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1821         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1822                            skbdesc->entry->entry_idx);
1823         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1824                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1825         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1826         rt2x00_desc_write(txd, 5, word);
1827
1828         rt2x00_desc_read(txd, 6, &word);
1829         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1830                            skbdesc->skb_dma);
1831         rt2x00_desc_write(txd, 6, word);
1832
1833         if (skbdesc->desc_len > TXINFO_SIZE) {
1834                 rt2x00_desc_read(txd, 11, &word);
1835                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len);
1836                 rt2x00_desc_write(txd, 11, word);
1837         }
1838
1839         rt2x00_desc_read(txd, 0, &word);
1840         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1841         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1842         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1843                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1844         rt2x00_set_field32(&word, TXD_W0_ACK,
1845                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1846         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1847                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1848         rt2x00_set_field32(&word, TXD_W0_OFDM,
1849                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1850         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1851         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1852                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1853         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1854                            test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1855         rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1856                            test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1857         rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1858         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1859         rt2x00_set_field32(&word, TXD_W0_BURST,
1860                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1861         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1862         rt2x00_desc_write(txd, 0, word);
1863 }
1864
1865 /*
1866  * TX data initialization
1867  */
1868 static void rt61pci_write_beacon(struct queue_entry *entry)
1869 {
1870         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1871         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1872         unsigned int beacon_base;
1873         u32 reg;
1874
1875         /*
1876          * Disable beaconing while we are reloading the beacon data,
1877          * otherwise we might be sending out invalid data.
1878          */
1879         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1880         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
1881         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
1882         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
1883         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1884
1885         /*
1886          * Write entire beacon with descriptor to register.
1887          */
1888         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1889         rt2x00pci_register_multiwrite(rt2x00dev,
1890                                       beacon_base,
1891                                       skbdesc->desc, skbdesc->desc_len);
1892         rt2x00pci_register_multiwrite(rt2x00dev,
1893                                       beacon_base + skbdesc->desc_len,
1894                                       entry->skb->data, entry->skb->len);
1895
1896         /*
1897          * Clean up beacon skb.
1898          */
1899         dev_kfree_skb_any(entry->skb);
1900         entry->skb = NULL;
1901 }
1902
1903 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1904                                   const enum data_queue_qid queue)
1905 {
1906         u32 reg;
1907
1908         if (queue == QID_BEACON) {
1909                 /*
1910                  * For Wi-Fi faily generated beacons between participating
1911                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1912                  */
1913                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1914
1915                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1916                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1917                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1918                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1919                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1920                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1921                 }
1922                 return;
1923         }
1924
1925         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1926         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1927         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1928         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1929         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1930         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1931 }
1932
1933 /*
1934  * RX control handlers
1935  */
1936 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1937 {
1938         u8 offset = rt2x00dev->lna_gain;
1939         u8 lna;
1940
1941         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1942         switch (lna) {
1943         case 3:
1944                 offset += 90;
1945                 break;
1946         case 2:
1947                 offset += 74;
1948                 break;
1949         case 1:
1950                 offset += 64;
1951                 break;
1952         default:
1953                 return 0;
1954         }
1955
1956         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1957                 if (lna == 3 || lna == 2)
1958                         offset += 10;
1959         }
1960
1961         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1962 }
1963
1964 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1965                                 struct rxdone_entry_desc *rxdesc)
1966 {
1967         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1968         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1969         u32 word0;
1970         u32 word1;
1971
1972         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1973         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1974
1975         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1976                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1977
1978         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1979                 rxdesc->cipher =
1980                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1981                 rxdesc->cipher_status =
1982                     rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1983         }
1984
1985         if (rxdesc->cipher != CIPHER_NONE) {
1986                 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
1987                 _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]);
1988                 rxdesc->dev_flags |= RXDONE_CRYPTO_IV;
1989
1990                 _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv);
1991                 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV;
1992
1993                 /*
1994                  * Hardware has stripped IV/EIV data from 802.11 frame during
1995                  * decryption. It has provided the data seperately but rt2x00lib
1996                  * should decide if it should be reinserted.
1997                  */
1998                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
1999
2000                 /*
2001                  * FIXME: Legacy driver indicates that the frame does
2002                  * contain the Michael Mic. Unfortunately, in rt2x00
2003                  * the MIC seems to be missing completely...
2004                  */
2005                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
2006
2007                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2008                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2009                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2010                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2011         }
2012
2013         /*
2014          * Obtain the status about this packet.
2015          * When frame was received with an OFDM bitrate,
2016          * the signal is the PLCP value. If it was received with
2017          * a CCK bitrate the signal is the rate in 100kbit/s.
2018          */
2019         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
2020         rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1);
2021         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
2022
2023         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
2024                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
2025         else
2026                 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE;
2027         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
2028                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2029 }
2030
2031 /*
2032  * Interrupt functions.
2033  */
2034 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2035 {
2036         struct data_queue *queue;
2037         struct queue_entry *entry;
2038         struct queue_entry *entry_done;
2039         struct queue_entry_priv_pci *entry_priv;
2040         struct txdone_entry_desc txdesc;
2041         u32 word;
2042         u32 reg;
2043         u32 old_reg;
2044         int type;
2045         int index;
2046
2047         /*
2048          * During each loop we will compare the freshly read
2049          * STA_CSR4 register value with the value read from
2050          * the previous loop. If the 2 values are equal then
2051          * we should stop processing because the chance it
2052          * quite big that the device has been unplugged and
2053          * we risk going into an endless loop.
2054          */
2055         old_reg = 0;
2056
2057         while (1) {
2058                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
2059                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
2060                         break;
2061
2062                 if (old_reg == reg)
2063                         break;
2064                 old_reg = reg;
2065
2066                 /*
2067                  * Skip this entry when it contains an invalid
2068                  * queue identication number.
2069                  */
2070                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
2071                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2072                 if (unlikely(!queue))
2073                         continue;
2074
2075                 /*
2076                  * Skip this entry when it contains an invalid
2077                  * index number.
2078                  */
2079                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
2080                 if (unlikely(index >= queue->limit))
2081                         continue;
2082
2083                 entry = &queue->entries[index];
2084                 entry_priv = entry->priv_data;
2085                 rt2x00_desc_read(entry_priv->desc, 0, &word);
2086
2087                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
2088                     !rt2x00_get_field32(word, TXD_W0_VALID))
2089                         return;
2090
2091                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2092                 while (entry != entry_done) {
2093                         /* Catch up.
2094                          * Just report any entries we missed as failed.
2095                          */
2096                         WARNING(rt2x00dev,
2097                                 "TX status report missed for entry %d\n",
2098                                 entry_done->entry_idx);
2099
2100                         txdesc.flags = 0;
2101                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2102                         txdesc.retry = 0;
2103
2104                         rt2x00lib_txdone(entry_done, &txdesc);
2105                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2106                 }
2107
2108                 /*
2109                  * Obtain the status about this packet.
2110                  */
2111                 txdesc.flags = 0;
2112                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
2113                 case 0: /* Success, maybe with retry */
2114                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2115                         break;
2116                 case 6: /* Failure, excessive retries */
2117                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
2118                         /* Don't break, this is a failed frame! */
2119                 default: /* Failure */
2120                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2121                 }
2122                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
2123
2124                 rt2x00lib_txdone(entry, &txdesc);
2125         }
2126 }
2127
2128 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2129 {
2130         struct rt2x00_dev *rt2x00dev = dev_instance;
2131         u32 reg_mcu;
2132         u32 reg;
2133
2134         /*
2135          * Get the interrupt sources & saved to local variable.
2136          * Write register value back to clear pending interrupts.
2137          */
2138         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
2139         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
2140
2141         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2142         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2143
2144         if (!reg && !reg_mcu)
2145                 return IRQ_NONE;
2146
2147         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2148                 return IRQ_HANDLED;
2149
2150         /*
2151          * Handle interrupts, walk through all bits
2152          * and run the tasks, the bits are checked in order of
2153          * priority.
2154          */
2155
2156         /*
2157          * 1 - Rx ring done interrupt.
2158          */
2159         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
2160                 rt2x00pci_rxdone(rt2x00dev);
2161
2162         /*
2163          * 2 - Tx ring done interrupt.
2164          */
2165         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
2166                 rt61pci_txdone(rt2x00dev);
2167
2168         /*
2169          * 3 - Handle MCU command done.
2170          */
2171         if (reg_mcu)
2172                 rt2x00pci_register_write(rt2x00dev,
2173                                          M2H_CMD_DONE_CSR, 0xffffffff);
2174
2175         return IRQ_HANDLED;
2176 }
2177
2178 /*
2179  * Device probe functions.
2180  */
2181 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2182 {
2183         struct eeprom_93cx6 eeprom;
2184         u32 reg;
2185         u16 word;
2186         u8 *mac;
2187         s8 value;
2188
2189         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2190
2191         eeprom.data = rt2x00dev;
2192         eeprom.register_read = rt61pci_eepromregister_read;
2193         eeprom.register_write = rt61pci_eepromregister_write;
2194         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2195             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2196         eeprom.reg_data_in = 0;
2197         eeprom.reg_data_out = 0;
2198         eeprom.reg_data_clock = 0;
2199         eeprom.reg_chip_select = 0;
2200
2201         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2202                                EEPROM_SIZE / sizeof(u16));
2203
2204         /*
2205          * Start validation of the data that has been read.
2206          */
2207         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2208         if (!is_valid_ether_addr(mac)) {
2209                 random_ether_addr(mac);
2210                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2211         }
2212
2213         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2214         if (word == 0xffff) {
2215                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
2216                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
2217                                    ANTENNA_B);
2218                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
2219                                    ANTENNA_B);
2220                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
2221                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
2222                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
2223                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
2224                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2225                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2226         }
2227
2228         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2229         if (word == 0xffff) {
2230                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
2231                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
2232                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
2233                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2234                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2235                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2236                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2237                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2238         }
2239
2240         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2241         if (word == 0xffff) {
2242                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2243                                    LED_MODE_DEFAULT);
2244                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2245                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2246         }
2247
2248         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2249         if (word == 0xffff) {
2250                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2251                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2252                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2253                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2254         }
2255
2256         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2257         if (word == 0xffff) {
2258                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2259                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2260                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2261                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2262         } else {
2263                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2264                 if (value < -10 || value > 10)
2265                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2266                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2267                 if (value < -10 || value > 10)
2268                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2269                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2270         }
2271
2272         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2273         if (word == 0xffff) {
2274                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2275                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2276                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2277                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
2278         } else {
2279                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2280                 if (value < -10 || value > 10)
2281                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2282                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2283                 if (value < -10 || value > 10)
2284                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2285                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2286         }
2287
2288         return 0;
2289 }
2290
2291 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2292 {
2293         u32 reg;
2294         u16 value;
2295         u16 eeprom;
2296         u16 device;
2297
2298         /*
2299          * Read EEPROM word for configuration.
2300          */
2301         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2302
2303         /*
2304          * Identify RF chipset.
2305          * To determine the RT chip we have to read the
2306          * PCI header of the device.
2307          */
2308         pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2309                              PCI_CONFIG_HEADER_DEVICE, &device);
2310         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2311         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2312         rt2x00_set_chip(rt2x00dev, device, value, reg);
2313
2314         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2315             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2316             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2317             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2318                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2319                 return -ENODEV;
2320         }
2321
2322         /*
2323          * Determine number of antenna's.
2324          */
2325         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2326                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2327
2328         /*
2329          * Identify default antenna configuration.
2330          */
2331         rt2x00dev->default_ant.tx =
2332             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2333         rt2x00dev->default_ant.rx =
2334             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2335
2336         /*
2337          * Read the Frame type.
2338          */
2339         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2340                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2341
2342         /*
2343          * Detect if this device has an hardware controlled radio.
2344          */
2345 #ifdef CONFIG_RT2X00_LIB_RFKILL
2346         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2347                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2348 #endif /* CONFIG_RT2X00_LIB_RFKILL */
2349
2350         /*
2351          * Read frequency offset and RF programming sequence.
2352          */
2353         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2354         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2355                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2356
2357         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2358
2359         /*
2360          * Read external LNA informations.
2361          */
2362         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2363
2364         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2365                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2366         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2367                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2368
2369         /*
2370          * When working with a RF2529 chip without double antenna
2371          * the antenna settings should be gathered from the NIC
2372          * eeprom word.
2373          */
2374         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2375             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2376                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2377                 case 0:
2378                         rt2x00dev->default_ant.tx = ANTENNA_B;
2379                         rt2x00dev->default_ant.rx = ANTENNA_A;
2380                         break;
2381                 case 1:
2382                         rt2x00dev->default_ant.tx = ANTENNA_B;
2383                         rt2x00dev->default_ant.rx = ANTENNA_B;
2384                         break;
2385                 case 2:
2386                         rt2x00dev->default_ant.tx = ANTENNA_A;
2387                         rt2x00dev->default_ant.rx = ANTENNA_A;
2388                         break;
2389                 case 3:
2390                         rt2x00dev->default_ant.tx = ANTENNA_A;
2391                         rt2x00dev->default_ant.rx = ANTENNA_B;
2392                         break;
2393                 }
2394
2395                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2396                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2397                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2398                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2399         }
2400
2401         /*
2402          * Store led settings, for correct led behaviour.
2403          * If the eeprom value is invalid,
2404          * switch to default led mode.
2405          */
2406 #ifdef CONFIG_RT2X00_LIB_LEDS
2407         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2408         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2409
2410         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2411         rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2412         if (value == LED_MODE_SIGNAL_STRENGTH)
2413                 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
2414                                  LED_TYPE_QUALITY);
2415
2416         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2417         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2418                            rt2x00_get_field16(eeprom,
2419                                               EEPROM_LED_POLARITY_GPIO_0));
2420         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2421                            rt2x00_get_field16(eeprom,
2422                                               EEPROM_LED_POLARITY_GPIO_1));
2423         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2424                            rt2x00_get_field16(eeprom,
2425                                               EEPROM_LED_POLARITY_GPIO_2));
2426         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2427                            rt2x00_get_field16(eeprom,
2428                                               EEPROM_LED_POLARITY_GPIO_3));
2429         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2430                            rt2x00_get_field16(eeprom,
2431                                               EEPROM_LED_POLARITY_GPIO_4));
2432         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2433                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2434         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2435                            rt2x00_get_field16(eeprom,
2436                                               EEPROM_LED_POLARITY_RDY_G));
2437         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2438                            rt2x00_get_field16(eeprom,
2439                                               EEPROM_LED_POLARITY_RDY_A));
2440 #endif /* CONFIG_RT2X00_LIB_LEDS */
2441
2442         return 0;
2443 }
2444
2445 /*
2446  * RF value list for RF5225 & RF5325
2447  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2448  */
2449 static const struct rf_channel rf_vals_noseq[] = {
2450         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2451         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2452         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2453         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2454         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2455         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2456         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2457         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2458         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2459         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2460         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2461         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2462         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2463         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2464
2465         /* 802.11 UNI / HyperLan 2 */
2466         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2467         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2468         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2469         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2470         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2471         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2472         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2473         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2474
2475         /* 802.11 HyperLan 2 */
2476         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2477         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2478         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2479         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2480         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2481         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2482         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2483         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2484         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2485         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2486
2487         /* 802.11 UNII */
2488         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2489         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2490         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2491         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2492         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2493         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2494
2495         /* MMAC(Japan)J52 ch 34,38,42,46 */
2496         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2497         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2498         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2499         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2500 };
2501
2502 /*
2503  * RF value list for RF5225 & RF5325
2504  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2505  */
2506 static const struct rf_channel rf_vals_seq[] = {
2507         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2508         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2509         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2510         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2511         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2512         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2513         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2514         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2515         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2516         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2517         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2518         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2519         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2520         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2521
2522         /* 802.11 UNI / HyperLan 2 */
2523         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2524         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2525         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2526         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2527         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2528         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2529         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2530         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2531
2532         /* 802.11 HyperLan 2 */
2533         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2534         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2535         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2536         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2537         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2538         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2539         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2540         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2541         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2542         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2543
2544         /* 802.11 UNII */
2545         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2546         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2547         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2548         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2549         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2550         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2551
2552         /* MMAC(Japan)J52 ch 34,38,42,46 */
2553         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2554         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2555         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2556         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2557 };
2558
2559 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2560 {
2561         struct hw_mode_spec *spec = &rt2x00dev->spec;
2562         struct channel_info *info;
2563         char *tx_power;
2564         unsigned int i;
2565
2566         /*
2567          * Initialize all hw fields.
2568          */
2569         rt2x00dev->hw->flags =
2570             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2571             IEEE80211_HW_SIGNAL_DBM;
2572         rt2x00dev->hw->extra_tx_headroom = 0;
2573
2574         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2575         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2576                                 rt2x00_eeprom_addr(rt2x00dev,
2577                                                    EEPROM_MAC_ADDR_0));
2578
2579         /*
2580          * Initialize hw_mode information.
2581          */
2582         spec->supported_bands = SUPPORT_BAND_2GHZ;
2583         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2584
2585         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2586                 spec->num_channels = 14;
2587                 spec->channels = rf_vals_noseq;
2588         } else {
2589                 spec->num_channels = 14;
2590                 spec->channels = rf_vals_seq;
2591         }
2592
2593         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2594             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2595                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2596                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2597         }
2598
2599         /*
2600          * Create channel information array
2601          */
2602         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2603         if (!info)
2604                 return -ENOMEM;
2605
2606         spec->channels_info = info;
2607
2608         tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2609         for (i = 0; i < 14; i++)
2610                 info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2611
2612         if (spec->num_channels > 14) {
2613                 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2614                 for (i = 14; i < spec->num_channels; i++)
2615                         info[i].tx_power1 = TXPOWER_FROM_DEV(tx_power[i]);
2616         }
2617
2618         return 0;
2619 }
2620
2621 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2622 {
2623         int retval;
2624
2625         /*
2626          * Allocate eeprom data.
2627          */
2628         retval = rt61pci_validate_eeprom(rt2x00dev);
2629         if (retval)
2630                 return retval;
2631
2632         retval = rt61pci_init_eeprom(rt2x00dev);
2633         if (retval)
2634                 return retval;
2635
2636         /*
2637          * Initialize hw specifications.
2638          */
2639         retval = rt61pci_probe_hw_mode(rt2x00dev);
2640         if (retval)
2641                 return retval;
2642
2643         /*
2644          * This device requires firmware and DMA mapped skbs.
2645          */
2646         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2647         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
2648         if (!modparam_nohwcrypt)
2649                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2650
2651         /*
2652          * Set the rssi offset.
2653          */
2654         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2655
2656         return 0;
2657 }
2658
2659 /*
2660  * IEEE80211 stack callback functions.
2661  */
2662 static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2663                            const struct ieee80211_tx_queue_params *params)
2664 {
2665         struct rt2x00_dev *rt2x00dev = hw->priv;
2666         struct data_queue *queue;
2667         struct rt2x00_field32 field;
2668         int retval;
2669         u32 reg;
2670
2671         /*
2672          * First pass the configuration through rt2x00lib, that will
2673          * update the queue settings and validate the input. After that
2674          * we are free to update the registers based on the value
2675          * in the queue parameter.
2676          */
2677         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2678         if (retval)
2679                 return retval;
2680
2681         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2682
2683         /* Update WMM TXOP register */
2684         if (queue_idx < 2) {
2685                 field.bit_offset = queue_idx * 16;
2686                 field.bit_mask = 0xffff << field.bit_offset;
2687
2688                 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
2689                 rt2x00_set_field32(&reg, field, queue->txop);
2690                 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
2691         } else if (queue_idx < 4) {
2692                 field.bit_offset = (queue_idx - 2) * 16;
2693                 field.bit_mask = 0xffff << field.bit_offset;
2694
2695                 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
2696                 rt2x00_set_field32(&reg, field, queue->txop);
2697                 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
2698         }
2699
2700         /* Update WMM registers */
2701         field.bit_offset = queue_idx * 4;
2702         field.bit_mask = 0xf << field.bit_offset;
2703
2704         rt2x00pci_register_read(rt2x00dev, AIFSN_CSR, &reg);
2705         rt2x00_set_field32(&reg, field, queue->aifs);
2706         rt2x00pci_register_write(rt2x00dev, AIFSN_CSR, reg);
2707
2708         rt2x00pci_register_read(rt2x00dev, CWMIN_CSR, &reg);
2709         rt2x00_set_field32(&reg, field, queue->cw_min);
2710         rt2x00pci_register_write(rt2x00dev, CWMIN_CSR, reg);
2711
2712         rt2x00pci_register_read(rt2x00dev, CWMAX_CSR, &reg);
2713         rt2x00_set_field32(&reg, field, queue->cw_max);
2714         rt2x00pci_register_write(rt2x00dev, CWMAX_CSR, reg);
2715
2716         return 0;
2717 }
2718
2719 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2720 {
2721         struct rt2x00_dev *rt2x00dev = hw->priv;
2722         u64 tsf;
2723         u32 reg;
2724
2725         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2726         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2727         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2728         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2729
2730         return tsf;
2731 }
2732
2733 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2734         .tx                     = rt2x00mac_tx,
2735         .start                  = rt2x00mac_start,
2736         .stop                   = rt2x00mac_stop,
2737         .add_interface          = rt2x00mac_add_interface,
2738         .remove_interface       = rt2x00mac_remove_interface,
2739         .config                 = rt2x00mac_config,
2740         .config_interface       = rt2x00mac_config_interface,
2741         .configure_filter       = rt2x00mac_configure_filter,
2742         .set_key                = rt2x00mac_set_key,
2743         .get_stats              = rt2x00mac_get_stats,
2744         .bss_info_changed       = rt2x00mac_bss_info_changed,
2745         .conf_tx                = rt61pci_conf_tx,
2746         .get_tx_stats           = rt2x00mac_get_tx_stats,
2747         .get_tsf                = rt61pci_get_tsf,
2748 };
2749
2750 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2751         .irq_handler            = rt61pci_interrupt,
2752         .probe_hw               = rt61pci_probe_hw,
2753         .get_firmware_name      = rt61pci_get_firmware_name,
2754         .get_firmware_crc       = rt61pci_get_firmware_crc,
2755         .load_firmware          = rt61pci_load_firmware,
2756         .initialize             = rt2x00pci_initialize,
2757         .uninitialize           = rt2x00pci_uninitialize,
2758         .get_entry_state        = rt61pci_get_entry_state,
2759         .clear_entry            = rt61pci_clear_entry,
2760         .set_device_state       = rt61pci_set_device_state,
2761         .rfkill_poll            = rt61pci_rfkill_poll,
2762         .link_stats             = rt61pci_link_stats,
2763         .reset_tuner            = rt61pci_reset_tuner,
2764         .link_tuner             = rt61pci_link_tuner,
2765         .write_tx_desc          = rt61pci_write_tx_desc,
2766         .write_tx_data          = rt2x00pci_write_tx_data,
2767         .write_beacon           = rt61pci_write_beacon,
2768         .kick_tx_queue          = rt61pci_kick_tx_queue,
2769         .fill_rxdone            = rt61pci_fill_rxdone,
2770         .config_shared_key      = rt61pci_config_shared_key,
2771         .config_pairwise_key    = rt61pci_config_pairwise_key,
2772         .config_filter          = rt61pci_config_filter,
2773         .config_intf            = rt61pci_config_intf,
2774         .config_erp             = rt61pci_config_erp,
2775         .config_ant             = rt61pci_config_ant,
2776         .config                 = rt61pci_config,
2777 };
2778
2779 static const struct data_queue_desc rt61pci_queue_rx = {
2780         .entry_num              = RX_ENTRIES,
2781         .data_size              = DATA_FRAME_SIZE,
2782         .desc_size              = RXD_DESC_SIZE,
2783         .priv_size              = sizeof(struct queue_entry_priv_pci),
2784 };
2785
2786 static const struct data_queue_desc rt61pci_queue_tx = {
2787         .entry_num              = TX_ENTRIES,
2788         .data_size              = DATA_FRAME_SIZE,
2789         .desc_size              = TXD_DESC_SIZE,
2790         .priv_size              = sizeof(struct queue_entry_priv_pci),
2791 };
2792
2793 static const struct data_queue_desc rt61pci_queue_bcn = {
2794         .entry_num              = 4 * BEACON_ENTRIES,
2795         .data_size              = 0, /* No DMA required for beacons */
2796         .desc_size              = TXINFO_SIZE,
2797         .priv_size              = sizeof(struct queue_entry_priv_pci),
2798 };
2799
2800 static const struct rt2x00_ops rt61pci_ops = {
2801         .name           = KBUILD_MODNAME,
2802         .max_sta_intf   = 1,
2803         .max_ap_intf    = 4,
2804         .eeprom_size    = EEPROM_SIZE,
2805         .rf_size        = RF_SIZE,
2806         .tx_queues      = NUM_TX_QUEUES,
2807         .rx             = &rt61pci_queue_rx,
2808         .tx             = &rt61pci_queue_tx,
2809         .bcn            = &rt61pci_queue_bcn,
2810         .lib            = &rt61pci_rt2x00_ops,
2811         .hw             = &rt61pci_mac80211_ops,
2812 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2813         .debugfs        = &rt61pci_rt2x00debug,
2814 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2815 };
2816
2817 /*
2818  * RT61pci module information.
2819  */
2820 static struct pci_device_id rt61pci_device_table[] = {
2821         /* RT2561s */
2822         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2823         /* RT2561 v2 */
2824         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2825         /* RT2661 */
2826         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2827         { 0, }
2828 };
2829
2830 MODULE_AUTHOR(DRV_PROJECT);
2831 MODULE_VERSION(DRV_VERSION);
2832 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2833 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2834                         "PCI & PCMCIA chipset based cards");
2835 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2836 MODULE_FIRMWARE(FIRMWARE_RT2561);
2837 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2838 MODULE_FIRMWARE(FIRMWARE_RT2661);
2839 MODULE_LICENSE("GPL");
2840
2841 static struct pci_driver rt61pci_driver = {
2842         .name           = KBUILD_MODNAME,
2843         .id_table       = rt61pci_device_table,
2844         .probe          = rt2x00pci_probe,
2845         .remove         = __devexit_p(rt2x00pci_remove),
2846         .suspend        = rt2x00pci_suspend,
2847         .resume         = rt2x00pci_resume,
2848 };
2849
2850 static int __init rt61pci_init(void)
2851 {
2852         return pci_register_driver(&rt61pci_driver);
2853 }
2854
2855 static void __exit rt61pci_exit(void)
2856 {
2857         pci_unregister_driver(&rt61pci_driver);
2858 }
2859
2860 module_init(rt61pci_init);
2861 module_exit(rt61pci_exit);