Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
[linux-2.6] / drivers / net / wireless / rt2x00 / rt2500pci.c
1 /*
2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3         <http://rt2x00.serialmonkey.com>
4
5         This program is free software; you can redistribute it and/or modify
6         it under the terms of the GNU General Public License as published by
7         the Free Software Foundation; either version 2 of the License, or
8         (at your option) any later version.
9
10         This program is distributed in the hope that it will be useful,
11         but WITHOUT ANY WARRANTY; without even the implied warranty of
12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13         GNU General Public License for more details.
14
15         You should have received a copy of the GNU General Public License
16         along with this program; if not, write to the
17         Free Software Foundation, Inc.,
18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19  */
20
21 /*
22         Module: rt2500pci
23         Abstract: rt2500pci device specific routines.
24         Supported chipsets: RT2560.
25  */
26
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
34
35 #include "rt2x00.h"
36 #include "rt2x00pci.h"
37 #include "rt2500pci.h"
38
39 /*
40  * Register access.
41  * All access to the CSR registers will go through the methods
42  * rt2x00pci_register_read and rt2x00pci_register_write.
43  * BBP and RF register require indirect register access,
44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
45  * These indirect registers work with busy bits,
46  * and we will try maximal REGISTER_BUSY_COUNT times to access
47  * the register while taking a REGISTER_BUSY_DELAY us delay
48  * between each attampt. When the busy bit is still set at that time,
49  * the access attempt is considered to have failed,
50  * and we will print an error.
51  */
52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
53 {
54         u32 reg;
55         unsigned int i;
56
57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60                         break;
61                 udelay(REGISTER_BUSY_DELAY);
62         }
63
64         return reg;
65 }
66
67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
68                                 const unsigned int word, const u8 value)
69 {
70         u32 reg;
71
72         /*
73          * Wait until the BBP becomes ready.
74          */
75         reg = rt2500pci_bbp_check(rt2x00dev);
76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78                 return;
79         }
80
81         /*
82          * Write the data into the BBP.
83          */
84         reg = 0;
85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91 }
92
93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
94                                const unsigned int word, u8 *value)
95 {
96         u32 reg;
97
98         /*
99          * Wait until the BBP becomes ready.
100          */
101         reg = rt2500pci_bbp_check(rt2x00dev);
102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104                 return;
105         }
106
107         /*
108          * Write the request into the BBP.
109          */
110         reg = 0;
111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117         /*
118          * Wait until the BBP becomes ready.
119          */
120         reg = rt2500pci_bbp_check(rt2x00dev);
121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123                 *value = 0xff;
124                 return;
125         }
126
127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128 }
129
130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
131                                const unsigned int word, const u32 value)
132 {
133         u32 reg;
134         unsigned int i;
135
136         if (!word)
137                 return;
138
139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142                         goto rf_write;
143                 udelay(REGISTER_BUSY_DELAY);
144         }
145
146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147         return;
148
149 rf_write:
150         reg = 0;
151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157         rt2x00_rf_write(rt2x00dev, word, value);
158 }
159
160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161 {
162         struct rt2x00_dev *rt2x00dev = eeprom->data;
163         u32 reg;
164
165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169         eeprom->reg_data_clock =
170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171         eeprom->reg_chip_select =
172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173 }
174
175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176 {
177         struct rt2x00_dev *rt2x00dev = eeprom->data;
178         u32 reg = 0;
179
180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183                            !!eeprom->reg_data_clock);
184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185                            !!eeprom->reg_chip_select);
186
187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188 }
189
190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
194                                const unsigned int word, u32 *data)
195 {
196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197 }
198
199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
200                                 const unsigned int word, u32 data)
201 {
202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203 }
204
205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
206         .owner  = THIS_MODULE,
207         .csr    = {
208                 .read           = rt2500pci_read_csr,
209                 .write          = rt2500pci_write_csr,
210                 .word_size      = sizeof(u32),
211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
212         },
213         .eeprom = {
214                 .read           = rt2x00_eeprom_read,
215                 .write          = rt2x00_eeprom_write,
216                 .word_size      = sizeof(u16),
217                 .word_count     = EEPROM_SIZE / sizeof(u16),
218         },
219         .bbp    = {
220                 .read           = rt2500pci_bbp_read,
221                 .write          = rt2500pci_bbp_write,
222                 .word_size      = sizeof(u8),
223                 .word_count     = BBP_SIZE / sizeof(u8),
224         },
225         .rf     = {
226                 .read           = rt2x00_rf_read,
227                 .write          = rt2500pci_rf_write,
228                 .word_size      = sizeof(u32),
229                 .word_count     = RF_SIZE / sizeof(u32),
230         },
231 };
232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234 #ifdef CONFIG_RT2500PCI_RFKILL
235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236 {
237         u32 reg;
238
239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241 }
242 #else
243 #define rt2500pci_rfkill_poll   NULL
244 #endif /* CONFIG_RT2500PCI_RFKILL */
245
246 #ifdef CONFIG_RT2500PCI_LEDS
247 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
248                                      enum led_brightness brightness)
249 {
250         struct rt2x00_led *led =
251             container_of(led_cdev, struct rt2x00_led, led_dev);
252         unsigned int enabled = brightness != LED_OFF;
253         u32 reg;
254
255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
259         else if (led->type == LED_TYPE_ACTIVITY)
260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
261
262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263 }
264
265 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
266                                unsigned long *delay_on,
267                                unsigned long *delay_off)
268 {
269         struct rt2x00_led *led =
270             container_of(led_cdev, struct rt2x00_led, led_dev);
271         u32 reg;
272
273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278         return 0;
279 }
280
281 static void rt2500pci_init_led(struct rt2x00_dev *rt2x00dev,
282                                struct rt2x00_led *led,
283                                enum led_type type)
284 {
285         led->rt2x00dev = rt2x00dev;
286         led->type = type;
287         led->led_dev.brightness_set = rt2500pci_brightness_set;
288         led->led_dev.blink_set = rt2500pci_blink_set;
289         led->flags = LED_INITIALIZED;
290 }
291 #endif /* CONFIG_RT2500PCI_LEDS */
292
293 /*
294  * Configuration handlers.
295  */
296 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
297                                     const unsigned int filter_flags)
298 {
299         u32 reg;
300
301         /*
302          * Start configuration steps.
303          * Note that the version error will always be dropped
304          * and broadcast frames will always be accepted since
305          * there is no filter for it at this time.
306          */
307         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
308         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
309                            !(filter_flags & FIF_FCSFAIL));
310         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
311                            !(filter_flags & FIF_PLCPFAIL));
312         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
313                            !(filter_flags & FIF_CONTROL));
314         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
315                            !(filter_flags & FIF_PROMISC_IN_BSS));
316         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
317                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
318                            !rt2x00dev->intf_ap_count);
319         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
320         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
321                            !(filter_flags & FIF_ALLMULTI));
322         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
323         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
324 }
325
326 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
327                                   struct rt2x00_intf *intf,
328                                   struct rt2x00intf_conf *conf,
329                                   const unsigned int flags)
330 {
331         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
332         unsigned int bcn_preload;
333         u32 reg;
334
335         if (flags & CONFIG_UPDATE_TYPE) {
336                 /*
337                  * Enable beacon config
338                  */
339                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
340                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
341                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
342                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
343                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
344
345                 /*
346                  * Enable synchronisation.
347                  */
348                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
349                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
350                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
351                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
352                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
353         }
354
355         if (flags & CONFIG_UPDATE_MAC)
356                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
357                                               conf->mac, sizeof(conf->mac));
358
359         if (flags & CONFIG_UPDATE_BSSID)
360                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
361                                               conf->bssid, sizeof(conf->bssid));
362 }
363
364 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
365                                  struct rt2x00lib_erp *erp)
366 {
367         int preamble_mask;
368         u32 reg;
369
370         /*
371          * When short preamble is enabled, we should set bit 0x08
372          */
373         preamble_mask = erp->short_preamble << 3;
374
375         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
376         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
377                            erp->ack_timeout);
378         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
379                            erp->ack_consume_time);
380         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
381
382         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
383         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
384         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
385         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
386         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
387
388         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
389         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
390         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
391         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
392         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
393
394         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
395         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
396         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
397         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
398         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
399
400         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
401         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
402         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
403         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
404         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
405 }
406
407 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
408                                      const int basic_rate_mask)
409 {
410         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
411 }
412
413 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
414                                      struct rf_channel *rf, const int txpower)
415 {
416         u8 r70;
417
418         /*
419          * Set TXpower.
420          */
421         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
422
423         /*
424          * Switch on tuning bits.
425          * For RT2523 devices we do not need to update the R1 register.
426          */
427         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
428                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
429         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
430
431         /*
432          * For RT2525 we should first set the channel to half band higher.
433          */
434         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
435                 static const u32 vals[] = {
436                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
437                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
438                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
439                         0x00080d2e, 0x00080d3a
440                 };
441
442                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
443                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
444                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
445                 if (rf->rf4)
446                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
447         }
448
449         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
450         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
451         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
452         if (rf->rf4)
453                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
454
455         /*
456          * Channel 14 requires the Japan filter bit to be set.
457          */
458         r70 = 0x46;
459         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
460         rt2500pci_bbp_write(rt2x00dev, 70, r70);
461
462         msleep(1);
463
464         /*
465          * Switch off tuning bits.
466          * For RT2523 devices we do not need to update the R1 register.
467          */
468         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
469                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
470                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
471         }
472
473         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
474         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
475
476         /*
477          * Clear false CRC during channel switch.
478          */
479         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
480 }
481
482 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
483                                      const int txpower)
484 {
485         u32 rf3;
486
487         rt2x00_rf_read(rt2x00dev, 3, &rf3);
488         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
489         rt2500pci_rf_write(rt2x00dev, 3, rf3);
490 }
491
492 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
493                                      struct antenna_setup *ant)
494 {
495         u32 reg;
496         u8 r14;
497         u8 r2;
498
499         /*
500          * We should never come here because rt2x00lib is supposed
501          * to catch this and send us the correct antenna explicitely.
502          */
503         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
504                ant->tx == ANTENNA_SW_DIVERSITY);
505
506         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
507         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
508         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
509
510         /*
511          * Configure the TX antenna.
512          */
513         switch (ant->tx) {
514         case ANTENNA_A:
515                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
516                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
517                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
518                 break;
519         case ANTENNA_B:
520         default:
521                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
522                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
523                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
524                 break;
525         }
526
527         /*
528          * Configure the RX antenna.
529          */
530         switch (ant->rx) {
531         case ANTENNA_A:
532                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
533                 break;
534         case ANTENNA_B:
535         default:
536                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
537                 break;
538         }
539
540         /*
541          * RT2525E and RT5222 need to flip TX I/Q
542          */
543         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
544             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
545                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
546                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
547                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
548
549                 /*
550                  * RT2525E does not need RX I/Q Flip.
551                  */
552                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
553                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
554         } else {
555                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
556                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
557         }
558
559         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
560         rt2500pci_bbp_write(rt2x00dev, 14, r14);
561         rt2500pci_bbp_write(rt2x00dev, 2, r2);
562 }
563
564 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
565                                       struct rt2x00lib_conf *libconf)
566 {
567         u32 reg;
568
569         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
570         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
571         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
572
573         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
574         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
575         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
576         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
577
578         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
579         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
580         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
581         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
582
583         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
584         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
585         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
586         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
587
588         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
589         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
590                            libconf->conf->beacon_int * 16);
591         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
592                            libconf->conf->beacon_int * 16);
593         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
594 }
595
596 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
597                              struct rt2x00lib_conf *libconf,
598                              const unsigned int flags)
599 {
600         if (flags & CONFIG_UPDATE_PHYMODE)
601                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
602         if (flags & CONFIG_UPDATE_CHANNEL)
603                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
604                                          libconf->conf->power_level);
605         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
606                 rt2500pci_config_txpower(rt2x00dev,
607                                          libconf->conf->power_level);
608         if (flags & CONFIG_UPDATE_ANTENNA)
609                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
610         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
611                 rt2500pci_config_duration(rt2x00dev, libconf);
612 }
613
614 /*
615  * Link tuning
616  */
617 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
618                                  struct link_qual *qual)
619 {
620         u32 reg;
621
622         /*
623          * Update FCS error count from register.
624          */
625         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
626         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
627
628         /*
629          * Update False CCA count from register.
630          */
631         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
632         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
633 }
634
635 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
636 {
637         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
638         rt2x00dev->link.vgc_level = 0x48;
639 }
640
641 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
642 {
643         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
644         u8 r17;
645
646         /*
647          * To prevent collisions with MAC ASIC on chipsets
648          * up to version C the link tuning should halt after 20
649          * seconds while being associated.
650          */
651         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
652             rt2x00dev->intf_associated &&
653             rt2x00dev->link.count > 20)
654                 return;
655
656         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
657
658         /*
659          * Chipset versions C and lower should directly continue
660          * to the dynamic CCA tuning. Chipset version D and higher
661          * should go straight to dynamic CCA tuning when they
662          * are not associated.
663          */
664         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
665             !rt2x00dev->intf_associated)
666                 goto dynamic_cca_tune;
667
668         /*
669          * A too low RSSI will cause too much false CCA which will
670          * then corrupt the R17 tuning. To remidy this the tuning should
671          * be stopped (While making sure the R17 value will not exceed limits)
672          */
673         if (rssi < -80 && rt2x00dev->link.count > 20) {
674                 if (r17 >= 0x41) {
675                         r17 = rt2x00dev->link.vgc_level;
676                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
677                 }
678                 return;
679         }
680
681         /*
682          * Special big-R17 for short distance
683          */
684         if (rssi >= -58) {
685                 if (r17 != 0x50)
686                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
687                 return;
688         }
689
690         /*
691          * Special mid-R17 for middle distance
692          */
693         if (rssi >= -74) {
694                 if (r17 != 0x41)
695                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
696                 return;
697         }
698
699         /*
700          * Leave short or middle distance condition, restore r17
701          * to the dynamic tuning range.
702          */
703         if (r17 >= 0x41) {
704                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
705                 return;
706         }
707
708 dynamic_cca_tune:
709
710         /*
711          * R17 is inside the dynamic tuning range,
712          * start tuning the link based on the false cca counter.
713          */
714         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
715                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
716                 rt2x00dev->link.vgc_level = r17;
717         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
718                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
719                 rt2x00dev->link.vgc_level = r17;
720         }
721 }
722
723 /*
724  * Initialization functions.
725  */
726 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
727                                    struct queue_entry *entry)
728 {
729         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
730         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
731         u32 word;
732
733         rt2x00_desc_read(entry_priv->desc, 1, &word);
734         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
735         rt2x00_desc_write(entry_priv->desc, 1, word);
736
737         rt2x00_desc_read(entry_priv->desc, 0, &word);
738         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
739         rt2x00_desc_write(entry_priv->desc, 0, word);
740 }
741
742 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
743                                    struct queue_entry *entry)
744 {
745         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
746         u32 word;
747
748         rt2x00_desc_read(entry_priv->desc, 0, &word);
749         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
750         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
751         rt2x00_desc_write(entry_priv->desc, 0, word);
752 }
753
754 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
755 {
756         struct queue_entry_priv_pci *entry_priv;
757         u32 reg;
758
759         /*
760          * Initialize registers.
761          */
762         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
763         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
764         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
765         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
766         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
767         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
768
769         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
770         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
771         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
772                            entry_priv->desc_dma);
773         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
774
775         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
776         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
777         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
778                            entry_priv->desc_dma);
779         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
780
781         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
782         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
783         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
784                            entry_priv->desc_dma);
785         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
786
787         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
788         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
789         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
790                            entry_priv->desc_dma);
791         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
792
793         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
794         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
795         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
796         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
797
798         entry_priv = rt2x00dev->rx->entries[0].priv_data;
799         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
800         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
801                            entry_priv->desc_dma);
802         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
803
804         return 0;
805 }
806
807 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
808 {
809         u32 reg;
810
811         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
812         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
813         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
814         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
815
816         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
817         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
818         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
819         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
820         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
821
822         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
823         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
824                            rt2x00dev->rx->data_size / 128);
825         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
826
827         /*
828          * Always use CWmin and CWmax set in descriptor.
829          */
830         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
831         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
832         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
833
834         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
835         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
836         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
837         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
838         rt2x00_set_field32(&reg, CSR14_TCFP, 0);
839         rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
840         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
841         rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
842         rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
843         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
844
845         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
846
847         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
848         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
849         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
850         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
851         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
852         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
853         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
854         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
855         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
856         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
857
858         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
859         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
860         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
861         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
862         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
863         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
864
865         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
866         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
867         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
868         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
869         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
870         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
871
872         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
873         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
874         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
875         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
876         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
877         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
878
879         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
880         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
881         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
882         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
883         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
884         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
885         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
886         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
887         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
888         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
889
890         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
891         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
892         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
893         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
894         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
895         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
896         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
897         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
898         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
899
900         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
901
902         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
903         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
904
905         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
906                 return -EBUSY;
907
908         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
909         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
910
911         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
912         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
913         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
914
915         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
916         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
917         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
918         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
919         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
920         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
921         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
922         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
923
924         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
925
926         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
927
928         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
929         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
930         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
931         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
932         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
933
934         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
935         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
936         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
937         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
938
939         /*
940          * We must clear the FCS and FIFO error count.
941          * These registers are cleared on read,
942          * so we may pass a useless variable to store the value.
943          */
944         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
945         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
946
947         return 0;
948 }
949
950 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
951 {
952         unsigned int i;
953         u8 value;
954
955         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
956                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
957                 if ((value != 0xff) && (value != 0x00))
958                         return 0;
959                 udelay(REGISTER_BUSY_DELAY);
960         }
961
962         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
963         return -EACCES;
964 }
965
966 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
967 {
968         unsigned int i;
969         u16 eeprom;
970         u8 reg_id;
971         u8 value;
972
973         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
974                 return -EACCES;
975
976         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
977         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
978         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
979         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
980         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
981         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
982         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
983         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
984         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
985         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
986         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
987         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
988         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
989         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
990         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
991         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
992         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
993         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
994         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
995         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
996         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
997         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
998         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
999         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1000         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1001         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1002         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1003         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1004         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1005         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1006
1007         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1008                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1009
1010                 if (eeprom != 0xffff && eeprom != 0x0000) {
1011                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1012                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1013                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1014                 }
1015         }
1016
1017         return 0;
1018 }
1019
1020 /*
1021  * Device state switch handlers.
1022  */
1023 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1024                                 enum dev_state state)
1025 {
1026         u32 reg;
1027
1028         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1029         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1030                            (state == STATE_RADIO_RX_OFF) ||
1031                            (state == STATE_RADIO_RX_OFF_LINK));
1032         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1033 }
1034
1035 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1036                                  enum dev_state state)
1037 {
1038         int mask = (state == STATE_RADIO_IRQ_OFF);
1039         u32 reg;
1040
1041         /*
1042          * When interrupts are being enabled, the interrupt registers
1043          * should clear the register to assure a clean state.
1044          */
1045         if (state == STATE_RADIO_IRQ_ON) {
1046                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1047                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1048         }
1049
1050         /*
1051          * Only toggle the interrupts bits we are going to use.
1052          * Non-checked interrupt bits are disabled by default.
1053          */
1054         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1055         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1056         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1057         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1058         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1059         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1060         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1061 }
1062
1063 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1064 {
1065         /*
1066          * Initialize all registers.
1067          */
1068         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1069                      rt2500pci_init_registers(rt2x00dev) ||
1070                      rt2500pci_init_bbp(rt2x00dev)))
1071                 return -EIO;
1072
1073         return 0;
1074 }
1075
1076 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1077 {
1078         u32 reg;
1079
1080         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1081
1082         /*
1083          * Disable synchronisation.
1084          */
1085         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1086
1087         /*
1088          * Cancel RX and TX.
1089          */
1090         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1091         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1092         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1093 }
1094
1095 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1096                                enum dev_state state)
1097 {
1098         u32 reg;
1099         unsigned int i;
1100         char put_to_sleep;
1101         char bbp_state;
1102         char rf_state;
1103
1104         put_to_sleep = (state != STATE_AWAKE);
1105
1106         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1107         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1108         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1109         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1110         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1111         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1112
1113         /*
1114          * Device is not guaranteed to be in the requested state yet.
1115          * We must wait until the register indicates that the
1116          * device has entered the correct state.
1117          */
1118         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1119                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1120                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1121                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1122                 if (bbp_state == state && rf_state == state)
1123                         return 0;
1124                 msleep(10);
1125         }
1126
1127         return -EBUSY;
1128 }
1129
1130 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1131                                       enum dev_state state)
1132 {
1133         int retval = 0;
1134
1135         switch (state) {
1136         case STATE_RADIO_ON:
1137                 retval = rt2500pci_enable_radio(rt2x00dev);
1138                 break;
1139         case STATE_RADIO_OFF:
1140                 rt2500pci_disable_radio(rt2x00dev);
1141                 break;
1142         case STATE_RADIO_RX_ON:
1143         case STATE_RADIO_RX_ON_LINK:
1144         case STATE_RADIO_RX_OFF:
1145         case STATE_RADIO_RX_OFF_LINK:
1146                 rt2500pci_toggle_rx(rt2x00dev, state);
1147                 break;
1148         case STATE_RADIO_IRQ_ON:
1149         case STATE_RADIO_IRQ_OFF:
1150                 rt2500pci_toggle_irq(rt2x00dev, state);
1151                 break;
1152         case STATE_DEEP_SLEEP:
1153         case STATE_SLEEP:
1154         case STATE_STANDBY:
1155         case STATE_AWAKE:
1156                 retval = rt2500pci_set_state(rt2x00dev, state);
1157                 break;
1158         default:
1159                 retval = -ENOTSUPP;
1160                 break;
1161         }
1162
1163         if (unlikely(retval))
1164                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1165                       state, retval);
1166
1167         return retval;
1168 }
1169
1170 /*
1171  * TX descriptor initialization
1172  */
1173 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1174                                     struct sk_buff *skb,
1175                                     struct txentry_desc *txdesc)
1176 {
1177         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1178         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1179         __le32 *txd = skbdesc->desc;
1180         u32 word;
1181
1182         /*
1183          * Start writing the descriptor words.
1184          */
1185         rt2x00_desc_read(entry_priv->desc, 1, &word);
1186         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1187         rt2x00_desc_write(entry_priv->desc, 1, word);
1188
1189         rt2x00_desc_read(txd, 2, &word);
1190         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1191         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1192         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1193         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1194         rt2x00_desc_write(txd, 2, word);
1195
1196         rt2x00_desc_read(txd, 3, &word);
1197         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1198         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1199         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1200         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1201         rt2x00_desc_write(txd, 3, word);
1202
1203         rt2x00_desc_read(txd, 10, &word);
1204         rt2x00_set_field32(&word, TXD_W10_RTS,
1205                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1206         rt2x00_desc_write(txd, 10, word);
1207
1208         rt2x00_desc_read(txd, 0, &word);
1209         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1210         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1211         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1212                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1213         rt2x00_set_field32(&word, TXD_W0_ACK,
1214                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1215         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1216                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1217         rt2x00_set_field32(&word, TXD_W0_OFDM,
1218                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1219         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1220         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1221         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1222                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1223         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1224         rt2x00_desc_write(txd, 0, word);
1225 }
1226
1227 /*
1228  * TX data initialization
1229  */
1230 static void rt2500pci_write_beacon(struct queue_entry *entry)
1231 {
1232         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1233         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1234         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1235         u32 word;
1236         u32 reg;
1237
1238         /*
1239          * Disable beaconing while we are reloading the beacon data,
1240          * otherwise we might be sending out invalid data.
1241          */
1242         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1243         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1244         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1245         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1246         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1247
1248         /*
1249          * Replace rt2x00lib allocated descriptor with the
1250          * pointer to the _real_ hardware descriptor.
1251          * After that, map the beacon to DMA and update the
1252          * descriptor.
1253          */
1254         memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1255         skbdesc->desc = entry_priv->desc;
1256
1257         rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1258
1259         rt2x00_desc_read(entry_priv->desc, 1, &word);
1260         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1261         rt2x00_desc_write(entry_priv->desc, 1, word);
1262 }
1263
1264 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1265                                     const enum data_queue_qid queue)
1266 {
1267         u32 reg;
1268
1269         if (queue == QID_BEACON) {
1270                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1271                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1272                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1273                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1274                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1275                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1276                 }
1277                 return;
1278         }
1279
1280         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1281         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1282         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1283         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1284         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1285 }
1286
1287 /*
1288  * RX control handlers
1289  */
1290 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1291                                   struct rxdone_entry_desc *rxdesc)
1292 {
1293         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1294         u32 word0;
1295         u32 word2;
1296
1297         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1298         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1299
1300         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1301                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1302         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1303                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1304
1305         /*
1306          * Obtain the status about this packet.
1307          * When frame was received with an OFDM bitrate,
1308          * the signal is the PLCP value. If it was received with
1309          * a CCK bitrate the signal is the rate in 100kbit/s.
1310          */
1311         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1312         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1313             entry->queue->rt2x00dev->rssi_offset;
1314         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1315
1316         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1317                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1318         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1319                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1320 }
1321
1322 /*
1323  * Interrupt functions.
1324  */
1325 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1326                              const enum data_queue_qid queue_idx)
1327 {
1328         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1329         struct queue_entry_priv_pci *entry_priv;
1330         struct queue_entry *entry;
1331         struct txdone_entry_desc txdesc;
1332         u32 word;
1333
1334         while (!rt2x00queue_empty(queue)) {
1335                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1336                 entry_priv = entry->priv_data;
1337                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1338
1339                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1340                     !rt2x00_get_field32(word, TXD_W0_VALID))
1341                         break;
1342
1343                 /*
1344                  * Obtain the status about this packet.
1345                  */
1346                 txdesc.flags = 0;
1347                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1348                 case 0: /* Success */
1349                 case 1: /* Success with retry */
1350                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1351                         break;
1352                 case 2: /* Failure, excessive retries */
1353                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1354                         /* Don't break, this is a failed frame! */
1355                 default: /* Failure */
1356                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1357                 }
1358                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1359
1360                 rt2x00lib_txdone(entry, &txdesc);
1361         }
1362 }
1363
1364 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1365 {
1366         struct rt2x00_dev *rt2x00dev = dev_instance;
1367         u32 reg;
1368
1369         /*
1370          * Get the interrupt sources & saved to local variable.
1371          * Write register value back to clear pending interrupts.
1372          */
1373         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1374         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1375
1376         if (!reg)
1377                 return IRQ_NONE;
1378
1379         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1380                 return IRQ_HANDLED;
1381
1382         /*
1383          * Handle interrupts, walk through all bits
1384          * and run the tasks, the bits are checked in order of
1385          * priority.
1386          */
1387
1388         /*
1389          * 1 - Beacon timer expired interrupt.
1390          */
1391         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1392                 rt2x00lib_beacondone(rt2x00dev);
1393
1394         /*
1395          * 2 - Rx ring done interrupt.
1396          */
1397         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1398                 rt2x00pci_rxdone(rt2x00dev);
1399
1400         /*
1401          * 3 - Atim ring transmit done interrupt.
1402          */
1403         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1404                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1405
1406         /*
1407          * 4 - Priority ring transmit done interrupt.
1408          */
1409         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1410                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1411
1412         /*
1413          * 5 - Tx ring transmit done interrupt.
1414          */
1415         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1416                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1417
1418         return IRQ_HANDLED;
1419 }
1420
1421 /*
1422  * Device probe functions.
1423  */
1424 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1425 {
1426         struct eeprom_93cx6 eeprom;
1427         u32 reg;
1428         u16 word;
1429         u8 *mac;
1430
1431         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1432
1433         eeprom.data = rt2x00dev;
1434         eeprom.register_read = rt2500pci_eepromregister_read;
1435         eeprom.register_write = rt2500pci_eepromregister_write;
1436         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1437             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1438         eeprom.reg_data_in = 0;
1439         eeprom.reg_data_out = 0;
1440         eeprom.reg_data_clock = 0;
1441         eeprom.reg_chip_select = 0;
1442
1443         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1444                                EEPROM_SIZE / sizeof(u16));
1445
1446         /*
1447          * Start validation of the data that has been read.
1448          */
1449         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1450         if (!is_valid_ether_addr(mac)) {
1451                 DECLARE_MAC_BUF(macbuf);
1452
1453                 random_ether_addr(mac);
1454                 EEPROM(rt2x00dev, "MAC: %s\n",
1455                        print_mac(macbuf, mac));
1456         }
1457
1458         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1459         if (word == 0xffff) {
1460                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1461                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1462                                    ANTENNA_SW_DIVERSITY);
1463                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1464                                    ANTENNA_SW_DIVERSITY);
1465                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1466                                    LED_MODE_DEFAULT);
1467                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1468                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1469                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1470                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1471                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1472         }
1473
1474         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1475         if (word == 0xffff) {
1476                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1477                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1478                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1479                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1480                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1481         }
1482
1483         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1484         if (word == 0xffff) {
1485                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1486                                    DEFAULT_RSSI_OFFSET);
1487                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1488                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1489         }
1490
1491         return 0;
1492 }
1493
1494 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1495 {
1496         u32 reg;
1497         u16 value;
1498         u16 eeprom;
1499
1500         /*
1501          * Read EEPROM word for configuration.
1502          */
1503         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1504
1505         /*
1506          * Identify RF chipset.
1507          */
1508         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1509         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1510         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1511
1512         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1513             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1514             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1515             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1516             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1517             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1518                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1519                 return -ENODEV;
1520         }
1521
1522         /*
1523          * Identify default antenna configuration.
1524          */
1525         rt2x00dev->default_ant.tx =
1526             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1527         rt2x00dev->default_ant.rx =
1528             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1529
1530         /*
1531          * Store led mode, for correct led behaviour.
1532          */
1533 #ifdef CONFIG_RT2500PCI_LEDS
1534         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1535
1536         rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1537         if (value == LED_MODE_TXRX_ACTIVITY)
1538                 rt2500pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1539                                    LED_TYPE_ACTIVITY);
1540 #endif /* CONFIG_RT2500PCI_LEDS */
1541
1542         /*
1543          * Detect if this device has an hardware controlled radio.
1544          */
1545 #ifdef CONFIG_RT2500PCI_RFKILL
1546         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1547                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1548 #endif /* CONFIG_RT2500PCI_RFKILL */
1549
1550         /*
1551          * Check if the BBP tuning should be enabled.
1552          */
1553         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1554
1555         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1556                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1557
1558         /*
1559          * Read the RSSI <-> dBm offset information.
1560          */
1561         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1562         rt2x00dev->rssi_offset =
1563             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1564
1565         return 0;
1566 }
1567
1568 /*
1569  * RF value list for RF2522
1570  * Supports: 2.4 GHz
1571  */
1572 static const struct rf_channel rf_vals_bg_2522[] = {
1573         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1574         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1575         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1576         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1577         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1578         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1579         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1580         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1581         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1582         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1583         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1584         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1585         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1586         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1587 };
1588
1589 /*
1590  * RF value list for RF2523
1591  * Supports: 2.4 GHz
1592  */
1593 static const struct rf_channel rf_vals_bg_2523[] = {
1594         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1595         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1596         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1597         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1598         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1599         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1600         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1601         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1602         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1603         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1604         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1605         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1606         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1607         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1608 };
1609
1610 /*
1611  * RF value list for RF2524
1612  * Supports: 2.4 GHz
1613  */
1614 static const struct rf_channel rf_vals_bg_2524[] = {
1615         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1616         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1617         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1618         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1619         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1620         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1621         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1622         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1623         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1624         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1625         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1626         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1627         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1628         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1629 };
1630
1631 /*
1632  * RF value list for RF2525
1633  * Supports: 2.4 GHz
1634  */
1635 static const struct rf_channel rf_vals_bg_2525[] = {
1636         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1637         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1638         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1639         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1640         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1641         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1642         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1643         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1644         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1645         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1646         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1647         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1648         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1649         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1650 };
1651
1652 /*
1653  * RF value list for RF2525e
1654  * Supports: 2.4 GHz
1655  */
1656 static const struct rf_channel rf_vals_bg_2525e[] = {
1657         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1658         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1659         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1660         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1661         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1662         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1663         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1664         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1665         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1666         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1667         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1668         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1669         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1670         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1671 };
1672
1673 /*
1674  * RF value list for RF5222
1675  * Supports: 2.4 GHz & 5.2 GHz
1676  */
1677 static const struct rf_channel rf_vals_5222[] = {
1678         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1679         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1680         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1681         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1682         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1683         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1684         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1685         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1686         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1687         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1688         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1689         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1690         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1691         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1692
1693         /* 802.11 UNI / HyperLan 2 */
1694         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1695         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1696         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1697         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1698         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1699         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1700         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1701         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1702
1703         /* 802.11 HyperLan 2 */
1704         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1705         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1706         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1707         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1708         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1709         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1710         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1711         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1712         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1713         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1714
1715         /* 802.11 UNII */
1716         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1717         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1718         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1719         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1720         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1721 };
1722
1723 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1724 {
1725         struct hw_mode_spec *spec = &rt2x00dev->spec;
1726         u8 *txpower;
1727         unsigned int i;
1728
1729         /*
1730          * Initialize all hw fields.
1731          */
1732         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1733                                IEEE80211_HW_SIGNAL_DBM;
1734
1735         rt2x00dev->hw->extra_tx_headroom = 0;
1736
1737         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1738         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1739                                 rt2x00_eeprom_addr(rt2x00dev,
1740                                                    EEPROM_MAC_ADDR_0));
1741
1742         /*
1743          * Convert tx_power array in eeprom.
1744          */
1745         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1746         for (i = 0; i < 14; i++)
1747                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1748
1749         /*
1750          * Initialize hw_mode information.
1751          */
1752         spec->supported_bands = SUPPORT_BAND_2GHZ;
1753         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1754         spec->tx_power_a = NULL;
1755         spec->tx_power_bg = txpower;
1756         spec->tx_power_default = DEFAULT_TXPOWER;
1757
1758         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1759                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1760                 spec->channels = rf_vals_bg_2522;
1761         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1762                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1763                 spec->channels = rf_vals_bg_2523;
1764         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1765                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1766                 spec->channels = rf_vals_bg_2524;
1767         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1768                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1769                 spec->channels = rf_vals_bg_2525;
1770         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1771                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1772                 spec->channels = rf_vals_bg_2525e;
1773         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1774                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1775                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1776                 spec->channels = rf_vals_5222;
1777         }
1778 }
1779
1780 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1781 {
1782         int retval;
1783
1784         /*
1785          * Allocate eeprom data.
1786          */
1787         retval = rt2500pci_validate_eeprom(rt2x00dev);
1788         if (retval)
1789                 return retval;
1790
1791         retval = rt2500pci_init_eeprom(rt2x00dev);
1792         if (retval)
1793                 return retval;
1794
1795         /*
1796          * Initialize hw specifications.
1797          */
1798         rt2500pci_probe_hw_mode(rt2x00dev);
1799
1800         /*
1801          * This device requires the atim queue and DMA-mapped skbs.
1802          */
1803         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1804         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
1805
1806         /*
1807          * Set the rssi offset.
1808          */
1809         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1810
1811         return 0;
1812 }
1813
1814 /*
1815  * IEEE80211 stack callback functions.
1816  */
1817 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1818                                      u32 short_retry, u32 long_retry)
1819 {
1820         struct rt2x00_dev *rt2x00dev = hw->priv;
1821         u32 reg;
1822
1823         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1824         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1825         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1826         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1827
1828         return 0;
1829 }
1830
1831 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1832 {
1833         struct rt2x00_dev *rt2x00dev = hw->priv;
1834         u64 tsf;
1835         u32 reg;
1836
1837         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1838         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1839         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1840         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1841
1842         return tsf;
1843 }
1844
1845 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1846 {
1847         struct rt2x00_dev *rt2x00dev = hw->priv;
1848         u32 reg;
1849
1850         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1851         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1852 }
1853
1854 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1855         .tx                     = rt2x00mac_tx,
1856         .start                  = rt2x00mac_start,
1857         .stop                   = rt2x00mac_stop,
1858         .add_interface          = rt2x00mac_add_interface,
1859         .remove_interface       = rt2x00mac_remove_interface,
1860         .config                 = rt2x00mac_config,
1861         .config_interface       = rt2x00mac_config_interface,
1862         .configure_filter       = rt2x00mac_configure_filter,
1863         .get_stats              = rt2x00mac_get_stats,
1864         .set_retry_limit        = rt2500pci_set_retry_limit,
1865         .bss_info_changed       = rt2x00mac_bss_info_changed,
1866         .conf_tx                = rt2x00mac_conf_tx,
1867         .get_tx_stats           = rt2x00mac_get_tx_stats,
1868         .get_tsf                = rt2500pci_get_tsf,
1869         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1870 };
1871
1872 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1873         .irq_handler            = rt2500pci_interrupt,
1874         .probe_hw               = rt2500pci_probe_hw,
1875         .initialize             = rt2x00pci_initialize,
1876         .uninitialize           = rt2x00pci_uninitialize,
1877         .init_rxentry           = rt2500pci_init_rxentry,
1878         .init_txentry           = rt2500pci_init_txentry,
1879         .set_device_state       = rt2500pci_set_device_state,
1880         .rfkill_poll            = rt2500pci_rfkill_poll,
1881         .link_stats             = rt2500pci_link_stats,
1882         .reset_tuner            = rt2500pci_reset_tuner,
1883         .link_tuner             = rt2500pci_link_tuner,
1884         .write_tx_desc          = rt2500pci_write_tx_desc,
1885         .write_tx_data          = rt2x00pci_write_tx_data,
1886         .write_beacon           = rt2500pci_write_beacon,
1887         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1888         .fill_rxdone            = rt2500pci_fill_rxdone,
1889         .config_filter          = rt2500pci_config_filter,
1890         .config_intf            = rt2500pci_config_intf,
1891         .config_erp             = rt2500pci_config_erp,
1892         .config                 = rt2500pci_config,
1893 };
1894
1895 static const struct data_queue_desc rt2500pci_queue_rx = {
1896         .entry_num              = RX_ENTRIES,
1897         .data_size              = DATA_FRAME_SIZE,
1898         .desc_size              = RXD_DESC_SIZE,
1899         .priv_size              = sizeof(struct queue_entry_priv_pci),
1900 };
1901
1902 static const struct data_queue_desc rt2500pci_queue_tx = {
1903         .entry_num              = TX_ENTRIES,
1904         .data_size              = DATA_FRAME_SIZE,
1905         .desc_size              = TXD_DESC_SIZE,
1906         .priv_size              = sizeof(struct queue_entry_priv_pci),
1907 };
1908
1909 static const struct data_queue_desc rt2500pci_queue_bcn = {
1910         .entry_num              = BEACON_ENTRIES,
1911         .data_size              = MGMT_FRAME_SIZE,
1912         .desc_size              = TXD_DESC_SIZE,
1913         .priv_size              = sizeof(struct queue_entry_priv_pci),
1914 };
1915
1916 static const struct data_queue_desc rt2500pci_queue_atim = {
1917         .entry_num              = ATIM_ENTRIES,
1918         .data_size              = DATA_FRAME_SIZE,
1919         .desc_size              = TXD_DESC_SIZE,
1920         .priv_size              = sizeof(struct queue_entry_priv_pci),
1921 };
1922
1923 static const struct rt2x00_ops rt2500pci_ops = {
1924         .name           = KBUILD_MODNAME,
1925         .max_sta_intf   = 1,
1926         .max_ap_intf    = 1,
1927         .eeprom_size    = EEPROM_SIZE,
1928         .rf_size        = RF_SIZE,
1929         .tx_queues      = NUM_TX_QUEUES,
1930         .rx             = &rt2500pci_queue_rx,
1931         .tx             = &rt2500pci_queue_tx,
1932         .bcn            = &rt2500pci_queue_bcn,
1933         .atim           = &rt2500pci_queue_atim,
1934         .lib            = &rt2500pci_rt2x00_ops,
1935         .hw             = &rt2500pci_mac80211_ops,
1936 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1937         .debugfs        = &rt2500pci_rt2x00debug,
1938 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1939 };
1940
1941 /*
1942  * RT2500pci module information.
1943  */
1944 static struct pci_device_id rt2500pci_device_table[] = {
1945         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1946         { 0, }
1947 };
1948
1949 MODULE_AUTHOR(DRV_PROJECT);
1950 MODULE_VERSION(DRV_VERSION);
1951 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1952 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1953 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1954 MODULE_LICENSE("GPL");
1955
1956 static struct pci_driver rt2500pci_driver = {
1957         .name           = KBUILD_MODNAME,
1958         .id_table       = rt2500pci_device_table,
1959         .probe          = rt2x00pci_probe,
1960         .remove         = __devexit_p(rt2x00pci_remove),
1961         .suspend        = rt2x00pci_suspend,
1962         .resume         = rt2x00pci_resume,
1963 };
1964
1965 static int __init rt2500pci_init(void)
1966 {
1967         return pci_register_driver(&rt2500pci_driver);
1968 }
1969
1970 static void __exit rt2500pci_exit(void)
1971 {
1972         pci_unregister_driver(&rt2500pci_driver);
1973 }
1974
1975 module_init(rt2500pci_init);
1976 module_exit(rt2500pci_exit);