git.oblomov.eu Git - linux-2.6/blob - sound/soc/codecs/wm8400.c

   1 /*
   2  * wm8400.c  --  WM8400 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/pm.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/mfd/wm8400-audio.h>
  23 #include <linux/mfd/wm8400-private.h>
  24 #include <sound/core.h>
  25 #include <sound/pcm.h>
  26 #include <sound/pcm_params.h>
  27 #include <sound/soc.h>
  28 #include <sound/soc-dapm.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31
  32 #include "wm8400.h"
  33
  34 /* Fake register for internal state */
  35 #define WM8400_INTDRIVBITS      (WM8400_REGISTER_COUNT + 1)
  36 #define WM8400_INMIXL_PWR                       0
  37 #define WM8400_AINLMUX_PWR                      1
  38 #define WM8400_INMIXR_PWR                       2
  39 #define WM8400_AINRMUX_PWR                      3
  40
  41 static struct regulator_bulk_data power[] = {
  42         {
  43                 .supply = "I2S1VDD",
  44         },
  45         {
  46                 .supply = "I2S2VDD",
  47         },
  48         {
  49                 .supply = "DCVDD",
  50         },
  51         {
  52                 .supply = "FLLVDD",
  53         },
  54         {
  55                 .supply = "HPVDD",
  56         },
  57         {
  58                 .supply = "SPKVDD",
  59         },
  60 };
  61
  62 /* codec private data */
  63 struct wm8400_priv {
  64         struct snd_soc_codec codec;
  65         struct wm8400 *wm8400;
  66         u16 fake_register;
  67         unsigned int sysclk;
  68         unsigned int pcmclk;
  69         struct work_struct work;
  70 };
  71
  72 static inline unsigned int wm8400_read(struct snd_soc_codec *codec,
  73                                        unsigned int reg)
  74 {
  75         struct wm8400_priv *wm8400 = codec->private_data;
  76
  77         if (reg == WM8400_INTDRIVBITS)
  78                 return wm8400->fake_register;
  79         else
  80                 return wm8400_reg_read(wm8400->wm8400, reg);
  81 }
  82
  83 /*
  84  * write to the wm8400 register space
  85  */
  86 static int wm8400_write(struct snd_soc_codec *codec, unsigned int reg,
  87         unsigned int value)
  88 {
  89         struct wm8400_priv *wm8400 = codec->private_data;
  90
  91         if (reg == WM8400_INTDRIVBITS) {
  92                 wm8400->fake_register = value;
  93                 return 0;
  94         } else
  95                 return wm8400_set_bits(wm8400->wm8400, reg, 0xffff, value);
  96 }
  97
  98 static void wm8400_codec_reset(struct snd_soc_codec *codec)
  99 {
 100         struct wm8400_priv *wm8400 = codec->private_data;
 101
 102         wm8400_reset_codec_reg_cache(wm8400->wm8400);
 103 }
 104
 105 static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600);
 106
 107 static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000);
 108
 109 static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, -2100, 0);
 110
 111 static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600);
 112
 113 static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0);
 114
 115 static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0);
 116
 117 static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763);
 118
 119 static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0);
 120
 121 static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
 122         struct snd_ctl_elem_value *ucontrol)
 123 {
 124         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 125         struct soc_mixer_control *mc =
 126                 (struct soc_mixer_control *)kcontrol->private_value;
 127         int reg = mc->reg;
 128         int ret;
 129         u16 val;
 130
 131         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 132         if (ret < 0)
 133                 return ret;
 134
 135         /* now hit the volume update bits (always bit 8) */
 136         val = wm8400_read(codec, reg);
 137         return wm8400_write(codec, reg, val | 0x0100);
 138 }
 139
 140 #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
 141 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 142         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 143                 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 144         .tlv.p = (tlv_array), \
 145         .info = snd_soc_info_volsw, \
 146         .get = snd_soc_get_volsw, .put = wm8400_outpga_put_volsw_vu, \
 147         .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
 148
 149
 150 static const char *wm8400_digital_sidetone[] =
 151         {"None", "Left ADC", "Right ADC", "Reserved"};
 152
 153 static const struct soc_enum wm8400_left_digital_sidetone_enum =
 154 SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE,
 155                 WM8400_ADC_TO_DACL_SHIFT, 2, wm8400_digital_sidetone);
 156
 157 static const struct soc_enum wm8400_right_digital_sidetone_enum =
 158 SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE,
 159                 WM8400_ADC_TO_DACR_SHIFT, 2, wm8400_digital_sidetone);
 160
 161 static const char *wm8400_adcmode[] =
 162         {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
 163
 164 static const struct soc_enum wm8400_right_adcmode_enum =
 165 SOC_ENUM_SINGLE(WM8400_ADC_CTRL, WM8400_ADC_HPF_CUT_SHIFT, 3, wm8400_adcmode);
 166
 167 static const struct snd_kcontrol_new wm8400_snd_controls[] = {
 168 /* INMIXL */
 169 SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
 170            1, 0),
 171 SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
 172            1, 0),
 173 /* INMIXR */
 174 SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
 175            1, 0),
 176 SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
 177            1, 0),
 178
 179 /* LOMIX */
 180 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
 181         WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
 182 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
 183         WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
 184 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
 185         WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
 186 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
 187         WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
 188 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
 189         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
 190 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
 191         WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
 192
 193 /* ROMIX */
 194 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
 195         WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
 196 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
 197         WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
 198 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
 199         WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
 200 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
 201         WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
 202 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
 203         WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
 204 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
 205         WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
 206
 207 /* LOUT */
 208 WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
 209         WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
 210 SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
 211
 212 /* ROUT */
 213 WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
 214         WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
 215 SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
 216
 217 /* LOPGA */
 218 WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
 219         WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
 220 SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
 221         WM8400_LOPGAZC_SHIFT, 1, 0),
 222
 223 /* ROPGA */
 224 WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
 225         WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
 226 SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
 227         WM8400_ROPGAZC_SHIFT, 1, 0),
 228
 229 SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
 230         WM8400_LONMUTE_SHIFT, 1, 0),
 231 SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
 232         WM8400_LOPMUTE_SHIFT, 1, 0),
 233 SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
 234         WM8400_LOATTN_SHIFT, 1, 0),
 235 SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
 236         WM8400_RONMUTE_SHIFT, 1, 0),
 237 SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
 238         WM8400_ROPMUTE_SHIFT, 1, 0),
 239 SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
 240         WM8400_ROATTN_SHIFT, 1, 0),
 241
 242 SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
 243         WM8400_OUT3MUTE_SHIFT, 1, 0),
 244 SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
 245         WM8400_OUT3ATTN_SHIFT, 1, 0),
 246
 247 SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
 248         WM8400_OUT4MUTE_SHIFT, 1, 0),
 249 SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
 250         WM8400_OUT4ATTN_SHIFT, 1, 0),
 251
 252 SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
 253         WM8400_CDMODE_SHIFT, 1, 0),
 254
 255 SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
 256         WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
 257 SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
 258         WM8400_DCGAIN_SHIFT, 6, 0),
 259 SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
 260         WM8400_ACGAIN_SHIFT, 6, 0),
 261
 262 WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
 263         WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
 264         127, 0, out_dac_tlv),
 265
 266 WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
 267         WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
 268         127, 0, out_dac_tlv),
 269
 270 SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
 271 SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
 272
 273 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
 274         WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
 275 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
 276         WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
 277
 278 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
 279         WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
 280
 281 SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
 282
 283 WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
 284         WM8400_LEFT_ADC_DIGITAL_VOLUME,
 285         WM8400_ADCL_VOL_SHIFT,
 286         WM8400_ADCL_VOL_MASK,
 287         0,
 288         in_adc_tlv),
 289
 290 WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
 291         WM8400_RIGHT_ADC_DIGITAL_VOLUME,
 292         WM8400_ADCR_VOL_SHIFT,
 293         WM8400_ADCR_VOL_MASK,
 294         0,
 295         in_adc_tlv),
 296
 297 WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
 298         WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
 299         WM8400_LIN12VOL_SHIFT,
 300         WM8400_LIN12VOL_MASK,
 301         0,
 302         in_pga_tlv),
 303
 304 SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
 305         WM8400_LI12ZC_SHIFT, 1, 0),
 306
 307 SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
 308         WM8400_LI12MUTE_SHIFT, 1, 0),
 309
 310 WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
 311         WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
 312         WM8400_LIN34VOL_SHIFT,
 313         WM8400_LIN34VOL_MASK,
 314         0,
 315         in_pga_tlv),
 316
 317 SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
 318         WM8400_LI34ZC_SHIFT, 1, 0),
 319
 320 SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
 321         WM8400_LI34MUTE_SHIFT, 1, 0),
 322
 323 WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
 324         WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
 325         WM8400_RIN12VOL_SHIFT,
 326         WM8400_RIN12VOL_MASK,
 327         0,
 328         in_pga_tlv),
 329
 330 SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
 331         WM8400_RI12ZC_SHIFT, 1, 0),
 332
 333 SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
 334         WM8400_RI12MUTE_SHIFT, 1, 0),
 335
 336 WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
 337         WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
 338         WM8400_RIN34VOL_SHIFT,
 339         WM8400_RIN34VOL_MASK,
 340         0,
 341         in_pga_tlv),
 342
 343 SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
 344         WM8400_RI34ZC_SHIFT, 1, 0),
 345
 346 SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
 347         WM8400_RI34MUTE_SHIFT, 1, 0),
 348
 349 };
 350
 351 /* add non dapm controls */
 352 static int wm8400_add_controls(struct snd_soc_codec *codec)
 353 {
 354         return snd_soc_add_controls(codec, wm8400_snd_controls,
 355                                 ARRAY_SIZE(wm8400_snd_controls));
 356 }
 357
 358 /*
 359  * _DAPM_ Controls
 360  */
 361
 362 static int inmixer_event (struct snd_soc_dapm_widget *w,
 363         struct snd_kcontrol *kcontrol, int event)
 364 {
 365         u16 reg, fakepower;
 366
 367         reg = wm8400_read(w->codec, WM8400_POWER_MANAGEMENT_2);
 368         fakepower = wm8400_read(w->codec, WM8400_INTDRIVBITS);
 369
 370         if (fakepower & ((1 << WM8400_INMIXL_PWR) |
 371                 (1 << WM8400_AINLMUX_PWR))) {
 372                 reg |= WM8400_AINL_ENA;
 373         } else {
 374                 reg &= ~WM8400_AINL_ENA;
 375         }
 376
 377         if (fakepower & ((1 << WM8400_INMIXR_PWR) |
 378                 (1 << WM8400_AINRMUX_PWR))) {
 379                 reg |= WM8400_AINR_ENA;
 380         } else {
 381                 reg &= ~WM8400_AINL_ENA;
 382         }
 383         wm8400_write(w->codec, WM8400_POWER_MANAGEMENT_2, reg);
 384
 385         return 0;
 386 }
 387
 388 static int outmixer_event (struct snd_soc_dapm_widget *w,
 389         struct snd_kcontrol * kcontrol, int event)
 390 {
 391         struct soc_mixer_control *mc =
 392                 (struct soc_mixer_control *)kcontrol->private_value;
 393         u32 reg_shift = mc->shift;
 394         int ret = 0;
 395         u16 reg;
 396
 397         switch (reg_shift) {
 398         case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
 399                 reg = wm8400_read(w->codec, WM8400_OUTPUT_MIXER1);
 400                 if (reg & WM8400_LDLO) {
 401                         printk(KERN_WARNING
 402                         "Cannot set as Output Mixer 1 LDLO Set\n");
 403                         ret = -1;
 404                 }
 405                 break;
 406         case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
 407                 reg = wm8400_read(w->codec, WM8400_OUTPUT_MIXER2);
 408                 if (reg & WM8400_RDRO) {
 409                         printk(KERN_WARNING
 410                         "Cannot set as Output Mixer 2 RDRO Set\n");
 411                         ret = -1;
 412                 }
 413                 break;
 414         case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
 415                 reg = wm8400_read(w->codec, WM8400_SPEAKER_MIXER);
 416                 if (reg & WM8400_LDSPK) {
 417                         printk(KERN_WARNING
 418                         "Cannot set as Speaker Mixer LDSPK Set\n");
 419                         ret = -1;
 420                 }
 421                 break;
 422         case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
 423                 reg = wm8400_read(w->codec, WM8400_SPEAKER_MIXER);
 424                 if (reg & WM8400_RDSPK) {
 425                         printk(KERN_WARNING
 426                         "Cannot set as Speaker Mixer RDSPK Set\n");
 427                         ret = -1;
 428                 }
 429                 break;
 430         }
 431
 432         return ret;
 433 }
 434
 435 /* INMIX dB values */
 436 static const unsigned int in_mix_tlv[] = {
 437         TLV_DB_RANGE_HEAD(1),
 438         0,7, TLV_DB_LINEAR_ITEM(-1200, 600),
 439 };
 440
 441 /* Left In PGA Connections */
 442 static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
 443 SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
 444 SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
 445 };
 446
 447 static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
 448 SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
 449 SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
 450 };
 451
 452 /* Right In PGA Connections */
 453 static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
 454 SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
 455 SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
 456 };
 457
 458 static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
 459 SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
 460 SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
 461 };
 462
 463 /* INMIXL */
 464 static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
 465 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
 466         WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
 467 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
 468         7, 0, in_mix_tlv),
 469 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
 470                 1, 0),
 471 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
 472                 1, 0),
 473 };
 474
 475 /* INMIXR */
 476 static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
 477 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
 478         WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
 479 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
 480         7, 0, in_mix_tlv),
 481 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
 482         1, 0),
 483 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
 484         1, 0),
 485 };
 486
 487 /* AINLMUX */
 488 static const char *wm8400_ainlmux[] =
 489         {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
 490
 491 static const struct soc_enum wm8400_ainlmux_enum =
 492 SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINLMODE_SHIFT,
 493         ARRAY_SIZE(wm8400_ainlmux), wm8400_ainlmux);
 494
 495 static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
 496 SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
 497
 498 /* DIFFINL */
 499
 500 /* AINRMUX */
 501 static const char *wm8400_ainrmux[] =
 502         {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
 503
 504 static const struct soc_enum wm8400_ainrmux_enum =
 505 SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINRMODE_SHIFT,
 506         ARRAY_SIZE(wm8400_ainrmux), wm8400_ainrmux);
 507
 508 static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
 509 SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
 510
 511 /* RXVOICE */
 512 static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = {
 513 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT,
 514                         WM8400_LR4BVOL_MASK, 0, in_mix_tlv),
 515 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT,
 516                         WM8400_RL4BVOL_MASK, 0, in_mix_tlv),
 517 };
 518
 519 /* LOMIX */
 520 static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
 521 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
 522         WM8400_LRBLO_SHIFT, 1, 0),
 523 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
 524         WM8400_LLBLO_SHIFT, 1, 0),
 525 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
 526         WM8400_LRI3LO_SHIFT, 1, 0),
 527 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
 528         WM8400_LLI3LO_SHIFT, 1, 0),
 529 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
 530         WM8400_LR12LO_SHIFT, 1, 0),
 531 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
 532         WM8400_LL12LO_SHIFT, 1, 0),
 533 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
 534         WM8400_LDLO_SHIFT, 1, 0),
 535 };
 536
 537 /* ROMIX */
 538 static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
 539 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
 540         WM8400_RLBRO_SHIFT, 1, 0),
 541 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
 542         WM8400_RRBRO_SHIFT, 1, 0),
 543 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
 544         WM8400_RLI3RO_SHIFT, 1, 0),
 545 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
 546         WM8400_RRI3RO_SHIFT, 1, 0),
 547 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
 548         WM8400_RL12RO_SHIFT, 1, 0),
 549 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
 550         WM8400_RR12RO_SHIFT, 1, 0),
 551 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
 552         WM8400_RDRO_SHIFT, 1, 0),
 553 };
 554
 555 /* LONMIX */
 556 static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
 557 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
 558         WM8400_LLOPGALON_SHIFT, 1, 0),
 559 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
 560         WM8400_LROPGALON_SHIFT, 1, 0),
 561 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
 562         WM8400_LOPLON_SHIFT, 1, 0),
 563 };
 564
 565 /* LOPMIX */
 566 static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
 567 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
 568         WM8400_LR12LOP_SHIFT, 1, 0),
 569 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
 570         WM8400_LL12LOP_SHIFT, 1, 0),
 571 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
 572         WM8400_LLOPGALOP_SHIFT, 1, 0),
 573 };
 574
 575 /* RONMIX */
 576 static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
 577 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
 578         WM8400_RROPGARON_SHIFT, 1, 0),
 579 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
 580         WM8400_RLOPGARON_SHIFT, 1, 0),
 581 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
 582         WM8400_ROPRON_SHIFT, 1, 0),
 583 };
 584
 585 /* ROPMIX */
 586 static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
 587 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
 588         WM8400_RL12ROP_SHIFT, 1, 0),
 589 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
 590         WM8400_RR12ROP_SHIFT, 1, 0),
 591 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
 592         WM8400_RROPGAROP_SHIFT, 1, 0),
 593 };
 594
 595 /* OUT3MIX */
 596 static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
 597 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
 598         WM8400_LI4O3_SHIFT, 1, 0),
 599 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
 600         WM8400_LPGAO3_SHIFT, 1, 0),
 601 };
 602
 603 /* OUT4MIX */
 604 static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
 605 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
 606         WM8400_RPGAO4_SHIFT, 1, 0),
 607 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
 608         WM8400_RI4O4_SHIFT, 1, 0),
 609 };
 610
 611 /* SPKMIX */
 612 static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
 613 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
 614         WM8400_LI2SPK_SHIFT, 1, 0),
 615 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
 616         WM8400_LB2SPK_SHIFT, 1, 0),
 617 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
 618         WM8400_LOPGASPK_SHIFT, 1, 0),
 619 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
 620         WM8400_LDSPK_SHIFT, 1, 0),
 621 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
 622         WM8400_RDSPK_SHIFT, 1, 0),
 623 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
 624         WM8400_ROPGASPK_SHIFT, 1, 0),
 625 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
 626         WM8400_RL12ROP_SHIFT, 1, 0),
 627 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
 628         WM8400_RI2SPK_SHIFT, 1, 0),
 629 };
 630
 631 static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
 632 /* Input Side */
 633 /* Input Lines */
 634 SND_SOC_DAPM_INPUT("LIN1"),
 635 SND_SOC_DAPM_INPUT("LIN2"),
 636 SND_SOC_DAPM_INPUT("LIN3"),
 637 SND_SOC_DAPM_INPUT("LIN4/RXN"),
 638 SND_SOC_DAPM_INPUT("RIN3"),
 639 SND_SOC_DAPM_INPUT("RIN4/RXP"),
 640 SND_SOC_DAPM_INPUT("RIN1"),
 641 SND_SOC_DAPM_INPUT("RIN2"),
 642 SND_SOC_DAPM_INPUT("Internal ADC Source"),
 643
 644 /* DACs */
 645 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
 646         WM8400_ADCL_ENA_SHIFT, 0),
 647 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
 648         WM8400_ADCR_ENA_SHIFT, 0),
 649
 650 /* Input PGAs */
 651 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
 652                    WM8400_LIN12_ENA_SHIFT,
 653                    0, &wm8400_dapm_lin12_pga_controls[0],
 654                    ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
 655 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
 656                    WM8400_LIN34_ENA_SHIFT,
 657                    0, &wm8400_dapm_lin34_pga_controls[0],
 658                    ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
 659 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
 660                    WM8400_RIN12_ENA_SHIFT,
 661                    0, &wm8400_dapm_rin12_pga_controls[0],
 662                    ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
 663 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
 664                    WM8400_RIN34_ENA_SHIFT,
 665                    0, &wm8400_dapm_rin34_pga_controls[0],
 666                    ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
 667
 668 /* INMIXL */
 669 SND_SOC_DAPM_MIXER_E("INMIXL", WM8400_INTDRIVBITS, WM8400_INMIXL_PWR, 0,
 670         &wm8400_dapm_inmixl_controls[0],
 671         ARRAY_SIZE(wm8400_dapm_inmixl_controls),
 672         inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 673
 674 /* AINLMUX */
 675 SND_SOC_DAPM_MUX_E("AILNMUX", WM8400_INTDRIVBITS, WM8400_AINLMUX_PWR, 0,
 676         &wm8400_dapm_ainlmux_controls, inmixer_event,
 677         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 678
 679 /* INMIXR */
 680 SND_SOC_DAPM_MIXER_E("INMIXR", WM8400_INTDRIVBITS, WM8400_INMIXR_PWR, 0,
 681         &wm8400_dapm_inmixr_controls[0],
 682         ARRAY_SIZE(wm8400_dapm_inmixr_controls),
 683         inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 684
 685 /* AINRMUX */
 686 SND_SOC_DAPM_MUX_E("AIRNMUX", WM8400_INTDRIVBITS, WM8400_AINRMUX_PWR, 0,
 687         &wm8400_dapm_ainrmux_controls, inmixer_event,
 688         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 689
 690 /* Output Side */
 691 /* DACs */
 692 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
 693         WM8400_DACL_ENA_SHIFT, 0),
 694 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
 695         WM8400_DACR_ENA_SHIFT, 0),
 696
 697 /* LOMIX */
 698 SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
 699                      WM8400_LOMIX_ENA_SHIFT,
 700                      0, &wm8400_dapm_lomix_controls[0],
 701                      ARRAY_SIZE(wm8400_dapm_lomix_controls),
 702                      outmixer_event, SND_SOC_DAPM_PRE_REG),
 703
 704 /* LONMIX */
 705 SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
 706                    0, &wm8400_dapm_lonmix_controls[0],
 707                    ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
 708
 709 /* LOPMIX */
 710 SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
 711                    0, &wm8400_dapm_lopmix_controls[0],
 712                    ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
 713
 714 /* OUT3MIX */
 715 SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
 716                    0, &wm8400_dapm_out3mix_controls[0],
 717                    ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
 718
 719 /* SPKMIX */
 720 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
 721                      0, &wm8400_dapm_spkmix_controls[0],
 722                      ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
 723                      SND_SOC_DAPM_PRE_REG),
 724
 725 /* OUT4MIX */
 726 SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
 727         0, &wm8400_dapm_out4mix_controls[0],
 728         ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
 729
 730 /* ROPMIX */
 731 SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
 732                    0, &wm8400_dapm_ropmix_controls[0],
 733                    ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
 734
 735 /* RONMIX */
 736 SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
 737                    0, &wm8400_dapm_ronmix_controls[0],
 738                    ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
 739
 740 /* ROMIX */
 741 SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
 742                      WM8400_ROMIX_ENA_SHIFT,
 743                      0, &wm8400_dapm_romix_controls[0],
 744                      ARRAY_SIZE(wm8400_dapm_romix_controls),
 745                      outmixer_event, SND_SOC_DAPM_PRE_REG),
 746
 747 /* LOUT PGA */
 748 SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
 749                  0, NULL, 0),
 750
 751 /* ROUT PGA */
 752 SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
 753                  0, NULL, 0),
 754
 755 /* LOPGA */
 756 SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
 757         NULL, 0),
 758
 759 /* ROPGA */
 760 SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
 761         NULL, 0),
 762
 763 /* MICBIAS */
 764 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8400_POWER_MANAGEMENT_1,
 765         WM8400_MIC1BIAS_ENA_SHIFT, 0),
 766
 767 SND_SOC_DAPM_OUTPUT("LON"),
 768 SND_SOC_DAPM_OUTPUT("LOP"),
 769 SND_SOC_DAPM_OUTPUT("OUT3"),
 770 SND_SOC_DAPM_OUTPUT("LOUT"),
 771 SND_SOC_DAPM_OUTPUT("SPKN"),
 772 SND_SOC_DAPM_OUTPUT("SPKP"),
 773 SND_SOC_DAPM_OUTPUT("ROUT"),
 774 SND_SOC_DAPM_OUTPUT("OUT4"),
 775 SND_SOC_DAPM_OUTPUT("ROP"),
 776 SND_SOC_DAPM_OUTPUT("RON"),
 777
 778 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
 779 };
 780
 781 static const struct snd_soc_dapm_route audio_map[] = {
 782         /* Make DACs turn on when playing even if not mixed into any outputs */
 783         {"Internal DAC Sink", NULL, "Left DAC"},
 784         {"Internal DAC Sink", NULL, "Right DAC"},
 785
 786         /* Make ADCs turn on when recording
 787          * even if not mixed from any inputs */
 788         {"Left ADC", NULL, "Internal ADC Source"},
 789         {"Right ADC", NULL, "Internal ADC Source"},
 790
 791         /* Input Side */
 792         /* LIN12 PGA */
 793         {"LIN12 PGA", "LIN1 Switch", "LIN1"},
 794         {"LIN12 PGA", "LIN2 Switch", "LIN2"},
 795         /* LIN34 PGA */
 796         {"LIN34 PGA", "LIN3 Switch", "LIN3"},
 797         {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
 798         /* INMIXL */
 799         {"INMIXL", "Record Left Volume", "LOMIX"},
 800         {"INMIXL", "LIN2 Volume", "LIN2"},
 801         {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
 802         {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
 803         /* AILNMUX */
 804         {"AILNMUX", "INMIXL Mix", "INMIXL"},
 805         {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
 806         {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
 807         {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
 808         {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
 809         /* ADC */
 810         {"Left ADC", NULL, "AILNMUX"},
 811
 812         /* RIN12 PGA */
 813         {"RIN12 PGA", "RIN1 Switch", "RIN1"},
 814         {"RIN12 PGA", "RIN2 Switch", "RIN2"},
 815         /* RIN34 PGA */
 816         {"RIN34 PGA", "RIN3 Switch", "RIN3"},
 817         {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
 818         /* INMIXL */
 819         {"INMIXR", "Record Right Volume", "ROMIX"},
 820         {"INMIXR", "RIN2 Volume", "RIN2"},
 821         {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
 822         {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
 823         /* AIRNMUX */
 824         {"AIRNMUX", "INMIXR Mix", "INMIXR"},
 825         {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
 826         {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
 827         {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
 828         {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
 829         /* ADC */
 830         {"Right ADC", NULL, "AIRNMUX"},
 831
 832         /* LOMIX */
 833         {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
 834         {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
 835         {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 836         {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 837         {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
 838         {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
 839         {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
 840
 841         /* ROMIX */
 842         {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
 843         {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
 844         {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 845         {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 846         {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
 847         {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
 848         {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
 849
 850         /* SPKMIX */
 851         {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
 852         {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
 853         {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
 854         {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
 855         {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
 856         {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
 857         {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
 858         {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
 859
 860         /* LONMIX */
 861         {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
 862         {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
 863         {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
 864
 865         /* LOPMIX */
 866         {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 867         {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 868         {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
 869
 870         /* OUT3MIX */
 871         {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
 872         {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
 873
 874         /* OUT4MIX */
 875         {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
 876         {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
 877
 878         /* RONMIX */
 879         {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
 880         {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
 881         {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
 882
 883         /* ROPMIX */
 884         {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 885         {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 886         {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
 887
 888         /* Out Mixer PGAs */
 889         {"LOPGA", NULL, "LOMIX"},
 890         {"ROPGA", NULL, "ROMIX"},
 891
 892         {"LOUT PGA", NULL, "LOMIX"},
 893         {"ROUT PGA", NULL, "ROMIX"},
 894
 895         /* Output Pins */
 896         {"LON", NULL, "LONMIX"},
 897         {"LOP", NULL, "LOPMIX"},
 898         {"OUT3", NULL, "OUT3MIX"},
 899         {"LOUT", NULL, "LOUT PGA"},
 900         {"SPKN", NULL, "SPKMIX"},
 901         {"ROUT", NULL, "ROUT PGA"},
 902         {"OUT4", NULL, "OUT4MIX"},
 903         {"ROP", NULL, "ROPMIX"},
 904         {"RON", NULL, "RONMIX"},
 905 };
 906
 907 static int wm8400_add_widgets(struct snd_soc_codec *codec)
 908 {
 909         snd_soc_dapm_new_controls(codec, wm8400_dapm_widgets,
 910                                   ARRAY_SIZE(wm8400_dapm_widgets));
 911
 912         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 913
 914         snd_soc_dapm_new_widgets(codec);
 915         return 0;
 916 }
 917
 918 /*
 919  * Clock after FLL and dividers
 920  */
 921 static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 922                 int clk_id, unsigned int freq, int dir)
 923 {
 924         struct snd_soc_codec *codec = codec_dai->codec;
 925         struct wm8400_priv *wm8400 = codec->private_data;
 926
 927         wm8400->sysclk = freq;
 928         return 0;
 929 }
 930
 931 /*
 932  * Sets ADC and Voice DAC format.
 933  */
 934 static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
 935                 unsigned int fmt)
 936 {
 937         struct snd_soc_codec *codec = codec_dai->codec;
 938         u16 audio1, audio3;
 939
 940         audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1);
 941         audio3 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_3);
 942
 943         /* set master/slave audio interface */
 944         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 945         case SND_SOC_DAIFMT_CBS_CFS:
 946                 audio3 &= ~WM8400_AIF_MSTR1;
 947                 break;
 948         case SND_SOC_DAIFMT_CBM_CFM:
 949                 audio3 |= WM8400_AIF_MSTR1;
 950                 break;
 951         default:
 952                 return -EINVAL;
 953         }
 954
 955         audio1 &= ~WM8400_AIF_FMT_MASK;
 956
 957         /* interface format */
 958         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 959         case SND_SOC_DAIFMT_I2S:
 960                 audio1 |= WM8400_AIF_FMT_I2S;
 961                 audio1 &= ~WM8400_AIF_LRCLK_INV;
 962                 break;
 963         case SND_SOC_DAIFMT_RIGHT_J:
 964                 audio1 |= WM8400_AIF_FMT_RIGHTJ;
 965                 audio1 &= ~WM8400_AIF_LRCLK_INV;
 966                 break;
 967         case SND_SOC_DAIFMT_LEFT_J:
 968                 audio1 |= WM8400_AIF_FMT_LEFTJ;
 969                 audio1 &= ~WM8400_AIF_LRCLK_INV;
 970                 break;
 971         case SND_SOC_DAIFMT_DSP_A:
 972                 audio1 |= WM8400_AIF_FMT_DSP;
 973                 audio1 &= ~WM8400_AIF_LRCLK_INV;
 974                 break;
 975         case SND_SOC_DAIFMT_DSP_B:
 976                 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
 977                 break;
 978         default:
 979                 return -EINVAL;
 980         }
 981
 982         wm8400_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
 983         wm8400_write(codec, WM8400_AUDIO_INTERFACE_3, audio3);
 984         return 0;
 985 }
 986
 987 static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 988                 int div_id, int div)
 989 {
 990         struct snd_soc_codec *codec = codec_dai->codec;
 991         u16 reg;
 992
 993         switch (div_id) {
 994         case WM8400_MCLK_DIV:
 995                 reg = wm8400_read(codec, WM8400_CLOCKING_2) &
 996                         ~WM8400_MCLK_DIV_MASK;
 997                 wm8400_write(codec, WM8400_CLOCKING_2, reg | div);
 998                 break;
 999         case WM8400_DACCLK_DIV:
1000                 reg = wm8400_read(codec, WM8400_CLOCKING_2) &
1001                         ~WM8400_DAC_CLKDIV_MASK;
1002                 wm8400_write(codec, WM8400_CLOCKING_2, reg | div);
1003                 break;
1004         case WM8400_ADCCLK_DIV:
1005                 reg = wm8400_read(codec, WM8400_CLOCKING_2) &
1006                         ~WM8400_ADC_CLKDIV_MASK;
1007                 wm8400_write(codec, WM8400_CLOCKING_2, reg | div);
1008                 break;
1009         case WM8400_BCLK_DIV:
1010                 reg = wm8400_read(codec, WM8400_CLOCKING_1) &
1011                         ~WM8400_BCLK_DIV_MASK;
1012                 wm8400_write(codec, WM8400_CLOCKING_1, reg | div);
1013                 break;
1014         default:
1015                 return -EINVAL;
1016         }
1017
1018         return 0;
1019 }
1020
1021 /*
1022  * Set PCM DAI bit size and sample rate.
1023  */
1024 static int wm8400_hw_params(struct snd_pcm_substream *substream,
1025         struct snd_pcm_hw_params *params,
1026         struct snd_soc_dai *dai)
1027 {
1028         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1029         struct snd_soc_device *socdev = rtd->socdev;
1030         struct snd_soc_codec *codec = socdev->card->codec;
1031         u16 audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1);
1032
1033         audio1 &= ~WM8400_AIF_WL_MASK;
1034         /* bit size */
1035         switch (params_format(params)) {
1036         case SNDRV_PCM_FORMAT_S16_LE:
1037                 break;
1038         case SNDRV_PCM_FORMAT_S20_3LE:
1039                 audio1 |= WM8400_AIF_WL_20BITS;
1040                 break;
1041         case SNDRV_PCM_FORMAT_S24_LE:
1042                 audio1 |= WM8400_AIF_WL_24BITS;
1043                 break;
1044         case SNDRV_PCM_FORMAT_S32_LE:
1045                 audio1 |= WM8400_AIF_WL_32BITS;
1046                 break;
1047         }
1048
1049         wm8400_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1050         return 0;
1051 }
1052
1053 static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1054 {
1055         struct snd_soc_codec *codec = dai->codec;
1056         u16 val = wm8400_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1057
1058         if (mute)
1059                 wm8400_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1060         else
1061                 wm8400_write(codec, WM8400_DAC_CTRL, val);
1062
1063         return 0;
1064 }
1065
1066 /* TODO: set bias for best performance at standby */
1067 static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1068                                  enum snd_soc_bias_level level)
1069 {
1070         struct wm8400_priv *wm8400 = codec->private_data;
1071         u16 val;
1072         int ret;
1073
1074         switch (level) {
1075         case SND_SOC_BIAS_ON:
1076                 break;
1077
1078         case SND_SOC_BIAS_PREPARE:
1079                 /* VMID=2*50k */
1080                 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1) &
1081                         ~WM8400_VMID_MODE_MASK;
1082                 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2);
1083                 break;
1084
1085         case SND_SOC_BIAS_STANDBY:
1086                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1087                         ret = regulator_bulk_enable(ARRAY_SIZE(power),
1088                                                     &power[0]);
1089                         if (ret != 0) {
1090                                 dev_err(wm8400->wm8400->dev,
1091                                         "Failed to enable regulators: %d\n",
1092                                         ret);
1093                                 return ret;
1094                         }
1095
1096                         wm8400_write(codec, WM8400_POWER_MANAGEMENT_1,
1097                                      WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1098
1099                         /* Enable all output discharge bits */
1100                         wm8400_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1101                                 WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1102                                 WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1103                                 WM8400_DIS_ROUT);
1104
1105                         /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1106                         wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1107                                      WM8400_BUFDCOPEN | WM8400_POBCTRL);
1108
1109                         msleep(500);
1110
1111                         /* Enable outputs */
1112                         val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1);
1113                         val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1114                                 WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1115                                 WM8400_ROUT_ENA;
1116                         wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1117
1118                         /* disable all output discharge bits */
1119                         wm8400_write(codec, WM8400_ANTIPOP1, 0);
1120
1121                         /* Enable VREF & VMID at 2x50k */
1122                         val |= 0x2 | WM8400_VREF_ENA;
1123                         wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1124
1125                         msleep(600);
1126
1127                         /* Enable BUFIOEN */
1128                         wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1129                                      WM8400_BUFDCOPEN | WM8400_POBCTRL |
1130                                      WM8400_BUFIOEN);
1131
1132                         /* Disable outputs */
1133                         val &= ~(WM8400_SPK_ENA | WM8400_OUT3_ENA |
1134                                  WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1135                                  WM8400_ROUT_ENA);
1136                         wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1137
1138                         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1139                         wm8400_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1140                 }
1141
1142                 /* VMID=2*300k */
1143                 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1) &
1144                         ~WM8400_VMID_MODE_MASK;
1145                 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4);
1146                 break;
1147
1148         case SND_SOC_BIAS_OFF:
1149                 /* Enable POBCTRL and SOFT_ST */
1150                 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1151                         WM8400_POBCTRL | WM8400_BUFIOEN);
1152
1153                 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1154                 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1155                         WM8400_BUFDCOPEN | WM8400_POBCTRL |
1156                         WM8400_BUFIOEN);
1157
1158                 /* mute DAC */
1159                 val = wm8400_read(codec, WM8400_DAC_CTRL);
1160                 wm8400_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1161
1162                 /* Enable any disabled outputs */
1163                 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1);
1164                 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1165                         WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1166                         WM8400_ROUT_ENA;
1167                 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1168
1169                 /* Disable VMID */
1170                 val &= ~WM8400_VMID_MODE_MASK;
1171                 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1172
1173                 msleep(300);
1174
1175                 /* Enable all output discharge bits */
1176                 wm8400_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1177                         WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1178                         WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1179                         WM8400_DIS_ROUT);
1180
1181                 /* Disable VREF */
1182                 val &= ~WM8400_VREF_ENA;
1183                 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1184
1185                 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1186                 wm8400_write(codec, WM8400_ANTIPOP2, 0x0);
1187
1188                 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1189                                              &power[0]);
1190                 if (ret != 0)
1191                         return ret;
1192
1193                 break;
1194         }
1195
1196         codec->bias_level = level;
1197         return 0;
1198 }
1199
1200 #define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1201
1202 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1203         SNDRV_PCM_FMTBIT_S24_LE)
1204
1205 static struct snd_soc_dai_ops wm8400_dai_ops = {
1206         .hw_params = wm8400_hw_params,
1207         .digital_mute = wm8400_mute,
1208         .set_fmt = wm8400_set_dai_fmt,
1209         .set_clkdiv = wm8400_set_dai_clkdiv,
1210         .set_sysclk = wm8400_set_dai_sysclk,
1211 };
1212
1213 /*
1214  * The WM8400 supports 2 different and mutually exclusive DAI
1215  * configurations.
1216  *
1217  * 1. ADC/DAC on Primary Interface
1218  * 2. ADC on Primary Interface/DAC on secondary
1219  */
1220 struct snd_soc_dai wm8400_dai = {
1221 /* ADC/DAC on primary */
1222         .name = "WM8400 ADC/DAC Primary",
1223         .id = 1,
1224         .playback = {
1225                 .stream_name = "Playback",
1226                 .channels_min = 1,
1227                 .channels_max = 2,
1228                 .rates = WM8400_RATES,
1229                 .formats = WM8400_FORMATS,
1230         },
1231         .capture = {
1232                 .stream_name = "Capture",
1233                 .channels_min = 1,
1234                 .channels_max = 2,
1235                 .rates = WM8400_RATES,
1236                 .formats = WM8400_FORMATS,
1237         },
1238         .ops = &wm8400_dai_ops,
1239 };
1240 EXPORT_SYMBOL_GPL(wm8400_dai);
1241
1242 static int wm8400_suspend(struct platform_device *pdev, pm_message_t state)
1243 {
1244         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1245         struct snd_soc_codec *codec = socdev->card->codec;
1246
1247         wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF);
1248
1249         return 0;
1250 }
1251
1252 static int wm8400_resume(struct platform_device *pdev)
1253 {
1254         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1255         struct snd_soc_codec *codec = socdev->card->codec;
1256
1257         wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1258
1259         return 0;
1260 }
1261
1262 static struct snd_soc_codec *wm8400_codec;
1263
1264 static int wm8400_probe(struct platform_device *pdev)
1265 {
1266         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1267         struct snd_soc_codec *codec;
1268         int ret;
1269
1270         if (!wm8400_codec) {
1271                 dev_err(&pdev->dev, "wm8400 not yet discovered\n");
1272                 return -ENODEV;
1273         }
1274         codec = wm8400_codec;
1275
1276         socdev->card->codec = codec;
1277
1278         /* register pcms */
1279         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1280         if (ret < 0) {
1281                 dev_err(&pdev->dev, "failed to create pcms\n");
1282                 goto pcm_err;
1283         }
1284
1285         wm8400_add_controls(codec);
1286         wm8400_add_widgets(codec);
1287
1288         ret = snd_soc_init_card(socdev);
1289         if (ret < 0) {
1290                 dev_err(&pdev->dev, "failed to register card\n");
1291                 goto card_err;
1292         }
1293
1294         return ret;
1295
1296 card_err:
1297         snd_soc_free_pcms(socdev);
1298         snd_soc_dapm_free(socdev);
1299 pcm_err:
1300         return ret;
1301 }
1302
1303 /* power down chip */
1304 static int wm8400_remove(struct platform_device *pdev)
1305 {
1306         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1307
1308         snd_soc_free_pcms(socdev);
1309         snd_soc_dapm_free(socdev);
1310
1311         return 0;
1312 }
1313
1314 struct snd_soc_codec_device soc_codec_dev_wm8400 = {
1315         .probe =        wm8400_probe,
1316         .remove =       wm8400_remove,
1317         .suspend =      wm8400_suspend,
1318         .resume =       wm8400_resume,
1319 };
1320
1321 static void wm8400_probe_deferred(struct work_struct *work)
1322 {
1323         struct wm8400_priv *priv = container_of(work, struct wm8400_priv,
1324                                                 work);
1325         struct snd_soc_codec *codec = &priv->codec;
1326         int ret;
1327
1328         /* charge output caps */
1329         wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1330
1331         /* We're done, tell the subsystem. */
1332         ret = snd_soc_register_codec(codec);
1333         if (ret != 0) {
1334                 dev_err(priv->wm8400->dev,
1335                         "Failed to register codec: %d\n", ret);
1336                 goto err;
1337         }
1338
1339         ret = snd_soc_register_dai(&wm8400_dai);
1340         if (ret != 0) {
1341                 dev_err(priv->wm8400->dev,
1342                         "Failed to register DAI: %d\n", ret);
1343                 goto err_codec;
1344         }
1345
1346         return;
1347
1348 err_codec:
1349         snd_soc_unregister_codec(codec);
1350 err:
1351         wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF);
1352 }
1353
1354 static int wm8400_codec_probe(struct platform_device *dev)
1355 {
1356         struct wm8400_priv *priv;
1357         int ret;
1358         u16 reg;
1359         struct snd_soc_codec *codec;
1360
1361         priv = kzalloc(sizeof(struct wm8400_priv), GFP_KERNEL);
1362         if (priv == NULL)
1363                 return -ENOMEM;
1364
1365         codec = &priv->codec;
1366         codec->private_data = priv;
1367         codec->control_data = dev->dev.driver_data;
1368         priv->wm8400 = dev->dev.driver_data;
1369
1370         ret = regulator_bulk_get(priv->wm8400->dev,
1371                                  ARRAY_SIZE(power), &power[0]);
1372         if (ret != 0) {
1373                 dev_err(&dev->dev, "Failed to get regulators: %d\n", ret);
1374                 goto err;
1375         }
1376
1377         codec->dev = &dev->dev;
1378         wm8400_dai.dev = &dev->dev;
1379
1380         codec->name = "WM8400";
1381         codec->owner = THIS_MODULE;
1382         codec->read = wm8400_read;
1383         codec->write = wm8400_write;
1384         codec->bias_level = SND_SOC_BIAS_OFF;
1385         codec->set_bias_level = wm8400_set_bias_level;
1386         codec->dai = &wm8400_dai;
1387         codec->num_dai = 1;
1388         codec->reg_cache_size = WM8400_REGISTER_COUNT;
1389         mutex_init(&codec->mutex);
1390         INIT_LIST_HEAD(&codec->dapm_widgets);
1391         INIT_LIST_HEAD(&codec->dapm_paths);
1392         INIT_WORK(&priv->work, wm8400_probe_deferred);
1393
1394         wm8400_codec_reset(codec);
1395
1396         reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1);
1397         wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
1398
1399         /* Latch volume update bits */
1400         reg = wm8400_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1401         wm8400_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1402                      reg & WM8400_IPVU);
1403         reg = wm8400_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1404         wm8400_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1405                      reg & WM8400_IPVU);
1406
1407         wm8400_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1408         wm8400_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1409
1410         wm8400_codec = codec;
1411
1412         if (!schedule_work(&priv->work)) {
1413                 ret = -EINVAL;
1414                 goto err_regulator;
1415         }
1416
1417         return 0;
1418
1419 err_regulator:
1420         wm8400_codec = NULL;
1421         regulator_bulk_free(ARRAY_SIZE(power), power);
1422 err:
1423         kfree(priv);
1424         return ret;
1425 }
1426
1427 static int __exit wm8400_codec_remove(struct platform_device *dev)
1428 {
1429         struct wm8400_priv *priv = wm8400_codec->private_data;
1430         u16 reg;
1431
1432         snd_soc_unregister_dai(&wm8400_dai);
1433         snd_soc_unregister_codec(wm8400_codec);
1434
1435         reg = wm8400_read(wm8400_codec, WM8400_POWER_MANAGEMENT_1);
1436         wm8400_write(wm8400_codec, WM8400_POWER_MANAGEMENT_1,
1437                      reg & (~WM8400_CODEC_ENA));
1438
1439         regulator_bulk_free(ARRAY_SIZE(power), power);
1440         kfree(priv);
1441
1442         wm8400_codec = NULL;
1443
1444         return 0;
1445 }
1446
1447 static struct platform_driver wm8400_codec_driver = {
1448         .driver = {
1449                 .name = "wm8400-codec",
1450                 .owner = THIS_MODULE,
1451         },
1452         .probe = wm8400_codec_probe,
1453         .remove = __exit_p(wm8400_codec_remove),
1454 };
1455
1456 static int __init wm8400_codec_init(void)
1457 {
1458         return platform_driver_register(&wm8400_codec_driver);
1459 }
1460 module_init(wm8400_codec_init);
1461
1462 static void __exit wm8400_codec_exit(void)
1463 {
1464         platform_driver_unregister(&wm8400_codec_driver);
1465 }
1466 module_exit(wm8400_codec_exit);
1467
1468 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8400);
1469
1470 MODULE_DESCRIPTION("ASoC WM8400 driver");
1471 MODULE_AUTHOR("Mark Brown");
1472 MODULE_LICENSE("GPL");
1473 MODULE_ALIAS("platform:wm8400-codec");