Merge branch 'master'
[linux-2.6] / drivers / net / gianfar.c
1 /*
2  * drivers/net/gianfar.c
3  *
4  * Gianfar Ethernet Driver
5  * This driver is designed for the non-CPM ethernet controllers
6  * on the 85xx and 83xx family of integrated processors
7  * Based on 8260_io/fcc_enet.c
8  *
9  * Author: Andy Fleming
10  * Maintainer: Kumar Gala
11  *
12  * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
13  *
14  * This program is free software; you can redistribute  it and/or modify it
15  * under  the terms of  the GNU General  Public License as published by the
16  * Free Software Foundation;  either version 2 of the  License, or (at your
17  * option) any later version.
18  *
19  *  Gianfar:  AKA Lambda Draconis, "Dragon"
20  *  RA 11 31 24.2
21  *  Dec +69 19 52
22  *  V 3.84
23  *  B-V +1.62
24  *
25  *  Theory of operation
26  *
27  *  The driver is initialized through platform_device.  Structures which
28  *  define the configuration needed by the board are defined in a
29  *  board structure in arch/ppc/platforms (though I do not
30  *  discount the possibility that other architectures could one
31  *  day be supported.
32  *
33  *  The Gianfar Ethernet Controller uses a ring of buffer
34  *  descriptors.  The beginning is indicated by a register
35  *  pointing to the physical address of the start of the ring.
36  *  The end is determined by a "wrap" bit being set in the
37  *  last descriptor of the ring.
38  *
39  *  When a packet is received, the RXF bit in the
40  *  IEVENT register is set, triggering an interrupt when the
41  *  corresponding bit in the IMASK register is also set (if
42  *  interrupt coalescing is active, then the interrupt may not
43  *  happen immediately, but will wait until either a set number
44  *  of frames or amount of time have passed).  In NAPI, the
45  *  interrupt handler will signal there is work to be done, and
46  *  exit.  Without NAPI, the packet(s) will be handled
47  *  immediately.  Both methods will start at the last known empty
48  *  descriptor, and process every subsequent descriptor until there
49  *  are none left with data (NAPI will stop after a set number of
50  *  packets to give time to other tasks, but will eventually
51  *  process all the packets).  The data arrives inside a
52  *  pre-allocated skb, and so after the skb is passed up to the
53  *  stack, a new skb must be allocated, and the address field in
54  *  the buffer descriptor must be updated to indicate this new
55  *  skb.
56  *
57  *  When the kernel requests that a packet be transmitted, the
58  *  driver starts where it left off last time, and points the
59  *  descriptor at the buffer which was passed in.  The driver
60  *  then informs the DMA engine that there are packets ready to
61  *  be transmitted.  Once the controller is finished transmitting
62  *  the packet, an interrupt may be triggered (under the same
63  *  conditions as for reception, but depending on the TXF bit).
64  *  The driver then cleans up the buffer.
65  */
66
67 #include <linux/config.h>
68 #include <linux/kernel.h>
69 #include <linux/sched.h>
70 #include <linux/string.h>
71 #include <linux/errno.h>
72 #include <linux/unistd.h>
73 #include <linux/slab.h>
74 #include <linux/interrupt.h>
75 #include <linux/init.h>
76 #include <linux/delay.h>
77 #include <linux/netdevice.h>
78 #include <linux/etherdevice.h>
79 #include <linux/skbuff.h>
80 #include <linux/if_vlan.h>
81 #include <linux/spinlock.h>
82 #include <linux/mm.h>
83 #include <linux/platform_device.h>
84 #include <linux/ip.h>
85 #include <linux/tcp.h>
86 #include <linux/udp.h>
87
88 #include <asm/io.h>
89 #include <asm/irq.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
96
97 #include "gianfar.h"
98 #include "gianfar_mii.h"
99
100 #define TX_TIMEOUT      (1*HZ)
101 #define SKB_ALLOC_TIMEOUT 1000000
102 #undef BRIEF_GFAR_ERRORS
103 #undef VERBOSE_GFAR_ERRORS
104
105 #ifdef CONFIG_GFAR_NAPI
106 #define RECEIVE(x) netif_receive_skb(x)
107 #else
108 #define RECEIVE(x) netif_rx(x)
109 #endif
110
111 const char gfar_driver_name[] = "Gianfar Ethernet";
112 const char gfar_driver_version[] = "1.3";
113
114 static int gfar_enet_open(struct net_device *dev);
115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void gfar_timeout(struct net_device *dev);
117 static int gfar_close(struct net_device *dev);
118 struct sk_buff *gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp);
119 static struct net_device_stats *gfar_get_stats(struct net_device *dev);
120 static int gfar_set_mac_address(struct net_device *dev);
121 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
122 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs);
123 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs);
124 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs);
125 static void adjust_link(struct net_device *dev);
126 static void init_registers(struct net_device *dev);
127 static int init_phy(struct net_device *dev);
128 static int gfar_probe(struct platform_device *pdev);
129 static int gfar_remove(struct platform_device *pdev);
130 static void free_skb_resources(struct gfar_private *priv);
131 static void gfar_set_multi(struct net_device *dev);
132 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
133 #ifdef CONFIG_GFAR_NAPI
134 static int gfar_poll(struct net_device *dev, int *budget);
135 #endif
136 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
137 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
138 static void gfar_vlan_rx_register(struct net_device *netdev,
139                                 struct vlan_group *grp);
140 static void gfar_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
141 void gfar_halt(struct net_device *dev);
142 void gfar_start(struct net_device *dev);
143 static void gfar_clear_exact_match(struct net_device *dev);
144 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
145
146 extern struct ethtool_ops gfar_ethtool_ops;
147
148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
150 MODULE_LICENSE("GPL");
151
152 /* Returns 1 if incoming frames use an FCB */
153 static inline int gfar_uses_fcb(struct gfar_private *priv)
154 {
155         return (priv->vlan_enable || priv->rx_csum_enable);
156 }
157
158 /* Set up the ethernet device structure, private data,
159  * and anything else we need before we start */
160 static int gfar_probe(struct platform_device *pdev)
161 {
162         u32 tempval;
163         struct net_device *dev = NULL;
164         struct gfar_private *priv = NULL;
165         struct gianfar_platform_data *einfo;
166         struct resource *r;
167         int idx;
168         int err = 0;
169
170         einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
171
172         if (NULL == einfo) {
173                 printk(KERN_ERR "gfar %d: Missing additional data!\n",
174                        pdev->id);
175
176                 return -ENODEV;
177         }
178
179         /* Create an ethernet device instance */
180         dev = alloc_etherdev(sizeof (*priv));
181
182         if (NULL == dev)
183                 return -ENOMEM;
184
185         priv = netdev_priv(dev);
186
187         /* Set the info in the priv to the current info */
188         priv->einfo = einfo;
189
190         /* fill out IRQ fields */
191         if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
192                 priv->interruptTransmit = platform_get_irq_byname(pdev, "tx");
193                 priv->interruptReceive = platform_get_irq_byname(pdev, "rx");
194                 priv->interruptError = platform_get_irq_byname(pdev, "error");
195         } else {
196                 priv->interruptTransmit = platform_get_irq(pdev, 0);
197         }
198
199         /* get a pointer to the register memory */
200         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
201         priv->regs = (struct gfar *)
202                 ioremap(r->start, sizeof (struct gfar));
203
204         if (NULL == priv->regs) {
205                 err = -ENOMEM;
206                 goto regs_fail;
207         }
208
209         spin_lock_init(&priv->lock);
210
211         platform_set_drvdata(pdev, dev);
212
213         /* Stop the DMA engine now, in case it was running before */
214         /* (The firmware could have used it, and left it running). */
215         /* To do this, we write Graceful Receive Stop and Graceful */
216         /* Transmit Stop, and then wait until the corresponding bits */
217         /* in IEVENT indicate the stops have completed. */
218         tempval = gfar_read(&priv->regs->dmactrl);
219         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
220         gfar_write(&priv->regs->dmactrl, tempval);
221
222         tempval = gfar_read(&priv->regs->dmactrl);
223         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
224         gfar_write(&priv->regs->dmactrl, tempval);
225
226         while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
227                 cpu_relax();
228
229         /* Reset MAC layer */
230         gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
231
232         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
233         gfar_write(&priv->regs->maccfg1, tempval);
234
235         /* Initialize MACCFG2. */
236         gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
237
238         /* Initialize ECNTRL */
239         gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
240
241         /* Copy the station address into the dev structure, */
242         memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
243
244         /* Set the dev->base_addr to the gfar reg region */
245         dev->base_addr = (unsigned long) (priv->regs);
246
247         SET_MODULE_OWNER(dev);
248         SET_NETDEV_DEV(dev, &pdev->dev);
249
250         /* Fill in the dev structure */
251         dev->open = gfar_enet_open;
252         dev->hard_start_xmit = gfar_start_xmit;
253         dev->tx_timeout = gfar_timeout;
254         dev->watchdog_timeo = TX_TIMEOUT;
255 #ifdef CONFIG_GFAR_NAPI
256         dev->poll = gfar_poll;
257         dev->weight = GFAR_DEV_WEIGHT;
258 #endif
259         dev->stop = gfar_close;
260         dev->get_stats = gfar_get_stats;
261         dev->change_mtu = gfar_change_mtu;
262         dev->mtu = 1500;
263         dev->set_multicast_list = gfar_set_multi;
264
265         dev->ethtool_ops = &gfar_ethtool_ops;
266
267         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
268                 priv->rx_csum_enable = 1;
269                 dev->features |= NETIF_F_IP_CSUM;
270         } else
271                 priv->rx_csum_enable = 0;
272
273         priv->vlgrp = NULL;
274
275         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
276                 dev->vlan_rx_register = gfar_vlan_rx_register;
277                 dev->vlan_rx_kill_vid = gfar_vlan_rx_kill_vid;
278
279                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
280
281                 priv->vlan_enable = 1;
282         }
283
284         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
285                 priv->extended_hash = 1;
286                 priv->hash_width = 9;
287
288                 priv->hash_regs[0] = &priv->regs->igaddr0;
289                 priv->hash_regs[1] = &priv->regs->igaddr1;
290                 priv->hash_regs[2] = &priv->regs->igaddr2;
291                 priv->hash_regs[3] = &priv->regs->igaddr3;
292                 priv->hash_regs[4] = &priv->regs->igaddr4;
293                 priv->hash_regs[5] = &priv->regs->igaddr5;
294                 priv->hash_regs[6] = &priv->regs->igaddr6;
295                 priv->hash_regs[7] = &priv->regs->igaddr7;
296                 priv->hash_regs[8] = &priv->regs->gaddr0;
297                 priv->hash_regs[9] = &priv->regs->gaddr1;
298                 priv->hash_regs[10] = &priv->regs->gaddr2;
299                 priv->hash_regs[11] = &priv->regs->gaddr3;
300                 priv->hash_regs[12] = &priv->regs->gaddr4;
301                 priv->hash_regs[13] = &priv->regs->gaddr5;
302                 priv->hash_regs[14] = &priv->regs->gaddr6;
303                 priv->hash_regs[15] = &priv->regs->gaddr7;
304
305         } else {
306                 priv->extended_hash = 0;
307                 priv->hash_width = 8;
308
309                 priv->hash_regs[0] = &priv->regs->gaddr0;
310                 priv->hash_regs[1] = &priv->regs->gaddr1;
311                 priv->hash_regs[2] = &priv->regs->gaddr2;
312                 priv->hash_regs[3] = &priv->regs->gaddr3;
313                 priv->hash_regs[4] = &priv->regs->gaddr4;
314                 priv->hash_regs[5] = &priv->regs->gaddr5;
315                 priv->hash_regs[6] = &priv->regs->gaddr6;
316                 priv->hash_regs[7] = &priv->regs->gaddr7;
317         }
318
319         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
320                 priv->padding = DEFAULT_PADDING;
321         else
322                 priv->padding = 0;
323
324         if (dev->features & NETIF_F_IP_CSUM)
325                 dev->hard_header_len += GMAC_FCB_LEN;
326
327         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
328         priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
329         priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
330
331         priv->txcoalescing = DEFAULT_TX_COALESCE;
332         priv->txcount = DEFAULT_TXCOUNT;
333         priv->txtime = DEFAULT_TXTIME;
334         priv->rxcoalescing = DEFAULT_RX_COALESCE;
335         priv->rxcount = DEFAULT_RXCOUNT;
336         priv->rxtime = DEFAULT_RXTIME;
337
338         /* Enable most messages by default */
339         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
340
341         err = register_netdev(dev);
342
343         if (err) {
344                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
345                                 dev->name);
346                 goto register_fail;
347         }
348
349         /* Create all the sysfs files */
350         gfar_init_sysfs(dev);
351
352         /* Print out the device info */
353         printk(KERN_INFO DEVICE_NAME, dev->name);
354         for (idx = 0; idx < 6; idx++)
355                 printk("%2.2x%c", dev->dev_addr[idx], idx == 5 ? ' ' : ':');
356         printk("\n");
357
358         /* Even more device info helps when determining which kernel */
359         /* provided which set of benchmarks. */
360 #ifdef CONFIG_GFAR_NAPI
361         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
362 #else
363         printk(KERN_INFO "%s: Running with NAPI disabled\n", dev->name);
364 #endif
365         printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
366                dev->name, priv->rx_ring_size, priv->tx_ring_size);
367
368         return 0;
369
370 register_fail:
371         iounmap((void *) priv->regs);
372 regs_fail:
373         free_netdev(dev);
374         return err;
375 }
376
377 static int gfar_remove(struct platform_device *pdev)
378 {
379         struct net_device *dev = platform_get_drvdata(pdev);
380         struct gfar_private *priv = netdev_priv(dev);
381
382         platform_set_drvdata(pdev, NULL);
383
384         iounmap((void *) priv->regs);
385         free_netdev(dev);
386
387         return 0;
388 }
389
390
391 /* Initializes driver's PHY state, and attaches to the PHY.
392  * Returns 0 on success.
393  */
394 static int init_phy(struct net_device *dev)
395 {
396         struct gfar_private *priv = netdev_priv(dev);
397         uint gigabit_support =
398                 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
399                 SUPPORTED_1000baseT_Full : 0;
400         struct phy_device *phydev;
401
402         priv->oldlink = 0;
403         priv->oldspeed = 0;
404         priv->oldduplex = -1;
405
406         phydev = phy_connect(dev, priv->einfo->bus_id, &adjust_link, 0);
407
408         if (IS_ERR(phydev)) {
409                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
410                 return PTR_ERR(phydev);
411         }
412
413         /* Remove any features not supported by the controller */
414         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
415         phydev->advertising = phydev->supported;
416
417         priv->phydev = phydev;
418
419         return 0;
420 }
421
422 static void init_registers(struct net_device *dev)
423 {
424         struct gfar_private *priv = netdev_priv(dev);
425
426         /* Clear IEVENT */
427         gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
428
429         /* Initialize IMASK */
430         gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
431
432         /* Init hash registers to zero */
433         gfar_write(&priv->regs->igaddr0, 0);
434         gfar_write(&priv->regs->igaddr1, 0);
435         gfar_write(&priv->regs->igaddr2, 0);
436         gfar_write(&priv->regs->igaddr3, 0);
437         gfar_write(&priv->regs->igaddr4, 0);
438         gfar_write(&priv->regs->igaddr5, 0);
439         gfar_write(&priv->regs->igaddr6, 0);
440         gfar_write(&priv->regs->igaddr7, 0);
441
442         gfar_write(&priv->regs->gaddr0, 0);
443         gfar_write(&priv->regs->gaddr1, 0);
444         gfar_write(&priv->regs->gaddr2, 0);
445         gfar_write(&priv->regs->gaddr3, 0);
446         gfar_write(&priv->regs->gaddr4, 0);
447         gfar_write(&priv->regs->gaddr5, 0);
448         gfar_write(&priv->regs->gaddr6, 0);
449         gfar_write(&priv->regs->gaddr7, 0);
450
451         /* Zero out the rmon mib registers if it has them */
452         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
453                 memset((void *) &(priv->regs->rmon), 0,
454                        sizeof (struct rmon_mib));
455
456                 /* Mask off the CAM interrupts */
457                 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
458                 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
459         }
460
461         /* Initialize the max receive buffer length */
462         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
463
464         /* Initialize the Minimum Frame Length Register */
465         gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
466
467         /* Assign the TBI an address which won't conflict with the PHYs */
468         gfar_write(&priv->regs->tbipa, TBIPA_VALUE);
469 }
470
471
472 /* Halt the receive and transmit queues */
473 void gfar_halt(struct net_device *dev)
474 {
475         struct gfar_private *priv = netdev_priv(dev);
476         struct gfar *regs = priv->regs;
477         u32 tempval;
478
479         /* Mask all interrupts */
480         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
481
482         /* Clear all interrupts */
483         gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
484
485         /* Stop the DMA, and wait for it to stop */
486         tempval = gfar_read(&priv->regs->dmactrl);
487         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
488             != (DMACTRL_GRS | DMACTRL_GTS)) {
489                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
490                 gfar_write(&priv->regs->dmactrl, tempval);
491
492                 while (!(gfar_read(&priv->regs->ievent) &
493                          (IEVENT_GRSC | IEVENT_GTSC)))
494                         cpu_relax();
495         }
496
497         /* Disable Rx and Tx */
498         tempval = gfar_read(&regs->maccfg1);
499         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
500         gfar_write(&regs->maccfg1, tempval);
501 }
502
503 void stop_gfar(struct net_device *dev)
504 {
505         struct gfar_private *priv = netdev_priv(dev);
506         struct gfar *regs = priv->regs;
507         unsigned long flags;
508
509         phy_stop(priv->phydev);
510
511         /* Lock it down */
512         spin_lock_irqsave(&priv->lock, flags);
513
514         gfar_halt(dev);
515
516         spin_unlock_irqrestore(&priv->lock, flags);
517
518         /* Free the IRQs */
519         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
520                 free_irq(priv->interruptError, dev);
521                 free_irq(priv->interruptTransmit, dev);
522                 free_irq(priv->interruptReceive, dev);
523         } else {
524                 free_irq(priv->interruptTransmit, dev);
525         }
526
527         free_skb_resources(priv);
528
529         dma_free_coherent(NULL,
530                         sizeof(struct txbd8)*priv->tx_ring_size
531                         + sizeof(struct rxbd8)*priv->rx_ring_size,
532                         priv->tx_bd_base,
533                         gfar_read(&regs->tbase0));
534 }
535
536 /* If there are any tx skbs or rx skbs still around, free them.
537  * Then free tx_skbuff and rx_skbuff */
538 static void free_skb_resources(struct gfar_private *priv)
539 {
540         struct rxbd8 *rxbdp;
541         struct txbd8 *txbdp;
542         int i;
543
544         /* Go through all the buffer descriptors and free their data buffers */
545         txbdp = priv->tx_bd_base;
546
547         for (i = 0; i < priv->tx_ring_size; i++) {
548
549                 if (priv->tx_skbuff[i]) {
550                         dma_unmap_single(NULL, txbdp->bufPtr,
551                                         txbdp->length,
552                                         DMA_TO_DEVICE);
553                         dev_kfree_skb_any(priv->tx_skbuff[i]);
554                         priv->tx_skbuff[i] = NULL;
555                 }
556         }
557
558         kfree(priv->tx_skbuff);
559
560         rxbdp = priv->rx_bd_base;
561
562         /* rx_skbuff is not guaranteed to be allocated, so only
563          * free it and its contents if it is allocated */
564         if(priv->rx_skbuff != NULL) {
565                 for (i = 0; i < priv->rx_ring_size; i++) {
566                         if (priv->rx_skbuff[i]) {
567                                 dma_unmap_single(NULL, rxbdp->bufPtr,
568                                                 priv->rx_buffer_size,
569                                                 DMA_FROM_DEVICE);
570
571                                 dev_kfree_skb_any(priv->rx_skbuff[i]);
572                                 priv->rx_skbuff[i] = NULL;
573                         }
574
575                         rxbdp->status = 0;
576                         rxbdp->length = 0;
577                         rxbdp->bufPtr = 0;
578
579                         rxbdp++;
580                 }
581
582                 kfree(priv->rx_skbuff);
583         }
584 }
585
586 void gfar_start(struct net_device *dev)
587 {
588         struct gfar_private *priv = netdev_priv(dev);
589         struct gfar *regs = priv->regs;
590         u32 tempval;
591
592         /* Enable Rx and Tx in MACCFG1 */
593         tempval = gfar_read(&regs->maccfg1);
594         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
595         gfar_write(&regs->maccfg1, tempval);
596
597         /* Initialize DMACTRL to have WWR and WOP */
598         tempval = gfar_read(&priv->regs->dmactrl);
599         tempval |= DMACTRL_INIT_SETTINGS;
600         gfar_write(&priv->regs->dmactrl, tempval);
601
602         /* Clear THLT, so that the DMA starts polling now */
603         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT);
604
605         /* Make sure we aren't stopped */
606         tempval = gfar_read(&priv->regs->dmactrl);
607         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
608         gfar_write(&priv->regs->dmactrl, tempval);
609
610         /* Unmask the interrupts we look for */
611         gfar_write(&regs->imask, IMASK_DEFAULT);
612 }
613
614 /* Bring the controller up and running */
615 int startup_gfar(struct net_device *dev)
616 {
617         struct txbd8 *txbdp;
618         struct rxbd8 *rxbdp;
619         dma_addr_t addr;
620         unsigned long vaddr;
621         int i;
622         struct gfar_private *priv = netdev_priv(dev);
623         struct gfar *regs = priv->regs;
624         int err = 0;
625         u32 rctrl = 0;
626         u32 attrs = 0;
627
628         gfar_write(&regs->imask, IMASK_INIT_CLEAR);
629
630         /* Allocate memory for the buffer descriptors */
631         vaddr = (unsigned long) dma_alloc_coherent(NULL,
632                         sizeof (struct txbd8) * priv->tx_ring_size +
633                         sizeof (struct rxbd8) * priv->rx_ring_size,
634                         &addr, GFP_KERNEL);
635
636         if (vaddr == 0) {
637                 if (netif_msg_ifup(priv))
638                         printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
639                                         dev->name);
640                 return -ENOMEM;
641         }
642
643         priv->tx_bd_base = (struct txbd8 *) vaddr;
644
645         /* enet DMA only understands physical addresses */
646         gfar_write(&regs->tbase0, addr);
647
648         /* Start the rx descriptor ring where the tx ring leaves off */
649         addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
650         vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
651         priv->rx_bd_base = (struct rxbd8 *) vaddr;
652         gfar_write(&regs->rbase0, addr);
653
654         /* Setup the skbuff rings */
655         priv->tx_skbuff =
656             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
657                                         priv->tx_ring_size, GFP_KERNEL);
658
659         if (NULL == priv->tx_skbuff) {
660                 if (netif_msg_ifup(priv))
661                         printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
662                                         dev->name);
663                 err = -ENOMEM;
664                 goto tx_skb_fail;
665         }
666
667         for (i = 0; i < priv->tx_ring_size; i++)
668                 priv->tx_skbuff[i] = NULL;
669
670         priv->rx_skbuff =
671             (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
672                                         priv->rx_ring_size, GFP_KERNEL);
673
674         if (NULL == priv->rx_skbuff) {
675                 if (netif_msg_ifup(priv))
676                         printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
677                                         dev->name);
678                 err = -ENOMEM;
679                 goto rx_skb_fail;
680         }
681
682         for (i = 0; i < priv->rx_ring_size; i++)
683                 priv->rx_skbuff[i] = NULL;
684
685         /* Initialize some variables in our dev structure */
686         priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
687         priv->cur_rx = priv->rx_bd_base;
688         priv->skb_curtx = priv->skb_dirtytx = 0;
689         priv->skb_currx = 0;
690
691         /* Initialize Transmit Descriptor Ring */
692         txbdp = priv->tx_bd_base;
693         for (i = 0; i < priv->tx_ring_size; i++) {
694                 txbdp->status = 0;
695                 txbdp->length = 0;
696                 txbdp->bufPtr = 0;
697                 txbdp++;
698         }
699
700         /* Set the last descriptor in the ring to indicate wrap */
701         txbdp--;
702         txbdp->status |= TXBD_WRAP;
703
704         rxbdp = priv->rx_bd_base;
705         for (i = 0; i < priv->rx_ring_size; i++) {
706                 struct sk_buff *skb = NULL;
707
708                 rxbdp->status = 0;
709
710                 skb = gfar_new_skb(dev, rxbdp);
711
712                 priv->rx_skbuff[i] = skb;
713
714                 rxbdp++;
715         }
716
717         /* Set the last descriptor in the ring to wrap */
718         rxbdp--;
719         rxbdp->status |= RXBD_WRAP;
720
721         /* If the device has multiple interrupts, register for
722          * them.  Otherwise, only register for the one */
723         if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
724                 /* Install our interrupt handlers for Error,
725                  * Transmit, and Receive */
726                 if (request_irq(priv->interruptError, gfar_error,
727                                 0, "enet_error", dev) < 0) {
728                         if (netif_msg_intr(priv))
729                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
730                                         dev->name, priv->interruptError);
731
732                         err = -1;
733                         goto err_irq_fail;
734                 }
735
736                 if (request_irq(priv->interruptTransmit, gfar_transmit,
737                                 0, "enet_tx", dev) < 0) {
738                         if (netif_msg_intr(priv))
739                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
740                                         dev->name, priv->interruptTransmit);
741
742                         err = -1;
743
744                         goto tx_irq_fail;
745                 }
746
747                 if (request_irq(priv->interruptReceive, gfar_receive,
748                                 0, "enet_rx", dev) < 0) {
749                         if (netif_msg_intr(priv))
750                                 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
751                                                 dev->name, priv->interruptReceive);
752
753                         err = -1;
754                         goto rx_irq_fail;
755                 }
756         } else {
757                 if (request_irq(priv->interruptTransmit, gfar_interrupt,
758                                 0, "gfar_interrupt", dev) < 0) {
759                         if (netif_msg_intr(priv))
760                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
761                                         dev->name, priv->interruptError);
762
763                         err = -1;
764                         goto err_irq_fail;
765                 }
766         }
767
768         phy_start(priv->phydev);
769
770         /* Configure the coalescing support */
771         if (priv->txcoalescing)
772                 gfar_write(&regs->txic,
773                            mk_ic_value(priv->txcount, priv->txtime));
774         else
775                 gfar_write(&regs->txic, 0);
776
777         if (priv->rxcoalescing)
778                 gfar_write(&regs->rxic,
779                            mk_ic_value(priv->rxcount, priv->rxtime));
780         else
781                 gfar_write(&regs->rxic, 0);
782
783         if (priv->rx_csum_enable)
784                 rctrl |= RCTRL_CHECKSUMMING;
785
786         if (priv->extended_hash) {
787                 rctrl |= RCTRL_EXTHASH;
788
789                 gfar_clear_exact_match(dev);
790                 rctrl |= RCTRL_EMEN;
791         }
792
793         if (priv->vlan_enable)
794                 rctrl |= RCTRL_VLAN;
795
796         if (priv->padding) {
797                 rctrl &= ~RCTRL_PAL_MASK;
798                 rctrl |= RCTRL_PADDING(priv->padding);
799         }
800
801         /* Init rctrl based on our settings */
802         gfar_write(&priv->regs->rctrl, rctrl);
803
804         if (dev->features & NETIF_F_IP_CSUM)
805                 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
806
807         /* Set the extraction length and index */
808         attrs = ATTRELI_EL(priv->rx_stash_size) |
809                 ATTRELI_EI(priv->rx_stash_index);
810
811         gfar_write(&priv->regs->attreli, attrs);
812
813         /* Start with defaults, and add stashing or locking
814          * depending on the approprate variables */
815         attrs = ATTR_INIT_SETTINGS;
816
817         if (priv->bd_stash_en)
818                 attrs |= ATTR_BDSTASH;
819
820         if (priv->rx_stash_size != 0)
821                 attrs |= ATTR_BUFSTASH;
822
823         gfar_write(&priv->regs->attr, attrs);
824
825         gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
826         gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
827         gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
828
829         /* Start the controller */
830         gfar_start(dev);
831
832         return 0;
833
834 rx_irq_fail:
835         free_irq(priv->interruptTransmit, dev);
836 tx_irq_fail:
837         free_irq(priv->interruptError, dev);
838 err_irq_fail:
839 rx_skb_fail:
840         free_skb_resources(priv);
841 tx_skb_fail:
842         dma_free_coherent(NULL,
843                         sizeof(struct txbd8)*priv->tx_ring_size
844                         + sizeof(struct rxbd8)*priv->rx_ring_size,
845                         priv->tx_bd_base,
846                         gfar_read(&regs->tbase0));
847
848         return err;
849 }
850
851 /* Called when something needs to use the ethernet device */
852 /* Returns 0 for success. */
853 static int gfar_enet_open(struct net_device *dev)
854 {
855         int err;
856
857         /* Initialize a bunch of registers */
858         init_registers(dev);
859
860         gfar_set_mac_address(dev);
861
862         err = init_phy(dev);
863
864         if(err)
865                 return err;
866
867         err = startup_gfar(dev);
868
869         netif_start_queue(dev);
870
871         return err;
872 }
873
874 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
875 {
876         struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
877
878         memset(fcb, 0, GMAC_FCB_LEN);
879
880         return fcb;
881 }
882
883 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
884 {
885         u8 flags = 0;
886
887         /* If we're here, it's a IP packet with a TCP or UDP
888          * payload.  We set it to checksum, using a pseudo-header
889          * we provide
890          */
891         flags = TXFCB_DEFAULT;
892
893         /* Tell the controller what the protocol is */
894         /* And provide the already calculated phcs */
895         if (skb->nh.iph->protocol == IPPROTO_UDP) {
896                 flags |= TXFCB_UDP;
897                 fcb->phcs = skb->h.uh->check;
898         } else
899                 fcb->phcs = skb->h.th->check;
900
901         /* l3os is the distance between the start of the
902          * frame (skb->data) and the start of the IP hdr.
903          * l4os is the distance between the start of the
904          * l3 hdr and the l4 hdr */
905         fcb->l3os = (u16)(skb->nh.raw - skb->data - GMAC_FCB_LEN);
906         fcb->l4os = (u16)(skb->h.raw - skb->nh.raw);
907
908         fcb->flags = flags;
909 }
910
911 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
912 {
913         fcb->flags |= TXFCB_VLN;
914         fcb->vlctl = vlan_tx_tag_get(skb);
915 }
916
917 /* This is called by the kernel when a frame is ready for transmission. */
918 /* It is pointed to by the dev->hard_start_xmit function pointer */
919 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
920 {
921         struct gfar_private *priv = netdev_priv(dev);
922         struct txfcb *fcb = NULL;
923         struct txbd8 *txbdp;
924         u16 status;
925
926         /* Update transmit stats */
927         priv->stats.tx_bytes += skb->len;
928
929         /* Lock priv now */
930         spin_lock_irq(&priv->lock);
931
932         /* Point at the first free tx descriptor */
933         txbdp = priv->cur_tx;
934
935         /* Clear all but the WRAP status flags */
936         status = txbdp->status & TXBD_WRAP;
937
938         /* Set up checksumming */
939         if (likely((dev->features & NETIF_F_IP_CSUM)
940                         && (CHECKSUM_HW == skb->ip_summed))) {
941                 fcb = gfar_add_fcb(skb, txbdp);
942                 status |= TXBD_TOE;
943                 gfar_tx_checksum(skb, fcb);
944         }
945
946         if (priv->vlan_enable &&
947                         unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
948                 if (unlikely(NULL == fcb)) {
949                         fcb = gfar_add_fcb(skb, txbdp);
950                         status |= TXBD_TOE;
951                 }
952
953                 gfar_tx_vlan(skb, fcb);
954         }
955
956         /* Set buffer length and pointer */
957         txbdp->length = skb->len;
958         txbdp->bufPtr = dma_map_single(NULL, skb->data,
959                         skb->len, DMA_TO_DEVICE);
960
961         /* Save the skb pointer so we can free it later */
962         priv->tx_skbuff[priv->skb_curtx] = skb;
963
964         /* Update the current skb pointer (wrapping if this was the last) */
965         priv->skb_curtx =
966             (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
967
968         /* Flag the BD as interrupt-causing */
969         status |= TXBD_INTERRUPT;
970
971         /* Flag the BD as ready to go, last in frame, and  */
972         /* in need of CRC */
973         status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
974
975         dev->trans_start = jiffies;
976
977         txbdp->status = status;
978
979         /* If this was the last BD in the ring, the next one */
980         /* is at the beginning of the ring */
981         if (txbdp->status & TXBD_WRAP)
982                 txbdp = priv->tx_bd_base;
983         else
984                 txbdp++;
985
986         /* If the next BD still needs to be cleaned up, then the bds
987            are full.  We need to tell the kernel to stop sending us stuff. */
988         if (txbdp == priv->dirty_tx) {
989                 netif_stop_queue(dev);
990
991                 priv->stats.tx_fifo_errors++;
992         }
993
994         /* Update the current txbd to the next one */
995         priv->cur_tx = txbdp;
996
997         /* Tell the DMA to go go go */
998         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
999
1000         /* Unlock priv */
1001         spin_unlock_irq(&priv->lock);
1002
1003         return 0;
1004 }
1005
1006 /* Stops the kernel queue, and halts the controller */
1007 static int gfar_close(struct net_device *dev)
1008 {
1009         struct gfar_private *priv = netdev_priv(dev);
1010         stop_gfar(dev);
1011
1012         /* Disconnect from the PHY */
1013         phy_disconnect(priv->phydev);
1014         priv->phydev = NULL;
1015
1016         netif_stop_queue(dev);
1017
1018         return 0;
1019 }
1020
1021 /* returns a net_device_stats structure pointer */
1022 static struct net_device_stats * gfar_get_stats(struct net_device *dev)
1023 {
1024         struct gfar_private *priv = netdev_priv(dev);
1025
1026         return &(priv->stats);
1027 }
1028
1029 /* Changes the mac address if the controller is not running. */
1030 int gfar_set_mac_address(struct net_device *dev)
1031 {
1032         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1033
1034         return 0;
1035 }
1036
1037
1038 /* Enables and disables VLAN insertion/extraction */
1039 static void gfar_vlan_rx_register(struct net_device *dev,
1040                 struct vlan_group *grp)
1041 {
1042         struct gfar_private *priv = netdev_priv(dev);
1043         unsigned long flags;
1044         u32 tempval;
1045
1046         spin_lock_irqsave(&priv->lock, flags);
1047
1048         priv->vlgrp = grp;
1049
1050         if (grp) {
1051                 /* Enable VLAN tag insertion */
1052                 tempval = gfar_read(&priv->regs->tctrl);
1053                 tempval |= TCTRL_VLINS;
1054
1055                 gfar_write(&priv->regs->tctrl, tempval);
1056                 
1057                 /* Enable VLAN tag extraction */
1058                 tempval = gfar_read(&priv->regs->rctrl);
1059                 tempval |= RCTRL_VLEX;
1060                 gfar_write(&priv->regs->rctrl, tempval);
1061         } else {
1062                 /* Disable VLAN tag insertion */
1063                 tempval = gfar_read(&priv->regs->tctrl);
1064                 tempval &= ~TCTRL_VLINS;
1065                 gfar_write(&priv->regs->tctrl, tempval);
1066
1067                 /* Disable VLAN tag extraction */
1068                 tempval = gfar_read(&priv->regs->rctrl);
1069                 tempval &= ~RCTRL_VLEX;
1070                 gfar_write(&priv->regs->rctrl, tempval);
1071         }
1072
1073         spin_unlock_irqrestore(&priv->lock, flags);
1074 }
1075
1076
1077 static void gfar_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
1078 {
1079         struct gfar_private *priv = netdev_priv(dev);
1080         unsigned long flags;
1081
1082         spin_lock_irqsave(&priv->lock, flags);
1083
1084         if (priv->vlgrp)
1085                 priv->vlgrp->vlan_devices[vid] = NULL;
1086
1087         spin_unlock_irqrestore(&priv->lock, flags);
1088 }
1089
1090
1091 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1092 {
1093         int tempsize, tempval;
1094         struct gfar_private *priv = netdev_priv(dev);
1095         int oldsize = priv->rx_buffer_size;
1096         int frame_size = new_mtu + ETH_HLEN;
1097
1098         if (priv->vlan_enable)
1099                 frame_size += VLAN_ETH_HLEN;
1100
1101         if (gfar_uses_fcb(priv))
1102                 frame_size += GMAC_FCB_LEN;
1103
1104         frame_size += priv->padding;
1105
1106         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1107                 if (netif_msg_drv(priv))
1108                         printk(KERN_ERR "%s: Invalid MTU setting\n",
1109                                         dev->name);
1110                 return -EINVAL;
1111         }
1112
1113         tempsize =
1114             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1115             INCREMENTAL_BUFFER_SIZE;
1116
1117         /* Only stop and start the controller if it isn't already
1118          * stopped, and we changed something */
1119         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1120                 stop_gfar(dev);
1121
1122         priv->rx_buffer_size = tempsize;
1123
1124         dev->mtu = new_mtu;
1125
1126         gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1127         gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1128
1129         /* If the mtu is larger than the max size for standard
1130          * ethernet frames (ie, a jumbo frame), then set maccfg2
1131          * to allow huge frames, and to check the length */
1132         tempval = gfar_read(&priv->regs->maccfg2);
1133
1134         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1135                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1136         else
1137                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1138
1139         gfar_write(&priv->regs->maccfg2, tempval);
1140
1141         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1142                 startup_gfar(dev);
1143
1144         return 0;
1145 }
1146
1147 /* gfar_timeout gets called when a packet has not been
1148  * transmitted after a set amount of time.
1149  * For now, assume that clearing out all the structures, and
1150  * starting over will fix the problem. */
1151 static void gfar_timeout(struct net_device *dev)
1152 {
1153         struct gfar_private *priv = netdev_priv(dev);
1154
1155         priv->stats.tx_errors++;
1156
1157         if (dev->flags & IFF_UP) {
1158                 stop_gfar(dev);
1159                 startup_gfar(dev);
1160         }
1161
1162         netif_schedule(dev);
1163 }
1164
1165 /* Interrupt Handler for Transmit complete */
1166 static irqreturn_t gfar_transmit(int irq, void *dev_id, struct pt_regs *regs)
1167 {
1168         struct net_device *dev = (struct net_device *) dev_id;
1169         struct gfar_private *priv = netdev_priv(dev);
1170         struct txbd8 *bdp;
1171
1172         /* Clear IEVENT */
1173         gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1174
1175         /* Lock priv */
1176         spin_lock(&priv->lock);
1177         bdp = priv->dirty_tx;
1178         while ((bdp->status & TXBD_READY) == 0) {
1179                 /* If dirty_tx and cur_tx are the same, then either the */
1180                 /* ring is empty or full now (it could only be full in the beginning, */
1181                 /* obviously).  If it is empty, we are done. */
1182                 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1183                         break;
1184
1185                 priv->stats.tx_packets++;
1186
1187                 /* Deferred means some collisions occurred during transmit, */
1188                 /* but we eventually sent the packet. */
1189                 if (bdp->status & TXBD_DEF)
1190                         priv->stats.collisions++;
1191
1192                 /* Free the sk buffer associated with this TxBD */
1193                 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1194                 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1195                 priv->skb_dirtytx =
1196                     (priv->skb_dirtytx +
1197                      1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1198
1199                 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1200                 if (bdp->status & TXBD_WRAP)
1201                         bdp = priv->tx_bd_base;
1202                 else
1203                         bdp++;
1204
1205                 /* Move dirty_tx to be the next bd */
1206                 priv->dirty_tx = bdp;
1207
1208                 /* We freed a buffer, so now we can restart transmission */
1209                 if (netif_queue_stopped(dev))
1210                         netif_wake_queue(dev);
1211         } /* while ((bdp->status & TXBD_READY) == 0) */
1212
1213         /* If we are coalescing the interrupts, reset the timer */
1214         /* Otherwise, clear it */
1215         if (priv->txcoalescing)
1216                 gfar_write(&priv->regs->txic,
1217                            mk_ic_value(priv->txcount, priv->txtime));
1218         else
1219                 gfar_write(&priv->regs->txic, 0);
1220
1221         spin_unlock(&priv->lock);
1222
1223         return IRQ_HANDLED;
1224 }
1225
1226 struct sk_buff * gfar_new_skb(struct net_device *dev, struct rxbd8 *bdp)
1227 {
1228         unsigned int alignamount;
1229         struct gfar_private *priv = netdev_priv(dev);
1230         struct sk_buff *skb = NULL;
1231         unsigned int timeout = SKB_ALLOC_TIMEOUT;
1232
1233         /* We have to allocate the skb, so keep trying till we succeed */
1234         while ((!skb) && timeout--)
1235                 skb = dev_alloc_skb(priv->rx_buffer_size + RXBUF_ALIGNMENT);
1236
1237         if (NULL == skb)
1238                 return NULL;
1239
1240         alignamount = RXBUF_ALIGNMENT -
1241                 (((unsigned) skb->data) & (RXBUF_ALIGNMENT - 1));
1242
1243         /* We need the data buffer to be aligned properly.  We will reserve
1244          * as many bytes as needed to align the data properly
1245          */
1246         skb_reserve(skb, alignamount);
1247
1248         skb->dev = dev;
1249
1250         bdp->bufPtr = dma_map_single(NULL, skb->data,
1251                         priv->rx_buffer_size, DMA_FROM_DEVICE);
1252
1253         bdp->length = 0;
1254
1255         /* Mark the buffer empty */
1256         bdp->status |= (RXBD_EMPTY | RXBD_INTERRUPT);
1257
1258         return skb;
1259 }
1260
1261 static inline void count_errors(unsigned short status, struct gfar_private *priv)
1262 {
1263         struct net_device_stats *stats = &priv->stats;
1264         struct gfar_extra_stats *estats = &priv->extra_stats;
1265
1266         /* If the packet was truncated, none of the other errors
1267          * matter */
1268         if (status & RXBD_TRUNCATED) {
1269                 stats->rx_length_errors++;
1270
1271                 estats->rx_trunc++;
1272
1273                 return;
1274         }
1275         /* Count the errors, if there were any */
1276         if (status & (RXBD_LARGE | RXBD_SHORT)) {
1277                 stats->rx_length_errors++;
1278
1279                 if (status & RXBD_LARGE)
1280                         estats->rx_large++;
1281                 else
1282                         estats->rx_short++;
1283         }
1284         if (status & RXBD_NONOCTET) {
1285                 stats->rx_frame_errors++;
1286                 estats->rx_nonoctet++;
1287         }
1288         if (status & RXBD_CRCERR) {
1289                 estats->rx_crcerr++;
1290                 stats->rx_crc_errors++;
1291         }
1292         if (status & RXBD_OVERRUN) {
1293                 estats->rx_overrun++;
1294                 stats->rx_crc_errors++;
1295         }
1296 }
1297
1298 irqreturn_t gfar_receive(int irq, void *dev_id, struct pt_regs *regs)
1299 {
1300         struct net_device *dev = (struct net_device *) dev_id;
1301         struct gfar_private *priv = netdev_priv(dev);
1302
1303 #ifdef CONFIG_GFAR_NAPI
1304         u32 tempval;
1305 #endif
1306
1307         /* Clear IEVENT, so rx interrupt isn't called again
1308          * because of this interrupt */
1309         gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1310
1311         /* support NAPI */
1312 #ifdef CONFIG_GFAR_NAPI
1313         if (netif_rx_schedule_prep(dev)) {
1314                 tempval = gfar_read(&priv->regs->imask);
1315                 tempval &= IMASK_RX_DISABLED;
1316                 gfar_write(&priv->regs->imask, tempval);
1317
1318                 __netif_rx_schedule(dev);
1319         } else {
1320                 if (netif_msg_rx_err(priv))
1321                         printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1322                                 dev->name, gfar_read(&priv->regs->ievent),
1323                                 gfar_read(&priv->regs->imask));
1324         }
1325 #else
1326
1327         spin_lock(&priv->lock);
1328         gfar_clean_rx_ring(dev, priv->rx_ring_size);
1329
1330         /* If we are coalescing interrupts, update the timer */
1331         /* Otherwise, clear it */
1332         if (priv->rxcoalescing)
1333                 gfar_write(&priv->regs->rxic,
1334                            mk_ic_value(priv->rxcount, priv->rxtime));
1335         else
1336                 gfar_write(&priv->regs->rxic, 0);
1337
1338         spin_unlock(&priv->lock);
1339 #endif
1340
1341         return IRQ_HANDLED;
1342 }
1343
1344 static inline int gfar_rx_vlan(struct sk_buff *skb,
1345                 struct vlan_group *vlgrp, unsigned short vlctl)
1346 {
1347 #ifdef CONFIG_GFAR_NAPI
1348         return vlan_hwaccel_receive_skb(skb, vlgrp, vlctl);
1349 #else
1350         return vlan_hwaccel_rx(skb, vlgrp, vlctl);
1351 #endif
1352 }
1353
1354 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1355 {
1356         /* If valid headers were found, and valid sums
1357          * were verified, then we tell the kernel that no
1358          * checksumming is necessary.  Otherwise, it is */
1359         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1360                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1361         else
1362                 skb->ip_summed = CHECKSUM_NONE;
1363 }
1364
1365
1366 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1367 {
1368         struct rxfcb *fcb = (struct rxfcb *)skb->data;
1369
1370         /* Remove the FCB from the skb */
1371         skb_pull(skb, GMAC_FCB_LEN);
1372
1373         return fcb;
1374 }
1375
1376 /* gfar_process_frame() -- handle one incoming packet if skb
1377  * isn't NULL.  */
1378 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1379                 int length)
1380 {
1381         struct gfar_private *priv = netdev_priv(dev);
1382         struct rxfcb *fcb = NULL;
1383
1384         if (NULL == skb) {
1385                 if (netif_msg_rx_err(priv))
1386                         printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1387                 priv->stats.rx_dropped++;
1388                 priv->extra_stats.rx_skbmissing++;
1389         } else {
1390                 int ret;
1391
1392                 /* Prep the skb for the packet */
1393                 skb_put(skb, length);
1394
1395                 /* Grab the FCB if there is one */
1396                 if (gfar_uses_fcb(priv))
1397                         fcb = gfar_get_fcb(skb);
1398
1399                 /* Remove the padded bytes, if there are any */
1400                 if (priv->padding)
1401                         skb_pull(skb, priv->padding);
1402
1403                 if (priv->rx_csum_enable)
1404                         gfar_rx_checksum(skb, fcb);
1405
1406                 /* Tell the skb what kind of packet this is */
1407                 skb->protocol = eth_type_trans(skb, dev);
1408
1409                 /* Send the packet up the stack */
1410                 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
1411                         ret = gfar_rx_vlan(skb, priv->vlgrp, fcb->vlctl);
1412                 else
1413                         ret = RECEIVE(skb);
1414
1415                 if (NET_RX_DROP == ret)
1416                         priv->extra_stats.kernel_dropped++;
1417         }
1418
1419         return 0;
1420 }
1421
1422 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1423  *   until the budget/quota has been reached. Returns the number
1424  *   of frames handled
1425  */
1426 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1427 {
1428         struct rxbd8 *bdp;
1429         struct sk_buff *skb;
1430         u16 pkt_len;
1431         int howmany = 0;
1432         struct gfar_private *priv = netdev_priv(dev);
1433
1434         /* Get the first full descriptor */
1435         bdp = priv->cur_rx;
1436
1437         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1438                 skb = priv->rx_skbuff[priv->skb_currx];
1439
1440                 if (!(bdp->status &
1441                       (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET
1442                        | RXBD_CRCERR | RXBD_OVERRUN | RXBD_TRUNCATED))) {
1443                         /* Increment the number of packets */
1444                         priv->stats.rx_packets++;
1445                         howmany++;
1446
1447                         /* Remove the FCS from the packet length */
1448                         pkt_len = bdp->length - 4;
1449
1450                         gfar_process_frame(dev, skb, pkt_len);
1451
1452                         priv->stats.rx_bytes += pkt_len;
1453                 } else {
1454                         count_errors(bdp->status, priv);
1455
1456                         if (skb)
1457                                 dev_kfree_skb_any(skb);
1458
1459                         priv->rx_skbuff[priv->skb_currx] = NULL;
1460                 }
1461
1462                 dev->last_rx = jiffies;
1463
1464                 /* Clear the status flags for this buffer */
1465                 bdp->status &= ~RXBD_STATS;
1466
1467                 /* Add another skb for the future */
1468                 skb = gfar_new_skb(dev, bdp);
1469                 priv->rx_skbuff[priv->skb_currx] = skb;
1470
1471                 /* Update to the next pointer */
1472                 if (bdp->status & RXBD_WRAP)
1473                         bdp = priv->rx_bd_base;
1474                 else
1475                         bdp++;
1476
1477                 /* update to point at the next skb */
1478                 priv->skb_currx =
1479                     (priv->skb_currx +
1480                      1) & RX_RING_MOD_MASK(priv->rx_ring_size);
1481
1482         }
1483
1484         /* Update the current rxbd pointer to be the next one */
1485         priv->cur_rx = bdp;
1486
1487         /* If no packets have arrived since the
1488          * last one we processed, clear the IEVENT RX and
1489          * BSY bits so that another interrupt won't be
1490          * generated when we set IMASK */
1491         if (bdp->status & RXBD_EMPTY)
1492                 gfar_write(&priv->regs->ievent, IEVENT_RX_MASK);
1493
1494         return howmany;
1495 }
1496
1497 #ifdef CONFIG_GFAR_NAPI
1498 static int gfar_poll(struct net_device *dev, int *budget)
1499 {
1500         int howmany;
1501         struct gfar_private *priv = netdev_priv(dev);
1502         int rx_work_limit = *budget;
1503
1504         if (rx_work_limit > dev->quota)
1505                 rx_work_limit = dev->quota;
1506
1507         howmany = gfar_clean_rx_ring(dev, rx_work_limit);
1508
1509         dev->quota -= howmany;
1510         rx_work_limit -= howmany;
1511         *budget -= howmany;
1512
1513         if (rx_work_limit >= 0) {
1514                 netif_rx_complete(dev);
1515
1516                 /* Clear the halt bit in RSTAT */
1517                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1518
1519                 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1520
1521                 /* If we are coalescing interrupts, update the timer */
1522                 /* Otherwise, clear it */
1523                 if (priv->rxcoalescing)
1524                         gfar_write(&priv->regs->rxic,
1525                                    mk_ic_value(priv->rxcount, priv->rxtime));
1526                 else
1527                         gfar_write(&priv->regs->rxic, 0);
1528         }
1529
1530         return (rx_work_limit < 0) ? 1 : 0;
1531 }
1532 #endif
1533
1534 /* The interrupt handler for devices with one interrupt */
1535 static irqreturn_t gfar_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1536 {
1537         struct net_device *dev = dev_id;
1538         struct gfar_private *priv = netdev_priv(dev);
1539
1540         /* Save ievent for future reference */
1541         u32 events = gfar_read(&priv->regs->ievent);
1542
1543         /* Clear IEVENT */
1544         gfar_write(&priv->regs->ievent, events);
1545
1546         /* Check for reception */
1547         if ((events & IEVENT_RXF0) || (events & IEVENT_RXB0))
1548                 gfar_receive(irq, dev_id, regs);
1549
1550         /* Check for transmit completion */
1551         if ((events & IEVENT_TXF) || (events & IEVENT_TXB))
1552                 gfar_transmit(irq, dev_id, regs);
1553
1554         /* Update error statistics */
1555         if (events & IEVENT_TXE) {
1556                 priv->stats.tx_errors++;
1557
1558                 if (events & IEVENT_LC)
1559                         priv->stats.tx_window_errors++;
1560                 if (events & IEVENT_CRL)
1561                         priv->stats.tx_aborted_errors++;
1562                 if (events & IEVENT_XFUN) {
1563                         if (netif_msg_tx_err(priv))
1564                                 printk(KERN_WARNING "%s: tx underrun. dropped packet\n", dev->name);
1565                         priv->stats.tx_dropped++;
1566                         priv->extra_stats.tx_underrun++;
1567
1568                         /* Reactivate the Tx Queues */
1569                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1570                 }
1571         }
1572         if (events & IEVENT_BSY) {
1573                 priv->stats.rx_errors++;
1574                 priv->extra_stats.rx_bsy++;
1575
1576                 gfar_receive(irq, dev_id, regs);
1577
1578 #ifndef CONFIG_GFAR_NAPI
1579                 /* Clear the halt bit in RSTAT */
1580                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1581 #endif
1582
1583                 if (netif_msg_rx_err(priv))
1584                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1585                                         dev->name,
1586                                         gfar_read(&priv->regs->rstat));
1587         }
1588         if (events & IEVENT_BABR) {
1589                 priv->stats.rx_errors++;
1590                 priv->extra_stats.rx_babr++;
1591
1592                 if (netif_msg_rx_err(priv))
1593                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1594         }
1595         if (events & IEVENT_EBERR) {
1596                 priv->extra_stats.eberr++;
1597                 if (netif_msg_rx_err(priv))
1598                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1599         }
1600         if ((events & IEVENT_RXC) && (netif_msg_rx_err(priv)))
1601                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1602
1603         if (events & IEVENT_BABT) {
1604                 priv->extra_stats.tx_babt++;
1605                 if (netif_msg_rx_err(priv))
1606                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
1607         }
1608
1609         return IRQ_HANDLED;
1610 }
1611
1612 /* Called every time the controller might need to be made
1613  * aware of new link state.  The PHY code conveys this
1614  * information through variables in the phydev structure, and this
1615  * function converts those variables into the appropriate
1616  * register values, and can bring down the device if needed.
1617  */
1618 static void adjust_link(struct net_device *dev)
1619 {
1620         struct gfar_private *priv = netdev_priv(dev);
1621         struct gfar *regs = priv->regs;
1622         unsigned long flags;
1623         struct phy_device *phydev = priv->phydev;
1624         int new_state = 0;
1625
1626         spin_lock_irqsave(&priv->lock, flags);
1627         if (phydev->link) {
1628                 u32 tempval = gfar_read(&regs->maccfg2);
1629                 u32 ecntrl = gfar_read(&regs->ecntrl);
1630
1631                 /* Now we make sure that we can be in full duplex mode.
1632                  * If not, we operate in half-duplex mode. */
1633                 if (phydev->duplex != priv->oldduplex) {
1634                         new_state = 1;
1635                         if (!(phydev->duplex))
1636                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
1637                         else
1638                                 tempval |= MACCFG2_FULL_DUPLEX;
1639
1640                         priv->oldduplex = phydev->duplex;
1641                 }
1642
1643                 if (phydev->speed != priv->oldspeed) {
1644                         new_state = 1;
1645                         switch (phydev->speed) {
1646                         case 1000:
1647                                 tempval =
1648                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1649                                 break;
1650                         case 100:
1651                         case 10:
1652                                 tempval =
1653                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1654
1655                                 /* Reduced mode distinguishes
1656                                  * between 10 and 100 */
1657                                 if (phydev->speed == SPEED_100)
1658                                         ecntrl |= ECNTRL_R100;
1659                                 else
1660                                         ecntrl &= ~(ECNTRL_R100);
1661                                 break;
1662                         default:
1663                                 if (netif_msg_link(priv))
1664                                         printk(KERN_WARNING
1665                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
1666                                                 dev->name, phydev->speed);
1667                                 break;
1668                         }
1669
1670                         priv->oldspeed = phydev->speed;
1671                 }
1672
1673                 gfar_write(&regs->maccfg2, tempval);
1674                 gfar_write(&regs->ecntrl, ecntrl);
1675
1676                 if (!priv->oldlink) {
1677                         new_state = 1;
1678                         priv->oldlink = 1;
1679                         netif_schedule(dev);
1680                 }
1681         } else if (priv->oldlink) {
1682                 new_state = 1;
1683                 priv->oldlink = 0;
1684                 priv->oldspeed = 0;
1685                 priv->oldduplex = -1;
1686         }
1687
1688         if (new_state && netif_msg_link(priv))
1689                 phy_print_status(phydev);
1690
1691         spin_unlock_irqrestore(&priv->lock, flags);
1692 }
1693
1694 /* Update the hash table based on the current list of multicast
1695  * addresses we subscribe to.  Also, change the promiscuity of
1696  * the device based on the flags (this function is called
1697  * whenever dev->flags is changed */
1698 static void gfar_set_multi(struct net_device *dev)
1699 {
1700         struct dev_mc_list *mc_ptr;
1701         struct gfar_private *priv = netdev_priv(dev);
1702         struct gfar *regs = priv->regs;
1703         u32 tempval;
1704
1705         if(dev->flags & IFF_PROMISC) {
1706                 if (netif_msg_drv(priv))
1707                         printk(KERN_INFO "%s: Entering promiscuous mode.\n",
1708                                         dev->name);
1709                 /* Set RCTRL to PROM */
1710                 tempval = gfar_read(&regs->rctrl);
1711                 tempval |= RCTRL_PROM;
1712                 gfar_write(&regs->rctrl, tempval);
1713         } else {
1714                 /* Set RCTRL to not PROM */
1715                 tempval = gfar_read(&regs->rctrl);
1716                 tempval &= ~(RCTRL_PROM);
1717                 gfar_write(&regs->rctrl, tempval);
1718         }
1719         
1720         if(dev->flags & IFF_ALLMULTI) {
1721                 /* Set the hash to rx all multicast frames */
1722                 gfar_write(&regs->igaddr0, 0xffffffff);
1723                 gfar_write(&regs->igaddr1, 0xffffffff);
1724                 gfar_write(&regs->igaddr2, 0xffffffff);
1725                 gfar_write(&regs->igaddr3, 0xffffffff);
1726                 gfar_write(&regs->igaddr4, 0xffffffff);
1727                 gfar_write(&regs->igaddr5, 0xffffffff);
1728                 gfar_write(&regs->igaddr6, 0xffffffff);
1729                 gfar_write(&regs->igaddr7, 0xffffffff);
1730                 gfar_write(&regs->gaddr0, 0xffffffff);
1731                 gfar_write(&regs->gaddr1, 0xffffffff);
1732                 gfar_write(&regs->gaddr2, 0xffffffff);
1733                 gfar_write(&regs->gaddr3, 0xffffffff);
1734                 gfar_write(&regs->gaddr4, 0xffffffff);
1735                 gfar_write(&regs->gaddr5, 0xffffffff);
1736                 gfar_write(&regs->gaddr6, 0xffffffff);
1737                 gfar_write(&regs->gaddr7, 0xffffffff);
1738         } else {
1739                 int em_num;
1740                 int idx;
1741
1742                 /* zero out the hash */
1743                 gfar_write(&regs->igaddr0, 0x0);
1744                 gfar_write(&regs->igaddr1, 0x0);
1745                 gfar_write(&regs->igaddr2, 0x0);
1746                 gfar_write(&regs->igaddr3, 0x0);
1747                 gfar_write(&regs->igaddr4, 0x0);
1748                 gfar_write(&regs->igaddr5, 0x0);
1749                 gfar_write(&regs->igaddr6, 0x0);
1750                 gfar_write(&regs->igaddr7, 0x0);
1751                 gfar_write(&regs->gaddr0, 0x0);
1752                 gfar_write(&regs->gaddr1, 0x0);
1753                 gfar_write(&regs->gaddr2, 0x0);
1754                 gfar_write(&regs->gaddr3, 0x0);
1755                 gfar_write(&regs->gaddr4, 0x0);
1756                 gfar_write(&regs->gaddr5, 0x0);
1757                 gfar_write(&regs->gaddr6, 0x0);
1758                 gfar_write(&regs->gaddr7, 0x0);
1759
1760                 /* If we have extended hash tables, we need to
1761                  * clear the exact match registers to prepare for
1762                  * setting them */
1763                 if (priv->extended_hash) {
1764                         em_num = GFAR_EM_NUM + 1;
1765                         gfar_clear_exact_match(dev);
1766                         idx = 1;
1767                 } else {
1768                         idx = 0;
1769                         em_num = 0;
1770                 }
1771
1772                 if(dev->mc_count == 0)
1773                         return;
1774
1775                 /* Parse the list, and set the appropriate bits */
1776                 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1777                         if (idx < em_num) {
1778                                 gfar_set_mac_for_addr(dev, idx,
1779                                                 mc_ptr->dmi_addr);
1780                                 idx++;
1781                         } else
1782                                 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1783                 }
1784         }
1785
1786         return;
1787 }
1788
1789
1790 /* Clears each of the exact match registers to zero, so they
1791  * don't interfere with normal reception */
1792 static void gfar_clear_exact_match(struct net_device *dev)
1793 {
1794         int idx;
1795         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1796
1797         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1798                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1799 }
1800
1801 /* Set the appropriate hash bit for the given addr */
1802 /* The algorithm works like so:
1803  * 1) Take the Destination Address (ie the multicast address), and
1804  * do a CRC on it (little endian), and reverse the bits of the
1805  * result.
1806  * 2) Use the 8 most significant bits as a hash into a 256-entry
1807  * table.  The table is controlled through 8 32-bit registers:
1808  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
1809  * gaddr7.  This means that the 3 most significant bits in the
1810  * hash index which gaddr register to use, and the 5 other bits
1811  * indicate which bit (assuming an IBM numbering scheme, which
1812  * for PowerPC (tm) is usually the case) in the register holds
1813  * the entry. */
1814 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1815 {
1816         u32 tempval;
1817         struct gfar_private *priv = netdev_priv(dev);
1818         u32 result = ether_crc(MAC_ADDR_LEN, addr);
1819         int width = priv->hash_width;
1820         u8 whichbit = (result >> (32 - width)) & 0x1f;
1821         u8 whichreg = result >> (32 - width + 5);
1822         u32 value = (1 << (31-whichbit));
1823
1824         tempval = gfar_read(priv->hash_regs[whichreg]);
1825         tempval |= value;
1826         gfar_write(priv->hash_regs[whichreg], tempval);
1827
1828         return;
1829 }
1830
1831
1832 /* There are multiple MAC Address register pairs on some controllers
1833  * This function sets the numth pair to a given address
1834  */
1835 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
1836 {
1837         struct gfar_private *priv = netdev_priv(dev);
1838         int idx;
1839         char tmpbuf[MAC_ADDR_LEN];
1840         u32 tempval;
1841         u32 *macptr = &priv->regs->macstnaddr1;
1842
1843         macptr += num*2;
1844
1845         /* Now copy it into the mac registers backwards, cuz */
1846         /* little endian is silly */
1847         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
1848                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
1849
1850         gfar_write(macptr, *((u32 *) (tmpbuf)));
1851
1852         tempval = *((u32 *) (tmpbuf + 4));
1853
1854         gfar_write(macptr+1, tempval);
1855 }
1856
1857 /* GFAR error interrupt handler */
1858 static irqreturn_t gfar_error(int irq, void *dev_id, struct pt_regs *regs)
1859 {
1860         struct net_device *dev = dev_id;
1861         struct gfar_private *priv = netdev_priv(dev);
1862
1863         /* Save ievent for future reference */
1864         u32 events = gfar_read(&priv->regs->ievent);
1865
1866         /* Clear IEVENT */
1867         gfar_write(&priv->regs->ievent, IEVENT_ERR_MASK);
1868
1869         /* Hmm... */
1870         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
1871                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1872                                 dev->name, events, gfar_read(&priv->regs->imask));
1873
1874         /* Update the error counters */
1875         if (events & IEVENT_TXE) {
1876                 priv->stats.tx_errors++;
1877
1878                 if (events & IEVENT_LC)
1879                         priv->stats.tx_window_errors++;
1880                 if (events & IEVENT_CRL)
1881                         priv->stats.tx_aborted_errors++;
1882                 if (events & IEVENT_XFUN) {
1883                         if (netif_msg_tx_err(priv))
1884                                 printk(KERN_DEBUG "%s: underrun.  packet dropped.\n",
1885                                                 dev->name);
1886                         priv->stats.tx_dropped++;
1887                         priv->extra_stats.tx_underrun++;
1888
1889                         /* Reactivate the Tx Queues */
1890                         gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1891                 }
1892                 if (netif_msg_tx_err(priv))
1893                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
1894         }
1895         if (events & IEVENT_BSY) {
1896                 priv->stats.rx_errors++;
1897                 priv->extra_stats.rx_bsy++;
1898
1899                 gfar_receive(irq, dev_id, regs);
1900
1901 #ifndef CONFIG_GFAR_NAPI
1902                 /* Clear the halt bit in RSTAT */
1903                 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1904 #endif
1905
1906                 if (netif_msg_rx_err(priv))
1907                         printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n",
1908                                         dev->name,
1909                                         gfar_read(&priv->regs->rstat));
1910         }
1911         if (events & IEVENT_BABR) {
1912                 priv->stats.rx_errors++;
1913                 priv->extra_stats.rx_babr++;
1914
1915                 if (netif_msg_rx_err(priv))
1916                         printk(KERN_DEBUG "%s: babbling error\n", dev->name);
1917         }
1918         if (events & IEVENT_EBERR) {
1919                 priv->extra_stats.eberr++;
1920                 if (netif_msg_rx_err(priv))
1921                         printk(KERN_DEBUG "%s: EBERR\n", dev->name);
1922         }
1923         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
1924                 if (netif_msg_rx_status(priv))
1925                         printk(KERN_DEBUG "%s: control frame\n", dev->name);
1926
1927         if (events & IEVENT_BABT) {
1928                 priv->extra_stats.tx_babt++;
1929                 if (netif_msg_tx_err(priv))
1930                         printk(KERN_DEBUG "%s: babt error\n", dev->name);
1931         }
1932         return IRQ_HANDLED;
1933 }
1934
1935 /* Structure for a device driver */
1936 static struct platform_driver gfar_driver = {
1937         .probe = gfar_probe,
1938         .remove = gfar_remove,
1939         .driver = {
1940                 .name = "fsl-gianfar",
1941         },
1942 };
1943
1944 static int __init gfar_init(void)
1945 {
1946         int err = gfar_mdio_init();
1947
1948         if (err)
1949                 return err;
1950
1951         err = platform_driver_register(&gfar_driver);
1952
1953         if (err)
1954                 gfar_mdio_exit();
1955         
1956         return err;
1957 }
1958
1959 static void __exit gfar_exit(void)
1960 {
1961         platform_driver_unregister(&gfar_driver);
1962         gfar_mdio_exit();
1963 }
1964
1965 module_init(gfar_init);
1966 module_exit(gfar_exit);
1967