git.oblomov.eu Git - linux-2.6/blob - sound/soc/codecs/wm8990.c

   1 /*
   2  * wm8990.c  --  WM8990 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008 Wolfson Microelectronics PLC.
   5  * Author: Liam Girdwood
   6  *         lg@opensource.wolfsonmicro.com or linux@wolfsonmicro.com
   7  *
   8  *  This program is free software; you can redistribute  it and/or modify it
   9  *  under  the terms of  the GNU General  Public License as published by the
  10  *  Free Software Foundation;  either version 2 of the  License, or (at your
  11  *  option) any later version.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/pm.h>
  20 #include <linux/i2c.h>
  21 #include <linux/platform_device.h>
  22 #include <sound/core.h>
  23 #include <sound/pcm.h>
  24 #include <sound/pcm_params.h>
  25 #include <sound/soc.h>
  26 #include <sound/soc-dapm.h>
  27 #include <sound/initval.h>
  28 #include <sound/tlv.h>
  29 #include <asm/div64.h>
  30
  31 #include "wm8990.h"
  32
  33 #define AUDIO_NAME "wm8990"
  34 #define WM8990_VERSION "0.2"
  35
  36 /* codec private data */
  37 struct wm8990_priv {
  38         unsigned int sysclk;
  39         unsigned int pcmclk;
  40 };
  41
  42 /*
  43  * wm8990 register cache.  Note that register 0 is not included in the
  44  * cache.
  45  */
  46 static const u16 wm8990_reg[] = {
  47         0x8990,     /* R0  - Reset */
  48         0x0000,     /* R1  - Power Management (1) */
  49         0x6000,     /* R2  - Power Management (2) */
  50         0x0000,     /* R3  - Power Management (3) */
  51         0x4050,     /* R4  - Audio Interface (1) */
  52         0x4000,     /* R5  - Audio Interface (2) */
  53         0x01C8,     /* R6  - Clocking (1) */
  54         0x0000,     /* R7  - Clocking (2) */
  55         0x0040,     /* R8  - Audio Interface (3) */
  56         0x0040,     /* R9  - Audio Interface (4) */
  57         0x0004,     /* R10 - DAC CTRL */
  58         0x00C0,     /* R11 - Left DAC Digital Volume */
  59         0x00C0,     /* R12 - Right DAC Digital Volume */
  60         0x0000,     /* R13 - Digital Side Tone */
  61         0x0100,     /* R14 - ADC CTRL */
  62         0x00C0,     /* R15 - Left ADC Digital Volume */
  63         0x00C0,     /* R16 - Right ADC Digital Volume */
  64         0x0000,     /* R17 */
  65         0x0000,     /* R18 - GPIO CTRL 1 */
  66         0x1000,     /* R19 - GPIO1 & GPIO2 */
  67         0x1010,     /* R20 - GPIO3 & GPIO4 */
  68         0x1010,     /* R21 - GPIO5 & GPIO6 */
  69         0x8000,     /* R22 - GPIOCTRL 2 */
  70         0x0800,     /* R23 - GPIO_POL */
  71         0x008B,     /* R24 - Left Line Input 1&2 Volume */
  72         0x008B,     /* R25 - Left Line Input 3&4 Volume */
  73         0x008B,     /* R26 - Right Line Input 1&2 Volume */
  74         0x008B,     /* R27 - Right Line Input 3&4 Volume */
  75         0x0000,     /* R28 - Left Output Volume */
  76         0x0000,     /* R29 - Right Output Volume */
  77         0x0066,     /* R30 - Line Outputs Volume */
  78         0x0022,     /* R31 - Out3/4 Volume */
  79         0x0079,     /* R32 - Left OPGA Volume */
  80         0x0079,     /* R33 - Right OPGA Volume */
  81         0x0003,     /* R34 - Speaker Volume */
  82         0x0003,     /* R35 - ClassD1 */
  83         0x0000,     /* R36 */
  84         0x0100,     /* R37 - ClassD3 */
  85         0x0079,     /* R38 - ClassD4 */
  86         0x0000,     /* R39 - Input Mixer1 */
  87         0x0000,     /* R40 - Input Mixer2 */
  88         0x0000,     /* R41 - Input Mixer3 */
  89         0x0000,     /* R42 - Input Mixer4 */
  90         0x0000,     /* R43 - Input Mixer5 */
  91         0x0000,     /* R44 - Input Mixer6 */
  92         0x0000,     /* R45 - Output Mixer1 */
  93         0x0000,     /* R46 - Output Mixer2 */
  94         0x0000,     /* R47 - Output Mixer3 */
  95         0x0000,     /* R48 - Output Mixer4 */
  96         0x0000,     /* R49 - Output Mixer5 */
  97         0x0000,     /* R50 - Output Mixer6 */
  98         0x0180,     /* R51 - Out3/4 Mixer */
  99         0x0000,     /* R52 - Line Mixer1 */
 100         0x0000,     /* R53 - Line Mixer2 */
 101         0x0000,     /* R54 - Speaker Mixer */
 102         0x0000,     /* R55 - Additional Control */
 103         0x0000,     /* R56 - AntiPOP1 */
 104         0x0000,     /* R57 - AntiPOP2 */
 105         0x0000,     /* R58 - MICBIAS */
 106         0x0000,     /* R59 */
 107         0x0008,     /* R60 - PLL1 */
 108         0x0031,     /* R61 - PLL2 */
 109         0x0026,     /* R62 - PLL3 */
 110 };
 111
 112 /*
 113  * read wm8990 register cache
 114  */
 115 static inline unsigned int wm8990_read_reg_cache(struct snd_soc_codec *codec,
 116         unsigned int reg)
 117 {
 118         u16 *cache = codec->reg_cache;
 119         BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1);
 120         return cache[reg];
 121 }
 122
 123 /*
 124  * write wm8990 register cache
 125  */
 126 static inline void wm8990_write_reg_cache(struct snd_soc_codec *codec,
 127         unsigned int reg, unsigned int value)
 128 {
 129         u16 *cache = codec->reg_cache;
 130         BUG_ON(reg > (ARRAY_SIZE(wm8990_reg)) - 1);
 131
 132         /* Reset register is uncached */
 133         if (reg == 0)
 134                 return;
 135
 136         cache[reg] = value;
 137 }
 138
 139 /*
 140  * write to the wm8990 register space
 141  */
 142 static int wm8990_write(struct snd_soc_codec *codec, unsigned int reg,
 143         unsigned int value)
 144 {
 145         u8 data[3];
 146
 147         data[0] = reg & 0xFF;
 148         data[1] = (value >> 8) & 0xFF;
 149         data[2] = value & 0xFF;
 150
 151         wm8990_write_reg_cache(codec, reg, value);
 152
 153         if (codec->hw_write(codec->control_data, data, 3) == 2)
 154                 return 0;
 155         else
 156                 return -EIO;
 157 }
 158
 159 #define wm8990_reset(c) wm8990_write(c, WM8990_RESET, 0)
 160
 161 static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600);
 162
 163 static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000);
 164
 165 static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, 0, -2100);
 166
 167 static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600);
 168
 169 static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0);
 170
 171 static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0);
 172
 173 static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763);
 174
 175 static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0);
 176
 177 static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
 178         struct snd_ctl_elem_value *ucontrol)
 179 {
 180         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 181         int reg = kcontrol->private_value & 0xff;
 182         int ret;
 183         u16 val;
 184
 185         ret = snd_soc_put_volsw(kcontrol, ucontrol);
 186         if (ret < 0)
 187                 return ret;
 188
 189         /* now hit the volume update bits (always bit 8) */
 190         val = wm8990_read_reg_cache(codec, reg);
 191         return wm8990_write(codec, reg, val | 0x0100);
 192 }
 193
 194 #define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
 195          tlv_array) {\
 196         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 197         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 198                   SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 199         .tlv.p = (tlv_array), \
 200         .info = snd_soc_info_volsw, \
 201         .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
 202         .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
 203
 204
 205 static const char *wm8990_digital_sidetone[] =
 206         {"None", "Left ADC", "Right ADC", "Reserved"};
 207
 208 static const struct soc_enum wm8990_left_digital_sidetone_enum =
 209 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
 210         WM8990_ADC_TO_DACL_SHIFT,
 211         WM8990_ADC_TO_DACL_MASK,
 212         wm8990_digital_sidetone);
 213
 214 static const struct soc_enum wm8990_right_digital_sidetone_enum =
 215 SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
 216         WM8990_ADC_TO_DACR_SHIFT,
 217         WM8990_ADC_TO_DACR_MASK,
 218         wm8990_digital_sidetone);
 219
 220 static const char *wm8990_adcmode[] =
 221         {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
 222
 223 static const struct soc_enum wm8990_right_adcmode_enum =
 224 SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
 225         WM8990_ADC_HPF_CUT_SHIFT,
 226         WM8990_ADC_HPF_CUT_MASK,
 227         wm8990_adcmode);
 228
 229 static const struct snd_kcontrol_new wm8990_snd_controls[] = {
 230 /* INMIXL */
 231 SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
 232 SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
 233 /* INMIXR */
 234 SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
 235 SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
 236
 237 /* LOMIX */
 238 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
 239         WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
 240 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
 241         WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
 242 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
 243         WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
 244 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
 245         WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
 246 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
 247         WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
 248 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
 249         WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
 250
 251 /* ROMIX */
 252 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
 253         WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
 254 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
 255         WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
 256 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
 257         WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
 258 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
 259         WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
 260 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
 261         WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
 262 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
 263         WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
 264
 265 /* LOUT */
 266 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
 267         WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
 268 SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
 269
 270 /* ROUT */
 271 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
 272         WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
 273 SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
 274
 275 /* LOPGA */
 276 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
 277         WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
 278 SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
 279         WM8990_LOPGAZC_BIT, 1, 0),
 280
 281 /* ROPGA */
 282 SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
 283         WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
 284 SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
 285         WM8990_ROPGAZC_BIT, 1, 0),
 286
 287 SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
 288         WM8990_LONMUTE_BIT, 1, 0),
 289 SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
 290         WM8990_LOPMUTE_BIT, 1, 0),
 291 SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
 292         WM8990_LOATTN_BIT, 1, 0),
 293 SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
 294         WM8990_RONMUTE_BIT, 1, 0),
 295 SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
 296         WM8990_ROPMUTE_BIT, 1, 0),
 297 SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
 298         WM8990_ROATTN_BIT, 1, 0),
 299
 300 SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
 301         WM8990_OUT3MUTE_BIT, 1, 0),
 302 SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
 303         WM8990_OUT3ATTN_BIT, 1, 0),
 304
 305 SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
 306         WM8990_OUT4MUTE_BIT, 1, 0),
 307 SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
 308         WM8990_OUT4ATTN_BIT, 1, 0),
 309
 310 SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
 311         WM8990_CDMODE_BIT, 1, 0),
 312
 313 SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
 314         WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
 315 SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
 316         WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
 317 SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
 318         WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
 319 SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
 320         WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
 321 SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
 322         WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
 323
 324 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
 325         WM8990_LEFT_DAC_DIGITAL_VOLUME,
 326         WM8990_DACL_VOL_SHIFT,
 327         WM8990_DACL_VOL_MASK,
 328         0,
 329         out_dac_tlv),
 330
 331 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
 332         WM8990_RIGHT_DAC_DIGITAL_VOLUME,
 333         WM8990_DACR_VOL_SHIFT,
 334         WM8990_DACR_VOL_MASK,
 335         0,
 336         out_dac_tlv),
 337
 338 SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
 339 SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
 340
 341 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
 342         WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
 343         out_sidetone_tlv),
 344 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
 345         WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
 346         out_sidetone_tlv),
 347
 348 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
 349         WM8990_ADC_HPF_ENA_BIT, 1, 0),
 350
 351 SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
 352
 353 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
 354         WM8990_LEFT_ADC_DIGITAL_VOLUME,
 355         WM8990_ADCL_VOL_SHIFT,
 356         WM8990_ADCL_VOL_MASK,
 357         0,
 358         in_adc_tlv),
 359
 360 SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
 361         WM8990_RIGHT_ADC_DIGITAL_VOLUME,
 362         WM8990_ADCR_VOL_SHIFT,
 363         WM8990_ADCR_VOL_MASK,
 364         0,
 365         in_adc_tlv),
 366
 367 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
 368         WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
 369         WM8990_LIN12VOL_SHIFT,
 370         WM8990_LIN12VOL_MASK,
 371         0,
 372         in_pga_tlv),
 373
 374 SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
 375         WM8990_LI12ZC_BIT, 1, 0),
 376
 377 SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
 378         WM8990_LI12MUTE_BIT, 1, 0),
 379
 380 SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
 381         WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
 382         WM8990_LIN34VOL_SHIFT,
 383         WM8990_LIN34VOL_MASK,
 384         0,
 385         in_pga_tlv),
 386
 387 SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
 388         WM8990_LI34ZC_BIT, 1, 0),
 389
 390 SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
 391         WM8990_LI34MUTE_BIT, 1, 0),
 392
 393 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
 394         WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
 395         WM8990_RIN12VOL_SHIFT,
 396         WM8990_RIN12VOL_MASK,
 397         0,
 398         in_pga_tlv),
 399
 400 SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
 401         WM8990_RI12ZC_BIT, 1, 0),
 402
 403 SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
 404         WM8990_RI12MUTE_BIT, 1, 0),
 405
 406 SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
 407         WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
 408         WM8990_RIN34VOL_SHIFT,
 409         WM8990_RIN34VOL_MASK,
 410         0,
 411         in_pga_tlv),
 412
 413 SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
 414         WM8990_RI34ZC_BIT, 1, 0),
 415
 416 SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
 417         WM8990_RI34MUTE_BIT, 1, 0),
 418
 419 };
 420
 421 /* add non dapm controls */
 422 static int wm8990_add_controls(struct snd_soc_codec *codec)
 423 {
 424         int err, i;
 425
 426         for (i = 0; i < ARRAY_SIZE(wm8990_snd_controls); i++) {
 427                 err = snd_ctl_add(codec->card,
 428                                 snd_soc_cnew(&wm8990_snd_controls[i], codec,
 429                                         NULL));
 430                 if (err < 0)
 431                         return err;
 432         }
 433         return 0;
 434 }
 435
 436 /*
 437  * _DAPM_ Controls
 438  */
 439
 440 static int inmixer_event(struct snd_soc_dapm_widget *w,
 441         struct snd_kcontrol *kcontrol, int event)
 442 {
 443         u16 reg, fakepower;
 444
 445         reg = wm8990_read_reg_cache(w->codec, WM8990_POWER_MANAGEMENT_2);
 446         fakepower = wm8990_read_reg_cache(w->codec, WM8990_INTDRIVBITS);
 447
 448         if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
 449                 (1 << WM8990_AINLMUX_PWR_BIT))) {
 450                 reg |= WM8990_AINL_ENA;
 451         } else {
 452                 reg &= ~WM8990_AINL_ENA;
 453         }
 454
 455         if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
 456                 (1 << WM8990_AINRMUX_PWR_BIT))) {
 457                 reg |= WM8990_AINR_ENA;
 458         } else {
 459                 reg &= ~WM8990_AINL_ENA;
 460         }
 461         wm8990_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
 462
 463         return 0;
 464 }
 465
 466 static int outmixer_event(struct snd_soc_dapm_widget *w,
 467         struct snd_kcontrol *kcontrol, int event)
 468 {
 469         u32 reg_shift = kcontrol->private_value & 0xfff;
 470         int ret = 0;
 471         u16 reg;
 472
 473         switch (reg_shift) {
 474         case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
 475                 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER1);
 476                 if (reg & WM8990_LDLO) {
 477                         printk(KERN_WARNING
 478                         "Cannot set as Output Mixer 1 LDLO Set\n");
 479                         ret = -1;
 480                 }
 481                 break;
 482         case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
 483                 reg = wm8990_read_reg_cache(w->codec, WM8990_OUTPUT_MIXER2);
 484                 if (reg & WM8990_RDRO) {
 485                         printk(KERN_WARNING
 486                         "Cannot set as Output Mixer 2 RDRO Set\n");
 487                         ret = -1;
 488                 }
 489                 break;
 490         case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
 491                 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER);
 492                 if (reg & WM8990_LDSPK) {
 493                         printk(KERN_WARNING
 494                         "Cannot set as Speaker Mixer LDSPK Set\n");
 495                         ret = -1;
 496                 }
 497                 break;
 498         case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
 499                 reg = wm8990_read_reg_cache(w->codec, WM8990_SPEAKER_MIXER);
 500                 if (reg & WM8990_RDSPK) {
 501                         printk(KERN_WARNING
 502                         "Cannot set as Speaker Mixer RDSPK Set\n");
 503                         ret = -1;
 504                 }
 505                 break;
 506         }
 507
 508         return ret;
 509 }
 510
 511 /* INMIX dB values */
 512 static const unsigned int in_mix_tlv[] = {
 513         TLV_DB_RANGE_HEAD(1),
 514         0, 7, TLV_DB_LINEAR_ITEM(-1200, 600),
 515 };
 516
 517 /* Left In PGA Connections */
 518 static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
 519 SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
 520 SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
 521 };
 522
 523 static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
 524 SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
 525 SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
 526 };
 527
 528 /* Right In PGA Connections */
 529 static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
 530 SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
 531 SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
 532 };
 533
 534 static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
 535 SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
 536 SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
 537 };
 538
 539 /* INMIXL */
 540 static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
 541 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
 542         WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
 543 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
 544         7, 0, in_mix_tlv),
 545 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
 546         1, 0),
 547 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
 548         1, 0),
 549 };
 550
 551 /* INMIXR */
 552 static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
 553 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
 554         WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
 555 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
 556         7, 0, in_mix_tlv),
 557 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
 558         1, 0),
 559 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
 560         1, 0),
 561 };
 562
 563 /* AINLMUX */
 564 static const char *wm8990_ainlmux[] =
 565         {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
 566
 567 static const struct soc_enum wm8990_ainlmux_enum =
 568 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
 569         ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
 570
 571 static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
 572 SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
 573
 574 /* DIFFINL */
 575
 576 /* AINRMUX */
 577 static const char *wm8990_ainrmux[] =
 578         {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
 579
 580 static const struct soc_enum wm8990_ainrmux_enum =
 581 SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
 582         ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
 583
 584 static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
 585 SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
 586
 587 /* RXVOICE */
 588 static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
 589 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
 590                         WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
 591 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
 592                         WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
 593 };
 594
 595 /* LOMIX */
 596 static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
 597 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
 598         WM8990_LRBLO_BIT, 1, 0),
 599 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
 600         WM8990_LLBLO_BIT, 1, 0),
 601 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
 602         WM8990_LRI3LO_BIT, 1, 0),
 603 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
 604         WM8990_LLI3LO_BIT, 1, 0),
 605 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
 606         WM8990_LR12LO_BIT, 1, 0),
 607 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
 608         WM8990_LL12LO_BIT, 1, 0),
 609 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
 610         WM8990_LDLO_BIT, 1, 0),
 611 };
 612
 613 /* ROMIX */
 614 static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
 615 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
 616         WM8990_RLBRO_BIT, 1, 0),
 617 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
 618         WM8990_RRBRO_BIT, 1, 0),
 619 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
 620         WM8990_RLI3RO_BIT, 1, 0),
 621 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
 622         WM8990_RRI3RO_BIT, 1, 0),
 623 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
 624         WM8990_RL12RO_BIT, 1, 0),
 625 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
 626         WM8990_RR12RO_BIT, 1, 0),
 627 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
 628         WM8990_RDRO_BIT, 1, 0),
 629 };
 630
 631 /* LONMIX */
 632 static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
 633 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
 634         WM8990_LLOPGALON_BIT, 1, 0),
 635 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
 636         WM8990_LROPGALON_BIT, 1, 0),
 637 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
 638         WM8990_LOPLON_BIT, 1, 0),
 639 };
 640
 641 /* LOPMIX */
 642 static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
 643 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
 644         WM8990_LR12LOP_BIT, 1, 0),
 645 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
 646         WM8990_LL12LOP_BIT, 1, 0),
 647 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
 648         WM8990_LLOPGALOP_BIT, 1, 0),
 649 };
 650
 651 /* RONMIX */
 652 static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
 653 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
 654         WM8990_RROPGARON_BIT, 1, 0),
 655 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
 656         WM8990_RLOPGARON_BIT, 1, 0),
 657 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
 658         WM8990_ROPRON_BIT, 1, 0),
 659 };
 660
 661 /* ROPMIX */
 662 static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
 663 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
 664         WM8990_RL12ROP_BIT, 1, 0),
 665 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
 666         WM8990_RR12ROP_BIT, 1, 0),
 667 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
 668         WM8990_RROPGAROP_BIT, 1, 0),
 669 };
 670
 671 /* OUT3MIX */
 672 static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
 673 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
 674         WM8990_LI4O3_BIT, 1, 0),
 675 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
 676         WM8990_LPGAO3_BIT, 1, 0),
 677 };
 678
 679 /* OUT4MIX */
 680 static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
 681 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
 682         WM8990_RPGAO4_BIT, 1, 0),
 683 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
 684         WM8990_RI4O4_BIT, 1, 0),
 685 };
 686
 687 /* SPKMIX */
 688 static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
 689 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
 690         WM8990_LI2SPK_BIT, 1, 0),
 691 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
 692         WM8990_LB2SPK_BIT, 1, 0),
 693 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
 694         WM8990_LOPGASPK_BIT, 1, 0),
 695 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
 696         WM8990_LDSPK_BIT, 1, 0),
 697 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
 698         WM8990_RDSPK_BIT, 1, 0),
 699 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
 700         WM8990_ROPGASPK_BIT, 1, 0),
 701 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
 702         WM8990_RL12ROP_BIT, 1, 0),
 703 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
 704         WM8990_RI2SPK_BIT, 1, 0),
 705 };
 706
 707 static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
 708 /* Input Side */
 709 /* Input Lines */
 710 SND_SOC_DAPM_INPUT("LIN1"),
 711 SND_SOC_DAPM_INPUT("LIN2"),
 712 SND_SOC_DAPM_INPUT("LIN3"),
 713 SND_SOC_DAPM_INPUT("LIN4/RXN"),
 714 SND_SOC_DAPM_INPUT("RIN3"),
 715 SND_SOC_DAPM_INPUT("RIN4/RXP"),
 716 SND_SOC_DAPM_INPUT("RIN1"),
 717 SND_SOC_DAPM_INPUT("RIN2"),
 718 SND_SOC_DAPM_INPUT("Internal ADC Source"),
 719
 720 /* DACs */
 721 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
 722         WM8990_ADCL_ENA_BIT, 0),
 723 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
 724         WM8990_ADCR_ENA_BIT, 0),
 725
 726 /* Input PGAs */
 727 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
 728         0, &wm8990_dapm_lin12_pga_controls[0],
 729         ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
 730 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
 731         0, &wm8990_dapm_lin34_pga_controls[0],
 732         ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
 733 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
 734         0, &wm8990_dapm_rin12_pga_controls[0],
 735         ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
 736 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
 737         0, &wm8990_dapm_rin34_pga_controls[0],
 738         ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
 739
 740 /* INMIXL */
 741 SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
 742         &wm8990_dapm_inmixl_controls[0],
 743         ARRAY_SIZE(wm8990_dapm_inmixl_controls),
 744         inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 745
 746 /* AINLMUX */
 747 SND_SOC_DAPM_MUX_E("AILNMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
 748         &wm8990_dapm_ainlmux_controls, inmixer_event,
 749         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 750
 751 /* INMIXR */
 752 SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
 753         &wm8990_dapm_inmixr_controls[0],
 754         ARRAY_SIZE(wm8990_dapm_inmixr_controls),
 755         inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 756
 757 /* AINRMUX */
 758 SND_SOC_DAPM_MUX_E("AIRNMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
 759         &wm8990_dapm_ainrmux_controls, inmixer_event,
 760         SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 761
 762 /* Output Side */
 763 /* DACs */
 764 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
 765         WM8990_DACL_ENA_BIT, 0),
 766 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
 767         WM8990_DACR_ENA_BIT, 0),
 768
 769 /* LOMIX */
 770 SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
 771         0, &wm8990_dapm_lomix_controls[0],
 772         ARRAY_SIZE(wm8990_dapm_lomix_controls),
 773         outmixer_event, SND_SOC_DAPM_PRE_REG),
 774
 775 /* LONMIX */
 776 SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
 777         &wm8990_dapm_lonmix_controls[0],
 778         ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
 779
 780 /* LOPMIX */
 781 SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
 782         &wm8990_dapm_lopmix_controls[0],
 783         ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
 784
 785 /* OUT3MIX */
 786 SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
 787         &wm8990_dapm_out3mix_controls[0],
 788         ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
 789
 790 /* SPKMIX */
 791 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
 792         &wm8990_dapm_spkmix_controls[0],
 793         ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
 794         SND_SOC_DAPM_PRE_REG),
 795
 796 /* OUT4MIX */
 797 SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
 798         &wm8990_dapm_out4mix_controls[0],
 799         ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
 800
 801 /* ROPMIX */
 802 SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
 803         &wm8990_dapm_ropmix_controls[0],
 804         ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
 805
 806 /* RONMIX */
 807 SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
 808         &wm8990_dapm_ronmix_controls[0],
 809         ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
 810
 811 /* ROMIX */
 812 SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
 813         0, &wm8990_dapm_romix_controls[0],
 814         ARRAY_SIZE(wm8990_dapm_romix_controls),
 815         outmixer_event, SND_SOC_DAPM_PRE_REG),
 816
 817 /* LOUT PGA */
 818 SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
 819         NULL, 0),
 820
 821 /* ROUT PGA */
 822 SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
 823         NULL, 0),
 824
 825 /* LOPGA */
 826 SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
 827         NULL, 0),
 828
 829 /* ROPGA */
 830 SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
 831         NULL, 0),
 832
 833 /* MICBIAS */
 834 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1,
 835         WM8990_MICBIAS_ENA_BIT, 0),
 836
 837 SND_SOC_DAPM_OUTPUT("LON"),
 838 SND_SOC_DAPM_OUTPUT("LOP"),
 839 SND_SOC_DAPM_OUTPUT("OUT3"),
 840 SND_SOC_DAPM_OUTPUT("LOUT"),
 841 SND_SOC_DAPM_OUTPUT("SPKN"),
 842 SND_SOC_DAPM_OUTPUT("SPKP"),
 843 SND_SOC_DAPM_OUTPUT("ROUT"),
 844 SND_SOC_DAPM_OUTPUT("OUT4"),
 845 SND_SOC_DAPM_OUTPUT("ROP"),
 846 SND_SOC_DAPM_OUTPUT("RON"),
 847
 848 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
 849 };
 850
 851 static const struct snd_soc_dapm_route audio_map[] = {
 852         /* Make DACs turn on when playing even if not mixed into any outputs */
 853         {"Internal DAC Sink", NULL, "Left DAC"},
 854         {"Internal DAC Sink", NULL, "Right DAC"},
 855
 856         /* Make ADCs turn on when recording even if not mixed from any inputs */
 857         {"Left ADC", NULL, "Internal ADC Source"},
 858         {"Right ADC", NULL, "Internal ADC Source"},
 859
 860         /* Input Side */
 861         /* LIN12 PGA */
 862         {"LIN12 PGA", "LIN1 Switch", "LIN1"},
 863         {"LIN12 PGA", "LIN2 Switch", "LIN2"},
 864         /* LIN34 PGA */
 865         {"LIN34 PGA", "LIN3 Switch", "LIN3"},
 866         {"LIN34 PGA", "LIN4 Switch", "LIN4"},
 867         /* INMIXL */
 868         {"INMIXL", "Record Left Volume", "LOMIX"},
 869         {"INMIXL", "LIN2 Volume", "LIN2"},
 870         {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
 871         {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
 872         /* AILNMUX */
 873         {"AILNMUX", "INMIXL Mix", "INMIXL"},
 874         {"AILNMUX", "DIFFINL Mix", "LIN12PGA"},
 875         {"AILNMUX", "DIFFINL Mix", "LIN34PGA"},
 876         {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
 877         {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
 878         /* ADC */
 879         {"Left ADC", NULL, "AILNMUX"},
 880
 881         /* RIN12 PGA */
 882         {"RIN12 PGA", "RIN1 Switch", "RIN1"},
 883         {"RIN12 PGA", "RIN2 Switch", "RIN2"},
 884         /* RIN34 PGA */
 885         {"RIN34 PGA", "RIN3 Switch", "RIN3"},
 886         {"RIN34 PGA", "RIN4 Switch", "RIN4"},
 887         /* INMIXL */
 888         {"INMIXR", "Record Right Volume", "ROMIX"},
 889         {"INMIXR", "RIN2 Volume", "RIN2"},
 890         {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
 891         {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
 892         /* AIRNMUX */
 893         {"AIRNMUX", "INMIXR Mix", "INMIXR"},
 894         {"AIRNMUX", "DIFFINR Mix", "RIN12PGA"},
 895         {"AIRNMUX", "DIFFINR Mix", "RIN34PGA"},
 896         {"AIRNMUX", "RXVOICE Mix", "RIN4/RXN"},
 897         {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
 898         /* ADC */
 899         {"Right ADC", NULL, "AIRNMUX"},
 900
 901         /* LOMIX */
 902         {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
 903         {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
 904         {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 905         {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 906         {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
 907         {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
 908         {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
 909
 910         /* ROMIX */
 911         {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
 912         {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
 913         {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
 914         {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
 915         {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
 916         {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
 917         {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
 918
 919         /* SPKMIX */
 920         {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
 921         {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
 922         {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
 923         {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
 924         {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
 925         {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
 926         {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
 927         {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
 928
 929         /* LONMIX */
 930         {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
 931         {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
 932         {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
 933
 934         /* LOPMIX */
 935         {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 936         {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 937         {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
 938
 939         /* OUT3MIX */
 940         {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXP"},
 941         {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
 942
 943         /* OUT4MIX */
 944         {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
 945         {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
 946
 947         /* RONMIX */
 948         {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
 949         {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
 950         {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
 951
 952         /* ROPMIX */
 953         {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
 954         {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
 955         {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
 956
 957         /* Out Mixer PGAs */
 958         {"LOPGA", NULL, "LOMIX"},
 959         {"ROPGA", NULL, "ROMIX"},
 960
 961         {"LOUT PGA", NULL, "LOMIX"},
 962         {"ROUT PGA", NULL, "ROMIX"},
 963
 964         /* Output Pins */
 965         {"LON", NULL, "LONMIX"},
 966         {"LOP", NULL, "LOPMIX"},
 967         {"OUT", NULL, "OUT3MIX"},
 968         {"LOUT", NULL, "LOUT PGA"},
 969         {"SPKN", NULL, "SPKMIX"},
 970         {"ROUT", NULL, "ROUT PGA"},
 971         {"OUT4", NULL, "OUT4MIX"},
 972         {"ROP", NULL, "ROPMIX"},
 973         {"RON", NULL, "RONMIX"},
 974 };
 975
 976 static int wm8990_add_widgets(struct snd_soc_codec *codec)
 977 {
 978         snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets,
 979                                   ARRAY_SIZE(wm8990_dapm_widgets));
 980
 981         /* set up the WM8990 audio map */
 982         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 983
 984         snd_soc_dapm_new_widgets(codec);
 985         return 0;
 986 }
 987
 988 /* PLL divisors */
 989 struct _pll_div {
 990         u32 div2;
 991         u32 n;
 992         u32 k;
 993 };
 994
 995 /* The size in bits of the pll divide multiplied by 10
 996  * to allow rounding later */
 997 #define FIXED_PLL_SIZE ((1 << 16) * 10)
 998
 999 static void pll_factors(struct _pll_div *pll_div, unsigned int target,
1000         unsigned int source)
1001 {
1002         u64 Kpart;
1003         unsigned int K, Ndiv, Nmod;
1004
1005
1006         Ndiv = target / source;
1007         if (Ndiv < 6) {
1008                 source >>= 1;
1009                 pll_div->div2 = 1;
1010                 Ndiv = target / source;
1011         } else
1012                 pll_div->div2 = 0;
1013
1014         if ((Ndiv < 6) || (Ndiv > 12))
1015                 printk(KERN_WARNING
1016                 "WM8990 N value outwith recommended range! N = %d\n", Ndiv);
1017
1018         pll_div->n = Ndiv;
1019         Nmod = target % source;
1020         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
1021
1022         do_div(Kpart, source);
1023
1024         K = Kpart & 0xFFFFFFFF;
1025
1026         /* Check if we need to round */
1027         if ((K % 10) >= 5)
1028                 K += 5;
1029
1030         /* Move down to proper range now rounding is done */
1031         K /= 10;
1032
1033         pll_div->k = K;
1034 }
1035
1036 static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai,
1037                 int pll_id, unsigned int freq_in, unsigned int freq_out)
1038 {
1039         u16 reg;
1040         struct snd_soc_codec *codec = codec_dai->codec;
1041         struct _pll_div pll_div;
1042
1043         if (freq_in && freq_out) {
1044                 pll_factors(&pll_div, freq_out * 4, freq_in);
1045
1046                 /* Turn on PLL */
1047                 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1048                 reg |= WM8990_PLL_ENA;
1049                 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1050
1051                 /* sysclk comes from PLL */
1052                 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2);
1053                 wm8990_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
1054
1055                 /* set up N , fractional mode and pre-divisor if neccessary */
1056                 wm8990_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
1057                         (pll_div.div2?WM8990_PRESCALE:0));
1058                 wm8990_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
1059                 wm8990_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
1060         } else {
1061                 /* Turn on PLL */
1062                 reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1063                 reg &= ~WM8990_PLL_ENA;
1064                 wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
1065         }
1066         return 0;
1067 }
1068
1069 /*
1070  * Clock after PLL and dividers
1071  */
1072 static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1073                 int clk_id, unsigned int freq, int dir)
1074 {
1075         struct snd_soc_codec *codec = codec_dai->codec;
1076         struct wm8990_priv *wm8990 = codec->private_data;
1077
1078         wm8990->sysclk = freq;
1079         return 0;
1080 }
1081
1082 /*
1083  * Set's ADC and Voice DAC format.
1084  */
1085 static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
1086                 unsigned int fmt)
1087 {
1088         struct snd_soc_codec *codec = codec_dai->codec;
1089         u16 audio1, audio3;
1090
1091         audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
1092         audio3 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_3);
1093
1094         /* set master/slave audio interface */
1095         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1096         case SND_SOC_DAIFMT_CBS_CFS:
1097                 audio3 &= ~WM8990_AIF_MSTR1;
1098                 break;
1099         case SND_SOC_DAIFMT_CBM_CFM:
1100                 audio3 |= WM8990_AIF_MSTR1;
1101                 break;
1102         default:
1103                 return -EINVAL;
1104         }
1105
1106         audio1 &= ~WM8990_AIF_FMT_MASK;
1107
1108         /* interface format */
1109         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1110         case SND_SOC_DAIFMT_I2S:
1111                 audio1 |= WM8990_AIF_TMF_I2S;
1112                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1113                 break;
1114         case SND_SOC_DAIFMT_RIGHT_J:
1115                 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1116                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1117                 break;
1118         case SND_SOC_DAIFMT_LEFT_J:
1119                 audio1 |= WM8990_AIF_TMF_LEFTJ;
1120                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1121                 break;
1122         case SND_SOC_DAIFMT_DSP_A:
1123                 audio1 |= WM8990_AIF_TMF_DSP;
1124                 audio1 &= ~WM8990_AIF_LRCLK_INV;
1125                 break;
1126         case SND_SOC_DAIFMT_DSP_B:
1127                 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1128                 break;
1129         default:
1130                 return -EINVAL;
1131         }
1132
1133         wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1134         wm8990_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
1135         return 0;
1136 }
1137
1138 static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1139                 int div_id, int div)
1140 {
1141         struct snd_soc_codec *codec = codec_dai->codec;
1142         u16 reg;
1143
1144         switch (div_id) {
1145         case WM8990_MCLK_DIV:
1146                 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1147                         ~WM8990_MCLK_DIV_MASK;
1148                 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1149                 break;
1150         case WM8990_DACCLK_DIV:
1151                 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1152                         ~WM8990_DAC_CLKDIV_MASK;
1153                 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1154                 break;
1155         case WM8990_ADCCLK_DIV:
1156                 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_2) &
1157                         ~WM8990_ADC_CLKDIV_MASK;
1158                 wm8990_write(codec, WM8990_CLOCKING_2, reg | div);
1159                 break;
1160         case WM8990_BCLK_DIV:
1161                 reg = wm8990_read_reg_cache(codec, WM8990_CLOCKING_1) &
1162                         ~WM8990_BCLK_DIV_MASK;
1163                 wm8990_write(codec, WM8990_CLOCKING_1, reg | div);
1164                 break;
1165         default:
1166                 return -EINVAL;
1167         }
1168
1169         return 0;
1170 }
1171
1172 /*
1173  * Set PCM DAI bit size and sample rate.
1174  */
1175 static int wm8990_hw_params(struct snd_pcm_substream *substream,
1176         struct snd_pcm_hw_params *params)
1177 {
1178         struct snd_soc_pcm_runtime *rtd = substream->private_data;
1179         struct snd_soc_device *socdev = rtd->socdev;
1180         struct snd_soc_codec *codec = socdev->codec;
1181         u16 audio1 = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_1);
1182
1183         audio1 &= ~WM8990_AIF_WL_MASK;
1184         /* bit size */
1185         switch (params_format(params)) {
1186         case SNDRV_PCM_FORMAT_S16_LE:
1187                 break;
1188         case SNDRV_PCM_FORMAT_S20_3LE:
1189                 audio1 |= WM8990_AIF_WL_20BITS;
1190                 break;
1191         case SNDRV_PCM_FORMAT_S24_LE:
1192                 audio1 |= WM8990_AIF_WL_24BITS;
1193                 break;
1194         case SNDRV_PCM_FORMAT_S32_LE:
1195                 audio1 |= WM8990_AIF_WL_32BITS;
1196                 break;
1197         }
1198
1199         wm8990_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1200         return 0;
1201 }
1202
1203 static int wm8990_mute(struct snd_soc_dai *dai, int mute)
1204 {
1205         struct snd_soc_codec *codec = dai->codec;
1206         u16 val;
1207
1208         val  = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
1209
1210         if (mute)
1211                 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1212         else
1213                 wm8990_write(codec, WM8990_DAC_CTRL, val);
1214
1215         return 0;
1216 }
1217
1218 static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1219         enum snd_soc_bias_level level)
1220 {
1221         u16 val;
1222
1223         switch (level) {
1224         case SND_SOC_BIAS_ON:
1225                 break;
1226         case SND_SOC_BIAS_PREPARE:
1227                 break;
1228         case SND_SOC_BIAS_STANDBY:
1229                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1230                         /* Enable all output discharge bits */
1231                         wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1232                                 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1233                                 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1234                                 WM8990_DIS_ROUT);
1235
1236                         /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1237                         wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1238                                      WM8990_BUFDCOPEN | WM8990_POBCTRL |
1239                                      WM8990_VMIDTOG);
1240
1241                         /* Delay to allow output caps to discharge */
1242                         msleep(msecs_to_jiffies(300));
1243
1244                         /* Disable VMIDTOG */
1245                         wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1246                                      WM8990_BUFDCOPEN | WM8990_POBCTRL);
1247
1248                         /* disable all output discharge bits */
1249                         wm8990_write(codec, WM8990_ANTIPOP1, 0);
1250
1251                         /* Enable outputs */
1252                         wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
1253
1254                         msleep(msecs_to_jiffies(50));
1255
1256                         /* Enable VMID at 2x50k */
1257                         wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
1258
1259                         msleep(msecs_to_jiffies(100));
1260
1261                         /* Enable VREF */
1262                         wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1263
1264                         msleep(msecs_to_jiffies(600));
1265
1266                         /* Enable BUFIOEN */
1267                         wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1268                                      WM8990_BUFDCOPEN | WM8990_POBCTRL |
1269                                      WM8990_BUFIOEN);
1270
1271                         /* Disable outputs */
1272                         wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
1273
1274                         /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1275                         wm8990_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
1276                 } else {
1277                         /* ON -> standby */
1278
1279                 }
1280                 break;
1281
1282         case SND_SOC_BIAS_OFF:
1283                 /* Enable POBCTRL and SOFT_ST */
1284                 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1285                         WM8990_POBCTRL | WM8990_BUFIOEN);
1286
1287                 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1288                 wm8990_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
1289                         WM8990_BUFDCOPEN | WM8990_POBCTRL |
1290                         WM8990_BUFIOEN);
1291
1292                 /* mute DAC */
1293                 val = wm8990_read_reg_cache(codec, WM8990_DAC_CTRL);
1294                 wm8990_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
1295
1296                 /* Enable any disabled outputs */
1297                 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
1298
1299                 /* Disable VMID */
1300                 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
1301
1302                 msleep(msecs_to_jiffies(300));
1303
1304                 /* Enable all output discharge bits */
1305                 wm8990_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
1306                         WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1307                         WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1308                         WM8990_DIS_ROUT);
1309
1310                 /* Disable VREF */
1311                 wm8990_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
1312
1313                 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1314                 wm8990_write(codec, WM8990_ANTIPOP2, 0x0);
1315                 break;
1316         }
1317
1318         codec->bias_level = level;
1319         return 0;
1320 }
1321
1322 #define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1323         SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1324         SNDRV_PCM_RATE_48000)
1325
1326 #define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1327         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1328
1329 /*
1330  * The WM8990 supports 2 different and mutually exclusive DAI
1331  * configurations.
1332  *
1333  * 1. ADC/DAC on Primary Interface
1334  * 2. ADC on Primary Interface/DAC on secondary
1335  */
1336 struct snd_soc_dai wm8990_dai = {
1337 /* ADC/DAC on primary */
1338         .name = "WM8990 ADC/DAC Primary",
1339         .id = 1,
1340         .playback = {
1341                 .stream_name = "Playback",
1342                 .channels_min = 1,
1343                 .channels_max = 2,
1344                 .rates = WM8990_RATES,
1345                 .formats = WM8990_FORMATS,},
1346         .capture = {
1347                 .stream_name = "Capture",
1348                 .channels_min = 1,
1349                 .channels_max = 2,
1350                 .rates = WM8990_RATES,
1351                 .formats = WM8990_FORMATS,},
1352         .ops = {
1353                 .hw_params = wm8990_hw_params,},
1354         .dai_ops = {
1355                 .digital_mute = wm8990_mute,
1356                 .set_fmt = wm8990_set_dai_fmt,
1357                 .set_clkdiv = wm8990_set_dai_clkdiv,
1358                 .set_pll = wm8990_set_dai_pll,
1359                 .set_sysclk = wm8990_set_dai_sysclk,
1360         },
1361 };
1362 EXPORT_SYMBOL_GPL(wm8990_dai);
1363
1364 static int wm8990_suspend(struct platform_device *pdev, pm_message_t state)
1365 {
1366         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1367         struct snd_soc_codec *codec = socdev->codec;
1368
1369         /* we only need to suspend if we are a valid card */
1370         if (!codec->card)
1371                 return 0;
1372
1373         wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1374         return 0;
1375 }
1376
1377 static int wm8990_resume(struct platform_device *pdev)
1378 {
1379         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1380         struct snd_soc_codec *codec = socdev->codec;
1381         int i;
1382         u8 data[2];
1383         u16 *cache = codec->reg_cache;
1384
1385         /* we only need to resume if we are a valid card */
1386         if (!codec->card)
1387                 return 0;
1388
1389         /* Sync reg_cache with the hardware */
1390         for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) {
1391                 if (i + 1 == WM8990_RESET)
1392                         continue;
1393                 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
1394                 data[1] = cache[i] & 0x00ff;
1395                 codec->hw_write(codec->control_data, data, 2);
1396         }
1397
1398         wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1399         return 0;
1400 }
1401
1402 /*
1403  * initialise the WM8990 driver
1404  * register the mixer and dsp interfaces with the kernel
1405  */
1406 static int wm8990_init(struct snd_soc_device *socdev)
1407 {
1408         struct snd_soc_codec *codec = socdev->codec;
1409         u16 reg;
1410         int ret = 0;
1411
1412         codec->name = "WM8990";
1413         codec->owner = THIS_MODULE;
1414         codec->read = wm8990_read_reg_cache;
1415         codec->write = wm8990_write;
1416         codec->set_bias_level = wm8990_set_bias_level;
1417         codec->dai = &wm8990_dai;
1418         codec->num_dai = 2;
1419         codec->reg_cache_size = ARRAY_SIZE(wm8990_reg);
1420         codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL);
1421
1422         if (codec->reg_cache == NULL)
1423                 return -ENOMEM;
1424
1425         wm8990_reset(codec);
1426
1427         /* register pcms */
1428         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1429         if (ret < 0) {
1430                 printk(KERN_ERR "wm8990: failed to create pcms\n");
1431                 goto pcm_err;
1432         }
1433
1434         /* charge output caps */
1435         codec->bias_level = SND_SOC_BIAS_OFF;
1436         wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1437
1438         reg = wm8990_read_reg_cache(codec, WM8990_AUDIO_INTERFACE_4);
1439         wm8990_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
1440
1441         reg = wm8990_read_reg_cache(codec, WM8990_GPIO1_GPIO2) &
1442                 ~WM8990_GPIO1_SEL_MASK;
1443         wm8990_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
1444
1445         reg = wm8990_read_reg_cache(codec, WM8990_POWER_MANAGEMENT_2);
1446         wm8990_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
1447
1448         wm8990_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1449         wm8990_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1450
1451         wm8990_add_controls(codec);
1452         wm8990_add_widgets(codec);
1453         ret = snd_soc_register_card(socdev);
1454         if (ret < 0) {
1455                 printk(KERN_ERR "wm8990: failed to register card\n");
1456                 goto card_err;
1457         }
1458         return ret;
1459
1460 card_err:
1461         snd_soc_free_pcms(socdev);
1462         snd_soc_dapm_free(socdev);
1463 pcm_err:
1464         kfree(codec->reg_cache);
1465         return ret;
1466 }
1467
1468 /* If the i2c layer weren't so broken, we could pass this kind of data
1469    around */
1470 static struct snd_soc_device *wm8990_socdev;
1471
1472 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1473
1474 /*
1475  * WM891 2 wire address is determined by GPIO5
1476  * state during powerup.
1477  *    low  = 0x34
1478  *    high = 0x36
1479  */
1480 static unsigned short normal_i2c[] = { 0, I2C_CLIENT_END };
1481
1482 /* Magic definition of all other variables and things */
1483 I2C_CLIENT_INSMOD;
1484
1485 static struct i2c_driver wm8990_i2c_driver;
1486 static struct i2c_client client_template;
1487
1488 static int wm8990_codec_probe(struct i2c_adapter *adap, int addr, int kind)
1489 {
1490         struct snd_soc_device *socdev = wm8990_socdev;
1491         struct wm8990_setup_data *setup = socdev->codec_data;
1492         struct snd_soc_codec *codec = socdev->codec;
1493         struct i2c_client *i2c;
1494         int ret;
1495
1496         if (addr != setup->i2c_address)
1497                 return -ENODEV;
1498
1499         client_template.adapter = adap;
1500         client_template.addr = addr;
1501
1502         i2c =  kmemdup(&client_template, sizeof(client_template), GFP_KERNEL);
1503         if (i2c == NULL)
1504                 return -ENOMEM;
1505
1506         i2c_set_clientdata(i2c, codec);
1507         codec->control_data = i2c;
1508
1509         ret = i2c_attach_client(i2c);
1510         if (ret < 0) {
1511                 pr_err("failed to attach codec at addr %x\n", addr);
1512                 goto err;
1513         }
1514
1515         ret = wm8990_init(socdev);
1516         if (ret < 0) {
1517                 pr_err("failed to initialise WM8990\n");
1518                 goto err;
1519         }
1520         return ret;
1521
1522 err:
1523         kfree(i2c);
1524         return ret;
1525 }
1526
1527 static int wm8990_i2c_detach(struct i2c_client *client)
1528 {
1529         struct snd_soc_codec *codec = i2c_get_clientdata(client);
1530         i2c_detach_client(client);
1531         kfree(codec->reg_cache);
1532         kfree(client);
1533         return 0;
1534 }
1535
1536 static int wm8990_i2c_attach(struct i2c_adapter *adap)
1537 {
1538         return i2c_probe(adap, &addr_data, wm8990_codec_probe);
1539 }
1540
1541 static struct i2c_driver wm8990_i2c_driver = {
1542         .driver = {
1543                 .name = "WM8990 I2C Codec",
1544                 .owner = THIS_MODULE,
1545         },
1546         .attach_adapter = wm8990_i2c_attach,
1547         .detach_client =  wm8990_i2c_detach,
1548         .command =        NULL,
1549 };
1550
1551 static struct i2c_client client_template = {
1552         .name =   "WM8990",
1553         .driver = &wm8990_i2c_driver,
1554 };
1555 #endif
1556
1557 static int wm8990_probe(struct platform_device *pdev)
1558 {
1559         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1560         struct wm8990_setup_data *setup;
1561         struct snd_soc_codec *codec;
1562         struct wm8990_priv *wm8990;
1563         int ret = 0;
1564
1565         pr_info("WM8990 Audio Codec %s\n", WM8990_VERSION);
1566
1567         setup = socdev->codec_data;
1568         codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1569         if (codec == NULL)
1570                 return -ENOMEM;
1571
1572         wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
1573         if (wm8990 == NULL) {
1574                 kfree(codec);
1575                 return -ENOMEM;
1576         }
1577
1578         codec->private_data = wm8990;
1579         socdev->codec = codec;
1580         mutex_init(&codec->mutex);
1581         INIT_LIST_HEAD(&codec->dapm_widgets);
1582         INIT_LIST_HEAD(&codec->dapm_paths);
1583         wm8990_socdev = socdev;
1584
1585 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1586         if (setup->i2c_address) {
1587                 normal_i2c[0] = setup->i2c_address;
1588                 codec->hw_write = (hw_write_t)i2c_master_send;
1589                 ret = i2c_add_driver(&wm8990_i2c_driver);
1590                 if (ret != 0)
1591                         printk(KERN_ERR "can't add i2c driver");
1592         }
1593 #else
1594                 /* Add other interfaces here */
1595 #endif
1596
1597         if (ret != 0) {
1598                 kfree(codec->private_data);
1599                 kfree(codec);
1600         }
1601         return ret;
1602 }
1603
1604 /* power down chip */
1605 static int wm8990_remove(struct platform_device *pdev)
1606 {
1607         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1608         struct snd_soc_codec *codec = socdev->codec;
1609
1610         if (codec->control_data)
1611                 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1612         snd_soc_free_pcms(socdev);
1613         snd_soc_dapm_free(socdev);
1614 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1615         i2c_del_driver(&wm8990_i2c_driver);
1616 #endif
1617         kfree(codec->private_data);
1618         kfree(codec);
1619
1620         return 0;
1621 }
1622
1623 struct snd_soc_codec_device soc_codec_dev_wm8990 = {
1624         .probe =        wm8990_probe,
1625         .remove =       wm8990_remove,
1626         .suspend =      wm8990_suspend,
1627         .resume =       wm8990_resume,
1628 };
1629 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990);
1630
1631 MODULE_DESCRIPTION("ASoC WM8990 driver");
1632 MODULE_AUTHOR("Liam Girdwood");
1633 MODULE_LICENSE("GPL");