Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / arch / arm / mach-s3c2410 / s3c2412-clock.c
1 /* linux/arch/arm/mach-s3c2410/s3c2412-clock.c
2  *
3  * Copyright (c) 2006 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * S3C2412,S3C2413 Clock control support
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21 */
22
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/sysdev.h>
30 #include <linux/clk.h>
31 #include <linux/mutex.h>
32 #include <linux/delay.h>
33
34 #include <asm/hardware.h>
35 #include <asm/io.h>
36
37 #include <asm/arch/regs-clock.h>
38 #include <asm/arch/regs-gpio.h>
39
40 #include "clock.h"
41 #include "cpu.h"
42
43 /* We currently have to assume that the system is running
44  * from the XTPll input, and that all ***REFCLKs are being
45  * fed from it, as we cannot read the state of OM[4] from
46  * software.
47  *
48  * It would be possible for each board initialisation to
49  * set the correct muxing at initialisation
50 */
51
52 int s3c2412_clkcon_enable(struct clk *clk, int enable)
53 {
54         unsigned int clocks = clk->ctrlbit;
55         unsigned long clkcon;
56
57         clkcon = __raw_readl(S3C2410_CLKCON);
58
59         if (enable)
60                 clkcon |= clocks;
61         else
62                 clkcon &= ~clocks;
63
64         __raw_writel(clkcon, S3C2410_CLKCON);
65
66         return 0;
67 }
68
69 static int s3c2412_upll_enable(struct clk *clk, int enable)
70 {
71         unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
72         unsigned long orig = upllcon;
73
74         if (!enable)
75                 upllcon |= S3C2412_PLLCON_OFF;
76         else
77                 upllcon &= ~S3C2412_PLLCON_OFF;
78
79         __raw_writel(upllcon, S3C2410_UPLLCON);
80
81         /* allow ~150uS for the PLL to settle and lock */
82
83         if (enable && (orig & S3C2412_PLLCON_OFF))
84                 udelay(150);
85
86         return 0;
87 }
88
89 /* clock selections */
90
91 /* CPU EXTCLK input */
92 static struct clk clk_ext = {
93         .name           = "extclk",
94         .id             = -1,
95 };
96
97 static struct clk clk_erefclk = {
98         .name           = "erefclk",
99         .id             = -1,
100 };
101
102 static struct clk clk_urefclk = {
103         .name           = "urefclk",
104         .id             = -1,
105 };
106
107 static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
108 {
109         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
110
111         if (parent == &clk_urefclk)
112                 clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
113         else if (parent == &clk_upll)
114                 clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
115         else
116                 return -EINVAL;
117
118         clk->parent = parent;
119
120         __raw_writel(clksrc, S3C2412_CLKSRC);
121         return 0;
122 }
123
124 static struct clk clk_usysclk = {
125         .name           = "usysclk",
126         .id             = -1,
127         .parent         = &clk_xtal,
128         .set_parent     = s3c2412_setparent_usysclk,
129 };
130
131 static struct clk clk_mrefclk = {
132         .name           = "mrefclk",
133         .parent         = &clk_xtal,
134         .id             = -1,
135 };
136
137 static struct clk clk_mdivclk = {
138         .name           = "mdivclk",
139         .parent         = &clk_xtal,
140         .id             = -1,
141 };
142
143 static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
144 {
145         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
146
147         if (parent == &clk_usysclk)
148                 clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
149         else if (parent == &clk_h)
150                 clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
151         else
152                 return -EINVAL;
153
154         clk->parent = parent;
155
156         __raw_writel(clksrc, S3C2412_CLKSRC);
157         return 0;
158 }
159
160 static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
161                                               unsigned long rate)
162 {
163         unsigned long parent_rate = clk_get_rate(clk->parent);
164         int div;
165
166         if (rate > parent_rate)
167                 return parent_rate;
168
169         div = parent_rate / rate;
170         if (div > 2)
171                 div = 2;
172
173         return parent_rate / div;
174 }
175
176 static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
177 {
178         unsigned long parent_rate = clk_get_rate(clk->parent);
179         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
180
181         return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
182 }
183
184 static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
185 {
186         unsigned long parent_rate = clk_get_rate(clk->parent);
187         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
188
189         rate = s3c2412_roundrate_usbsrc(clk, rate);
190
191         if ((parent_rate / rate) == 2)
192                 clkdivn |= S3C2412_CLKDIVN_USB48DIV;
193         else
194                 clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
195
196         __raw_writel(clkdivn, S3C2410_CLKDIVN);
197         return 0;
198 }
199
200 static struct clk clk_usbsrc = {
201         .name           = "usbsrc",
202         .id             = -1,
203         .get_rate       = s3c2412_getrate_usbsrc,
204         .set_rate       = s3c2412_setrate_usbsrc,
205         .round_rate     = s3c2412_roundrate_usbsrc,
206         .set_parent     = s3c2412_setparent_usbsrc,
207 };
208
209 static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
210 {
211         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
212
213         if (parent == &clk_mdivclk)
214                 clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
215         else if (parent == &clk_upll)
216                 clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
217         else
218                 return -EINVAL;
219
220         clk->parent = parent;
221
222         __raw_writel(clksrc, S3C2412_CLKSRC);
223         return 0;
224 }
225
226 static struct clk clk_msysclk = {
227         .name           = "msysclk",
228         .id             = -1,
229         .set_parent     = s3c2412_setparent_msysclk,
230 };
231
232 /* these next clocks have an divider immediately after them,
233  * so we can register them with their divider and leave out the
234  * intermediate clock stage
235 */
236 static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
237                                               unsigned long rate)
238 {
239         unsigned long parent_rate = clk_get_rate(clk->parent);
240         int div;
241
242         if (rate > parent_rate)
243                 return parent_rate;
244
245         /* note, we remove the +/- 1 calculations as they cancel out */
246
247         div = (rate / parent_rate);
248
249         if (div < 1)
250                 div = 1;
251         else if (div > 16)
252                 div = 16;
253
254         return parent_rate / div;
255 }
256
257 static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
258 {
259         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
260
261         if (parent == &clk_erefclk)
262                 clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
263         else if (parent == &clk_mpll)
264                 clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
265         else
266                 return -EINVAL;
267
268         clk->parent = parent;
269
270         __raw_writel(clksrc, S3C2412_CLKSRC);
271         return 0;
272 }
273
274 static unsigned long s3c2412_getrate_uart(struct clk *clk)
275 {
276         unsigned long parent_rate = clk_get_rate(clk->parent);
277         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
278
279         div &= S3C2412_CLKDIVN_UARTDIV_MASK;
280         div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
281
282         return parent_rate / (div + 1);
283 }
284
285 static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
286 {
287         unsigned long parent_rate = clk_get_rate(clk->parent);
288         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
289
290         rate = s3c2412_roundrate_clksrc(clk, rate);
291
292         clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
293         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
294
295         __raw_writel(clkdivn, S3C2410_CLKDIVN);
296         return 0;
297 }
298
299 static struct clk clk_uart = {
300         .name           = "uartclk",
301         .id             = -1,
302         .get_rate       = s3c2412_getrate_uart,
303         .set_rate       = s3c2412_setrate_uart,
304         .set_parent     = s3c2412_setparent_uart,
305         .round_rate     = s3c2412_roundrate_clksrc,
306 };
307
308 static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
309 {
310         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
311
312         if (parent == &clk_erefclk)
313                 clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
314         else if (parent == &clk_mpll)
315                 clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
316         else
317                 return -EINVAL;
318
319         clk->parent = parent;
320
321         __raw_writel(clksrc, S3C2412_CLKSRC);
322         return 0;
323 }
324
325 static unsigned long s3c2412_getrate_i2s(struct clk *clk)
326 {
327         unsigned long parent_rate = clk_get_rate(clk->parent);
328         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
329
330         div &= S3C2412_CLKDIVN_I2SDIV_MASK;
331         div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
332
333         return parent_rate / (div + 1);
334 }
335
336 static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
337 {
338         unsigned long parent_rate = clk_get_rate(clk->parent);
339         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
340
341         rate = s3c2412_roundrate_clksrc(clk, rate);
342
343         clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
344         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
345
346         __raw_writel(clkdivn, S3C2410_CLKDIVN);
347         return 0;
348 }
349
350 static struct clk clk_i2s = {
351         .name           = "i2sclk",
352         .id             = -1,
353         .get_rate       = s3c2412_getrate_i2s,
354         .set_rate       = s3c2412_setrate_i2s,
355         .set_parent     = s3c2412_setparent_i2s,
356         .round_rate     = s3c2412_roundrate_clksrc,
357 };
358
359 static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
360 {
361         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
362
363         if (parent == &clk_usysclk)
364                 clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
365         else if (parent == &clk_h)
366                 clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
367         else
368                 return -EINVAL;
369
370         clk->parent = parent;
371
372         __raw_writel(clksrc, S3C2412_CLKSRC);
373         return 0;
374 }
375 static unsigned long s3c2412_getrate_cam(struct clk *clk)
376 {
377         unsigned long parent_rate = clk_get_rate(clk->parent);
378         unsigned long div = __raw_readl(S3C2410_CLKDIVN);
379
380         div &= S3C2412_CLKDIVN_CAMDIV_MASK;
381         div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
382
383         return parent_rate / (div + 1);
384 }
385
386 static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
387 {
388         unsigned long parent_rate = clk_get_rate(clk->parent);
389         unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
390
391         rate = s3c2412_roundrate_clksrc(clk, rate);
392
393         clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
394         clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
395
396         __raw_writel(clkdivn, S3C2410_CLKDIVN);
397         return 0;
398 }
399
400 static struct clk clk_cam = {
401         .name           = "camif-upll", /* same as 2440 name */
402         .id             = -1,
403         .get_rate       = s3c2412_getrate_cam,
404         .set_rate       = s3c2412_setrate_cam,
405         .set_parent     = s3c2412_setparent_cam,
406         .round_rate     = s3c2412_roundrate_clksrc,
407 };
408
409 /* standard clock definitions */
410
411 static struct clk init_clocks_disable[] = {
412         {
413                 .name           = "nand",
414                 .id             = -1,
415                 .parent         = &clk_h,
416                 .enable         = s3c2412_clkcon_enable,
417                 .ctrlbit        = S3C2412_CLKCON_NAND,
418         }, {
419                 .name           = "sdi",
420                 .id             = -1,
421                 .parent         = &clk_p,
422                 .enable         = s3c2412_clkcon_enable,
423                 .ctrlbit        = S3C2412_CLKCON_SDI,
424         }, {
425                 .name           = "adc",
426                 .id             = -1,
427                 .parent         = &clk_p,
428                 .enable         = s3c2412_clkcon_enable,
429                 .ctrlbit        = S3C2412_CLKCON_ADC,
430         }, {
431                 .name           = "i2c",
432                 .id             = -1,
433                 .parent         = &clk_p,
434                 .enable         = s3c2412_clkcon_enable,
435                 .ctrlbit        = S3C2412_CLKCON_IIC,
436         }, {
437                 .name           = "iis",
438                 .id             = -1,
439                 .parent         = &clk_p,
440                 .enable         = s3c2412_clkcon_enable,
441                 .ctrlbit        = S3C2412_CLKCON_IIS,
442         }, {
443                 .name           = "spi",
444                 .id             = -1,
445                 .parent         = &clk_p,
446                 .enable         = s3c2412_clkcon_enable,
447                 .ctrlbit        = S3C2412_CLKCON_SPI,
448         }
449 };
450
451 static struct clk init_clocks[] = {
452         {
453                 .name           = "dma",
454                 .id             = 0,
455                 .parent         = &clk_h,
456                 .enable         = s3c2412_clkcon_enable,
457                 .ctrlbit        = S3C2412_CLKCON_DMA0,
458         }, {
459                 .name           = "dma",
460                 .id             = 1,
461                 .parent         = &clk_h,
462                 .enable         = s3c2412_clkcon_enable,
463                 .ctrlbit        = S3C2412_CLKCON_DMA1,
464         }, {
465                 .name           = "dma",
466                 .id             = 2,
467                 .parent         = &clk_h,
468                 .enable         = s3c2412_clkcon_enable,
469                 .ctrlbit        = S3C2412_CLKCON_DMA2,
470         }, {
471                 .name           = "dma",
472                 .id             = 3,
473                 .parent         = &clk_h,
474                 .enable         = s3c2412_clkcon_enable,
475                 .ctrlbit        = S3C2412_CLKCON_DMA3,
476         }, {
477                 .name           = "lcd",
478                 .id             = -1,
479                 .parent         = &clk_h,
480                 .enable         = s3c2412_clkcon_enable,
481                 .ctrlbit        = S3C2412_CLKCON_LCDC,
482         }, {
483                 .name           = "gpio",
484                 .id             = -1,
485                 .parent         = &clk_p,
486                 .enable         = s3c2412_clkcon_enable,
487                 .ctrlbit        = S3C2412_CLKCON_GPIO,
488         }, {
489                 .name           = "usb-host",
490                 .id             = -1,
491                 .parent         = &clk_h,
492                 .enable         = s3c2412_clkcon_enable,
493                 .ctrlbit        = S3C2412_CLKCON_USBH,
494         }, {
495                 .name           = "usb-device",
496                 .id             = -1,
497                 .parent         = &clk_h,
498                 .enable         = s3c2412_clkcon_enable,
499                 .ctrlbit        = S3C2412_CLKCON_USBD,
500         }, {
501                 .name           = "timers",
502                 .id             = -1,
503                 .parent         = &clk_p,
504                 .enable         = s3c2412_clkcon_enable,
505                 .ctrlbit        = S3C2412_CLKCON_PWMT,
506         }, {
507                 .name           = "uart",
508                 .id             = 0,
509                 .parent         = &clk_p,
510                 .enable         = s3c2412_clkcon_enable,
511                 .ctrlbit        = S3C2412_CLKCON_UART0,
512         }, {
513                 .name           = "uart",
514                 .id             = 1,
515                 .parent         = &clk_p,
516                 .enable         = s3c2412_clkcon_enable,
517                 .ctrlbit        = S3C2412_CLKCON_UART1,
518         }, {
519                 .name           = "uart",
520                 .id             = 2,
521                 .parent         = &clk_p,
522                 .enable         = s3c2412_clkcon_enable,
523                 .ctrlbit        = S3C2412_CLKCON_UART2,
524         }, {
525                 .name           = "rtc",
526                 .id             = -1,
527                 .parent         = &clk_p,
528                 .enable         = s3c2412_clkcon_enable,
529                 .ctrlbit        = S3C2412_CLKCON_RTC,
530         }, {
531                 .name           = "watchdog",
532                 .id             = -1,
533                 .parent         = &clk_p,
534                 .ctrlbit        = 0,
535         }, {
536                 .name           = "usb-bus-gadget",
537                 .id             = -1,
538                 .parent         = &clk_usb_bus,
539                 .enable         = s3c2412_clkcon_enable,
540                 .ctrlbit        = S3C2412_CLKCON_USB_DEV48,
541         }, {
542                 .name           = "usb-bus-host",
543                 .id             = -1,
544                 .parent         = &clk_usb_bus,
545                 .enable         = s3c2412_clkcon_enable,
546                 .ctrlbit        = S3C2412_CLKCON_USB_HOST48,
547         }
548 };
549
550 /* clocks to add where we need to check their parentage */
551
552 struct clk_init {
553         struct clk      *clk;
554         unsigned int     bit;
555         struct clk      *src_0;
556         struct clk      *src_1;
557 };
558
559 struct clk_init clks_src[] __initdata = {
560         {
561                 .clk    = &clk_usysclk,
562                 .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
563                 .src_0  = &clk_urefclk,
564                 .src_1  = &clk_upll,
565         }, {
566                 .clk    = &clk_i2s,
567                 .bit    = S3C2412_CLKSRC_I2SCLK_MPLL,
568                 .src_0  = &clk_erefclk,
569                 .src_1  = &clk_mpll,
570         }, {
571                 .clk    = &clk_cam,
572                 .bit    = S3C2412_CLKSRC_CAMCLK_HCLK,
573                 .src_0  = &clk_usysclk,
574                 .src_1  = &clk_h,
575         }, {
576                 .clk    = &clk_msysclk,
577                 .bit    = S3C2412_CLKSRC_MSYSCLK_MPLL,
578                 .src_0  = &clk_mdivclk,
579                 .src_1  = &clk_mpll,
580         }, {
581                 .clk    = &clk_uart,
582                 .bit    = S3C2412_CLKSRC_UARTCLK_MPLL,
583                 .src_0  = &clk_erefclk,
584                 .src_1  = &clk_mpll,
585         }, {
586                 .clk    = &clk_usbsrc,
587                 .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
588                 .src_0  = &clk_usysclk,
589                 .src_1  = &clk_h,
590         },
591 };
592
593 /* s3c2412_clk_initparents
594  *
595  * Initialise the parents for the clocks that we get at start-time
596 */
597
598 static void __init s3c2412_clk_initparents(void)
599 {
600         unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
601         struct clk_init *cip = clks_src;
602         struct clk *src;
603         int ptr;
604         int ret;
605
606         for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
607                 ret = s3c24xx_register_clock(cip->clk);
608                 if (ret < 0) {
609                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
610                                cip->clk->name, ret);
611                 }
612
613                 src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
614
615                 printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
616                 clk_set_parent(cip->clk, src);
617         }
618 }
619
620 /* clocks to add straight away */
621
622 struct clk *clks[] __initdata = {
623         &clk_ext,
624         &clk_usb_bus,
625         &clk_erefclk,
626         &clk_urefclk,
627         &clk_mrefclk,
628 };
629
630 int __init s3c2412_baseclk_add(void)
631 {
632         unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
633         struct clk *clkp;
634         int ret;
635         int ptr;
636
637         clk_upll.enable = s3c2412_upll_enable;
638         clk_usb_bus.parent = &clk_usbsrc;
639         clk_usb_bus.rate = 0x0;
640
641         s3c2412_clk_initparents();
642
643         for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
644                 clkp = clks[ptr];
645
646                 ret = s3c24xx_register_clock(clkp);
647                 if (ret < 0) {
648                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
649                                clkp->name, ret);
650                 }
651         }
652
653         /* ensure usb bus clock is within correct rate of 48MHz */
654
655         if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
656                 printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
657
658                 /* for the moment, let's use the UPLL, and see if we can
659                  * get 48MHz */
660
661                 clk_set_parent(&clk_usysclk, &clk_upll);
662                 clk_set_parent(&clk_usbsrc, &clk_usysclk);
663                 clk_set_rate(&clk_usbsrc, 48*1000*1000);
664         }
665
666         printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
667                (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
668                print_mhz(clk_get_rate(&clk_upll)),
669                print_mhz(clk_get_rate(&clk_usb_bus)));
670
671         /* register clocks from clock array */
672
673         clkp = init_clocks;
674         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
675                 /* ensure that we note the clock state */
676
677                 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
678
679                 ret = s3c24xx_register_clock(clkp);
680                 if (ret < 0) {
681                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
682                                clkp->name, ret);
683                 }
684         }
685
686         /* We must be careful disabling the clocks we are not intending to
687          * be using at boot time, as subsytems such as the LCD which do
688          * their own DMA requests to the bus can cause the system to lockup
689          * if they where in the middle of requesting bus access.
690          *
691          * Disabling the LCD clock if the LCD is active is very dangerous,
692          * and therefore the bootloader should be careful to not enable
693          * the LCD clock if it is not needed.
694         */
695
696         /* install (and disable) the clocks we do not need immediately */
697
698         clkp = init_clocks_disable;
699         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
700
701                 ret = s3c24xx_register_clock(clkp);
702                 if (ret < 0) {
703                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
704                                clkp->name, ret);
705                 }
706
707                 s3c2412_clkcon_enable(clkp, 0);
708         }
709
710         return 0;
711 }