Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
[linux-2.6] / arch / x86_64 / kernel / pci-calgary.c
1 /*
2  * Derived from arch/powerpc/kernel/iommu.c
3  *
4  * Copyright (C) IBM Corporation, 2006
5  *
6  * Author: Jon Mason <jdmason@us.ibm.com>
7  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
8
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
22  */
23
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/mm.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <linux/pci_ids.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <asm/proto.h>
39 #include <asm/calgary.h>
40 #include <asm/tce.h>
41 #include <asm/pci-direct.h>
42 #include <asm/system.h>
43 #include <asm/dma.h>
44
45 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
46 #define PCI_VENDOR_DEVICE_ID_CALGARY \
47         (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
48
49 /* we need these for register space address calculation */
50 #define START_ADDRESS           0xfe000000
51 #define CHASSIS_BASE            0
52 #define ONE_BASED_CHASSIS_NUM   1
53
54 /* register offsets inside the host bridge space */
55 #define PHB_CSR_OFFSET          0x0110
56 #define PHB_PLSSR_OFFSET        0x0120
57 #define PHB_CONFIG_RW_OFFSET    0x0160
58 #define PHB_IOBASE_BAR_LOW      0x0170
59 #define PHB_IOBASE_BAR_HIGH     0x0180
60 #define PHB_MEM_1_LOW           0x0190
61 #define PHB_MEM_1_HIGH          0x01A0
62 #define PHB_IO_ADDR_SIZE        0x01B0
63 #define PHB_MEM_1_SIZE          0x01C0
64 #define PHB_MEM_ST_OFFSET       0x01D0
65 #define PHB_AER_OFFSET          0x0200
66 #define PHB_CONFIG_0_HIGH       0x0220
67 #define PHB_CONFIG_0_LOW        0x0230
68 #define PHB_CONFIG_0_END        0x0240
69 #define PHB_MEM_2_LOW           0x02B0
70 #define PHB_MEM_2_HIGH          0x02C0
71 #define PHB_MEM_2_SIZE_HIGH     0x02D0
72 #define PHB_MEM_2_SIZE_LOW      0x02E0
73 #define PHB_DOSHOLE_OFFSET      0x08E0
74
75 /* PHB_CONFIG_RW */
76 #define PHB_TCE_ENABLE          0x20000000
77 #define PHB_SLOT_DISABLE        0x1C000000
78 #define PHB_DAC_DISABLE         0x01000000
79 #define PHB_MEM2_ENABLE         0x00400000
80 #define PHB_MCSR_ENABLE         0x00100000
81 /* TAR (Table Address Register) */
82 #define TAR_SW_BITS             0x0000ffffffff800fUL
83 #define TAR_VALID               0x0000000000000008UL
84 /* CSR (Channel/DMA Status Register) */
85 #define CSR_AGENT_MASK          0xffe0ffff
86
87 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
88 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
89 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
90 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
91 #define PHBS_PER_CALGARY        4
92
93 /* register offsets in Calgary's internal register space */
94 static const unsigned long tar_offsets[] = {
95         0x0580 /* TAR0 */,
96         0x0588 /* TAR1 */,
97         0x0590 /* TAR2 */,
98         0x0598 /* TAR3 */
99 };
100
101 static const unsigned long split_queue_offsets[] = {
102         0x4870 /* SPLIT QUEUE 0 */,
103         0x5870 /* SPLIT QUEUE 1 */,
104         0x6870 /* SPLIT QUEUE 2 */,
105         0x7870 /* SPLIT QUEUE 3 */
106 };
107
108 static const unsigned long phb_offsets[] = {
109         0x8000 /* PHB0 */,
110         0x9000 /* PHB1 */,
111         0xA000 /* PHB2 */,
112         0xB000 /* PHB3 */
113 };
114
115 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
116 static int translate_empty_slots __read_mostly = 0;
117 static int calgary_detected __read_mostly = 0;
118
119 struct calgary_bus_info {
120         void *tce_space;
121         unsigned char translation_disabled;
122         signed char phbid;
123 };
124
125 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
126
127 static void tce_cache_blast(struct iommu_table *tbl);
128
129 /* enable this to stress test the chip's TCE cache */
130 #ifdef CONFIG_IOMMU_DEBUG
131 int debugging __read_mostly = 1;
132
133 static inline unsigned long verify_bit_range(unsigned long* bitmap,
134         int expected, unsigned long start, unsigned long end)
135 {
136         unsigned long idx = start;
137
138         BUG_ON(start >= end);
139
140         while (idx < end) {
141                 if (!!test_bit(idx, bitmap) != expected)
142                         return idx;
143                 ++idx;
144         }
145
146         /* all bits have the expected value */
147         return ~0UL;
148 }
149 #else /* debugging is disabled */
150 int debugging __read_mostly = 0;
151
152 static inline unsigned long verify_bit_range(unsigned long* bitmap,
153         int expected, unsigned long start, unsigned long end)
154 {
155         return ~0UL;
156 }
157 #endif /* CONFIG_IOMMU_DEBUG */
158
159 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
160 {
161         unsigned int npages;
162
163         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
164         npages >>= PAGE_SHIFT;
165
166         return npages;
167 }
168
169 static inline int translate_phb(struct pci_dev* dev)
170 {
171         int disabled = bus_info[dev->bus->number].translation_disabled;
172         return !disabled;
173 }
174
175 static void iommu_range_reserve(struct iommu_table *tbl,
176         unsigned long start_addr, unsigned int npages)
177 {
178         unsigned long index;
179         unsigned long end;
180         unsigned long badbit;
181
182         index = start_addr >> PAGE_SHIFT;
183
184         /* bail out if we're asked to reserve a region we don't cover */
185         if (index >= tbl->it_size)
186                 return;
187
188         end = index + npages;
189         if (end > tbl->it_size) /* don't go off the table */
190                 end = tbl->it_size;
191
192         badbit = verify_bit_range(tbl->it_map, 0, index, end);
193         if (badbit != ~0UL) {
194                 if (printk_ratelimit())
195                         printk(KERN_ERR "Calgary: entry already allocated at "
196                                "0x%lx tbl %p dma 0x%lx npages %u\n",
197                                badbit, tbl, start_addr, npages);
198         }
199
200         set_bit_string(tbl->it_map, index, npages);
201 }
202
203 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
204         unsigned int npages)
205 {
206         unsigned long offset;
207
208         BUG_ON(npages == 0);
209
210         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
211                                        tbl->it_size, npages);
212         if (offset == ~0UL) {
213                 tce_cache_blast(tbl);
214                 offset = find_next_zero_string(tbl->it_map, 0,
215                                                tbl->it_size, npages);
216                 if (offset == ~0UL) {
217                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
218                         if (panic_on_overflow)
219                                 panic("Calgary: fix the allocator.\n");
220                         else
221                                 return bad_dma_address;
222                 }
223         }
224
225         set_bit_string(tbl->it_map, offset, npages);
226         tbl->it_hint = offset + npages;
227         BUG_ON(tbl->it_hint > tbl->it_size);
228
229         return offset;
230 }
231
232 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
233         unsigned int npages, int direction)
234 {
235         unsigned long entry, flags;
236         dma_addr_t ret = bad_dma_address;
237
238         spin_lock_irqsave(&tbl->it_lock, flags);
239
240         entry = iommu_range_alloc(tbl, npages);
241
242         if (unlikely(entry == bad_dma_address))
243                 goto error;
244
245         /* set the return dma address */
246         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
247
248         /* put the TCEs in the HW table */
249         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
250                   direction);
251
252         spin_unlock_irqrestore(&tbl->it_lock, flags);
253
254         return ret;
255
256 error:
257         spin_unlock_irqrestore(&tbl->it_lock, flags);
258         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
259                "iommu %p\n", npages, tbl);
260         return bad_dma_address;
261 }
262
263 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
264         unsigned int npages)
265 {
266         unsigned long entry;
267         unsigned long badbit;
268
269         entry = dma_addr >> PAGE_SHIFT;
270
271         BUG_ON(entry + npages > tbl->it_size);
272
273         tce_free(tbl, entry, npages);
274
275         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
276         if (badbit != ~0UL) {
277                 if (printk_ratelimit())
278                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
279                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
280                                badbit, tbl, dma_addr, entry, npages);
281         }
282
283         __clear_bit_string(tbl->it_map, entry, npages);
284 }
285
286 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
287         unsigned int npages)
288 {
289         unsigned long flags;
290
291         spin_lock_irqsave(&tbl->it_lock, flags);
292
293         __iommu_free(tbl, dma_addr, npages);
294
295         spin_unlock_irqrestore(&tbl->it_lock, flags);
296 }
297
298 static void __calgary_unmap_sg(struct iommu_table *tbl,
299         struct scatterlist *sglist, int nelems, int direction)
300 {
301         while (nelems--) {
302                 unsigned int npages;
303                 dma_addr_t dma = sglist->dma_address;
304                 unsigned int dmalen = sglist->dma_length;
305
306                 if (dmalen == 0)
307                         break;
308
309                 npages = num_dma_pages(dma, dmalen);
310                 __iommu_free(tbl, dma, npages);
311                 sglist++;
312         }
313 }
314
315 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
316                       int nelems, int direction)
317 {
318         unsigned long flags;
319         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
320
321         if (!translate_phb(to_pci_dev(dev)))
322                 return;
323
324         spin_lock_irqsave(&tbl->it_lock, flags);
325
326         __calgary_unmap_sg(tbl, sglist, nelems, direction);
327
328         spin_unlock_irqrestore(&tbl->it_lock, flags);
329 }
330
331 static int calgary_nontranslate_map_sg(struct device* dev,
332         struct scatterlist *sg, int nelems, int direction)
333 {
334         int i;
335
336         for (i = 0; i < nelems; i++ ) {
337                 struct scatterlist *s = &sg[i];
338                 BUG_ON(!s->page);
339                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
340                 s->dma_length = s->length;
341         }
342         return nelems;
343 }
344
345 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
346         int nelems, int direction)
347 {
348         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
349         unsigned long flags;
350         unsigned long vaddr;
351         unsigned int npages;
352         unsigned long entry;
353         int i;
354
355         if (!translate_phb(to_pci_dev(dev)))
356                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
357
358         spin_lock_irqsave(&tbl->it_lock, flags);
359
360         for (i = 0; i < nelems; i++ ) {
361                 struct scatterlist *s = &sg[i];
362                 BUG_ON(!s->page);
363
364                 vaddr = (unsigned long)page_address(s->page) + s->offset;
365                 npages = num_dma_pages(vaddr, s->length);
366
367                 entry = iommu_range_alloc(tbl, npages);
368                 if (entry == bad_dma_address) {
369                         /* makes sure unmap knows to stop */
370                         s->dma_length = 0;
371                         goto error;
372                 }
373
374                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
375
376                 /* insert into HW table */
377                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
378                           direction);
379
380                 s->dma_length = s->length;
381         }
382
383         spin_unlock_irqrestore(&tbl->it_lock, flags);
384
385         return nelems;
386 error:
387         __calgary_unmap_sg(tbl, sg, nelems, direction);
388         for (i = 0; i < nelems; i++) {
389                 sg[i].dma_address = bad_dma_address;
390                 sg[i].dma_length = 0;
391         }
392         spin_unlock_irqrestore(&tbl->it_lock, flags);
393         return 0;
394 }
395
396 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
397         size_t size, int direction)
398 {
399         dma_addr_t dma_handle = bad_dma_address;
400         unsigned long uaddr;
401         unsigned int npages;
402         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
403
404         uaddr = (unsigned long)vaddr;
405         npages = num_dma_pages(uaddr, size);
406
407         if (translate_phb(to_pci_dev(dev)))
408                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
409         else
410                 dma_handle = virt_to_bus(vaddr);
411
412         return dma_handle;
413 }
414
415 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
416         size_t size, int direction)
417 {
418         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
419         unsigned int npages;
420
421         if (!translate_phb(to_pci_dev(dev)))
422                 return;
423
424         npages = num_dma_pages(dma_handle, size);
425         iommu_free(tbl, dma_handle, npages);
426 }
427
428 void* calgary_alloc_coherent(struct device *dev, size_t size,
429         dma_addr_t *dma_handle, gfp_t flag)
430 {
431         void *ret = NULL;
432         dma_addr_t mapping;
433         unsigned int npages, order;
434         struct iommu_table *tbl;
435
436         tbl = to_pci_dev(dev)->bus->self->sysdata;
437
438         size = PAGE_ALIGN(size); /* size rounded up to full pages */
439         npages = size >> PAGE_SHIFT;
440         order = get_order(size);
441
442         /* alloc enough pages (and possibly more) */
443         ret = (void *)__get_free_pages(flag, order);
444         if (!ret)
445                 goto error;
446         memset(ret, 0, size);
447
448         if (translate_phb(to_pci_dev(dev))) {
449                 /* set up tces to cover the allocated range */
450                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
451                 if (mapping == bad_dma_address)
452                         goto free;
453
454                 *dma_handle = mapping;
455         } else /* non translated slot */
456                 *dma_handle = virt_to_bus(ret);
457
458         return ret;
459
460 free:
461         free_pages((unsigned long)ret, get_order(size));
462         ret = NULL;
463 error:
464         return ret;
465 }
466
467 static struct dma_mapping_ops calgary_dma_ops = {
468         .alloc_coherent = calgary_alloc_coherent,
469         .map_single = calgary_map_single,
470         .unmap_single = calgary_unmap_single,
471         .map_sg = calgary_map_sg,
472         .unmap_sg = calgary_unmap_sg,
473 };
474
475 static inline int busno_to_phbid(unsigned char num)
476 {
477         return bus_info[num].phbid;
478 }
479
480 static inline unsigned long split_queue_offset(unsigned char num)
481 {
482         size_t idx = busno_to_phbid(num);
483
484         return split_queue_offsets[idx];
485 }
486
487 static inline unsigned long tar_offset(unsigned char num)
488 {
489         size_t idx = busno_to_phbid(num);
490
491         return tar_offsets[idx];
492 }
493
494 static inline unsigned long phb_offset(unsigned char num)
495 {
496         size_t idx = busno_to_phbid(num);
497
498         return phb_offsets[idx];
499 }
500
501 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
502 {
503         unsigned long target = ((unsigned long)bar) | offset;
504         return (void __iomem*)target;
505 }
506
507 static void tce_cache_blast(struct iommu_table *tbl)
508 {
509         u64 val;
510         u32 aer;
511         int i = 0;
512         void __iomem *bbar = tbl->bbar;
513         void __iomem *target;
514
515         /* disable arbitration on the bus */
516         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
517         aer = readl(target);
518         writel(0, target);
519
520         /* read plssr to ensure it got there */
521         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
522         val = readl(target);
523
524         /* poll split queues until all DMA activity is done */
525         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
526         do {
527                 val = readq(target);
528                 i++;
529         } while ((val & 0xff) != 0xff && i < 100);
530         if (i == 100)
531                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
532                        "continuing anyway\n");
533
534         /* invalidate TCE cache */
535         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
536         writeq(tbl->tar_val, target);
537
538         /* enable arbitration */
539         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
540         writel(aer, target);
541         (void)readl(target); /* flush */
542 }
543
544 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
545         u64 limit)
546 {
547         unsigned int numpages;
548
549         limit = limit | 0xfffff;
550         limit++;
551
552         numpages = ((limit - start) >> PAGE_SHIFT);
553         iommu_range_reserve(dev->sysdata, start, numpages);
554 }
555
556 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
557 {
558         void __iomem *target;
559         u64 low, high, sizelow;
560         u64 start, limit;
561         struct iommu_table *tbl = dev->sysdata;
562         unsigned char busnum = dev->bus->number;
563         void __iomem *bbar = tbl->bbar;
564
565         /* peripheral MEM_1 region */
566         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
567         low = be32_to_cpu(readl(target));
568         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
569         high = be32_to_cpu(readl(target));
570         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
571         sizelow = be32_to_cpu(readl(target));
572
573         start = (high << 32) | low;
574         limit = sizelow;
575
576         calgary_reserve_mem_region(dev, start, limit);
577 }
578
579 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
580 {
581         void __iomem *target;
582         u32 val32;
583         u64 low, high, sizelow, sizehigh;
584         u64 start, limit;
585         struct iommu_table *tbl = dev->sysdata;
586         unsigned char busnum = dev->bus->number;
587         void __iomem *bbar = tbl->bbar;
588
589         /* is it enabled? */
590         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
591         val32 = be32_to_cpu(readl(target));
592         if (!(val32 & PHB_MEM2_ENABLE))
593                 return;
594
595         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
596         low = be32_to_cpu(readl(target));
597         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
598         high = be32_to_cpu(readl(target));
599         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
600         sizelow = be32_to_cpu(readl(target));
601         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
602         sizehigh = be32_to_cpu(readl(target));
603
604         start = (high << 32) | low;
605         limit = (sizehigh << 32) | sizelow;
606
607         calgary_reserve_mem_region(dev, start, limit);
608 }
609
610 /*
611  * some regions of the IO address space do not get translated, so we
612  * must not give devices IO addresses in those regions. The regions
613  * are the 640KB-1MB region and the two PCI peripheral memory holes.
614  * Reserve all of them in the IOMMU bitmap to avoid giving them out
615  * later.
616  */
617 static void __init calgary_reserve_regions(struct pci_dev *dev)
618 {
619         unsigned int npages;
620         void __iomem *bbar;
621         unsigned char busnum;
622         u64 start;
623         struct iommu_table *tbl = dev->sysdata;
624
625         bbar = tbl->bbar;
626         busnum = dev->bus->number;
627
628         /* reserve bad_dma_address in case it's a legal address */
629         iommu_range_reserve(tbl, bad_dma_address, 1);
630
631         /* avoid the BIOS/VGA first 640KB-1MB region */
632         start = (640 * 1024);
633         npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
634         iommu_range_reserve(tbl, start, npages);
635
636         /* reserve the two PCI peripheral memory regions in IO space */
637         calgary_reserve_peripheral_mem_1(dev);
638         calgary_reserve_peripheral_mem_2(dev);
639 }
640
641 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
642 {
643         u64 val64;
644         u64 table_phys;
645         void __iomem *target;
646         int ret;
647         struct iommu_table *tbl;
648
649         /* build TCE tables for each PHB */
650         ret = build_tce_table(dev, bbar);
651         if (ret)
652                 return ret;
653
654         tbl = dev->sysdata;
655         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
656         tce_free(tbl, 0, tbl->it_size);
657
658         calgary_reserve_regions(dev);
659
660         /* set TARs for each PHB */
661         target = calgary_reg(bbar, tar_offset(dev->bus->number));
662         val64 = be64_to_cpu(readq(target));
663
664         /* zero out all TAR bits under sw control */
665         val64 &= ~TAR_SW_BITS;
666
667         tbl = dev->sysdata;
668         table_phys = (u64)__pa(tbl->it_base);
669         val64 |= table_phys;
670
671         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
672         val64 |= (u64) specified_table_size;
673
674         tbl->tar_val = cpu_to_be64(val64);
675         writeq(tbl->tar_val, target);
676         readq(target); /* flush */
677
678         return 0;
679 }
680
681 static void __init calgary_free_bus(struct pci_dev *dev)
682 {
683         u64 val64;
684         struct iommu_table *tbl = dev->sysdata;
685         void __iomem *target;
686         unsigned int bitmapsz;
687
688         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
689         val64 = be64_to_cpu(readq(target));
690         val64 &= ~TAR_SW_BITS;
691         writeq(cpu_to_be64(val64), target);
692         readq(target); /* flush */
693
694         bitmapsz = tbl->it_size / BITS_PER_BYTE;
695         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
696         tbl->it_map = NULL;
697
698         kfree(tbl);
699         dev->sysdata = NULL;
700
701         /* Can't free bootmem allocated memory after system is up :-( */
702         bus_info[dev->bus->number].tce_space = NULL;
703 }
704
705 static void calgary_watchdog(unsigned long data)
706 {
707         struct pci_dev *dev = (struct pci_dev *)data;
708         struct iommu_table *tbl = dev->sysdata;
709         void __iomem *bbar = tbl->bbar;
710         u32 val32;
711         void __iomem *target;
712
713         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
714         val32 = be32_to_cpu(readl(target));
715
716         /* If no error, the agent ID in the CSR is not valid */
717         if (val32 & CSR_AGENT_MASK) {
718                 printk(KERN_EMERG "calgary_watchdog: DMA error on bus %d, "
719                                   "CSR = %#x\n", dev->bus->number, val32);
720                 writel(0, target);
721
722                 /* Disable bus that caused the error */
723                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
724                                            PHB_CONFIG_RW_OFFSET);
725                 val32 = be32_to_cpu(readl(target));
726                 val32 |= PHB_SLOT_DISABLE;
727                 writel(cpu_to_be32(val32), target);
728                 readl(target); /* flush */
729         } else {
730                 /* Reset the timer */
731                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
732         }
733 }
734
735 static void __init calgary_enable_translation(struct pci_dev *dev)
736 {
737         u32 val32;
738         unsigned char busnum;
739         void __iomem *target;
740         void __iomem *bbar;
741         struct iommu_table *tbl;
742
743         busnum = dev->bus->number;
744         tbl = dev->sysdata;
745         bbar = tbl->bbar;
746
747         /* enable TCE in PHB Config Register */
748         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
749         val32 = be32_to_cpu(readl(target));
750         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
751
752         printk(KERN_INFO "Calgary: enabling translation on PHB %d\n", busnum);
753         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
754                "bus.\n");
755
756         writel(cpu_to_be32(val32), target);
757         readl(target); /* flush */
758
759         init_timer(&tbl->watchdog_timer);
760         tbl->watchdog_timer.function = &calgary_watchdog;
761         tbl->watchdog_timer.data = (unsigned long)dev;
762         mod_timer(&tbl->watchdog_timer, jiffies);
763 }
764
765 static void __init calgary_disable_translation(struct pci_dev *dev)
766 {
767         u32 val32;
768         unsigned char busnum;
769         void __iomem *target;
770         void __iomem *bbar;
771         struct iommu_table *tbl;
772
773         busnum = dev->bus->number;
774         tbl = dev->sysdata;
775         bbar = tbl->bbar;
776
777         /* disable TCE in PHB Config Register */
778         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
779         val32 = be32_to_cpu(readl(target));
780         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
781
782         printk(KERN_INFO "Calgary: disabling translation on PHB %d!\n", busnum);
783         writel(cpu_to_be32(val32), target);
784         readl(target); /* flush */
785
786         del_timer_sync(&tbl->watchdog_timer);
787 }
788
789 static inline unsigned int __init locate_register_space(struct pci_dev *dev)
790 {
791         int rionodeid;
792         u32 address;
793
794         rionodeid = (dev->bus->number % 15 > 4) ? 3 : 2;
795         /*
796          * register space address calculation as follows:
797          * FE0MB-8MB*OneBasedChassisNumber+1MB*(RioNodeId-ChassisBase)
798          * ChassisBase is always zero for x366/x260/x460
799          * RioNodeId is 2 for first Calgary, 3 for second Calgary
800          */
801         address = START_ADDRESS -
802                 (0x800000 * (ONE_BASED_CHASSIS_NUM + dev->bus->number / 15)) +
803                 (0x100000) * (rionodeid - CHASSIS_BASE);
804         return address;
805 }
806
807 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
808 {
809         pci_dev_get(dev);
810         dev->sysdata = NULL;
811         dev->bus->self = dev;
812 }
813
814 static int __init calgary_init_one(struct pci_dev *dev)
815 {
816         u32 address;
817         void __iomem *bbar;
818         int ret;
819
820         address = locate_register_space(dev);
821         /* map entire 1MB of Calgary config space */
822         bbar = ioremap_nocache(address, 1024 * 1024);
823         if (!bbar) {
824                 ret = -ENODATA;
825                 goto done;
826         }
827
828         ret = calgary_setup_tar(dev, bbar);
829         if (ret)
830                 goto iounmap;
831
832         pci_dev_get(dev);
833         dev->bus->self = dev;
834         calgary_enable_translation(dev);
835
836         return 0;
837
838 iounmap:
839         iounmap(bbar);
840 done:
841         return ret;
842 }
843
844 static int __init calgary_init(void)
845 {
846         int i, ret = -ENODEV;
847         struct pci_dev *dev = NULL;
848
849         for (i = 0; i < MAX_PHB_BUS_NUM; i++) {
850                 dev = pci_get_device(PCI_VENDOR_ID_IBM,
851                                      PCI_DEVICE_ID_IBM_CALGARY,
852                                      dev);
853                 if (!dev)
854                         break;
855                 if (!translate_phb(dev)) {
856                         calgary_init_one_nontraslated(dev);
857                         continue;
858                 }
859                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
860                         continue;
861
862                 ret = calgary_init_one(dev);
863                 if (ret)
864                         goto error;
865         }
866
867         return ret;
868
869 error:
870         for (i--; i >= 0; i--) {
871                 dev = pci_find_device_reverse(PCI_VENDOR_ID_IBM,
872                                               PCI_DEVICE_ID_IBM_CALGARY,
873                                               dev);
874                 if (!dev)
875                         break;
876                 if (!translate_phb(dev)) {
877                         pci_dev_put(dev);
878                         continue;
879                 }
880                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
881                         continue;
882
883                 calgary_disable_translation(dev);
884                 calgary_free_bus(dev);
885                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
886         }
887
888         return ret;
889 }
890
891 static inline int __init determine_tce_table_size(u64 ram)
892 {
893         int ret;
894
895         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
896                 return specified_table_size;
897
898         /*
899          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
900          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
901          * larger table size has twice as many entries, so shift the
902          * max ram address by 13 to divide by 8K and then look at the
903          * order of the result to choose between 0-7.
904          */
905         ret = get_order(ram >> 13);
906         if (ret > TCE_TABLE_SIZE_8M)
907                 ret = TCE_TABLE_SIZE_8M;
908
909         return ret;
910 }
911
912 void __init detect_calgary(void)
913 {
914         u32 val;
915         int bus;
916         void *tbl;
917         int calgary_found = 0;
918         int phb = -1;
919
920         /*
921          * if the user specified iommu=off or iommu=soft or we found
922          * another HW IOMMU already, bail out.
923          */
924         if (swiotlb || no_iommu || iommu_detected)
925                 return;
926
927         if (!early_pci_allowed())
928                 return;
929
930         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
931
932         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
933                 int dev;
934                 struct calgary_bus_info *info = &bus_info[bus];
935                 info->phbid = -1;
936
937                 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
938                         continue;
939
940                 /*
941                  * There are 4 PHBs per Calgary chip.  Set phb to which phb (0-3)
942                  * it is connected to releative to the clagary chip.
943                  */
944                 phb = (phb + 1) % PHBS_PER_CALGARY;
945
946                 if (info->translation_disabled)
947                         continue;
948
949                 /*
950                  * Scan the slots of the PCI bus to see if there is a device present.
951                  * The parent bus will be the zero-ith device, so start at 1.
952                  */
953                 for (dev = 1; dev < 8; dev++) {
954                         val = read_pci_config(bus, dev, 0, 0);
955                         if (val != 0xffffffff || translate_empty_slots) {
956                                 tbl = alloc_tce_table();
957                                 if (!tbl)
958                                         goto cleanup;
959                                 info->tce_space = tbl;
960                                 info->phbid = phb;
961                                 calgary_found = 1;
962                                 break;
963                         }
964                 }
965         }
966
967         if (calgary_found) {
968                 iommu_detected = 1;
969                 calgary_detected = 1;
970                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
971                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
972                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
973                        debugging ? "enabled" : "disabled");
974         }
975         return;
976
977 cleanup:
978         for (--bus; bus >= 0; --bus) {
979                 struct calgary_bus_info *info = &bus_info[bus];
980
981                 if (info->tce_space)
982                         free_tce_table(info->tce_space);
983         }
984 }
985
986 int __init calgary_iommu_init(void)
987 {
988         int ret;
989
990         if (no_iommu || swiotlb)
991                 return -ENODEV;
992
993         if (!calgary_detected)
994                 return -ENODEV;
995
996         /* ok, we're trying to use Calgary - let's roll */
997         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
998
999         ret = calgary_init();
1000         if (ret) {
1001                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1002                        "falling back to no_iommu\n", ret);
1003                 if (end_pfn > MAX_DMA32_PFN)
1004                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1005                                         "32bit PCI may malfunction.\n");
1006                 return ret;
1007         }
1008
1009         force_iommu = 1;
1010         dma_ops = &calgary_dma_ops;
1011
1012         return 0;
1013 }
1014
1015 static int __init calgary_parse_options(char *p)
1016 {
1017         unsigned int bridge;
1018         size_t len;
1019         char* endp;
1020
1021         while (*p) {
1022                 if (!strncmp(p, "64k", 3))
1023                         specified_table_size = TCE_TABLE_SIZE_64K;
1024                 else if (!strncmp(p, "128k", 4))
1025                         specified_table_size = TCE_TABLE_SIZE_128K;
1026                 else if (!strncmp(p, "256k", 4))
1027                         specified_table_size = TCE_TABLE_SIZE_256K;
1028                 else if (!strncmp(p, "512k", 4))
1029                         specified_table_size = TCE_TABLE_SIZE_512K;
1030                 else if (!strncmp(p, "1M", 2))
1031                         specified_table_size = TCE_TABLE_SIZE_1M;
1032                 else if (!strncmp(p, "2M", 2))
1033                         specified_table_size = TCE_TABLE_SIZE_2M;
1034                 else if (!strncmp(p, "4M", 2))
1035                         specified_table_size = TCE_TABLE_SIZE_4M;
1036                 else if (!strncmp(p, "8M", 2))
1037                         specified_table_size = TCE_TABLE_SIZE_8M;
1038
1039                 len = strlen("translate_empty_slots");
1040                 if (!strncmp(p, "translate_empty_slots", len))
1041                         translate_empty_slots = 1;
1042
1043                 len = strlen("disable");
1044                 if (!strncmp(p, "disable", len)) {
1045                         p += len;
1046                         if (*p == '=')
1047                                 ++p;
1048                         if (*p == '\0')
1049                                 break;
1050                         bridge = simple_strtol(p, &endp, 0);
1051                         if (p == endp)
1052                                 break;
1053
1054                         if (bridge < MAX_PHB_BUS_NUM) {
1055                                 printk(KERN_INFO "Calgary: disabling "
1056                                        "translation for PHB 0x%x\n", bridge);
1057                                 bus_info[bridge].translation_disabled = 1;
1058                         }
1059                 }
1060
1061                 p = strpbrk(p, ",");
1062                 if (!p)
1063                         break;
1064
1065                 p++; /* skip ',' */
1066         }
1067         return 1;
1068 }
1069 __setup("calgary=", calgary_parse_options);