git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/b43/phy.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   6   Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   This program is free software; you can redistribute it and/or modify
  12   it under the terms of the GNU General Public License as published by
  13   the Free Software Foundation; either version 2 of the License, or
  14   (at your option) any later version.
  15
  16   This program is distributed in the hope that it will be useful,
  17   but WITHOUT ANY WARRANTY; without even the implied warranty of
  18   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19   GNU General Public License for more details.
  20
  21   You should have received a copy of the GNU General Public License
  22   along with this program; see the file COPYING.  If not, write to
  23   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  24   Boston, MA 02110-1301, USA.
  25
  26 */
  27
  28 #include <linux/delay.h>
  29 #include <linux/types.h>
  30
  31 #include "b43.h"
  32 #include "phy.h"
  33 #include "main.h"
  34 #include "tables.h"
  35 #include "lo.h"
  36
  37 static const s8 b43_tssi2dbm_b_table[] = {
  38         0x4D, 0x4C, 0x4B, 0x4A,
  39         0x4A, 0x49, 0x48, 0x47,
  40         0x47, 0x46, 0x45, 0x45,
  41         0x44, 0x43, 0x42, 0x42,
  42         0x41, 0x40, 0x3F, 0x3E,
  43         0x3D, 0x3C, 0x3B, 0x3A,
  44         0x39, 0x38, 0x37, 0x36,
  45         0x35, 0x34, 0x32, 0x31,
  46         0x30, 0x2F, 0x2D, 0x2C,
  47         0x2B, 0x29, 0x28, 0x26,
  48         0x25, 0x23, 0x21, 0x1F,
  49         0x1D, 0x1A, 0x17, 0x14,
  50         0x10, 0x0C, 0x06, 0x00,
  51         -7, -7, -7, -7,
  52         -7, -7, -7, -7,
  53         -7, -7, -7, -7,
  54 };
  55
  56 static const s8 b43_tssi2dbm_g_table[] = {
  57         77, 77, 77, 76,
  58         76, 76, 75, 75,
  59         74, 74, 73, 73,
  60         73, 72, 72, 71,
  61         71, 70, 70, 69,
  62         68, 68, 67, 67,
  63         66, 65, 65, 64,
  64         63, 63, 62, 61,
  65         60, 59, 58, 57,
  66         56, 55, 54, 53,
  67         52, 50, 49, 47,
  68         45, 43, 40, 37,
  69         33, 28, 22, 14,
  70         5, -7, -20, -20,
  71         -20, -20, -20, -20,
  72         -20, -20, -20, -20,
  73 };
  74
  75 const u8 b43_radio_channel_codes_bg[] = {
  76         12, 17, 22, 27,
  77         32, 37, 42, 47,
  78         52, 57, 62, 67,
  79         72, 84,
  80 };
  81
  82 static void b43_phy_initg(struct b43_wldev *dev);
  83
  84 /* Reverse the bits of a 4bit value.
  85  * Example:  1101 is flipped 1011
  86  */
  87 static u16 flip_4bit(u16 value)
  88 {
  89         u16 flipped = 0x0000;
  90
  91         B43_WARN_ON(value & ~0x000F);
  92
  93         flipped |= (value & 0x0001) << 3;
  94         flipped |= (value & 0x0002) << 1;
  95         flipped |= (value & 0x0004) >> 1;
  96         flipped |= (value & 0x0008) >> 3;
  97
  98         return flipped;
  99 }
 100
 101 static void generate_rfatt_list(struct b43_wldev *dev,
 102                                 struct b43_rfatt_list *list)
 103 {
 104         struct b43_phy *phy = &dev->phy;
 105
 106         /* APHY.rev < 5 || GPHY.rev < 6 */
 107         static const struct b43_rfatt rfatt_0[] = {
 108                 {.att = 3,.with_padmix = 0,},
 109                 {.att = 1,.with_padmix = 0,},
 110                 {.att = 5,.with_padmix = 0,},
 111                 {.att = 7,.with_padmix = 0,},
 112                 {.att = 9,.with_padmix = 0,},
 113                 {.att = 2,.with_padmix = 0,},
 114                 {.att = 0,.with_padmix = 0,},
 115                 {.att = 4,.with_padmix = 0,},
 116                 {.att = 6,.with_padmix = 0,},
 117                 {.att = 8,.with_padmix = 0,},
 118                 {.att = 1,.with_padmix = 1,},
 119                 {.att = 2,.with_padmix = 1,},
 120                 {.att = 3,.with_padmix = 1,},
 121                 {.att = 4,.with_padmix = 1,},
 122         };
 123         /* Radio.rev == 8 && Radio.version == 0x2050 */
 124         static const struct b43_rfatt rfatt_1[] = {
 125                 {.att = 2,.with_padmix = 1,},
 126                 {.att = 4,.with_padmix = 1,},
 127                 {.att = 6,.with_padmix = 1,},
 128                 {.att = 8,.with_padmix = 1,},
 129                 {.att = 10,.with_padmix = 1,},
 130                 {.att = 12,.with_padmix = 1,},
 131                 {.att = 14,.with_padmix = 1,},
 132         };
 133         /* Otherwise */
 134         static const struct b43_rfatt rfatt_2[] = {
 135                 {.att = 0,.with_padmix = 1,},
 136                 {.att = 2,.with_padmix = 1,},
 137                 {.att = 4,.with_padmix = 1,},
 138                 {.att = 6,.with_padmix = 1,},
 139                 {.att = 8,.with_padmix = 1,},
 140                 {.att = 9,.with_padmix = 1,},
 141                 {.att = 9,.with_padmix = 1,},
 142         };
 143
 144         if ((phy->type == B43_PHYTYPE_A && phy->rev < 5) ||
 145             (phy->type == B43_PHYTYPE_G && phy->rev < 6)) {
 146                 /* Software pctl */
 147                 list->list = rfatt_0;
 148                 list->len = ARRAY_SIZE(rfatt_0);
 149                 list->min_val = 0;
 150                 list->max_val = 9;
 151                 return;
 152         }
 153         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 154                 /* Hardware pctl */
 155                 list->list = rfatt_1;
 156                 list->len = ARRAY_SIZE(rfatt_1);
 157                 list->min_val = 2;
 158                 list->max_val = 14;
 159                 return;
 160         }
 161         /* Hardware pctl */
 162         list->list = rfatt_2;
 163         list->len = ARRAY_SIZE(rfatt_2);
 164         list->min_val = 0;
 165         list->max_val = 9;
 166 }
 167
 168 static void generate_bbatt_list(struct b43_wldev *dev,
 169                                 struct b43_bbatt_list *list)
 170 {
 171         static const struct b43_bbatt bbatt_0[] = {
 172                 {.att = 0,},
 173                 {.att = 1,},
 174                 {.att = 2,},
 175                 {.att = 3,},
 176                 {.att = 4,},
 177                 {.att = 5,},
 178                 {.att = 6,},
 179                 {.att = 7,},
 180                 {.att = 8,},
 181         };
 182
 183         list->list = bbatt_0;
 184         list->len = ARRAY_SIZE(bbatt_0);
 185         list->min_val = 0;
 186         list->max_val = 8;
 187 }
 188
 189 bool b43_has_hardware_pctl(struct b43_phy *phy)
 190 {
 191         if (!phy->hardware_power_control)
 192                 return 0;
 193         switch (phy->type) {
 194         case B43_PHYTYPE_A:
 195                 if (phy->rev >= 5)
 196                         return 1;
 197                 break;
 198         case B43_PHYTYPE_G:
 199                 if (phy->rev >= 6)
 200                         return 1;
 201                 break;
 202         default:
 203                 B43_WARN_ON(1);
 204         }
 205         return 0;
 206 }
 207
 208 static void b43_shm_clear_tssi(struct b43_wldev *dev)
 209 {
 210         struct b43_phy *phy = &dev->phy;
 211
 212         switch (phy->type) {
 213         case B43_PHYTYPE_A:
 214                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0068, 0x7F7F);
 215                 b43_shm_write16(dev, B43_SHM_SHARED, 0x006a, 0x7F7F);
 216                 break;
 217         case B43_PHYTYPE_B:
 218         case B43_PHYTYPE_G:
 219                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
 220                 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
 221                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
 222                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
 223                 break;
 224         }
 225 }
 226
 227 void b43_raw_phy_lock(struct b43_wldev *dev)
 228 {
 229         struct b43_phy *phy = &dev->phy;
 230
 231         B43_WARN_ON(!irqs_disabled());
 232
 233         /* We had a check for MACCTL==0 here, but I think that doesn't
 234          * make sense, as MACCTL is never 0 when this is called.
 235          *      --mb */
 236         B43_WARN_ON(b43_read32(dev, B43_MMIO_MACCTL) == 0);
 237
 238         if (dev->dev->id.revision < 3) {
 239                 b43_mac_suspend(dev);
 240                 spin_lock(&phy->lock);
 241         } else {
 242                 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
 243                         b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
 244         }
 245         phy->locked = 1;
 246 }
 247
 248 void b43_raw_phy_unlock(struct b43_wldev *dev)
 249 {
 250         struct b43_phy *phy = &dev->phy;
 251
 252         B43_WARN_ON(!irqs_disabled());
 253         if (dev->dev->id.revision < 3) {
 254                 if (phy->locked) {
 255                         spin_unlock(&phy->lock);
 256                         b43_mac_enable(dev);
 257                 }
 258         } else {
 259                 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
 260                         b43_power_saving_ctl_bits(dev, 0);
 261         }
 262         phy->locked = 0;
 263 }
 264
 265 /* Different PHYs require different register routing flags.
 266  * This adjusts (and does sanity checks on) the routing flags.
 267  */
 268 static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
 269                                             u16 offset, struct b43_wldev *dev)
 270 {
 271         if (phy->type == B43_PHYTYPE_A) {
 272                 /* OFDM registers are base-registers for the A-PHY. */
 273                 offset &= ~B43_PHYROUTE_OFDM_GPHY;
 274         }
 275         if (offset & B43_PHYROUTE_EXT_GPHY) {
 276                 /* Ext-G registers are only available on G-PHYs */
 277                 if (phy->type != B43_PHYTYPE_G) {
 278                         b43dbg(dev->wl, "EXT-G PHY access at "
 279                                "0x%04X on %u type PHY\n", offset, phy->type);
 280                 }
 281         }
 282
 283         return offset;
 284 }
 285
 286 u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
 287 {
 288         struct b43_phy *phy = &dev->phy;
 289
 290         offset = adjust_phyreg_for_phytype(phy, offset, dev);
 291         b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
 292         return b43_read16(dev, B43_MMIO_PHY_DATA);
 293 }
 294
 295 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
 296 {
 297         struct b43_phy *phy = &dev->phy;
 298
 299         offset = adjust_phyreg_for_phytype(phy, offset, dev);
 300         b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
 301         mmiowb();
 302         b43_write16(dev, B43_MMIO_PHY_DATA, val);
 303 }
 304
 305 static void b43_radio_set_txpower_a(struct b43_wldev *dev, u16 txpower);
 306
 307 /* Adjust the transmission power output (G-PHY) */
 308 void b43_set_txpower_g(struct b43_wldev *dev,
 309                        const struct b43_bbatt *bbatt,
 310                        const struct b43_rfatt *rfatt, u8 tx_control)
 311 {
 312         struct b43_phy *phy = &dev->phy;
 313         struct b43_txpower_lo_control *lo = phy->lo_control;
 314         u16 bb, rf;
 315         u16 tx_bias, tx_magn;
 316
 317         bb = bbatt->att;
 318         rf = rfatt->att;
 319         tx_bias = lo->tx_bias;
 320         tx_magn = lo->tx_magn;
 321         if (unlikely(tx_bias == 0xFF))
 322                 tx_bias = 0;
 323
 324         /* Save the values for later */
 325         phy->tx_control = tx_control;
 326         memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
 327         memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
 328
 329         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
 330                 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
 331                        "rfatt(%u), tx_control(0x%02X), "
 332                        "tx_bias(0x%02X), tx_magn(0x%02X)\n",
 333                        bb, rf, tx_control, tx_bias, tx_magn);
 334         }
 335
 336         b43_phy_set_baseband_attenuation(dev, bb);
 337         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
 338         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 339                 b43_radio_write16(dev, 0x43,
 340                                   (rf & 0x000F) | (tx_control & 0x0070));
 341         } else {
 342                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
 343                                               & 0xFFF0) | (rf & 0x000F));
 344                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 345                                               & ~0x0070) | (tx_control &
 346                                                             0x0070));
 347         }
 348         if (has_tx_magnification(phy)) {
 349                 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
 350         } else {
 351                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 352                                               & 0xFFF0) | (tx_bias & 0x000F));
 353         }
 354         if (phy->type == B43_PHYTYPE_G)
 355                 b43_lo_g_adjust(dev);
 356 }
 357
 358 static void default_baseband_attenuation(struct b43_wldev *dev,
 359                                          struct b43_bbatt *bb)
 360 {
 361         struct b43_phy *phy = &dev->phy;
 362
 363         if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
 364                 bb->att = 0;
 365         else
 366                 bb->att = 2;
 367 }
 368
 369 static void default_radio_attenuation(struct b43_wldev *dev,
 370                                       struct b43_rfatt *rf)
 371 {
 372         struct ssb_bus *bus = dev->dev->bus;
 373         struct b43_phy *phy = &dev->phy;
 374
 375         rf->with_padmix = 0;
 376
 377         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
 378             bus->boardinfo.type == SSB_BOARD_BCM4309G) {
 379                 if (bus->boardinfo.rev < 0x43) {
 380                         rf->att = 2;
 381                         return;
 382                 } else if (bus->boardinfo.rev < 0x51) {
 383                         rf->att = 3;
 384                         return;
 385                 }
 386         }
 387
 388         if (phy->type == B43_PHYTYPE_A) {
 389                 rf->att = 0x60;
 390                 return;
 391         }
 392
 393         switch (phy->radio_ver) {
 394         case 0x2053:
 395                 switch (phy->radio_rev) {
 396                 case 1:
 397                         rf->att = 6;
 398                         return;
 399                 }
 400                 break;
 401         case 0x2050:
 402                 switch (phy->radio_rev) {
 403                 case 0:
 404                         rf->att = 5;
 405                         return;
 406                 case 1:
 407                         if (phy->type == B43_PHYTYPE_G) {
 408                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 409                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 410                                     && bus->boardinfo.rev >= 30)
 411                                         rf->att = 3;
 412                                 else if (bus->boardinfo.vendor ==
 413                                          SSB_BOARDVENDOR_BCM
 414                                          && bus->boardinfo.type ==
 415                                          SSB_BOARD_BU4306)
 416                                         rf->att = 3;
 417                                 else
 418                                         rf->att = 1;
 419                         } else {
 420                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 421                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 422                                     && bus->boardinfo.rev >= 30)
 423                                         rf->att = 7;
 424                                 else
 425                                         rf->att = 6;
 426                         }
 427                         return;
 428                 case 2:
 429                         if (phy->type == B43_PHYTYPE_G) {
 430                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
 431                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
 432                                     && bus->boardinfo.rev >= 30)
 433                                         rf->att = 3;
 434                                 else if (bus->boardinfo.vendor ==
 435                                          SSB_BOARDVENDOR_BCM
 436                                          && bus->boardinfo.type ==
 437                                          SSB_BOARD_BU4306)
 438                                         rf->att = 5;
 439                                 else if (bus->chip_id == 0x4320)
 440                                         rf->att = 4;
 441                                 else
 442                                         rf->att = 3;
 443                         } else
 444                                 rf->att = 6;
 445                         return;
 446                 case 3:
 447                         rf->att = 5;
 448                         return;
 449                 case 4:
 450                 case 5:
 451                         rf->att = 1;
 452                         return;
 453                 case 6:
 454                 case 7:
 455                         rf->att = 5;
 456                         return;
 457                 case 8:
 458                         rf->att = 0xA;
 459                         rf->with_padmix = 1;
 460                         return;
 461                 case 9:
 462                 default:
 463                         rf->att = 5;
 464                         return;
 465                 }
 466         }
 467         rf->att = 5;
 468 }
 469
 470 static u16 default_tx_control(struct b43_wldev *dev)
 471 {
 472         struct b43_phy *phy = &dev->phy;
 473
 474         if (phy->radio_ver != 0x2050)
 475                 return 0;
 476         if (phy->radio_rev == 1)
 477                 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
 478         if (phy->radio_rev < 6)
 479                 return B43_TXCTL_PA2DB;
 480         if (phy->radio_rev == 8)
 481                 return B43_TXCTL_TXMIX;
 482         return 0;
 483 }
 484
 485 /* This func is called "PHY calibrate" in the specs... */
 486 void b43_phy_early_init(struct b43_wldev *dev)
 487 {
 488         struct b43_phy *phy = &dev->phy;
 489         struct b43_txpower_lo_control *lo = phy->lo_control;
 490
 491         default_baseband_attenuation(dev, &phy->bbatt);
 492         default_radio_attenuation(dev, &phy->rfatt);
 493         phy->tx_control = (default_tx_control(dev) << 4);
 494
 495         /* Commit previous writes */
 496         b43_read32(dev, B43_MMIO_MACCTL);
 497
 498         if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
 499                 generate_rfatt_list(dev, &lo->rfatt_list);
 500                 generate_bbatt_list(dev, &lo->bbatt_list);
 501         }
 502         if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
 503                 /* Workaround: Temporarly disable gmode through the early init
 504                  * phase, as the gmode stuff is not needed for phy rev 1 */
 505                 phy->gmode = 0;
 506                 b43_wireless_core_reset(dev, 0);
 507                 b43_phy_initg(dev);
 508                 phy->gmode = 1;
 509                 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
 510         }
 511 }
 512
 513 /* GPHY_TSSI_Power_Lookup_Table_Init */
 514 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
 515 {
 516         struct b43_phy *phy = &dev->phy;
 517         int i;
 518         u16 value;
 519
 520         for (i = 0; i < 32; i++)
 521                 b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
 522         for (i = 32; i < 64; i++)
 523                 b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
 524         for (i = 0; i < 64; i += 2) {
 525                 value = (u16) phy->tssi2dbm[i];
 526                 value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
 527                 b43_phy_write(dev, 0x380 + (i / 2), value);
 528         }
 529 }
 530
 531 /* GPHY_Gain_Lookup_Table_Init */
 532 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
 533 {
 534         struct b43_phy *phy = &dev->phy;
 535         struct b43_txpower_lo_control *lo = phy->lo_control;
 536         u16 nr_written = 0;
 537         u16 tmp;
 538         u8 rf, bb;
 539
 540         if (!lo->lo_measured) {
 541                 b43_phy_write(dev, 0x3FF, 0);
 542                 return;
 543         }
 544
 545         for (rf = 0; rf < lo->rfatt_list.len; rf++) {
 546                 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
 547                         if (nr_written >= 0x40)
 548                                 return;
 549                         tmp = lo->bbatt_list.list[bb].att;
 550                         tmp <<= 8;
 551                         if (phy->radio_rev == 8)
 552                                 tmp |= 0x50;
 553                         else
 554                                 tmp |= 0x40;
 555                         tmp |= lo->rfatt_list.list[rf].att;
 556                         b43_phy_write(dev, 0x3C0 + nr_written, tmp);
 557                         nr_written++;
 558                 }
 559         }
 560 }
 561
 562 /* GPHY_DC_Lookup_Table */
 563 void b43_gphy_dc_lt_init(struct b43_wldev *dev)
 564 {
 565         struct b43_phy *phy = &dev->phy;
 566         struct b43_txpower_lo_control *lo = phy->lo_control;
 567         struct b43_loctl *loctl0;
 568         struct b43_loctl *loctl1;
 569         int i;
 570         int rf_offset, bb_offset;
 571         u16 tmp;
 572
 573         for (i = 0; i < lo->rfatt_list.len + lo->bbatt_list.len; i += 2) {
 574                 rf_offset = i / lo->rfatt_list.len;
 575                 bb_offset = i % lo->rfatt_list.len;
 576
 577                 loctl0 = b43_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
 578                                           &lo->bbatt_list.list[bb_offset]);
 579                 if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
 580                         rf_offset = (i + 1) / lo->rfatt_list.len;
 581                         bb_offset = (i + 1) % lo->rfatt_list.len;
 582
 583                         loctl1 =
 584                             b43_get_lo_g_ctl(dev,
 585                                              &lo->rfatt_list.list[rf_offset],
 586                                              &lo->bbatt_list.list[bb_offset]);
 587                 } else
 588                         loctl1 = loctl0;
 589
 590                 tmp = ((u16) loctl0->q & 0xF);
 591                 tmp |= ((u16) loctl0->i & 0xF) << 4;
 592                 tmp |= ((u16) loctl1->q & 0xF) << 8;
 593                 tmp |= ((u16) loctl1->i & 0xF) << 12;   //FIXME?
 594                 b43_phy_write(dev, 0x3A0 + (i / 2), tmp);
 595         }
 596 }
 597
 598 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
 599 {
 600         //TODO
 601 }
 602
 603 static void hardware_pctl_init_gphy(struct b43_wldev *dev)
 604 {
 605         struct b43_phy *phy = &dev->phy;
 606
 607         b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
 608                       | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
 609         b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
 610                       | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
 611         b43_gphy_tssi_power_lt_init(dev);
 612         b43_gphy_gain_lt_init(dev);
 613         b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
 614         b43_phy_write(dev, 0x0014, 0x0000);
 615
 616         B43_WARN_ON(phy->rev < 6);
 617         b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
 618                       | 0x0800);
 619         b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
 620                       & 0xFEFF);
 621         b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
 622                       & 0xFFBF);
 623
 624         b43_gphy_dc_lt_init(dev);
 625 }
 626
 627 /* HardwarePowerControl init for A and G PHY */
 628 static void b43_hardware_pctl_init(struct b43_wldev *dev)
 629 {
 630         struct b43_phy *phy = &dev->phy;
 631
 632         if (!b43_has_hardware_pctl(phy)) {
 633                 /* No hardware power control */
 634                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
 635                 return;
 636         }
 637         /* Init the hwpctl related hardware */
 638         switch (phy->type) {
 639         case B43_PHYTYPE_A:
 640                 hardware_pctl_init_aphy(dev);
 641                 break;
 642         case B43_PHYTYPE_G:
 643                 hardware_pctl_init_gphy(dev);
 644                 break;
 645         default:
 646                 B43_WARN_ON(1);
 647         }
 648         /* Enable hardware pctl in firmware. */
 649         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
 650 }
 651
 652 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
 653 {
 654         struct b43_phy *phy = &dev->phy;
 655
 656         if (!b43_has_hardware_pctl(phy)) {
 657                 b43_phy_write(dev, 0x047A, 0xC111);
 658                 return;
 659         }
 660
 661         b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
 662         b43_phy_write(dev, 0x002F, 0x0202);
 663         b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
 664         b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
 665         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 666                 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
 667                                             & 0xFF0F) | 0x0010);
 668                 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
 669                               | 0x8000);
 670                 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
 671                                             & 0xFFC0) | 0x0010);
 672                 b43_phy_write(dev, 0x002E, 0xC07F);
 673                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 674                               | 0x0400);
 675         } else {
 676                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 677                               | 0x0200);
 678                 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
 679                               | 0x0400);
 680                 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
 681                               & 0x7FFF);
 682                 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
 683                               & 0xFFFE);
 684                 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
 685                                             & 0xFFC0) | 0x0010);
 686                 b43_phy_write(dev, 0x002E, 0xC07F);
 687                 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
 688                                             & 0xFF0F) | 0x0010);
 689         }
 690 }
 691
 692 /* Intialize B/G PHY power control
 693  * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
 694  */
 695 static void b43_phy_init_pctl(struct b43_wldev *dev)
 696 {
 697         struct ssb_bus *bus = dev->dev->bus;
 698         struct b43_phy *phy = &dev->phy;
 699         struct b43_rfatt old_rfatt;
 700         struct b43_bbatt old_bbatt;
 701         u8 old_tx_control = 0;
 702
 703         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 704             (bus->boardinfo.type == SSB_BOARD_BU4306))
 705                 return;
 706
 707         b43_phy_write(dev, 0x0028, 0x8018);
 708
 709         /* This does something with the Analog... */
 710         b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
 711                     & 0xFFDF);
 712
 713         if (phy->type == B43_PHYTYPE_G && !phy->gmode)
 714                 return;
 715         b43_hardware_pctl_early_init(dev);
 716         if (phy->cur_idle_tssi == 0) {
 717                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
 718                         b43_radio_write16(dev, 0x0076,
 719                                           (b43_radio_read16(dev, 0x0076)
 720                                            & 0x00F7) | 0x0084);
 721                 } else {
 722                         struct b43_rfatt rfatt;
 723                         struct b43_bbatt bbatt;
 724
 725                         memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
 726                         memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
 727                         old_tx_control = phy->tx_control;
 728
 729                         bbatt.att = 11;
 730                         if (phy->radio_rev == 8) {
 731                                 rfatt.att = 15;
 732                                 rfatt.with_padmix = 1;
 733                         } else {
 734                                 rfatt.att = 9;
 735                                 rfatt.with_padmix = 0;
 736                         }
 737                         b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
 738                 }
 739                 b43_dummy_transmission(dev);
 740                 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
 741                 if (B43_DEBUG) {
 742                         /* Current-Idle-TSSI sanity check. */
 743                         if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
 744                                 b43dbg(dev->wl,
 745                                        "!WARNING! Idle-TSSI phy->cur_idle_tssi "
 746                                        "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
 747                                        "adjustment.\n", phy->cur_idle_tssi,
 748                                        phy->tgt_idle_tssi);
 749                                 phy->cur_idle_tssi = 0;
 750                         }
 751                 }
 752                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
 753                         b43_radio_write16(dev, 0x0076,
 754                                           b43_radio_read16(dev, 0x0076)
 755                                           & 0xFF7B);
 756                 } else {
 757                         b43_set_txpower_g(dev, &old_bbatt,
 758                                           &old_rfatt, old_tx_control);
 759                 }
 760         }
 761         b43_hardware_pctl_init(dev);
 762         b43_shm_clear_tssi(dev);
 763 }
 764
 765 static void b43_phy_agcsetup(struct b43_wldev *dev)
 766 {
 767         struct b43_phy *phy = &dev->phy;
 768         u16 offset = 0x0000;
 769
 770         if (phy->rev == 1)
 771                 offset = 0x4C00;
 772
 773         b43_ofdmtab_write16(dev, offset, 0, 0x00FE);
 774         b43_ofdmtab_write16(dev, offset, 1, 0x000D);
 775         b43_ofdmtab_write16(dev, offset, 2, 0x0013);
 776         b43_ofdmtab_write16(dev, offset, 3, 0x0019);
 777
 778         if (phy->rev == 1) {
 779                 b43_ofdmtab_write16(dev, 0x1800, 0, 0x2710);
 780                 b43_ofdmtab_write16(dev, 0x1801, 0, 0x9B83);
 781                 b43_ofdmtab_write16(dev, 0x1802, 0, 0x9B83);
 782                 b43_ofdmtab_write16(dev, 0x1803, 0, 0x0F8D);
 783                 b43_phy_write(dev, 0x0455, 0x0004);
 784         }
 785
 786         b43_phy_write(dev, 0x04A5, (b43_phy_read(dev, 0x04A5)
 787                                     & 0x00FF) | 0x5700);
 788         b43_phy_write(dev, 0x041A, (b43_phy_read(dev, 0x041A)
 789                                     & 0xFF80) | 0x000F);
 790         b43_phy_write(dev, 0x041A, (b43_phy_read(dev, 0x041A)
 791                                     & 0xC07F) | 0x2B80);
 792         b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
 793                                     & 0xF0FF) | 0x0300);
 794
 795         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
 796                           | 0x0008);
 797
 798         b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
 799                                     & 0xFFF0) | 0x0008);
 800         b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
 801                                     & 0xF0FF) | 0x0600);
 802         b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
 803                                     & 0xF0FF) | 0x0700);
 804         b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
 805                                     & 0xF0FF) | 0x0100);
 806
 807         if (phy->rev == 1) {
 808                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
 809                                             & 0xFFF0) | 0x0007);
 810         }
 811
 812         b43_phy_write(dev, 0x0488, (b43_phy_read(dev, 0x0488)
 813                                     & 0xFF00) | 0x001C);
 814         b43_phy_write(dev, 0x0488, (b43_phy_read(dev, 0x0488)
 815                                     & 0xC0FF) | 0x0200);
 816         b43_phy_write(dev, 0x0496, (b43_phy_read(dev, 0x0496)
 817                                     & 0xFF00) | 0x001C);
 818         b43_phy_write(dev, 0x0489, (b43_phy_read(dev, 0x0489)
 819                                     & 0xFF00) | 0x0020);
 820         b43_phy_write(dev, 0x0489, (b43_phy_read(dev, 0x0489)
 821                                     & 0xC0FF) | 0x0200);
 822         b43_phy_write(dev, 0x0482, (b43_phy_read(dev, 0x0482)
 823                                     & 0xFF00) | 0x002E);
 824         b43_phy_write(dev, 0x0496, (b43_phy_read(dev, 0x0496)
 825                                     & 0x00FF) | 0x1A00);
 826         b43_phy_write(dev, 0x0481, (b43_phy_read(dev, 0x0481)
 827                                     & 0xFF00) | 0x0028);
 828         b43_phy_write(dev, 0x0481, (b43_phy_read(dev, 0x0481)
 829                                     & 0x00FF) | 0x2C00);
 830
 831         if (phy->rev == 1) {
 832                 b43_phy_write(dev, 0x0430, 0x092B);
 833                 b43_phy_write(dev, 0x041B, (b43_phy_read(dev, 0x041B)
 834                                             & 0xFFE1) | 0x0002);
 835         } else {
 836                 b43_phy_write(dev, 0x041B, b43_phy_read(dev, 0x041B)
 837                               & 0xFFE1);
 838                 b43_phy_write(dev, 0x041F, 0x287A);
 839                 b43_phy_write(dev, 0x0420, (b43_phy_read(dev, 0x0420)
 840                                             & 0xFFF0) | 0x0004);
 841         }
 842
 843         if (phy->rev >= 6) {
 844                 b43_phy_write(dev, 0x0422, 0x287A);
 845                 b43_phy_write(dev, 0x0420, (b43_phy_read(dev, 0x0420)
 846                                             & 0x0FFF) | 0x3000);
 847         }
 848
 849         b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
 850                                     & 0x8080) | 0x7874);
 851         b43_phy_write(dev, 0x048E, 0x1C00);
 852
 853         offset = 0x0800;
 854         if (phy->rev == 1) {
 855                 offset = 0x5400;
 856                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
 857                                             & 0xF0FF) | 0x0600);
 858                 b43_phy_write(dev, 0x048B, 0x005E);
 859                 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
 860                                             & 0xFF00) | 0x001E);
 861                 b43_phy_write(dev, 0x048D, 0x0002);
 862         }
 863         b43_ofdmtab_write16(dev, offset, 0, 0x00);
 864         b43_ofdmtab_write16(dev, offset, 1, 0x07);
 865         b43_ofdmtab_write16(dev, offset, 2, 0x10);
 866         b43_ofdmtab_write16(dev, offset, 3, 0x1C);
 867
 868         if (phy->rev >= 6) {
 869                 b43_phy_write(dev, 0x0426, b43_phy_read(dev, 0x0426)
 870                               & 0xFFFC);
 871                 b43_phy_write(dev, 0x0426, b43_phy_read(dev, 0x0426)
 872                               & 0xEFFF);
 873         }
 874 }
 875
 876 static void b43_phy_setupg(struct b43_wldev *dev)
 877 {
 878         struct ssb_bus *bus = dev->dev->bus;
 879         struct b43_phy *phy = &dev->phy;
 880         u16 i;
 881
 882         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
 883         if (phy->rev == 1) {
 884                 b43_phy_write(dev, 0x0406, 0x4F19);
 885                 b43_phy_write(dev, B43_PHY_G_CRS,
 886                               (b43_phy_read(dev, B43_PHY_G_CRS) & 0xFC3F) |
 887                               0x0340);
 888                 b43_phy_write(dev, 0x042C, 0x005A);
 889                 b43_phy_write(dev, 0x0427, 0x001A);
 890
 891                 for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
 892                         b43_ofdmtab_write16(dev, 0x5800, i,
 893                                             b43_tab_finefreqg[i]);
 894                 for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
 895                         b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noiseg1[i]);
 896                 for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
 897                         b43_ofdmtab_write16(dev, 0x2000, i, b43_tab_rotor[i]);
 898         } else {
 899                 /* nrssi values are signed 6-bit values. Not sure why we write 0x7654 here... */
 900                 b43_nrssi_hw_write(dev, 0xBA98, (s16) 0x7654);
 901
 902                 if (phy->rev == 2) {
 903                         b43_phy_write(dev, 0x04C0, 0x1861);
 904                         b43_phy_write(dev, 0x04C1, 0x0271);
 905                 } else if (phy->rev > 2) {
 906                         b43_phy_write(dev, 0x04C0, 0x0098);
 907                         b43_phy_write(dev, 0x04C1, 0x0070);
 908                         b43_phy_write(dev, 0x04C9, 0x0080);
 909                 }
 910                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x800);
 911
 912                 for (i = 0; i < 64; i++)
 913                         b43_ofdmtab_write16(dev, 0x4000, i, i);
 914                 for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
 915                         b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noiseg2[i]);
 916         }
 917
 918         if (phy->rev <= 2)
 919                 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
 920                         b43_ofdmtab_write16(dev, 0x1400, i,
 921                                             b43_tab_noisescaleg1[i]);
 922         else if ((phy->rev >= 7) && (b43_phy_read(dev, 0x0449) & 0x0200))
 923                 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
 924                         b43_ofdmtab_write16(dev, 0x1400, i,
 925                                             b43_tab_noisescaleg3[i]);
 926         else
 927                 for (i = 0; i < B43_TAB_NOISESCALEG_SIZE; i++)
 928                         b43_ofdmtab_write16(dev, 0x1400, i,
 929                                             b43_tab_noisescaleg2[i]);
 930
 931         if (phy->rev == 2)
 932                 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++)
 933                         b43_ofdmtab_write16(dev, 0x5000, i,
 934                                             b43_tab_sigmasqr1[i]);
 935         else if ((phy->rev > 2) && (phy->rev <= 8))
 936                 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++)
 937                         b43_ofdmtab_write16(dev, 0x5000, i,
 938                                             b43_tab_sigmasqr2[i]);
 939
 940         if (phy->rev == 1) {
 941                 for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
 942                         b43_ofdmtab_write32(dev, 0x2400, i, b43_tab_retard[i]);
 943                 for (i = 4; i < 20; i++)
 944                         b43_ofdmtab_write16(dev, 0x5400, i, 0x0020);
 945                 b43_phy_agcsetup(dev);
 946
 947                 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 948                     (bus->boardinfo.type == SSB_BOARD_BU4306) &&
 949                     (bus->boardinfo.rev == 0x17))
 950                         return;
 951
 952                 b43_ofdmtab_write16(dev, 0x5001, 0, 0x0002);
 953                 b43_ofdmtab_write16(dev, 0x5002, 0, 0x0001);
 954         } else {
 955                 for (i = 0; i < 0x20; i++)
 956                         b43_ofdmtab_write16(dev, 0x1000, i, 0x0820);
 957                 b43_phy_agcsetup(dev);
 958                 b43_phy_read(dev, 0x0400);      /* dummy read */
 959                 b43_phy_write(dev, 0x0403, 0x1000);
 960                 b43_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
 961                 b43_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
 962
 963                 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
 964                     (bus->boardinfo.type == SSB_BOARD_BU4306) &&
 965                     (bus->boardinfo.rev == 0x17))
 966                         return;
 967
 968                 b43_ofdmtab_write16(dev, 0x0401, 0, 0x0002);
 969                 b43_ofdmtab_write16(dev, 0x0402, 0, 0x0001);
 970         }
 971 }
 972
 973 /* Initialize the noisescaletable for APHY */
 974 static void b43_phy_init_noisescaletbl(struct b43_wldev *dev)
 975 {
 976         struct b43_phy *phy = &dev->phy;
 977         int i;
 978
 979         for (i = 0; i < 12; i++) {
 980                 if (phy->rev == 2)
 981                         b43_ofdmtab_write16(dev, 0x1400, i, 0x6767);
 982                 else
 983                         b43_ofdmtab_write16(dev, 0x1400, i, 0x2323);
 984         }
 985         if (phy->rev == 2)
 986                 b43_ofdmtab_write16(dev, 0x1400, i, 0x6700);
 987         else
 988                 b43_ofdmtab_write16(dev, 0x1400, i, 0x2300);
 989         for (i = 0; i < 11; i++) {
 990                 if (phy->rev == 2)
 991                         b43_ofdmtab_write16(dev, 0x1400, i, 0x6767);
 992                 else
 993                         b43_ofdmtab_write16(dev, 0x1400, i, 0x2323);
 994         }
 995         if (phy->rev == 2)
 996                 b43_ofdmtab_write16(dev, 0x1400, i, 0x0067);
 997         else
 998                 b43_ofdmtab_write16(dev, 0x1400, i, 0x0023);
 999 }
1000
1001 static void b43_phy_setupa(struct b43_wldev *dev)
1002 {
1003         struct b43_phy *phy = &dev->phy;
1004         u16 i;
1005
1006         B43_WARN_ON(phy->type != B43_PHYTYPE_A);
1007         switch (phy->rev) {
1008         case 2:
1009                 b43_phy_write(dev, 0x008E, 0x3800);
1010                 b43_phy_write(dev, 0x0035, 0x03FF);
1011                 b43_phy_write(dev, 0x0036, 0x0400);
1012
1013                 b43_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
1014
1015                 b43_phy_write(dev, 0x001C, 0x0FF9);
1016                 b43_phy_write(dev, 0x0020, b43_phy_read(dev, 0x0020) & 0xFF0F);
1017                 b43_ofdmtab_write16(dev, 0x3C0C, 0, 0x07BF);
1018                 b43_radio_write16(dev, 0x0002, 0x07BF);
1019
1020                 b43_phy_write(dev, 0x0024, 0x4680);
1021                 b43_phy_write(dev, 0x0020, 0x0003);
1022                 b43_phy_write(dev, 0x001D, 0x0F40);
1023                 b43_phy_write(dev, 0x001F, 0x1C00);
1024
1025                 b43_phy_write(dev, 0x002A, (b43_phy_read(dev, 0x002A)
1026                                             & 0x00FF) | 0x0400);
1027                 b43_phy_write(dev, 0x002B, b43_phy_read(dev, 0x002B)
1028                               & 0xFBFF);
1029                 b43_phy_write(dev, 0x008E, 0x58C1);
1030
1031                 b43_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
1032                 b43_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
1033                 b43_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
1034                 b43_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
1035                 b43_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
1036
1037                 b43_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
1038                 b43_ofdmtab_write16(dev, 0x0000, 1, 0x0013);
1039                 b43_ofdmtab_write16(dev, 0x0000, 2, 0x0013);
1040                 b43_ofdmtab_write16(dev, 0x0000, 3, 0x0013);
1041                 b43_ofdmtab_write16(dev, 0x0000, 4, 0x0015);
1042                 b43_ofdmtab_write16(dev, 0x0000, 5, 0x0015);
1043                 b43_ofdmtab_write16(dev, 0x0000, 6, 0x0019);
1044
1045                 b43_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
1046                 b43_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
1047                 b43_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
1048
1049                 for (i = 0; i < 16; i++)
1050                         b43_ofdmtab_write16(dev, 0x4000, i, (0x8 + i) & 0x000F);
1051
1052                 b43_ofdmtab_write16(dev, 0x3003, 0, 0x1044);
1053                 b43_ofdmtab_write16(dev, 0x3004, 0, 0x7201);
1054                 b43_ofdmtab_write16(dev, 0x3006, 0, 0x0040);
1055                 b43_ofdmtab_write16(dev, 0x3001, 0,
1056                                     (b43_ofdmtab_read16(dev, 0x3001, 0) &
1057                                      0x0010) | 0x0008);
1058
1059                 for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
1060                         b43_ofdmtab_write16(dev, 0x5800, i,
1061                                             b43_tab_finefreqa[i]);
1062                 for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
1063                         b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noisea2[i]);
1064                 for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
1065                         b43_ofdmtab_write32(dev, 0x2000, i, b43_tab_rotor[i]);
1066                 b43_phy_init_noisescaletbl(dev);
1067                 for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
1068                         b43_ofdmtab_write32(dev, 0x2400, i, b43_tab_retard[i]);
1069                 break;
1070         case 3:
1071                 for (i = 0; i < 64; i++)
1072                         b43_ofdmtab_write16(dev, 0x4000, i, i);
1073
1074                 b43_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
1075
1076                 b43_phy_write(dev, 0x001C, 0x0FF9);
1077                 b43_phy_write(dev, 0x0020, b43_phy_read(dev, 0x0020) & 0xFF0F);
1078                 b43_radio_write16(dev, 0x0002, 0x07BF);
1079
1080                 b43_phy_write(dev, 0x0024, 0x4680);
1081                 b43_phy_write(dev, 0x0020, 0x0003);
1082                 b43_phy_write(dev, 0x001D, 0x0F40);
1083                 b43_phy_write(dev, 0x001F, 0x1C00);
1084                 b43_phy_write(dev, 0x002A, (b43_phy_read(dev, 0x002A)
1085                                             & 0x00FF) | 0x0400);
1086
1087                 b43_ofdmtab_write16(dev, 0x3000, 1,
1088                                     (b43_ofdmtab_read16(dev, 0x3000, 1)
1089                                      & 0x0010) | 0x0008);
1090                 for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++) {
1091                         b43_ofdmtab_write16(dev, 0x1800, i, b43_tab_noisea3[i]);
1092                 }
1093                 b43_phy_init_noisescaletbl(dev);
1094                 for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
1095                         b43_ofdmtab_write16(dev, 0x5000, i,
1096                                             b43_tab_sigmasqr1[i]);
1097                 }
1098
1099                 b43_phy_write(dev, 0x0003, 0x1808);
1100
1101                 b43_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
1102                 b43_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
1103                 b43_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
1104                 b43_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
1105                 b43_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
1106
1107                 b43_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
1108                 b43_ofdmtab_write16(dev, 0x0001, 0, 0x0013);
1109                 b43_ofdmtab_write16(dev, 0x0002, 0, 0x0013);
1110                 b43_ofdmtab_write16(dev, 0x0003, 0, 0x0013);
1111                 b43_ofdmtab_write16(dev, 0x0004, 0, 0x0015);
1112                 b43_ofdmtab_write16(dev, 0x0005, 0, 0x0015);
1113                 b43_ofdmtab_write16(dev, 0x0006, 0, 0x0019);
1114
1115                 b43_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
1116                 b43_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
1117                 b43_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
1118
1119                 b43_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
1120                 b43_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
1121                 break;
1122         default:
1123                 B43_WARN_ON(1);
1124         }
1125 }
1126
1127 /* Initialize APHY. This is also called for the GPHY in some cases. */
1128 static void b43_phy_inita(struct b43_wldev *dev)
1129 {
1130         struct ssb_bus *bus = dev->dev->bus;
1131         struct b43_phy *phy = &dev->phy;
1132         u16 tval;
1133
1134         might_sleep();
1135
1136         if (phy->type == B43_PHYTYPE_A) {
1137                 b43_phy_setupa(dev);
1138         } else {
1139                 b43_phy_setupg(dev);
1140                 if (phy->gmode &&
1141                     (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL))
1142                         b43_phy_write(dev, 0x046E, 0x03CF);
1143                 return;
1144         }
1145
1146         b43_phy_write(dev, B43_PHY_A_CRS,
1147                       (b43_phy_read(dev, B43_PHY_A_CRS) & 0xF83C) | 0x0340);
1148         b43_phy_write(dev, 0x0034, 0x0001);
1149
1150         //TODO: RSSI AGC
1151         b43_phy_write(dev, B43_PHY_A_CRS,
1152                       b43_phy_read(dev, B43_PHY_A_CRS) | (1 << 14));
1153         b43_radio_init2060(dev);
1154
1155         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1156             ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
1157              (bus->boardinfo.type == SSB_BOARD_BU4309))) {
1158                 if (phy->lofcal == 0xFFFF) {
1159                         //TODO: LOF Cal
1160                         b43_radio_set_tx_iq(dev);
1161                 } else
1162                         b43_radio_write16(dev, 0x001E, phy->lofcal);
1163         }
1164
1165         b43_phy_write(dev, 0x007A, 0xF111);
1166
1167         if (phy->cur_idle_tssi == 0) {
1168                 b43_radio_write16(dev, 0x0019, 0x0000);
1169                 b43_radio_write16(dev, 0x0017, 0x0020);
1170
1171                 tval = b43_ofdmtab_read16(dev, 0x3001, 0);
1172                 if (phy->rev == 1) {
1173                         b43_ofdmtab_write16(dev, 0x3001, 0,
1174                                             (b43_ofdmtab_read16(dev, 0x3001, 0)
1175                                              & 0xFF87)
1176                                             | 0x0058);
1177                 } else {
1178                         b43_ofdmtab_write16(dev, 0x3001, 0,
1179                                             (b43_ofdmtab_read16(dev, 0x3001, 0)
1180                                              & 0xFFC3)
1181                                             | 0x002C);
1182                 }
1183                 b43_dummy_transmission(dev);
1184                 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_A_PCTL);
1185                 b43_ofdmtab_write16(dev, 0x3001, 0, tval);
1186
1187                 b43_radio_set_txpower_a(dev, 0x0018);
1188         }
1189         b43_shm_clear_tssi(dev);
1190 }
1191
1192 static void b43_phy_initb2(struct b43_wldev *dev)
1193 {
1194         struct b43_phy *phy = &dev->phy;
1195         u16 offset, val;
1196
1197         b43_write16(dev, 0x03EC, 0x3F22);
1198         b43_phy_write(dev, 0x0020, 0x301C);
1199         b43_phy_write(dev, 0x0026, 0x0000);
1200         b43_phy_write(dev, 0x0030, 0x00C6);
1201         b43_phy_write(dev, 0x0088, 0x3E00);
1202         val = 0x3C3D;
1203         for (offset = 0x0089; offset < 0x00A7; offset++) {
1204                 b43_phy_write(dev, offset, val);
1205                 val -= 0x0202;
1206         }
1207         b43_phy_write(dev, 0x03E4, 0x3000);
1208         b43_radio_selectchannel(dev, phy->channel, 0);
1209         if (phy->radio_ver != 0x2050) {
1210                 b43_radio_write16(dev, 0x0075, 0x0080);
1211                 b43_radio_write16(dev, 0x0079, 0x0081);
1212         }
1213         b43_radio_write16(dev, 0x0050, 0x0020);
1214         b43_radio_write16(dev, 0x0050, 0x0023);
1215         if (phy->radio_ver == 0x2050) {
1216                 b43_radio_write16(dev, 0x0050, 0x0020);
1217                 b43_radio_write16(dev, 0x005A, 0x0070);
1218                 b43_radio_write16(dev, 0x005B, 0x007B);
1219                 b43_radio_write16(dev, 0x005C, 0x00B0);
1220                 b43_radio_write16(dev, 0x007A, 0x000F);
1221                 b43_phy_write(dev, 0x0038, 0x0677);
1222                 b43_radio_init2050(dev);
1223         }
1224         b43_phy_write(dev, 0x0014, 0x0080);
1225         b43_phy_write(dev, 0x0032, 0x00CA);
1226         b43_phy_write(dev, 0x0032, 0x00CC);
1227         b43_phy_write(dev, 0x0035, 0x07C2);
1228         b43_lo_b_measure(dev);
1229         b43_phy_write(dev, 0x0026, 0xCC00);
1230         if (phy->radio_ver != 0x2050)
1231                 b43_phy_write(dev, 0x0026, 0xCE00);
1232         b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1000);
1233         b43_phy_write(dev, 0x002A, 0x88A3);
1234         if (phy->radio_ver != 0x2050)
1235                 b43_phy_write(dev, 0x002A, 0x88C2);
1236         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1237         b43_phy_init_pctl(dev);
1238 }
1239
1240 static void b43_phy_initb4(struct b43_wldev *dev)
1241 {
1242         struct b43_phy *phy = &dev->phy;
1243         u16 offset, val;
1244
1245         b43_write16(dev, 0x03EC, 0x3F22);
1246         b43_phy_write(dev, 0x0020, 0x301C);
1247         b43_phy_write(dev, 0x0026, 0x0000);
1248         b43_phy_write(dev, 0x0030, 0x00C6);
1249         b43_phy_write(dev, 0x0088, 0x3E00);
1250         val = 0x3C3D;
1251         for (offset = 0x0089; offset < 0x00A7; offset++) {
1252                 b43_phy_write(dev, offset, val);
1253                 val -= 0x0202;
1254         }
1255         b43_phy_write(dev, 0x03E4, 0x3000);
1256         b43_radio_selectchannel(dev, phy->channel, 0);
1257         if (phy->radio_ver != 0x2050) {
1258                 b43_radio_write16(dev, 0x0075, 0x0080);
1259                 b43_radio_write16(dev, 0x0079, 0x0081);
1260         }
1261         b43_radio_write16(dev, 0x0050, 0x0020);
1262         b43_radio_write16(dev, 0x0050, 0x0023);
1263         if (phy->radio_ver == 0x2050) {
1264                 b43_radio_write16(dev, 0x0050, 0x0020);
1265                 b43_radio_write16(dev, 0x005A, 0x0070);
1266                 b43_radio_write16(dev, 0x005B, 0x007B);
1267                 b43_radio_write16(dev, 0x005C, 0x00B0);
1268                 b43_radio_write16(dev, 0x007A, 0x000F);
1269                 b43_phy_write(dev, 0x0038, 0x0677);
1270                 b43_radio_init2050(dev);
1271         }
1272         b43_phy_write(dev, 0x0014, 0x0080);
1273         b43_phy_write(dev, 0x0032, 0x00CA);
1274         if (phy->radio_ver == 0x2050)
1275                 b43_phy_write(dev, 0x0032, 0x00E0);
1276         b43_phy_write(dev, 0x0035, 0x07C2);
1277
1278         b43_lo_b_measure(dev);
1279
1280         b43_phy_write(dev, 0x0026, 0xCC00);
1281         if (phy->radio_ver == 0x2050)
1282                 b43_phy_write(dev, 0x0026, 0xCE00);
1283         b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1100);
1284         b43_phy_write(dev, 0x002A, 0x88A3);
1285         if (phy->radio_ver == 0x2050)
1286                 b43_phy_write(dev, 0x002A, 0x88C2);
1287         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1288         if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
1289                 b43_calc_nrssi_slope(dev);
1290                 b43_calc_nrssi_threshold(dev);
1291         }
1292         b43_phy_init_pctl(dev);
1293 }
1294
1295 static void b43_phy_initb5(struct b43_wldev *dev)
1296 {
1297         struct ssb_bus *bus = dev->dev->bus;
1298         struct b43_phy *phy = &dev->phy;
1299         u16 offset, value;
1300         u8 old_channel;
1301
1302         if (phy->analog == 1) {
1303                 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1304                                   | 0x0050);
1305         }
1306         if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1307             (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1308                 value = 0x2120;
1309                 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1310                         b43_phy_write(dev, offset, value);
1311                         value += 0x202;
1312                 }
1313         }
1314         b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1315                       | 0x0700);
1316         if (phy->radio_ver == 0x2050)
1317                 b43_phy_write(dev, 0x0038, 0x0667);
1318
1319         if (phy->gmode || phy->rev >= 2) {
1320                 if (phy->radio_ver == 0x2050) {
1321                         b43_radio_write16(dev, 0x007A,
1322                                           b43_radio_read16(dev, 0x007A)
1323                                           | 0x0020);
1324                         b43_radio_write16(dev, 0x0051,
1325                                           b43_radio_read16(dev, 0x0051)
1326                                           | 0x0004);
1327                 }
1328                 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1329
1330                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1331                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1332
1333                 b43_phy_write(dev, 0x001C, 0x186A);
1334
1335                 b43_phy_write(dev, 0x0013,
1336                               (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1337                 b43_phy_write(dev, 0x0035,
1338                               (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1339                 b43_phy_write(dev, 0x005D,
1340                               (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1341         }
1342
1343         if (dev->bad_frames_preempt) {
1344                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1345                               b43_phy_read(dev,
1346                                            B43_PHY_RADIO_BITFIELD) | (1 << 11));
1347         }
1348
1349         if (phy->analog == 1) {
1350                 b43_phy_write(dev, 0x0026, 0xCE00);
1351                 b43_phy_write(dev, 0x0021, 0x3763);
1352                 b43_phy_write(dev, 0x0022, 0x1BC3);
1353                 b43_phy_write(dev, 0x0023, 0x06F9);
1354                 b43_phy_write(dev, 0x0024, 0x037E);
1355         } else
1356                 b43_phy_write(dev, 0x0026, 0xCC00);
1357         b43_phy_write(dev, 0x0030, 0x00C6);
1358         b43_write16(dev, 0x03EC, 0x3F22);
1359
1360         if (phy->analog == 1)
1361                 b43_phy_write(dev, 0x0020, 0x3E1C);
1362         else
1363                 b43_phy_write(dev, 0x0020, 0x301C);
1364
1365         if (phy->analog == 0)
1366                 b43_write16(dev, 0x03E4, 0x3000);
1367
1368         old_channel = phy->channel;
1369         /* Force to channel 7, even if not supported. */
1370         b43_radio_selectchannel(dev, 7, 0);
1371
1372         if (phy->radio_ver != 0x2050) {
1373                 b43_radio_write16(dev, 0x0075, 0x0080);
1374                 b43_radio_write16(dev, 0x0079, 0x0081);
1375         }
1376
1377         b43_radio_write16(dev, 0x0050, 0x0020);
1378         b43_radio_write16(dev, 0x0050, 0x0023);
1379
1380         if (phy->radio_ver == 0x2050) {
1381                 b43_radio_write16(dev, 0x0050, 0x0020);
1382                 b43_radio_write16(dev, 0x005A, 0x0070);
1383         }
1384
1385         b43_radio_write16(dev, 0x005B, 0x007B);
1386         b43_radio_write16(dev, 0x005C, 0x00B0);
1387
1388         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1389
1390         b43_radio_selectchannel(dev, old_channel, 0);
1391
1392         b43_phy_write(dev, 0x0014, 0x0080);
1393         b43_phy_write(dev, 0x0032, 0x00CA);
1394         b43_phy_write(dev, 0x002A, 0x88A3);
1395
1396         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1397
1398         if (phy->radio_ver == 0x2050)
1399                 b43_radio_write16(dev, 0x005D, 0x000D);
1400
1401         b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1402 }
1403
1404 static void b43_phy_initb6(struct b43_wldev *dev)
1405 {
1406         struct b43_phy *phy = &dev->phy;
1407         u16 offset, val;
1408         u8 old_channel;
1409
1410         b43_phy_write(dev, 0x003E, 0x817A);
1411         b43_radio_write16(dev, 0x007A,
1412                           (b43_radio_read16(dev, 0x007A) | 0x0058));
1413         if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1414                 b43_radio_write16(dev, 0x51, 0x37);
1415                 b43_radio_write16(dev, 0x52, 0x70);
1416                 b43_radio_write16(dev, 0x53, 0xB3);
1417                 b43_radio_write16(dev, 0x54, 0x9B);
1418                 b43_radio_write16(dev, 0x5A, 0x88);
1419                 b43_radio_write16(dev, 0x5B, 0x88);
1420                 b43_radio_write16(dev, 0x5D, 0x88);
1421                 b43_radio_write16(dev, 0x5E, 0x88);
1422                 b43_radio_write16(dev, 0x7D, 0x88);
1423                 b43_hf_write(dev, b43_hf_read(dev)
1424                              | B43_HF_TSSIRPSMW);
1425         }
1426         B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7);        /* We had code for these revs here... */
1427         if (phy->radio_rev == 8) {
1428                 b43_radio_write16(dev, 0x51, 0);
1429                 b43_radio_write16(dev, 0x52, 0x40);
1430                 b43_radio_write16(dev, 0x53, 0xB7);
1431                 b43_radio_write16(dev, 0x54, 0x98);
1432                 b43_radio_write16(dev, 0x5A, 0x88);
1433                 b43_radio_write16(dev, 0x5B, 0x6B);
1434                 b43_radio_write16(dev, 0x5C, 0x0F);
1435                 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_ALTIQ) {
1436                         b43_radio_write16(dev, 0x5D, 0xFA);
1437                         b43_radio_write16(dev, 0x5E, 0xD8);
1438                 } else {
1439                         b43_radio_write16(dev, 0x5D, 0xF5);
1440                         b43_radio_write16(dev, 0x5E, 0xB8);
1441                 }
1442                 b43_radio_write16(dev, 0x0073, 0x0003);
1443                 b43_radio_write16(dev, 0x007D, 0x00A8);
1444                 b43_radio_write16(dev, 0x007C, 0x0001);
1445                 b43_radio_write16(dev, 0x007E, 0x0008);
1446         }
1447         val = 0x1E1F;
1448         for (offset = 0x0088; offset < 0x0098; offset++) {
1449                 b43_phy_write(dev, offset, val);
1450                 val -= 0x0202;
1451         }
1452         val = 0x3E3F;
1453         for (offset = 0x0098; offset < 0x00A8; offset++) {
1454                 b43_phy_write(dev, offset, val);
1455                 val -= 0x0202;
1456         }
1457         val = 0x2120;
1458         for (offset = 0x00A8; offset < 0x00C8; offset++) {
1459                 b43_phy_write(dev, offset, (val & 0x3F3F));
1460                 val += 0x0202;
1461         }
1462         if (phy->type == B43_PHYTYPE_G) {
1463                 b43_radio_write16(dev, 0x007A,
1464                                   b43_radio_read16(dev, 0x007A) | 0x0020);
1465                 b43_radio_write16(dev, 0x0051,
1466                                   b43_radio_read16(dev, 0x0051) | 0x0004);
1467                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1468                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1469                 b43_phy_write(dev, 0x5B, 0);
1470                 b43_phy_write(dev, 0x5C, 0);
1471         }
1472
1473         old_channel = phy->channel;
1474         if (old_channel >= 8)
1475                 b43_radio_selectchannel(dev, 1, 0);
1476         else
1477                 b43_radio_selectchannel(dev, 13, 0);
1478
1479         b43_radio_write16(dev, 0x0050, 0x0020);
1480         b43_radio_write16(dev, 0x0050, 0x0023);
1481         udelay(40);
1482         if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1483                 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1484                                               | 0x0002));
1485                 b43_radio_write16(dev, 0x50, 0x20);
1486         }
1487         if (phy->radio_rev <= 2) {
1488                 b43_radio_write16(dev, 0x7C, 0x20);
1489                 b43_radio_write16(dev, 0x5A, 0x70);
1490                 b43_radio_write16(dev, 0x5B, 0x7B);
1491                 b43_radio_write16(dev, 0x5C, 0xB0);
1492         }
1493         b43_radio_write16(dev, 0x007A,
1494                           (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1495
1496         b43_radio_selectchannel(dev, old_channel, 0);
1497
1498         b43_phy_write(dev, 0x0014, 0x0200);
1499         if (phy->radio_rev >= 6)
1500                 b43_phy_write(dev, 0x2A, 0x88C2);
1501         else
1502                 b43_phy_write(dev, 0x2A, 0x8AC0);
1503         b43_phy_write(dev, 0x0038, 0x0668);
1504         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1505         if (phy->radio_rev <= 5) {
1506                 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1507                                           & 0xFF80) | 0x0003);
1508         }
1509         if (phy->radio_rev <= 2)
1510                 b43_radio_write16(dev, 0x005D, 0x000D);
1511
1512         if (phy->analog == 4) {
1513                 b43_write16(dev, 0x3E4, 9);
1514                 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1515                               & 0x0FFF);
1516         } else {
1517                 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1518                               | 0x0004);
1519         }
1520         if (phy->type == B43_PHYTYPE_B) {
1521                 b43_write16(dev, 0x03E6, 0x8140);
1522                 b43_phy_write(dev, 0x0016, 0x0410);
1523                 b43_phy_write(dev, 0x0017, 0x0820);
1524                 b43_phy_write(dev, 0x0062, 0x0007);
1525                 b43_radio_init2050(dev);
1526                 b43_lo_g_measure(dev);
1527                 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI) {
1528                         b43_calc_nrssi_slope(dev);
1529                         b43_calc_nrssi_threshold(dev);
1530                 }
1531                 b43_phy_init_pctl(dev);
1532         } else if (phy->type == B43_PHYTYPE_G)
1533                 b43_write16(dev, 0x03E6, 0x0);
1534 }
1535
1536 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1537 {
1538         struct b43_phy *phy = &dev->phy;
1539         u16 backup_phy[16] = { 0 };
1540         u16 backup_radio[3];
1541         u16 backup_bband;
1542         u16 i, j, loop_i_max;
1543         u16 trsw_rx;
1544         u16 loop1_outer_done, loop1_inner_done;
1545
1546         backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1547         backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1548         backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1549         backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1550         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1551                 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1552                 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1553         }
1554         backup_phy[6] = b43_phy_read(dev, B43_PHY_BASE(0x5A));
1555         backup_phy[7] = b43_phy_read(dev, B43_PHY_BASE(0x59));
1556         backup_phy[8] = b43_phy_read(dev, B43_PHY_BASE(0x58));
1557         backup_phy[9] = b43_phy_read(dev, B43_PHY_BASE(0x0A));
1558         backup_phy[10] = b43_phy_read(dev, B43_PHY_BASE(0x03));
1559         backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1560         backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1561         backup_phy[13] = b43_phy_read(dev, B43_PHY_BASE(0x2B));
1562         backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1563         backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1564         backup_bband = phy->bbatt.att;
1565         backup_radio[0] = b43_radio_read16(dev, 0x52);
1566         backup_radio[1] = b43_radio_read16(dev, 0x43);
1567         backup_radio[2] = b43_radio_read16(dev, 0x7A);
1568
1569         b43_phy_write(dev, B43_PHY_CRS0,
1570                       b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1571         b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1572                       b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1573         b43_phy_write(dev, B43_PHY_RFOVER,
1574                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1575         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1576                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1577         b43_phy_write(dev, B43_PHY_RFOVER,
1578                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1579         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1580                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1581         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1582                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1583                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1584                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1585                               b43_phy_read(dev,
1586                                            B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1587                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1588                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1589                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1590                               b43_phy_read(dev,
1591                                            B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1592         }
1593         b43_phy_write(dev, B43_PHY_RFOVER,
1594                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1595         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1596                       b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1597         b43_phy_write(dev, B43_PHY_RFOVER,
1598                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1599         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1600                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1601                        & 0xFFCF) | 0x10);
1602
1603         b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0780);
1604         b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
1605         b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
1606
1607         b43_phy_write(dev, B43_PHY_BASE(0x0A),
1608                       b43_phy_read(dev, B43_PHY_BASE(0x0A)) | 0x2000);
1609         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1610                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1611                               b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1612                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1613                               b43_phy_read(dev,
1614                                            B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1615         }
1616         b43_phy_write(dev, B43_PHY_BASE(0x03),
1617                       (b43_phy_read(dev, B43_PHY_BASE(0x03))
1618                        & 0xFF9F) | 0x40);
1619
1620         if (phy->radio_rev == 8) {
1621                 b43_radio_write16(dev, 0x43, 0x000F);
1622         } else {
1623                 b43_radio_write16(dev, 0x52, 0);
1624                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1625                                               & 0xFFF0) | 0x9);
1626         }
1627         b43_phy_set_baseband_attenuation(dev, 11);
1628
1629         if (phy->rev >= 3)
1630                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1631         else
1632                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1633         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1634
1635         b43_phy_write(dev, B43_PHY_BASE(0x2B),
1636                       (b43_phy_read(dev, B43_PHY_BASE(0x2B))
1637                        & 0xFFC0) | 0x01);
1638         b43_phy_write(dev, B43_PHY_BASE(0x2B),
1639                       (b43_phy_read(dev, B43_PHY_BASE(0x2B))
1640                        & 0xC0FF) | 0x800);
1641
1642         b43_phy_write(dev, B43_PHY_RFOVER,
1643                       b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1644         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1645                       b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1646
1647         if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_EXTLNA) {
1648                 if (phy->rev >= 7) {
1649                         b43_phy_write(dev, B43_PHY_RFOVER,
1650                                       b43_phy_read(dev, B43_PHY_RFOVER)
1651                                       | 0x0800);
1652                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1653                                       b43_phy_read(dev, B43_PHY_RFOVERVAL)
1654                                       | 0x8000);
1655                 }
1656         }
1657         b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1658                           & 0x00F7);
1659
1660         j = 0;
1661         loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1662         for (i = 0; i < loop_i_max; i++) {
1663                 for (j = 0; j < 16; j++) {
1664                         b43_radio_write16(dev, 0x43, i);
1665                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1666                                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1667                                        & 0xF0FF) | (j << 8));
1668                         b43_phy_write(dev, B43_PHY_PGACTL,
1669                                       (b43_phy_read(dev, B43_PHY_PGACTL)
1670                                        & 0x0FFF) | 0xA000);
1671                         b43_phy_write(dev, B43_PHY_PGACTL,
1672                                       b43_phy_read(dev, B43_PHY_PGACTL)
1673                                       | 0xF000);
1674                         udelay(20);
1675                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1676                                 goto exit_loop1;
1677                 }
1678         }
1679       exit_loop1:
1680         loop1_outer_done = i;
1681         loop1_inner_done = j;
1682         if (j >= 8) {
1683                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1684                               b43_phy_read(dev, B43_PHY_RFOVERVAL)
1685                               | 0x30);
1686                 trsw_rx = 0x1B;
1687                 for (j = j - 8; j < 16; j++) {
1688                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1689                                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1690                                        & 0xF0FF) | (j << 8));
1691                         b43_phy_write(dev, B43_PHY_PGACTL,
1692                                       (b43_phy_read(dev, B43_PHY_PGACTL)
1693                                        & 0x0FFF) | 0xA000);
1694                         b43_phy_write(dev, B43_PHY_PGACTL,
1695                                       b43_phy_read(dev, B43_PHY_PGACTL)
1696                                       | 0xF000);
1697                         udelay(20);
1698                         trsw_rx -= 3;
1699                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1700                                 goto exit_loop2;
1701                 }
1702         } else
1703                 trsw_rx = 0x18;
1704       exit_loop2:
1705
1706         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1707                 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1708                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1709         }
1710         b43_phy_write(dev, B43_PHY_BASE(0x5A), backup_phy[6]);
1711         b43_phy_write(dev, B43_PHY_BASE(0x59), backup_phy[7]);
1712         b43_phy_write(dev, B43_PHY_BASE(0x58), backup_phy[8]);
1713         b43_phy_write(dev, B43_PHY_BASE(0x0A), backup_phy[9]);
1714         b43_phy_write(dev, B43_PHY_BASE(0x03), backup_phy[10]);
1715         b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1716         b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1717         b43_phy_write(dev, B43_PHY_BASE(0x2B), backup_phy[13]);
1718         b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1719
1720         b43_phy_set_baseband_attenuation(dev, backup_bband);
1721
1722         b43_radio_write16(dev, 0x52, backup_radio[0]);
1723         b43_radio_write16(dev, 0x43, backup_radio[1]);
1724         b43_radio_write16(dev, 0x7A, backup_radio[2]);
1725
1726         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1727         udelay(10);
1728         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1729         b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1730         b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1731         b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1732
1733         phy->max_lb_gain =
1734             ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1735         phy->trsw_rx_gain = trsw_rx * 2;
1736 }
1737
1738 static void b43_phy_initg(struct b43_wldev *dev)
1739 {
1740         struct b43_phy *phy = &dev->phy;
1741         u16 tmp;
1742
1743         if (phy->rev == 1)
1744                 b43_phy_initb5(dev);
1745         else
1746                 b43_phy_initb6(dev);
1747
1748         if (phy->rev >= 2 || phy->gmode)
1749                 b43_phy_inita(dev);
1750
1751         if (phy->rev >= 2) {
1752                 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
1753                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
1754         }
1755         if (phy->rev == 2) {
1756                 b43_phy_write(dev, B43_PHY_RFOVER, 0);
1757                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1758         }
1759         if (phy->rev > 5) {
1760                 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
1761                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1762         }
1763         if (phy->gmode || phy->rev >= 2) {
1764                 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
1765                 tmp &= B43_PHYVER_VERSION;
1766                 if (tmp == 3 || tmp == 5) {
1767                         b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
1768                         b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
1769                 }
1770                 if (tmp == 5) {
1771                         b43_phy_write(dev, B43_PHY_OFDM(0xCC),
1772                                       (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
1773                                        & 0x00FF) | 0x1F00);
1774                 }
1775         }
1776         if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
1777                 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
1778         if (phy->radio_rev == 8) {
1779                 b43_phy_write(dev, B43_PHY_EXTG(0x01),
1780                               b43_phy_read(dev, B43_PHY_EXTG(0x01))
1781                               | 0x80);
1782                 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
1783                               b43_phy_read(dev, B43_PHY_OFDM(0x3E))
1784                               | 0x4);
1785         }
1786         if (has_loopback_gain(phy))
1787                 b43_calc_loopback_gain(dev);
1788
1789         if (phy->radio_rev != 8) {
1790                 if (phy->initval == 0xFFFF)
1791                         phy->initval = b43_radio_init2050(dev);
1792                 else
1793                         b43_radio_write16(dev, 0x0078, phy->initval);
1794         }
1795         if (phy->lo_control->tx_bias == 0xFF) {
1796                 b43_lo_g_measure(dev);
1797         } else {
1798                 if (has_tx_magnification(phy)) {
1799                         b43_radio_write16(dev, 0x52,
1800                                           (b43_radio_read16(dev, 0x52) & 0xFF00)
1801                                           | phy->lo_control->tx_bias | phy->
1802                                           lo_control->tx_magn);
1803                 } else {
1804                         b43_radio_write16(dev, 0x52,
1805                                           (b43_radio_read16(dev, 0x52) & 0xFFF0)
1806                                           | phy->lo_control->tx_bias);
1807                 }
1808                 if (phy->rev >= 6) {
1809                         b43_phy_write(dev, B43_PHY_BASE(0x36),
1810                                       (b43_phy_read(dev, B43_PHY_BASE(0x36))
1811                                        & 0x0FFF) | (phy->lo_control->
1812                                                     tx_bias << 12));
1813                 }
1814                 if (dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_PACTRL)
1815                         b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x8075);
1816                 else
1817                         b43_phy_write(dev, B43_PHY_BASE(0x2E), 0x807F);
1818                 if (phy->rev < 2)
1819                         b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x101);
1820                 else
1821                         b43_phy_write(dev, B43_PHY_BASE(0x2F), 0x202);
1822         }
1823         if (phy->gmode || phy->rev >= 2) {
1824                 b43_lo_g_adjust(dev);
1825                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
1826         }
1827
1828         if (!(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
1829                 /* The specs state to update the NRSSI LT with
1830                  * the value 0x7FFFFFFF here. I think that is some weird
1831                  * compiler optimization in the original driver.
1832                  * Essentially, what we do here is resetting all NRSSI LT
1833                  * entries to -32 (see the limit_value() in nrssi_hw_update())
1834                  */
1835                 b43_nrssi_hw_update(dev, 0xFFFF);       //FIXME?
1836                 b43_calc_nrssi_threshold(dev);
1837         } else if (phy->gmode || phy->rev >= 2) {
1838                 if (phy->nrssi[0] == -1000) {
1839                         B43_WARN_ON(phy->nrssi[1] != -1000);
1840                         b43_calc_nrssi_slope(dev);
1841                 } else
1842                         b43_calc_nrssi_threshold(dev);
1843         }
1844         if (phy->radio_rev == 8)
1845                 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
1846         b43_phy_init_pctl(dev);
1847         /* FIXME: The spec says in the following if, the 0 should be replaced
1848            'if OFDM may not be used in the current locale'
1849            but OFDM is legal everywhere */
1850         if ((dev->dev->bus->chip_id == 0x4306
1851              && dev->dev->bus->chip_package == 2) || 0) {
1852                 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1853                               & 0xBFFF);
1854                 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
1855                               b43_phy_read(dev, B43_PHY_OFDM(0xC3))
1856                               & 0x7FFF);
1857         }
1858 }
1859
1860 /* Set the baseband attenuation value on chip. */
1861 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
1862                                       u16 baseband_attenuation)
1863 {
1864         struct b43_phy *phy = &dev->phy;
1865
1866         if (phy->analog == 0) {
1867                 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
1868                                                  & 0xFFF0) |
1869                             baseband_attenuation);
1870         } else if (phy->analog > 1) {
1871                 b43_phy_write(dev, B43_PHY_DACCTL,
1872                               (b43_phy_read(dev, B43_PHY_DACCTL)
1873                                & 0xFFC3) | (baseband_attenuation << 2));
1874         } else {
1875                 b43_phy_write(dev, B43_PHY_DACCTL,
1876                               (b43_phy_read(dev, B43_PHY_DACCTL)
1877                                & 0xFF87) | (baseband_attenuation << 3));
1878         }
1879 }
1880
1881 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1882  * This function converts a TSSI value to dBm in Q5.2
1883  */
1884 static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
1885 {
1886         struct b43_phy *phy = &dev->phy;
1887         s8 dbm = 0;
1888         s32 tmp;
1889
1890         tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
1891
1892         switch (phy->type) {
1893         case B43_PHYTYPE_A:
1894                 tmp += 0x80;
1895                 tmp = limit_value(tmp, 0x00, 0xFF);
1896                 dbm = phy->tssi2dbm[tmp];
1897                 //TODO: There's a FIXME on the specs
1898                 break;
1899         case B43_PHYTYPE_B:
1900         case B43_PHYTYPE_G:
1901                 tmp = limit_value(tmp, 0x00, 0x3F);
1902                 dbm = phy->tssi2dbm[tmp];
1903                 break;
1904         default:
1905                 B43_WARN_ON(1);
1906         }
1907
1908         return dbm;
1909 }
1910
1911 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
1912                                      int *_bbatt, int *_rfatt)
1913 {
1914         int rfatt = *_rfatt;
1915         int bbatt = *_bbatt;
1916         struct b43_txpower_lo_control *lo = dev->phy.lo_control;
1917
1918         /* Get baseband and radio attenuation values into their permitted ranges.
1919          * Radio attenuation affects power level 4 times as much as baseband. */
1920
1921         /* Range constants */
1922         const int rf_min = lo->rfatt_list.min_val;
1923         const int rf_max = lo->rfatt_list.max_val;
1924         const int bb_min = lo->bbatt_list.min_val;
1925         const int bb_max = lo->bbatt_list.max_val;
1926
1927         while (1) {
1928                 if (rfatt > rf_max && bbatt > bb_max - 4)
1929                         break;  /* Can not get it into ranges */
1930                 if (rfatt < rf_min && bbatt < bb_min + 4)
1931                         break;  /* Can not get it into ranges */
1932                 if (bbatt > bb_max && rfatt > rf_max - 1)
1933                         break;  /* Can not get it into ranges */
1934                 if (bbatt < bb_min && rfatt < rf_min + 1)
1935                         break;  /* Can not get it into ranges */
1936
1937                 if (bbatt > bb_max) {
1938                         bbatt -= 4;
1939                         rfatt += 1;
1940                         continue;
1941                 }
1942                 if (bbatt < bb_min) {
1943                         bbatt += 4;
1944                         rfatt -= 1;
1945                         continue;
1946                 }
1947                 if (rfatt > rf_max) {
1948                         rfatt -= 1;
1949                         bbatt += 4;
1950                         continue;
1951                 }
1952                 if (rfatt < rf_min) {
1953                         rfatt += 1;
1954                         bbatt -= 4;
1955                         continue;
1956                 }
1957                 break;
1958         }
1959
1960         *_rfatt = limit_value(rfatt, rf_min, rf_max);
1961         *_bbatt = limit_value(bbatt, bb_min, bb_max);
1962 }
1963
1964 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1965 void b43_phy_xmitpower(struct b43_wldev *dev)
1966 {
1967         struct ssb_bus *bus = dev->dev->bus;
1968         struct b43_phy *phy = &dev->phy;
1969
1970         if (phy->cur_idle_tssi == 0)
1971                 return;
1972         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1973             (bus->boardinfo.type == SSB_BOARD_BU4306))
1974                 return;
1975 #ifdef CONFIG_B43_DEBUG
1976         if (phy->manual_txpower_control)
1977                 return;
1978 #endif
1979
1980         switch (phy->type) {
1981         case B43_PHYTYPE_A:{
1982
1983                         //TODO: Nothing for A PHYs yet :-/
1984
1985                         break;
1986                 }
1987         case B43_PHYTYPE_B:
1988         case B43_PHYTYPE_G:{
1989                         u16 tmp;
1990                         s8 v0, v1, v2, v3;
1991                         s8 average;
1992                         int max_pwr;
1993                         int desired_pwr, estimated_pwr, pwr_adjust;
1994                         int rfatt_delta, bbatt_delta;
1995                         int rfatt, bbatt;
1996                         u8 tx_control;
1997                         unsigned long phylock_flags;
1998
1999                         tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
2000                         v0 = (s8) (tmp & 0x00FF);
2001                         v1 = (s8) ((tmp & 0xFF00) >> 8);
2002                         tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
2003                         v2 = (s8) (tmp & 0x00FF);
2004                         v3 = (s8) ((tmp & 0xFF00) >> 8);
2005                         tmp = 0;
2006
2007                         if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
2008                             || v3 == 0x7F) {
2009                                 tmp =
2010                                     b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
2011                                 v0 = (s8) (tmp & 0x00FF);
2012                                 v1 = (s8) ((tmp & 0xFF00) >> 8);
2013                                 tmp =
2014                                     b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
2015                                 v2 = (s8) (tmp & 0x00FF);
2016                                 v3 = (s8) ((tmp & 0xFF00) >> 8);
2017                                 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
2018                                     || v3 == 0x7F)
2019                                         return;
2020                                 v0 = (v0 + 0x20) & 0x3F;
2021                                 v1 = (v1 + 0x20) & 0x3F;
2022                                 v2 = (v2 + 0x20) & 0x3F;
2023                                 v3 = (v3 + 0x20) & 0x3F;
2024                                 tmp = 1;
2025                         }
2026                         b43_shm_clear_tssi(dev);
2027
2028                         average = (v0 + v1 + v2 + v3 + 2) / 4;
2029
2030                         if (tmp
2031                             && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) &
2032                                 0x8))
2033                                 average -= 13;
2034
2035                         estimated_pwr =
2036                             b43_phy_estimate_power_out(dev, average);
2037
2038                         max_pwr = dev->dev->bus->sprom.r1.maxpwr_bg;
2039                         if ((dev->dev->bus->sprom.r1.
2040                              boardflags_lo & B43_BFL_PACTRL)
2041                             && (phy->type == B43_PHYTYPE_G))
2042                                 max_pwr -= 0x3;
2043                         if (unlikely(max_pwr <= 0)) {
2044                                 b43warn(dev->wl,
2045                                         "Invalid max-TX-power value in SPROM.\n");
2046                                 max_pwr = 60;   /* fake it */
2047                                 dev->dev->bus->sprom.r1.maxpwr_bg = max_pwr;
2048                         }
2049
2050                         /*TODO:
2051                            max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
2052                            where REG is the max power as per the regulatory domain
2053                          */
2054
2055                         /* Get desired power (in Q5.2) */
2056                         desired_pwr = INT_TO_Q52(phy->power_level);
2057                         /* And limit it. max_pwr already is Q5.2 */
2058                         desired_pwr = limit_value(desired_pwr, 0, max_pwr);
2059                         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2060                                 b43dbg(dev->wl,
2061                                        "Current TX power output: " Q52_FMT
2062                                        " dBm, " "Desired TX power output: "
2063                                        Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
2064                                        Q52_ARG(desired_pwr));
2065                         }
2066
2067                         /* Calculate the adjustment delta. */
2068                         pwr_adjust = desired_pwr - estimated_pwr;
2069
2070                         /* RF attenuation delta. */
2071                         rfatt_delta = ((pwr_adjust + 7) / 8);
2072                         /* Lower attenuation => Bigger power output. Negate it. */
2073                         rfatt_delta = -rfatt_delta;
2074
2075                         /* Baseband attenuation delta. */
2076                         bbatt_delta = pwr_adjust / 2;
2077                         /* Lower attenuation => Bigger power output. Negate it. */
2078                         bbatt_delta = -bbatt_delta;
2079                         /* RF att affects power level 4 times as much as
2080                          * Baseband attennuation. Subtract it. */
2081                         bbatt_delta -= 4 * rfatt_delta;
2082
2083                         /* So do we finally need to adjust something? */
2084                         if ((rfatt_delta == 0) && (bbatt_delta == 0)) {
2085                                 b43_lo_g_ctl_mark_cur_used(dev);
2086                                 return;
2087                         }
2088
2089                         /* Calculate the new attenuation values. */
2090                         bbatt = phy->bbatt.att;
2091                         bbatt += bbatt_delta;
2092                         rfatt = phy->rfatt.att;
2093                         rfatt += rfatt_delta;
2094
2095                         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2096                         tx_control = phy->tx_control;
2097                         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2098                                 if (rfatt <= 1) {
2099                                         if (tx_control == 0) {
2100                                                 tx_control =
2101                                                     B43_TXCTL_PA2DB |
2102                                                     B43_TXCTL_TXMIX;
2103                                                 rfatt += 2;
2104                                                 bbatt += 2;
2105                                         } else if (dev->dev->bus->sprom.r1.
2106                                                    boardflags_lo &
2107                                                    B43_BFL_PACTRL) {
2108                                                 bbatt += 4 * (rfatt - 2);
2109                                                 rfatt = 2;
2110                                         }
2111                                 } else if (rfatt > 4 && tx_control) {
2112                                         tx_control = 0;
2113                                         if (bbatt < 3) {
2114                                                 rfatt -= 3;
2115                                                 bbatt += 2;
2116                                         } else {
2117                                                 rfatt -= 2;
2118                                                 bbatt -= 2;
2119                                         }
2120                                 }
2121                         }
2122                         /* Save the control values */
2123                         phy->tx_control = tx_control;
2124                         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2125                         phy->rfatt.att = rfatt;
2126                         phy->bbatt.att = bbatt;
2127
2128                         /* Adjust the hardware */
2129                         b43_phy_lock(dev, phylock_flags);
2130                         b43_radio_lock(dev);
2131                         b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
2132                                           phy->tx_control);
2133                         b43_lo_g_ctl_mark_cur_used(dev);
2134                         b43_radio_unlock(dev);
2135                         b43_phy_unlock(dev, phylock_flags);
2136                         break;
2137                 }
2138         default:
2139                 B43_WARN_ON(1);
2140         }
2141 }
2142
2143 static inline s32 b43_tssi2dbm_ad(s32 num, s32 den)
2144 {
2145         if (num < 0)
2146                 return num / den;
2147         else
2148                 return (num + den / 2) / den;
2149 }
2150
2151 static inline
2152     s8 b43_tssi2dbm_entry(s8 entry[], u8 index, s16 pab0, s16 pab1, s16 pab2)
2153 {
2154         s32 m1, m2, f = 256, q, delta;
2155         s8 i = 0;
2156
2157         m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2158         m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2159         do {
2160                 if (i > 15)
2161                         return -EINVAL;
2162                 q = b43_tssi2dbm_ad(f * 4096 -
2163                                     b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2164                 delta = abs(q - f);
2165                 f = q;
2166                 i++;
2167         } while (delta >= 2);
2168         entry[index] = limit_value(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2169         return 0;
2170 }
2171
2172 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
2173 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
2174 {
2175         struct b43_phy *phy = &dev->phy;
2176         s16 pab0, pab1, pab2;
2177         u8 idx;
2178         s8 *dyn_tssi2dbm;
2179
2180         if (phy->type == B43_PHYTYPE_A) {
2181                 pab0 = (s16) (dev->dev->bus->sprom.r1.pa1b0);
2182                 pab1 = (s16) (dev->dev->bus->sprom.r1.pa1b1);
2183                 pab2 = (s16) (dev->dev->bus->sprom.r1.pa1b2);
2184         } else {
2185                 pab0 = (s16) (dev->dev->bus->sprom.r1.pa0b0);
2186                 pab1 = (s16) (dev->dev->bus->sprom.r1.pa0b1);
2187                 pab2 = (s16) (dev->dev->bus->sprom.r1.pa0b2);
2188         }
2189
2190         if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
2191                 phy->tgt_idle_tssi = 0x34;
2192                 phy->tssi2dbm = b43_tssi2dbm_b_table;
2193                 return 0;
2194         }
2195
2196         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2197             pab0 != -1 && pab1 != -1 && pab2 != -1) {
2198                 /* The pabX values are set in SPROM. Use them. */
2199                 if (phy->type == B43_PHYTYPE_A) {
2200                         if ((s8) dev->dev->bus->sprom.r1.itssi_a != 0 &&
2201                             (s8) dev->dev->bus->sprom.r1.itssi_a != -1)
2202                                 phy->tgt_idle_tssi =
2203                                     (s8) (dev->dev->bus->sprom.r1.itssi_a);
2204                         else
2205                                 phy->tgt_idle_tssi = 62;
2206                 } else {
2207                         if ((s8) dev->dev->bus->sprom.r1.itssi_bg != 0 &&
2208                             (s8) dev->dev->bus->sprom.r1.itssi_bg != -1)
2209                                 phy->tgt_idle_tssi =
2210                                     (s8) (dev->dev->bus->sprom.r1.itssi_bg);
2211                         else
2212                                 phy->tgt_idle_tssi = 62;
2213                 }
2214                 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
2215                 if (dyn_tssi2dbm == NULL) {
2216                         b43err(dev->wl, "Could not allocate memory"
2217                                "for tssi2dbm table\n");
2218                         return -ENOMEM;
2219                 }
2220                 for (idx = 0; idx < 64; idx++)
2221                         if (b43_tssi2dbm_entry
2222                             (dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
2223                                 phy->tssi2dbm = NULL;
2224                                 b43err(dev->wl, "Could not generate "
2225                                        "tssi2dBm table\n");
2226                                 kfree(dyn_tssi2dbm);
2227                                 return -ENODEV;
2228                         }
2229                 phy->tssi2dbm = dyn_tssi2dbm;
2230                 phy->dyn_tssi_tbl = 1;
2231         } else {
2232                 /* pabX values not set in SPROM. */
2233                 switch (phy->type) {
2234                 case B43_PHYTYPE_A:
2235                         /* APHY needs a generated table. */
2236                         phy->tssi2dbm = NULL;
2237                         b43err(dev->wl, "Could not generate tssi2dBm "
2238                                "table (wrong SPROM info)!\n");
2239                         return -ENODEV;
2240                 case B43_PHYTYPE_B:
2241                         phy->tgt_idle_tssi = 0x34;
2242                         phy->tssi2dbm = b43_tssi2dbm_b_table;
2243                         break;
2244                 case B43_PHYTYPE_G:
2245                         phy->tgt_idle_tssi = 0x34;
2246                         phy->tssi2dbm = b43_tssi2dbm_g_table;
2247                         break;
2248                 }
2249         }
2250
2251         return 0;
2252 }
2253
2254 int b43_phy_init(struct b43_wldev *dev)
2255 {
2256         struct b43_phy *phy = &dev->phy;
2257         int err = -ENODEV;
2258
2259         switch (phy->type) {
2260         case B43_PHYTYPE_A:
2261                 if (phy->rev == 2 || phy->rev == 3) {
2262                         b43_phy_inita(dev);
2263                         err = 0;
2264                 }
2265                 break;
2266         case B43_PHYTYPE_B:
2267                 switch (phy->rev) {
2268                 case 2:
2269                         b43_phy_initb2(dev);
2270                         err = 0;
2271                         break;
2272                 case 4:
2273                         b43_phy_initb4(dev);
2274                         err = 0;
2275                         break;
2276                 case 5:
2277                         b43_phy_initb5(dev);
2278                         err = 0;
2279                         break;
2280                 case 6:
2281                         b43_phy_initb6(dev);
2282                         err = 0;
2283                         break;
2284                 }
2285                 break;
2286         case B43_PHYTYPE_G:
2287                 b43_phy_initg(dev);
2288                 err = 0;
2289                 break;
2290         }
2291         if (err)
2292                 b43err(dev->wl, "Unknown PHYTYPE found\n");
2293
2294         return err;
2295 }
2296
2297 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
2298 {
2299         struct b43_phy *phy = &dev->phy;
2300         u32 hf;
2301         u16 tmp;
2302         int autodiv = 0;
2303
2304         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2305                 autodiv = 1;
2306
2307         hf = b43_hf_read(dev);
2308         hf &= ~B43_HF_ANTDIVHELP;
2309         b43_hf_write(dev, hf);
2310
2311         switch (phy->type) {
2312         case B43_PHYTYPE_A:
2313         case B43_PHYTYPE_G:
2314                 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2315                 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2316                 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2317                     << B43_PHY_BBANDCFG_RXANT_SHIFT;
2318                 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2319
2320                 if (autodiv) {
2321                         tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2322                         if (antenna == B43_ANTENNA_AUTO0)
2323                                 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2324                         else
2325                                 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2326                         b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2327                 }
2328                 if (phy->type == B43_PHYTYPE_G) {
2329                         tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2330                         if (autodiv)
2331                                 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2332                         else
2333                                 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2334                         b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2335                         if (phy->rev >= 2) {
2336                                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2337                                 tmp |= B43_PHY_OFDM61_10;
2338                                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2339
2340                                 tmp =
2341                                     b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2342                                 tmp = (tmp & 0xFF00) | 0x15;
2343                                 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2344                                               tmp);
2345
2346                                 if (phy->rev == 2) {
2347                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2348                                                       8);
2349                                 } else {
2350                                         tmp =
2351                                             b43_phy_read(dev,
2352                                                          B43_PHY_ADIVRELATED);
2353                                         tmp = (tmp & 0xFF00) | 8;
2354                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2355                                                       tmp);
2356                                 }
2357                         }
2358                         if (phy->rev >= 6)
2359                                 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2360                 } else {
2361                         if (phy->rev < 3) {
2362                                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2363                                 tmp = (tmp & 0xFF00) | 0x24;
2364                                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2365                         } else {
2366                                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2367                                 tmp |= 0x10;
2368                                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2369                                 if (phy->analog == 3) {
2370                                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2371                                                       0x1D);
2372                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2373                                                       8);
2374                                 } else {
2375                                         b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2376                                                       0x3A);
2377                                         tmp =
2378                                             b43_phy_read(dev,
2379                                                          B43_PHY_ADIVRELATED);
2380                                         tmp = (tmp & 0xFF00) | 8;
2381                                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2382                                                       tmp);
2383                                 }
2384                         }
2385                 }
2386                 break;
2387         case B43_PHYTYPE_B:
2388                 tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
2389                 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2390                 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2391                     << B43_PHY_BBANDCFG_RXANT_SHIFT;
2392                 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
2393                 break;
2394         default:
2395                 B43_WARN_ON(1);
2396         }
2397
2398         hf |= B43_HF_ANTDIVHELP;
2399         b43_hf_write(dev, hf);
2400 }
2401
2402 /* Get the freq, as it has to be written to the device. */
2403 static inline u16 channel2freq_bg(u8 channel)
2404 {
2405         B43_WARN_ON(!(channel >= 1 && channel <= 14));
2406
2407         return b43_radio_channel_codes_bg[channel - 1];
2408 }
2409
2410 /* Get the freq, as it has to be written to the device. */
2411 static inline u16 channel2freq_a(u8 channel)
2412 {
2413         B43_WARN_ON(channel > 200);
2414
2415         return (5000 + 5 * channel);
2416 }
2417
2418 void b43_radio_lock(struct b43_wldev *dev)
2419 {
2420         u32 macctl;
2421
2422         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2423         macctl |= B43_MACCTL_RADIOLOCK;
2424         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2425         /* Commit the write and wait for the device
2426          * to exit any radio register access. */
2427         b43_read32(dev, B43_MMIO_MACCTL);
2428         udelay(10);
2429 }
2430
2431 void b43_radio_unlock(struct b43_wldev *dev)
2432 {
2433         u32 macctl;
2434
2435         /* Commit any write */
2436         b43_read16(dev, B43_MMIO_PHY_VER);
2437         /* unlock */
2438         macctl = b43_read32(dev, B43_MMIO_MACCTL);
2439         macctl &= ~B43_MACCTL_RADIOLOCK;
2440         b43_write32(dev, B43_MMIO_MACCTL, macctl);
2441 }
2442
2443 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2444 {
2445         struct b43_phy *phy = &dev->phy;
2446
2447         switch (phy->type) {
2448         case B43_PHYTYPE_A:
2449                 offset |= 0x0040;
2450                 break;
2451         case B43_PHYTYPE_B:
2452                 if (phy->radio_ver == 0x2053) {
2453                         if (offset < 0x70)
2454                                 offset += 0x80;
2455                         else if (offset < 0x80)
2456                                 offset += 0x70;
2457                 } else if (phy->radio_ver == 0x2050) {
2458                         offset |= 0x80;
2459                 } else
2460                         B43_WARN_ON(1);
2461                 break;
2462         case B43_PHYTYPE_G:
2463                 offset |= 0x80;
2464                 break;
2465         }
2466
2467         b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2468         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2469 }
2470
2471 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2472 {
2473         b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2474         mmiowb();
2475         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2476 }
2477
2478 static void b43_set_all_gains(struct b43_wldev *dev,
2479                               s16 first, s16 second, s16 third)
2480 {
2481         struct b43_phy *phy = &dev->phy;
2482         u16 i;
2483         u16 start = 0x08, end = 0x18;
2484         u16 tmp;
2485         u16 table;
2486
2487         if (phy->rev <= 1) {
2488                 start = 0x10;
2489                 end = 0x20;
2490         }
2491
2492         table = B43_OFDMTAB_GAINX;
2493         if (phy->rev <= 1)
2494                 table = B43_OFDMTAB_GAINX_R1;
2495         for (i = 0; i < 4; i++)
2496                 b43_ofdmtab_write16(dev, table, i, first);
2497
2498         for (i = start; i < end; i++)
2499                 b43_ofdmtab_write16(dev, table, i, second);
2500
2501         if (third != -1) {
2502                 tmp = ((u16) third << 14) | ((u16) third << 6);
2503                 b43_phy_write(dev, 0x04A0,
2504                               (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
2505                 b43_phy_write(dev, 0x04A1,
2506                               (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
2507                 b43_phy_write(dev, 0x04A2,
2508                               (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
2509         }
2510         b43_dummy_transmission(dev);
2511 }
2512
2513 static void b43_set_original_gains(struct b43_wldev *dev)
2514 {
2515         struct b43_phy *phy = &dev->phy;
2516         u16 i, tmp;
2517         u16 table;
2518         u16 start = 0x0008, end = 0x0018;
2519
2520         if (phy->rev <= 1) {
2521                 start = 0x0010;
2522                 end = 0x0020;
2523         }
2524
2525         table = B43_OFDMTAB_GAINX;
2526         if (phy->rev <= 1)
2527                 table = B43_OFDMTAB_GAINX_R1;
2528         for (i = 0; i < 4; i++) {
2529                 tmp = (i & 0xFFFC);
2530                 tmp |= (i & 0x0001) << 1;
2531                 tmp |= (i & 0x0002) >> 1;
2532
2533                 b43_ofdmtab_write16(dev, table, i, tmp);
2534         }
2535
2536         for (i = start; i < end; i++)
2537                 b43_ofdmtab_write16(dev, table, i, i - start);
2538
2539         b43_phy_write(dev, 0x04A0,
2540                       (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
2541         b43_phy_write(dev, 0x04A1,
2542                       (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
2543         b43_phy_write(dev, 0x04A2,
2544                       (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
2545         b43_dummy_transmission(dev);
2546 }
2547
2548 /* Synthetic PU workaround */
2549 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
2550 {
2551         struct b43_phy *phy = &dev->phy;
2552
2553         might_sleep();
2554
2555         if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
2556                 /* We do not need the workaround. */
2557                 return;
2558         }
2559
2560         if (channel <= 10) {
2561                 b43_write16(dev, B43_MMIO_CHANNEL,
2562                             channel2freq_bg(channel + 4));
2563         } else {
2564                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
2565         }
2566         msleep(1);
2567         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2568 }
2569
2570 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
2571 {
2572         struct b43_phy *phy = &dev->phy;
2573         u8 ret = 0;
2574         u16 saved, rssi, temp;
2575         int i, j = 0;
2576
2577         saved = b43_phy_read(dev, 0x0403);
2578         b43_radio_selectchannel(dev, channel, 0);
2579         b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2580         if (phy->aci_hw_rssi)
2581                 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2582         else
2583                 rssi = saved & 0x3F;
2584         /* clamp temp to signed 5bit */
2585         if (rssi > 32)
2586                 rssi -= 64;
2587         for (i = 0; i < 100; i++) {
2588                 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2589                 if (temp > 32)
2590                         temp -= 64;
2591                 if (temp < rssi)
2592                         j++;
2593                 if (j >= 20)
2594                         ret = 1;
2595         }
2596         b43_phy_write(dev, 0x0403, saved);
2597
2598         return ret;
2599 }
2600
2601 u8 b43_radio_aci_scan(struct b43_wldev * dev)
2602 {
2603         struct b43_phy *phy = &dev->phy;
2604         u8 ret[13];
2605         unsigned int channel = phy->channel;
2606         unsigned int i, j, start, end;
2607         unsigned long phylock_flags;
2608
2609         if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2610                 return 0;
2611
2612         b43_phy_lock(dev, phylock_flags);
2613         b43_radio_lock(dev);
2614         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2615         b43_phy_write(dev, B43_PHY_G_CRS,
2616                       b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2617         b43_set_all_gains(dev, 3, 8, 1);
2618
2619         start = (channel - 5 > 0) ? channel - 5 : 1;
2620         end = (channel + 5 < 14) ? channel + 5 : 13;
2621
2622         for (i = start; i <= end; i++) {
2623                 if (abs(channel - i) > 2)
2624                         ret[i - 1] = b43_radio_aci_detect(dev, i);
2625         }
2626         b43_radio_selectchannel(dev, channel, 0);
2627         b43_phy_write(dev, 0x0802,
2628                       (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2629         b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2630         b43_phy_write(dev, B43_PHY_G_CRS,
2631                       b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2632         b43_set_original_gains(dev);
2633         for (i = 0; i < 13; i++) {
2634                 if (!ret[i])
2635                         continue;
2636                 end = (i + 5 < 13) ? i + 5 : 13;
2637                 for (j = i; j < end; j++)
2638                         ret[j] = 1;
2639         }
2640         b43_radio_unlock(dev);
2641         b43_phy_unlock(dev, phylock_flags);
2642
2643         return ret[channel - 1];
2644 }
2645
2646 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2647 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
2648 {
2649         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2650         mmiowb();
2651         b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
2652 }
2653
2654 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2655 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
2656 {
2657         u16 val;
2658
2659         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2660         val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
2661
2662         return (s16) val;
2663 }
2664
2665 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2666 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
2667 {
2668         u16 i;
2669         s16 tmp;
2670
2671         for (i = 0; i < 64; i++) {
2672                 tmp = b43_nrssi_hw_read(dev, i);
2673                 tmp -= val;
2674                 tmp = limit_value(tmp, -32, 31);
2675                 b43_nrssi_hw_write(dev, i, tmp);
2676         }
2677 }
2678
2679 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2680 void b43_nrssi_mem_update(struct b43_wldev *dev)
2681 {
2682         struct b43_phy *phy = &dev->phy;
2683         s16 i, delta;
2684         s32 tmp;
2685
2686         delta = 0x1F - phy->nrssi[0];
2687         for (i = 0; i < 64; i++) {
2688                 tmp = (i - delta) * phy->nrssislope;
2689                 tmp /= 0x10000;
2690                 tmp += 0x3A;
2691                 tmp = limit_value(tmp, 0, 0x3F);
2692                 phy->nrssi_lt[i] = tmp;
2693         }
2694 }
2695
2696 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
2697 {
2698         struct b43_phy *phy = &dev->phy;
2699         u16 backup[20] = { 0 };
2700         s16 v47F;
2701         u16 i;
2702         u16 saved = 0xFFFF;
2703
2704         backup[0] = b43_phy_read(dev, 0x0001);
2705         backup[1] = b43_phy_read(dev, 0x0811);
2706         backup[2] = b43_phy_read(dev, 0x0812);
2707         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2708                 backup[3] = b43_phy_read(dev, 0x0814);
2709                 backup[4] = b43_phy_read(dev, 0x0815);
2710         }
2711         backup[5] = b43_phy_read(dev, 0x005A);
2712         backup[6] = b43_phy_read(dev, 0x0059);
2713         backup[7] = b43_phy_read(dev, 0x0058);
2714         backup[8] = b43_phy_read(dev, 0x000A);
2715         backup[9] = b43_phy_read(dev, 0x0003);
2716         backup[10] = b43_radio_read16(dev, 0x007A);
2717         backup[11] = b43_radio_read16(dev, 0x0043);
2718
2719         b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
2720         b43_phy_write(dev, 0x0001,
2721                       (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
2722         b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2723         b43_phy_write(dev, 0x0812,
2724                       (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
2725         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
2726         if (phy->rev >= 6) {
2727                 backup[12] = b43_phy_read(dev, 0x002E);
2728                 backup[13] = b43_phy_read(dev, 0x002F);
2729                 backup[14] = b43_phy_read(dev, 0x080F);
2730                 backup[15] = b43_phy_read(dev, 0x0810);
2731                 backup[16] = b43_phy_read(dev, 0x0801);
2732                 backup[17] = b43_phy_read(dev, 0x0060);
2733                 backup[18] = b43_phy_read(dev, 0x0014);
2734                 backup[19] = b43_phy_read(dev, 0x0478);
2735
2736                 b43_phy_write(dev, 0x002E, 0);
2737                 b43_phy_write(dev, 0x002F, 0);
2738                 b43_phy_write(dev, 0x080F, 0);
2739                 b43_phy_write(dev, 0x0810, 0);
2740                 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
2741                 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
2742                 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
2743                 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
2744         }
2745         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
2746         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
2747         udelay(30);
2748
2749         v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2750         if (v47F >= 0x20)
2751                 v47F -= 0x40;
2752         if (v47F == 31) {
2753                 for (i = 7; i >= 4; i--) {
2754                         b43_radio_write16(dev, 0x007B, i);
2755                         udelay(20);
2756                         v47F =
2757                             (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2758                         if (v47F >= 0x20)
2759                                 v47F -= 0x40;
2760                         if (v47F < 31 && saved == 0xFFFF)
2761                                 saved = i;
2762                 }
2763                 if (saved == 0xFFFF)
2764                         saved = 4;
2765         } else {
2766                 b43_radio_write16(dev, 0x007A,
2767                                   b43_radio_read16(dev, 0x007A) & 0x007F);
2768                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2769                         b43_phy_write(dev, 0x0814,
2770                                       b43_phy_read(dev, 0x0814) | 0x0001);
2771                         b43_phy_write(dev, 0x0815,
2772                                       b43_phy_read(dev, 0x0815) & 0xFFFE);
2773                 }
2774                 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2775                 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
2776                 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
2777                 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
2778                 b43_phy_write(dev, 0x005A, 0x0480);
2779                 b43_phy_write(dev, 0x0059, 0x0810);
2780                 b43_phy_write(dev, 0x0058, 0x000D);
2781                 if (phy->rev == 0) {
2782                         b43_phy_write(dev, 0x0003, 0x0122);
2783                 } else {
2784                         b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
2785                                       | 0x2000);
2786                 }
2787                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2788                         b43_phy_write(dev, 0x0814,
2789                                       b43_phy_read(dev, 0x0814) | 0x0004);
2790                         b43_phy_write(dev, 0x0815,
2791                                       b43_phy_read(dev, 0x0815) & 0xFFFB);
2792                 }
2793                 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
2794                               | 0x0040);
2795                 b43_radio_write16(dev, 0x007A,
2796                                   b43_radio_read16(dev, 0x007A) | 0x000F);
2797                 b43_set_all_gains(dev, 3, 0, 1);
2798                 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
2799                                                 & 0x00F0) | 0x000F);
2800                 udelay(30);
2801                 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2802                 if (v47F >= 0x20)
2803                         v47F -= 0x40;
2804                 if (v47F == -32) {
2805                         for (i = 0; i < 4; i++) {
2806                                 b43_radio_write16(dev, 0x007B, i);
2807                                 udelay(20);
2808                                 v47F =
2809                                     (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
2810                                            0x003F);
2811                                 if (v47F >= 0x20)
2812                                         v47F -= 0x40;
2813                                 if (v47F > -31 && saved == 0xFFFF)
2814                                         saved = i;
2815                         }
2816                         if (saved == 0xFFFF)
2817                                 saved = 3;
2818                 } else
2819                         saved = 0;
2820         }
2821         b43_radio_write16(dev, 0x007B, saved);
2822
2823         if (phy->rev >= 6) {
2824                 b43_phy_write(dev, 0x002E, backup[12]);
2825                 b43_phy_write(dev, 0x002F, backup[13]);
2826                 b43_phy_write(dev, 0x080F, backup[14]);
2827                 b43_phy_write(dev, 0x0810, backup[15]);
2828         }
2829         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
2830                 b43_phy_write(dev, 0x0814, backup[3]);
2831                 b43_phy_write(dev, 0x0815, backup[4]);
2832         }
2833         b43_phy_write(dev, 0x005A, backup[5]);
2834         b43_phy_write(dev, 0x0059, backup[6]);
2835         b43_phy_write(dev, 0x0058, backup[7]);
2836         b43_phy_write(dev, 0x000A, backup[8]);
2837         b43_phy_write(dev, 0x0003, backup[9]);
2838         b43_radio_write16(dev, 0x0043, backup[11]);
2839         b43_radio_write16(dev, 0x007A, backup[10]);
2840         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
2841         b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
2842         b43_set_original_gains(dev);
2843         if (phy->rev >= 6) {
2844                 b43_phy_write(dev, 0x0801, backup[16]);
2845                 b43_phy_write(dev, 0x0060, backup[17]);
2846                 b43_phy_write(dev, 0x0014, backup[18]);
2847                 b43_phy_write(dev, 0x0478, backup[19]);
2848         }
2849         b43_phy_write(dev, 0x0001, backup[0]);
2850         b43_phy_write(dev, 0x0812, backup[2]);
2851         b43_phy_write(dev, 0x0811, backup[1]);
2852 }
2853
2854 void b43_calc_nrssi_slope(struct b43_wldev *dev)
2855 {
2856         struct b43_phy *phy = &dev->phy;
2857         u16 backup[18] = { 0 };
2858         u16 tmp;
2859         s16 nrssi0, nrssi1;
2860
2861         switch (phy->type) {
2862         case B43_PHYTYPE_B:
2863                 backup[0] = b43_radio_read16(dev, 0x007A);
2864                 backup[1] = b43_radio_read16(dev, 0x0052);
2865                 backup[2] = b43_radio_read16(dev, 0x0043);
2866                 backup[3] = b43_phy_read(dev, 0x0030);
2867                 backup[4] = b43_phy_read(dev, 0x0026);
2868                 backup[5] = b43_phy_read(dev, 0x0015);
2869                 backup[6] = b43_phy_read(dev, 0x002A);
2870                 backup[7] = b43_phy_read(dev, 0x0020);
2871                 backup[8] = b43_phy_read(dev, 0x005A);
2872                 backup[9] = b43_phy_read(dev, 0x0059);
2873                 backup[10] = b43_phy_read(dev, 0x0058);
2874                 backup[11] = b43_read16(dev, 0x03E2);
2875                 backup[12] = b43_read16(dev, 0x03E6);
2876                 backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2877
2878                 tmp = b43_radio_read16(dev, 0x007A);
2879                 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
2880                 b43_radio_write16(dev, 0x007A, tmp);
2881                 b43_phy_write(dev, 0x0030, 0x00FF);
2882                 b43_write16(dev, 0x03EC, 0x7F7F);
2883                 b43_phy_write(dev, 0x0026, 0x0000);
2884                 b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
2885                 b43_phy_write(dev, 0x002A, 0x08A3);
2886                 b43_radio_write16(dev, 0x007A,
2887                                   b43_radio_read16(dev, 0x007A) | 0x0080);
2888
2889                 nrssi0 = (s16) b43_phy_read(dev, 0x0027);
2890                 b43_radio_write16(dev, 0x007A,
2891                                   b43_radio_read16(dev, 0x007A) & 0x007F);
2892                 if (phy->rev >= 2) {
2893                         b43_write16(dev, 0x03E6, 0x0040);
2894                 } else if (phy->rev == 0) {
2895                         b43_write16(dev, 0x03E6, 0x0122);
2896                 } else {
2897                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2898                                     b43_read16(dev,
2899                                                B43_MMIO_CHANNEL_EXT) & 0x2000);
2900                 }
2901                 b43_phy_write(dev, 0x0020, 0x3F3F);
2902                 b43_phy_write(dev, 0x0015, 0xF330);
2903                 b43_radio_write16(dev, 0x005A, 0x0060);
2904                 b43_radio_write16(dev, 0x0043,
2905                                   b43_radio_read16(dev, 0x0043) & 0x00F0);
2906                 b43_phy_write(dev, 0x005A, 0x0480);
2907                 b43_phy_write(dev, 0x0059, 0x0810);
2908                 b43_phy_write(dev, 0x0058, 0x000D);
2909                 udelay(20);
2910
2911                 nrssi1 = (s16) b43_phy_read(dev, 0x0027);
2912                 b43_phy_write(dev, 0x0030, backup[3]);
2913                 b43_radio_write16(dev, 0x007A, backup[0]);
2914                 b43_write16(dev, 0x03E2, backup[11]);
2915                 b43_phy_write(dev, 0x0026, backup[4]);
2916                 b43_phy_write(dev, 0x0015, backup[5]);
2917                 b43_phy_write(dev, 0x002A, backup[6]);
2918                 b43_synth_pu_workaround(dev, phy->channel);
2919                 if (phy->rev != 0)
2920                         b43_write16(dev, 0x03F4, backup[13]);
2921
2922                 b43_phy_write(dev, 0x0020, backup[7]);
2923                 b43_phy_write(dev, 0x005A, backup[8]);
2924                 b43_phy_write(dev, 0x0059, backup[9]);
2925                 b43_phy_write(dev, 0x0058, backup[10]);
2926                 b43_radio_write16(dev, 0x0052, backup[1]);
2927                 b43_radio_write16(dev, 0x0043, backup[2]);
2928
2929                 if (nrssi0 == nrssi1)
2930                         phy->nrssislope = 0x00010000;
2931                 else
2932                         phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2933
2934                 if (nrssi0 <= -4) {
2935                         phy->nrssi[0] = nrssi0;
2936                         phy->nrssi[1] = nrssi1;
2937                 }
2938                 break;
2939         case B43_PHYTYPE_G:
2940                 if (phy->radio_rev >= 9)
2941                         return;
2942                 if (phy->radio_rev == 8)
2943                         b43_calc_nrssi_offset(dev);
2944
2945                 b43_phy_write(dev, B43_PHY_G_CRS,
2946                               b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2947                 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2948                 backup[7] = b43_read16(dev, 0x03E2);
2949                 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
2950                 backup[0] = b43_radio_read16(dev, 0x007A);
2951                 backup[1] = b43_radio_read16(dev, 0x0052);
2952                 backup[2] = b43_radio_read16(dev, 0x0043);
2953                 backup[3] = b43_phy_read(dev, 0x0015);
2954                 backup[4] = b43_phy_read(dev, 0x005A);
2955                 backup[5] = b43_phy_read(dev, 0x0059);
2956                 backup[6] = b43_phy_read(dev, 0x0058);
2957                 backup[8] = b43_read16(dev, 0x03E6);
2958                 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2959                 if (phy->rev >= 3) {
2960                         backup[10] = b43_phy_read(dev, 0x002E);
2961                         backup[11] = b43_phy_read(dev, 0x002F);
2962                         backup[12] = b43_phy_read(dev, 0x080F);
2963                         backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
2964                         backup[14] = b43_phy_read(dev, 0x0801);
2965                         backup[15] = b43_phy_read(dev, 0x0060);
2966                         backup[16] = b43_phy_read(dev, 0x0014);
2967                         backup[17] = b43_phy_read(dev, 0x0478);
2968                         b43_phy_write(dev, 0x002E, 0);
2969                         b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
2970                         switch (phy->rev) {
2971                         case 4:
2972                         case 6:
2973                         case 7:
2974                                 b43_phy_write(dev, 0x0478,
2975                                               b43_phy_read(dev, 0x0478)
2976                                               | 0x0100);
2977                                 b43_phy_write(dev, 0x0801,
2978                                               b43_phy_read(dev, 0x0801)
2979                                               | 0x0040);
2980                                 break;
2981                         case 3:
2982                         case 5:
2983                                 b43_phy_write(dev, 0x0801,
2984                                               b43_phy_read(dev, 0x0801)
2985                                               & 0xFFBF);
2986                                 break;
2987                         }
2988                         b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
2989                                       | 0x0040);
2990                         b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
2991                                       | 0x0200);
2992                 }
2993                 b43_radio_write16(dev, 0x007A,
2994                                   b43_radio_read16(dev, 0x007A) | 0x0070);
2995                 b43_set_all_gains(dev, 0, 8, 0);
2996                 b43_radio_write16(dev, 0x007A,
2997                                   b43_radio_read16(dev, 0x007A) & 0x00F7);
2998                 if (phy->rev >= 2) {
2999                         b43_phy_write(dev, 0x0811,
3000                                       (b43_phy_read(dev, 0x0811) & 0xFFCF) |
3001                                       0x0030);
3002                         b43_phy_write(dev, 0x0812,
3003                                       (b43_phy_read(dev, 0x0812) & 0xFFCF) |
3004                                       0x0010);
3005                 }
3006                 b43_radio_write16(dev, 0x007A,
3007                                   b43_radio_read16(dev, 0x007A) | 0x0080);
3008                 udelay(20);
3009
3010                 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
3011                 if (nrssi0 >= 0x0020)
3012                         nrssi0 -= 0x0040;
3013
3014                 b43_radio_write16(dev, 0x007A,
3015                                   b43_radio_read16(dev, 0x007A) & 0x007F);
3016                 if (phy->rev >= 2) {
3017                         b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
3018                                                     & 0xFF9F) | 0x0040);
3019                 }
3020
3021                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3022                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3023                             | 0x2000);
3024                 b43_radio_write16(dev, 0x007A,
3025                                   b43_radio_read16(dev, 0x007A) | 0x000F);
3026                 b43_phy_write(dev, 0x0015, 0xF330);
3027                 if (phy->rev >= 2) {
3028                         b43_phy_write(dev, 0x0812,
3029                                       (b43_phy_read(dev, 0x0812) & 0xFFCF) |
3030                                       0x0020);
3031                         b43_phy_write(dev, 0x0811,
3032                                       (b43_phy_read(dev, 0x0811) & 0xFFCF) |
3033                                       0x0020);
3034                 }
3035
3036                 b43_set_all_gains(dev, 3, 0, 1);
3037                 if (phy->radio_rev == 8) {
3038                         b43_radio_write16(dev, 0x0043, 0x001F);
3039                 } else {
3040                         tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
3041                         b43_radio_write16(dev, 0x0052, tmp | 0x0060);
3042                         tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
3043                         b43_radio_write16(dev, 0x0043, tmp | 0x0009);
3044                 }
3045                 b43_phy_write(dev, 0x005A, 0x0480);
3046                 b43_phy_write(dev, 0x0059, 0x0810);
3047                 b43_phy_write(dev, 0x0058, 0x000D);
3048                 udelay(20);
3049                 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
3050                 if (nrssi1 >= 0x0020)
3051                         nrssi1 -= 0x0040;
3052                 if (nrssi0 == nrssi1)
3053                         phy->nrssislope = 0x00010000;
3054                 else
3055                         phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
3056                 if (nrssi0 >= -4) {
3057                         phy->nrssi[0] = nrssi1;
3058                         phy->nrssi[1] = nrssi0;
3059                 }
3060                 if (phy->rev >= 3) {
3061                         b43_phy_write(dev, 0x002E, backup[10]);
3062                         b43_phy_write(dev, 0x002F, backup[11]);
3063                         b43_phy_write(dev, 0x080F, backup[12]);
3064                         b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
3065                 }
3066                 if (phy->rev >= 2) {
3067                         b43_phy_write(dev, 0x0812,
3068                                       b43_phy_read(dev, 0x0812) & 0xFFCF);
3069                         b43_phy_write(dev, 0x0811,
3070                                       b43_phy_read(dev, 0x0811) & 0xFFCF);
3071                 }
3072
3073                 b43_radio_write16(dev, 0x007A, backup[0]);
3074                 b43_radio_write16(dev, 0x0052, backup[1]);
3075                 b43_radio_write16(dev, 0x0043, backup[2]);
3076                 b43_write16(dev, 0x03E2, backup[7]);
3077                 b43_write16(dev, 0x03E6, backup[8]);
3078                 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
3079                 b43_phy_write(dev, 0x0015, backup[3]);
3080                 b43_phy_write(dev, 0x005A, backup[4]);
3081                 b43_phy_write(dev, 0x0059, backup[5]);
3082                 b43_phy_write(dev, 0x0058, backup[6]);
3083                 b43_synth_pu_workaround(dev, phy->channel);
3084                 b43_phy_write(dev, 0x0802,
3085                               b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
3086                 b43_set_original_gains(dev);
3087                 b43_phy_write(dev, B43_PHY_G_CRS,
3088                               b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
3089                 if (phy->rev >= 3) {
3090                         b43_phy_write(dev, 0x0801, backup[14]);
3091                         b43_phy_write(dev, 0x0060, backup[15]);
3092                         b43_phy_write(dev, 0x0014, backup[16]);
3093                         b43_phy_write(dev, 0x0478, backup[17]);
3094                 }
3095                 b43_nrssi_mem_update(dev);
3096                 b43_calc_nrssi_threshold(dev);
3097                 break;
3098         default:
3099                 B43_WARN_ON(1);
3100         }
3101 }
3102
3103 void b43_calc_nrssi_threshold(struct b43_wldev *dev)
3104 {
3105         struct b43_phy *phy = &dev->phy;
3106         s32 threshold;
3107         s32 a, b;
3108         s16 tmp16;
3109         u16 tmp_u16;
3110
3111         switch (phy->type) {
3112         case B43_PHYTYPE_B:{
3113                         if (phy->radio_ver != 0x2050)
3114                                 return;
3115                         if (!
3116                             (dev->dev->bus->sprom.r1.
3117                              boardflags_lo & B43_BFL_RSSI))
3118                                 return;
3119
3120                         if (phy->radio_rev >= 6) {
3121                                 threshold =
3122                                     (phy->nrssi[1] - phy->nrssi[0]) * 32;
3123                                 threshold += 20 * (phy->nrssi[0] + 1);
3124                                 threshold /= 40;
3125                         } else
3126                                 threshold = phy->nrssi[1] - 5;
3127
3128                         threshold = limit_value(threshold, 0, 0x3E);
3129                         b43_phy_read(dev, 0x0020);      /* dummy read */
3130                         b43_phy_write(dev, 0x0020,
3131                                       (((u16) threshold) << 8) | 0x001C);
3132
3133                         if (phy->radio_rev >= 6) {
3134                                 b43_phy_write(dev, 0x0087, 0x0E0D);
3135                                 b43_phy_write(dev, 0x0086, 0x0C0B);
3136                                 b43_phy_write(dev, 0x0085, 0x0A09);
3137                                 b43_phy_write(dev, 0x0084, 0x0808);
3138                                 b43_phy_write(dev, 0x0083, 0x0808);
3139                                 b43_phy_write(dev, 0x0082, 0x0604);
3140                                 b43_phy_write(dev, 0x0081, 0x0302);
3141                                 b43_phy_write(dev, 0x0080, 0x0100);
3142                         }
3143                         break;
3144                 }
3145         case B43_PHYTYPE_G:
3146                 if (!phy->gmode ||
3147                     !(dev->dev->bus->sprom.r1.boardflags_lo & B43_BFL_RSSI)) {
3148                         tmp16 = b43_nrssi_hw_read(dev, 0x20);
3149                         if (tmp16 >= 0x20)
3150                                 tmp16 -= 0x40;
3151                         if (tmp16 < 3) {
3152                                 b43_phy_write(dev, 0x048A,
3153                                               (b43_phy_read(dev, 0x048A)
3154                                                & 0xF000) | 0x09EB);
3155                         } else {
3156                                 b43_phy_write(dev, 0x048A,
3157                                               (b43_phy_read(dev, 0x048A)
3158                                                & 0xF000) | 0x0AED);
3159                         }
3160                 } else {
3161                         if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
3162                                 a = 0xE;
3163                                 b = 0xA;
3164                         } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
3165                                 a = 0x13;
3166                                 b = 0x12;
3167                         } else {
3168                                 a = 0xE;
3169                                 b = 0x11;
3170                         }
3171
3172                         a = a * (phy->nrssi[1] - phy->nrssi[0]);
3173                         a += (phy->nrssi[0] << 6);
3174                         if (a < 32)
3175                                 a += 31;
3176                         else
3177                                 a += 32;
3178                         a = a >> 6;
3179                         a = limit_value(a, -31, 31);
3180
3181                         b = b * (phy->nrssi[1] - phy->nrssi[0]);
3182                         b += (phy->nrssi[0] << 6);
3183                         if (b < 32)
3184                                 b += 31;
3185                         else
3186                                 b += 32;
3187                         b = b >> 6;
3188                         b = limit_value(b, -31, 31);
3189
3190                         tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
3191                         tmp_u16 |= ((u32) b & 0x0000003F);
3192                         tmp_u16 |= (((u32) a & 0x0000003F) << 6);
3193                         b43_phy_write(dev, 0x048A, tmp_u16);
3194                 }
3195                 break;
3196         default:
3197                 B43_WARN_ON(1);
3198         }
3199 }
3200
3201 /* Stack implementation to save/restore values from the
3202  * interference mitigation code.
3203  * It is save to restore values in random order.
3204  */
3205 static void _stack_save(u32 * _stackptr, size_t * stackidx,
3206                         u8 id, u16 offset, u16 value)
3207 {
3208         u32 *stackptr = &(_stackptr[*stackidx]);
3209
3210         B43_WARN_ON(offset & 0xF000);
3211         B43_WARN_ON(id & 0xF0);
3212         *stackptr = offset;
3213         *stackptr |= ((u32) id) << 12;
3214         *stackptr |= ((u32) value) << 16;
3215         (*stackidx)++;
3216         B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
3217 }
3218
3219 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
3220 {
3221         size_t i;
3222
3223         B43_WARN_ON(offset & 0xF000);
3224         B43_WARN_ON(id & 0xF0);
3225         for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
3226                 if ((*stackptr & 0x00000FFF) != offset)
3227                         continue;
3228                 if (((*stackptr & 0x0000F000) >> 12) != id)
3229                         continue;
3230                 return ((*stackptr & 0xFFFF0000) >> 16);
3231         }
3232         B43_WARN_ON(1);
3233
3234         return 0;
3235 }
3236
3237 #define phy_stacksave(offset)                                   \
3238         do {                                                    \
3239                 _stack_save(stack, &stackidx, 0x1, (offset),    \
3240                             b43_phy_read(dev, (offset)));       \
3241         } while (0)
3242 #define phy_stackrestore(offset)                                \
3243         do {                                                    \
3244                 b43_phy_write(dev, (offset),            \
3245                                   _stack_restore(stack, 0x1,    \
3246                                                  (offset)));    \
3247         } while (0)
3248 #define radio_stacksave(offset)                                         \
3249         do {                                                            \
3250                 _stack_save(stack, &stackidx, 0x2, (offset),            \
3251                             b43_radio_read16(dev, (offset)));   \
3252         } while (0)
3253 #define radio_stackrestore(offset)                                      \
3254         do {                                                            \
3255                 b43_radio_write16(dev, (offset),                        \
3256                                       _stack_restore(stack, 0x2,        \
3257                                                      (offset)));        \
3258         } while (0)
3259 #define ofdmtab_stacksave(table, offset)                        \
3260         do {                                                    \
3261                 _stack_save(stack, &stackidx, 0x3, (offset)|(table),    \
3262                             b43_ofdmtab_read16(dev, (table), (offset)));        \
3263         } while (0)
3264 #define ofdmtab_stackrestore(table, offset)                     \
3265         do {                                                    \
3266                 b43_ofdmtab_write16(dev, (table),       (offset),       \
3267                                   _stack_restore(stack, 0x3,    \
3268                                                  (offset)|(table)));    \
3269         } while (0)
3270
3271 static void
3272 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
3273 {
3274         struct b43_phy *phy = &dev->phy;
3275         u16 tmp, flipped;
3276         size_t stackidx = 0;
3277         u32 *stack = phy->interfstack;
3278
3279         switch (mode) {
3280         case B43_INTERFMODE_NONWLAN:
3281                 if (phy->rev != 1) {
3282                         b43_phy_write(dev, 0x042B,
3283                                       b43_phy_read(dev, 0x042B) | 0x0800);
3284                         b43_phy_write(dev, B43_PHY_G_CRS,
3285                                       b43_phy_read(dev,
3286                                                    B43_PHY_G_CRS) & ~0x4000);
3287                         break;
3288                 }
3289                 radio_stacksave(0x0078);
3290                 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
3291                 flipped = flip_4bit(tmp);
3292                 if (flipped < 10 && flipped >= 8)
3293                         flipped = 7;
3294                 else if (flipped >= 10)
3295                         flipped -= 3;
3296                 flipped = flip_4bit(flipped);
3297                 flipped = (flipped << 1) | 0x0020;
3298                 b43_radio_write16(dev, 0x0078, flipped);
3299
3300                 b43_calc_nrssi_threshold(dev);
3301
3302                 phy_stacksave(0x0406);
3303                 b43_phy_write(dev, 0x0406, 0x7E28);
3304
3305                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
3306                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3307                               b43_phy_read(dev,
3308                                            B43_PHY_RADIO_BITFIELD) | 0x1000);
3309
3310                 phy_stacksave(0x04A0);
3311                 b43_phy_write(dev, 0x04A0,
3312                               (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
3313                 phy_stacksave(0x04A1);
3314                 b43_phy_write(dev, 0x04A1,
3315                               (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
3316                 phy_stacksave(0x04A2);
3317                 b43_phy_write(dev, 0x04A2,
3318                               (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
3319                 phy_stacksave(0x04A8);
3320                 b43_phy_write(dev, 0x04A8,
3321                               (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
3322                 phy_stacksave(0x04AB);
3323                 b43_phy_write(dev, 0x04AB,
3324                               (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
3325
3326                 phy_stacksave(0x04A7);
3327                 b43_phy_write(dev, 0x04A7, 0x0002);
3328                 phy_stacksave(0x04A3);
3329                 b43_phy_write(dev, 0x04A3, 0x287A);
3330                 phy_stacksave(0x04A9);
3331                 b43_phy_write(dev, 0x04A9, 0x2027);
3332                 phy_stacksave(0x0493);
3333                 b43_phy_write(dev, 0x0493, 0x32F5);
3334                 phy_stacksave(0x04AA);
3335                 b43_phy_write(dev, 0x04AA, 0x2027);
3336                 phy_stacksave(0x04AC);
3337                 b43_phy_write(dev, 0x04AC, 0x32F5);
3338                 break;
3339         case B43_INTERFMODE_MANUALWLAN:
3340                 if (b43_phy_read(dev, 0x0033) & 0x0800)
3341                         break;
3342
3343                 phy->aci_enable = 1;
3344
3345                 phy_stacksave(B43_PHY_RADIO_BITFIELD);
3346                 phy_stacksave(B43_PHY_G_CRS);
3347                 if (phy->rev < 2) {
3348                         phy_stacksave(0x0406);
3349                 } else {
3350                         phy_stacksave(0x04C0);
3351                         phy_stacksave(0x04C1);
3352                 }
3353                 phy_stacksave(0x0033);
3354                 phy_stacksave(0x04A7);
3355                 phy_stacksave(0x04A3);
3356                 phy_stacksave(0x04A9);
3357                 phy_stacksave(0x04AA);
3358                 phy_stacksave(0x04AC);
3359                 phy_stacksave(0x0493);
3360                 phy_stacksave(0x04A1);
3361                 phy_stacksave(0x04A0);
3362                 phy_stacksave(0x04A2);
3363                 phy_stacksave(0x048A);
3364                 phy_stacksave(0x04A8);
3365                 phy_stacksave(0x04AB);
3366                 if (phy->rev == 2) {
3367                         phy_stacksave(0x04AD);
3368                         phy_stacksave(0x04AE);
3369                 } else if (phy->rev >= 3) {
3370                         phy_stacksave(0x04AD);
3371                         phy_stacksave(0x0415);
3372                         phy_stacksave(0x0416);
3373                         phy_stacksave(0x0417);
3374                         ofdmtab_stacksave(0x1A00, 0x2);
3375                         ofdmtab_stacksave(0x1A00, 0x3);
3376                 }
3377                 phy_stacksave(0x042B);
3378                 phy_stacksave(0x048C);
3379
3380                 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3381                               b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3382                               & ~0x1000);
3383                 b43_phy_write(dev, B43_PHY_G_CRS,
3384                               (b43_phy_read(dev, B43_PHY_G_CRS)
3385                                & 0xFFFC) | 0x0002);
3386
3387                 b43_phy_write(dev, 0x0033, 0x0800);
3388                 b43_phy_write(dev, 0x04A3, 0x2027);
3389                 b43_phy_write(dev, 0x04A9, 0x1CA8);
3390                 b43_phy_write(dev, 0x0493, 0x287A);
3391                 b43_phy_write(dev, 0x04AA, 0x1CA8);
3392                 b43_phy_write(dev, 0x04AC, 0x287A);
3393
3394                 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3395                                             & 0xFFC0) | 0x001A);
3396                 b43_phy_write(dev, 0x04A7, 0x000D);
3397
3398                 if (phy->rev < 2) {
3399                         b43_phy_write(dev, 0x0406, 0xFF0D);
3400                 } else if (phy->rev == 2) {
3401                         b43_phy_write(dev, 0x04C0, 0xFFFF);
3402                         b43_phy_write(dev, 0x04C1, 0x00A9);
3403                 } else {
3404                         b43_phy_write(dev, 0x04C0, 0x00C1);
3405                         b43_phy_write(dev, 0x04C1, 0x0059);
3406                 }
3407
3408                 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3409                                             & 0xC0FF) | 0x1800);
3410                 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3411                                             & 0xFFC0) | 0x0015);
3412                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3413                                             & 0xCFFF) | 0x1000);
3414                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3415                                             & 0xF0FF) | 0x0A00);
3416                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3417                                             & 0xCFFF) | 0x1000);
3418                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3419                                             & 0xF0FF) | 0x0800);
3420                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3421                                             & 0xFFCF) | 0x0010);
3422                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3423                                             & 0xFFF0) | 0x0005);
3424                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3425                                             & 0xFFCF) | 0x0010);
3426                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3427                                             & 0xFFF0) | 0x0006);
3428                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3429                                             & 0xF0FF) | 0x0800);
3430                 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3431                                             & 0xF0FF) | 0x0500);
3432                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3433                                             & 0xFFF0) | 0x000B);
3434
3435                 if (phy->rev >= 3) {
3436                         b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3437                                       & ~0x8000);
3438                         b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
3439                                                     & 0x8000) | 0x36D8);
3440                         b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
3441                                                     & 0x8000) | 0x36D8);
3442                         b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
3443                                                     & 0xFE00) | 0x016D);
3444                 } else {
3445                         b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3446                                       | 0x1000);
3447                         b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
3448                                                     & 0x9FFF) | 0x2000);
3449                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
3450                 }
3451                 if (phy->rev >= 2) {
3452                         b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
3453                                       | 0x0800);
3454                 }
3455                 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
3456                                             & 0xF0FF) | 0x0200);
3457                 if (phy->rev == 2) {
3458                         b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
3459                                                     & 0xFF00) | 0x007F);
3460                         b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
3461                                                     & 0x00FF) | 0x1300);
3462                 } else if (phy->rev >= 6) {
3463                         b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
3464                         b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
3465                         b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
3466                                       & 0x00FF);
3467                 }
3468                 b43_calc_nrssi_slope(dev);
3469                 break;
3470         default:
3471                 B43_WARN_ON(1);
3472         }
3473 }
3474
3475 static void
3476 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
3477 {
3478         struct b43_phy *phy = &dev->phy;
3479         u32 *stack = phy->interfstack;
3480
3481         switch (mode) {
3482         case B43_INTERFMODE_NONWLAN:
3483                 if (phy->rev != 1) {
3484                         b43_phy_write(dev, 0x042B,
3485                                       b43_phy_read(dev, 0x042B) & ~0x0800);
3486                         b43_phy_write(dev, B43_PHY_G_CRS,
3487                                       b43_phy_read(dev,
3488                                                    B43_PHY_G_CRS) | 0x4000);
3489                         break;
3490                 }
3491                 radio_stackrestore(0x0078);
3492                 b43_calc_nrssi_threshold(dev);
3493                 phy_stackrestore(0x0406);
3494                 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
3495                 if (!dev->bad_frames_preempt) {
3496                         b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3497                                       b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3498                                       & ~(1 << 11));
3499                 }
3500                 b43_phy_write(dev, B43_PHY_G_CRS,
3501                               b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
3502                 phy_stackrestore(0x04A0);
3503                 phy_stackrestore(0x04A1);
3504                 phy_stackrestore(0x04A2);
3505                 phy_stackrestore(0x04A8);
3506                 phy_stackrestore(0x04AB);
3507                 phy_stackrestore(0x04A7);
3508                 phy_stackrestore(0x04A3);
3509                 phy_stackrestore(0x04A9);
3510                 phy_stackrestore(0x0493);
3511                 phy_stackrestore(0x04AA);
3512                 phy_stackrestore(0x04AC);
3513                 break;
3514         case B43_INTERFMODE_MANUALWLAN:
3515                 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
3516                         break;
3517
3518                 phy->aci_enable = 0;
3519
3520                 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
3521                 phy_stackrestore(B43_PHY_G_CRS);
3522                 phy_stackrestore(0x0033);
3523                 phy_stackrestore(0x04A3);
3524                 phy_stackrestore(0x04A9);
3525                 phy_stackrestore(0x0493);
3526                 phy_stackrestore(0x04AA);
3527                 phy_stackrestore(0x04AC);
3528                 phy_stackrestore(0x04A0);
3529                 phy_stackrestore(0x04A7);
3530                 if (phy->rev >= 2) {
3531                         phy_stackrestore(0x04C0);
3532                         phy_stackrestore(0x04C1);
3533                 } else
3534                         phy_stackrestore(0x0406);
3535                 phy_stackrestore(0x04A1);
3536                 phy_stackrestore(0x04AB);
3537                 phy_stackrestore(0x04A8);
3538                 if (phy->rev == 2) {
3539                         phy_stackrestore(0x04AD);
3540                         phy_stackrestore(0x04AE);
3541                 } else if (phy->rev >= 3) {
3542                         phy_stackrestore(0x04AD);
3543                         phy_stackrestore(0x0415);
3544                         phy_stackrestore(0x0416);
3545                         phy_stackrestore(0x0417);
3546                         ofdmtab_stackrestore(0x1A00, 0x2);
3547                         ofdmtab_stackrestore(0x1A00, 0x3);
3548                 }
3549                 phy_stackrestore(0x04A2);
3550                 phy_stackrestore(0x048A);
3551                 phy_stackrestore(0x042B);
3552                 phy_stackrestore(0x048C);
3553                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
3554                 b43_calc_nrssi_slope(dev);
3555                 break;
3556         default:
3557                 B43_WARN_ON(1);
3558         }
3559 }
3560
3561 #undef phy_stacksave
3562 #undef phy_stackrestore
3563 #undef radio_stacksave
3564 #undef radio_stackrestore
3565 #undef ofdmtab_stacksave
3566 #undef ofdmtab_stackrestore
3567
3568 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
3569 {
3570         struct b43_phy *phy = &dev->phy;
3571         int currentmode;
3572
3573         if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
3574                 return -ENODEV;
3575
3576         phy->aci_wlan_automatic = 0;
3577         switch (mode) {
3578         case B43_INTERFMODE_AUTOWLAN:
3579                 phy->aci_wlan_automatic = 1;
3580                 if (phy->aci_enable)
3581                         mode = B43_INTERFMODE_MANUALWLAN;
3582                 else
3583                         mode = B43_INTERFMODE_NONE;
3584                 break;
3585         case B43_INTERFMODE_NONE:
3586         case B43_INTERFMODE_NONWLAN:
3587         case B43_INTERFMODE_MANUALWLAN:
3588                 break;
3589         default:
3590                 return -EINVAL;
3591         }
3592
3593         currentmode = phy->interfmode;
3594         if (currentmode == mode)
3595                 return 0;
3596         if (currentmode != B43_INTERFMODE_NONE)
3597                 b43_radio_interference_mitigation_disable(dev, currentmode);
3598
3599         if (mode == B43_INTERFMODE_NONE) {
3600                 phy->aci_enable = 0;
3601                 phy->aci_hw_rssi = 0;
3602         } else
3603                 b43_radio_interference_mitigation_enable(dev, mode);
3604         phy->interfmode = mode;
3605
3606         return 0;
3607 }
3608
3609 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
3610 {
3611         u16 reg, index, ret;
3612
3613         static const u8 rcc_table[] = {
3614                 0x02, 0x03, 0x01, 0x0F,
3615                 0x06, 0x07, 0x05, 0x0F,
3616                 0x0A, 0x0B, 0x09, 0x0F,
3617                 0x0E, 0x0F, 0x0D, 0x0F,
3618         };
3619
3620         reg = b43_radio_read16(dev, 0x60);
3621         index = (reg & 0x001E) >> 1;
3622         ret = rcc_table[index] << 1;
3623         ret |= (reg & 0x0001);
3624         ret |= 0x0020;
3625
3626         return ret;
3627 }
3628
3629 #define LPD(L, P, D)    (((L) << 2) | ((P) << 1) | ((D) << 0))
3630 static u16 radio2050_rfover_val(struct b43_wldev *dev,
3631                                 u16 phy_register, unsigned int lpd)
3632 {
3633         struct b43_phy *phy = &dev->phy;
3634         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
3635
3636         if (!phy->gmode)
3637                 return 0;
3638
3639         if (has_loopback_gain(phy)) {
3640                 int max_lb_gain = phy->max_lb_gain;
3641                 u16 extlna;
3642                 u16 i;
3643
3644                 if (phy->radio_rev == 8)
3645                         max_lb_gain += 0x3E;
3646                 else
3647                         max_lb_gain += 0x26;
3648                 if (max_lb_gain >= 0x46) {
3649                         extlna = 0x3000;
3650                         max_lb_gain -= 0x46;
3651                 } else if (max_lb_gain >= 0x3A) {
3652                         extlna = 0x1000;
3653                         max_lb_gain -= 0x3A;
3654                 } else if (max_lb_gain >= 0x2E) {
3655                         extlna = 0x2000;
3656                         max_lb_gain -= 0x2E;
3657                 } else {
3658                         extlna = 0;
3659                         max_lb_gain -= 0x10;
3660                 }
3661
3662                 for (i = 0; i < 16; i++) {
3663                         max_lb_gain -= (i * 6);
3664                         if (max_lb_gain < 6)
3665                                 break;
3666                 }
3667
3668                 if ((phy->rev < 7) ||
3669                     !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
3670                         if (phy_register == B43_PHY_RFOVER) {
3671                                 return 0x1B3;
3672                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3673                                 extlna |= (i << 8);
3674                                 switch (lpd) {
3675                                 case LPD(0, 1, 1):
3676                                         return 0x0F92;
3677                                 case LPD(0, 0, 1):
3678                                 case LPD(1, 0, 1):
3679                                         return (0x0092 | extlna);
3680                                 case LPD(1, 0, 0):
3681                                         return (0x0093 | extlna);
3682                                 }
3683                                 B43_WARN_ON(1);
3684                         }
3685                         B43_WARN_ON(1);
3686                 } else {
3687                         if (phy_register == B43_PHY_RFOVER) {
3688                                 return 0x9B3;
3689                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3690                                 if (extlna)
3691                                         extlna |= 0x8000;
3692                                 extlna |= (i << 8);
3693                                 switch (lpd) {
3694                                 case LPD(0, 1, 1):
3695                                         return 0x8F92;
3696                                 case LPD(0, 0, 1):
3697                                         return (0x8092 | extlna);
3698                                 case LPD(1, 0, 1):
3699                                         return (0x2092 | extlna);
3700                                 case LPD(1, 0, 0):
3701                                         return (0x2093 | extlna);
3702                                 }
3703                                 B43_WARN_ON(1);
3704                         }
3705                         B43_WARN_ON(1);
3706                 }
3707         } else {
3708                 if ((phy->rev < 7) ||
3709                     !(sprom->r1.boardflags_lo & B43_BFL_EXTLNA)) {
3710                         if (phy_register == B43_PHY_RFOVER) {
3711                                 return 0x1B3;
3712                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3713                                 switch (lpd) {
3714                                 case LPD(0, 1, 1):
3715                                         return 0x0FB2;
3716                                 case LPD(0, 0, 1):
3717                                         return 0x00B2;
3718                                 case LPD(1, 0, 1):
3719                                         return 0x30B2;
3720                                 case LPD(1, 0, 0):
3721                                         return 0x30B3;
3722                                 }
3723                                 B43_WARN_ON(1);
3724                         }
3725                         B43_WARN_ON(1);
3726                 } else {
3727                         if (phy_register == B43_PHY_RFOVER) {
3728                                 return 0x9B3;
3729                         } else if (phy_register == B43_PHY_RFOVERVAL) {
3730                                 switch (lpd) {
3731                                 case LPD(0, 1, 1):
3732                                         return 0x8FB2;
3733                                 case LPD(0, 0, 1):
3734                                         return 0x80B2;
3735                                 case LPD(1, 0, 1):
3736                                         return 0x20B2;
3737                                 case LPD(1, 0, 0):
3738                                         return 0x20B3;
3739                                 }
3740                                 B43_WARN_ON(1);
3741                         }
3742                         B43_WARN_ON(1);
3743                 }
3744         }
3745         return 0;
3746 }
3747
3748 struct init2050_saved_values {
3749         /* Core registers */
3750         u16 reg_3EC;
3751         u16 reg_3E6;
3752         u16 reg_3F4;
3753         /* Radio registers */
3754         u16 radio_43;
3755         u16 radio_51;
3756         u16 radio_52;
3757         /* PHY registers */
3758         u16 phy_pgactl;
3759         u16 phy_base_5A;
3760         u16 phy_base_59;
3761         u16 phy_base_58;
3762         u16 phy_base_30;
3763         u16 phy_rfover;
3764         u16 phy_rfoverval;
3765         u16 phy_analogover;
3766         u16 phy_analogoverval;
3767         u16 phy_crs0;
3768         u16 phy_classctl;
3769         u16 phy_lo_mask;
3770         u16 phy_lo_ctl;
3771         u16 phy_syncctl;
3772 };
3773
3774 u16 b43_radio_init2050(struct b43_wldev *dev)
3775 {
3776         struct b43_phy *phy = &dev->phy;
3777         struct init2050_saved_values sav;
3778         u16 rcc;
3779         u16 radio78;
3780         u16 ret;
3781         u16 i, j;
3782         u32 tmp1 = 0, tmp2 = 0;
3783
3784         memset(&sav, 0, sizeof(sav));   /* get rid of "may be used uninitialized..." */
3785
3786         sav.radio_43 = b43_radio_read16(dev, 0x43);
3787         sav.radio_51 = b43_radio_read16(dev, 0x51);
3788         sav.radio_52 = b43_radio_read16(dev, 0x52);
3789         sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
3790         sav.phy_base_5A = b43_phy_read(dev, B43_PHY_BASE(0x5A));
3791         sav.phy_base_59 = b43_phy_read(dev, B43_PHY_BASE(0x59));
3792         sav.phy_base_58 = b43_phy_read(dev, B43_PHY_BASE(0x58));
3793
3794         if (phy->type == B43_PHYTYPE_B) {
3795                 sav.phy_base_30 = b43_phy_read(dev, B43_PHY_BASE(0x30));
3796                 sav.reg_3EC = b43_read16(dev, 0x3EC);
3797
3798                 b43_phy_write(dev, B43_PHY_BASE(0x30), 0xFF);
3799                 b43_write16(dev, 0x3EC, 0x3F3F);
3800         } else if (phy->gmode || phy->rev >= 2) {
3801                 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3802                 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3803                 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
3804                 sav.phy_analogoverval =
3805                     b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
3806                 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
3807                 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
3808
3809                 b43_phy_write(dev, B43_PHY_ANALOGOVER,
3810                               b43_phy_read(dev, B43_PHY_ANALOGOVER)
3811                               | 0x0003);
3812                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3813                               b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
3814                               & 0xFFFC);
3815                 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
3816                               & 0x7FFF);
3817                 b43_phy_write(dev, B43_PHY_CLASSCTL,
3818                               b43_phy_read(dev, B43_PHY_CLASSCTL)
3819                               & 0xFFFC);
3820                 if (has_loopback_gain(phy)) {
3821                         sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
3822                         sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
3823
3824                         if (phy->rev >= 3)
3825                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
3826                         else
3827                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
3828                         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
3829                 }
3830
3831                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3832                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3833                                                    LPD(0, 1, 1)));
3834                 b43_phy_write(dev, B43_PHY_RFOVER,
3835                               radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
3836         }
3837         b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
3838
3839         sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
3840         b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
3841                       & 0xFF7F);
3842         sav.reg_3E6 = b43_read16(dev, 0x3E6);
3843         sav.reg_3F4 = b43_read16(dev, 0x3F4);
3844
3845         if (phy->analog == 0) {
3846                 b43_write16(dev, 0x03E6, 0x0122);
3847         } else {
3848                 if (phy->analog >= 2) {
3849                         b43_phy_write(dev, B43_PHY_BASE(0x03),
3850                                       (b43_phy_read(dev, B43_PHY_BASE(0x03))
3851                                        & 0xFFBF) | 0x40);
3852                 }
3853                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3854                             (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
3855         }
3856
3857         rcc = b43_radio_core_calibration_value(dev);
3858
3859         if (phy->type == B43_PHYTYPE_B)
3860                 b43_radio_write16(dev, 0x78, 0x26);
3861         if (phy->gmode || phy->rev >= 2) {
3862                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3863                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3864                                                    LPD(0, 1, 1)));
3865         }
3866         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
3867         b43_phy_write(dev, B43_PHY_BASE(0x2B), 0x1403);
3868         if (phy->gmode || phy->rev >= 2) {
3869                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3870                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3871                                                    LPD(0, 0, 1)));
3872         }
3873         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
3874         b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
3875                           | 0x0004);
3876         if (phy->radio_rev == 8) {
3877                 b43_radio_write16(dev, 0x43, 0x1F);
3878         } else {
3879                 b43_radio_write16(dev, 0x52, 0);
3880                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
3881                                               & 0xFFF0) | 0x0009);
3882         }
3883         b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3884
3885         for (i = 0; i < 16; i++) {
3886                 b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0480);
3887                 b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
3888                 b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
3889                 if (phy->gmode || phy->rev >= 2) {
3890                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3891                                       radio2050_rfover_val(dev,
3892                                                            B43_PHY_RFOVERVAL,
3893                                                            LPD(1, 0, 1)));
3894                 }
3895                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3896                 udelay(10);
3897                 if (phy->gmode || phy->rev >= 2) {
3898                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3899                                       radio2050_rfover_val(dev,
3900                                                            B43_PHY_RFOVERVAL,
3901                                                            LPD(1, 0, 1)));
3902                 }
3903                 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3904                 udelay(10);
3905                 if (phy->gmode || phy->rev >= 2) {
3906                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3907                                       radio2050_rfover_val(dev,
3908                                                            B43_PHY_RFOVERVAL,
3909                                                            LPD(1, 0, 0)));
3910                 }
3911                 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3912                 udelay(20);
3913                 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3914                 b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3915                 if (phy->gmode || phy->rev >= 2) {
3916                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
3917                                       radio2050_rfover_val(dev,
3918                                                            B43_PHY_RFOVERVAL,
3919                                                            LPD(1, 0, 1)));
3920                 }
3921                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3922         }
3923         udelay(10);
3924
3925         b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3926         tmp1++;
3927         tmp1 >>= 9;
3928
3929         for (i = 0; i < 16; i++) {
3930                 radio78 = ((flip_4bit(i) << 1) | 0x20);
3931                 b43_radio_write16(dev, 0x78, radio78);
3932                 udelay(10);
3933                 for (j = 0; j < 16; j++) {
3934                         b43_phy_write(dev, B43_PHY_BASE(0x5A), 0x0D80);
3935                         b43_phy_write(dev, B43_PHY_BASE(0x59), 0xC810);
3936                         b43_phy_write(dev, B43_PHY_BASE(0x58), 0x000D);
3937                         if (phy->gmode || phy->rev >= 2) {
3938                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3939                                               radio2050_rfover_val(dev,
3940                                                                    B43_PHY_RFOVERVAL,
3941                                                                    LPD(1, 0,
3942                                                                        1)));
3943                         }
3944                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3945                         udelay(10);
3946                         if (phy->gmode || phy->rev >= 2) {
3947                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3948                                               radio2050_rfover_val(dev,
3949                                                                    B43_PHY_RFOVERVAL,
3950                                                                    LPD(1, 0,
3951                                                                        1)));
3952                         }
3953                         b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3954                         udelay(10);
3955                         if (phy->gmode || phy->rev >= 2) {
3956                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3957                                               radio2050_rfover_val(dev,
3958                                                                    B43_PHY_RFOVERVAL,
3959                                                                    LPD(1, 0,
3960                                                                        0)));
3961                         }
3962                         b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3963                         udelay(10);
3964                         tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3965                         b43_phy_write(dev, B43_PHY_BASE(0x58), 0);
3966                         if (phy->gmode || phy->rev >= 2) {
3967                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3968                                               radio2050_rfover_val(dev,
3969                                                                    B43_PHY_RFOVERVAL,
3970                                                                    LPD(1, 0,
3971                                                                        1)));
3972                         }
3973                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3974                 }
3975                 tmp2++;
3976                 tmp2 >>= 8;
3977                 if (tmp1 < tmp2)
3978                         break;
3979         }
3980
3981         /* Restore the registers */
3982         b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
3983         b43_radio_write16(dev, 0x51, sav.radio_51);
3984         b43_radio_write16(dev, 0x52, sav.radio_52);
3985         b43_radio_write16(dev, 0x43, sav.radio_43);
3986         b43_phy_write(dev, B43_PHY_BASE(0x5A), sav.phy_base_5A);
3987         b43_phy_write(dev, B43_PHY_BASE(0x59), sav.phy_base_59);
3988         b43_phy_write(dev, B43_PHY_BASE(0x58), sav.phy_base_58);
3989         b43_write16(dev, 0x3E6, sav.reg_3E6);
3990         if (phy->analog != 0)
3991                 b43_write16(dev, 0x3F4, sav.reg_3F4);
3992         b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
3993         b43_synth_pu_workaround(dev, phy->channel);
3994         if (phy->type == B43_PHYTYPE_B) {
3995                 b43_phy_write(dev, B43_PHY_BASE(0x30), sav.phy_base_30);
3996                 b43_write16(dev, 0x3EC, sav.reg_3EC);
3997         } else if (phy->gmode) {
3998                 b43_write16(dev, B43_MMIO_PHY_RADIO,
3999                             b43_read16(dev, B43_MMIO_PHY_RADIO)
4000                             & 0x7FFF);
4001                 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
4002                 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
4003                 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
4004                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
4005                               sav.phy_analogoverval);
4006                 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
4007                 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
4008                 if (has_loopback_gain(phy)) {
4009                         b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
4010                         b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
4011                 }
4012         }
4013         if (i > 15)
4014                 ret = radio78;
4015         else
4016                 ret = rcc;
4017
4018         return ret;
4019 }
4020
4021 void b43_radio_init2060(struct b43_wldev *dev)
4022 {
4023         int err;
4024
4025         b43_radio_write16(dev, 0x0004, 0x00C0);
4026         b43_radio_write16(dev, 0x0005, 0x0008);
4027         b43_radio_write16(dev, 0x0009, 0x0040);
4028         b43_radio_write16(dev, 0x0005, 0x00AA);
4029         b43_radio_write16(dev, 0x0032, 0x008F);
4030         b43_radio_write16(dev, 0x0006, 0x008F);
4031         b43_radio_write16(dev, 0x0034, 0x008F);
4032         b43_radio_write16(dev, 0x002C, 0x0007);
4033         b43_radio_write16(dev, 0x0082, 0x0080);
4034         b43_radio_write16(dev, 0x0080, 0x0000);
4035         b43_radio_write16(dev, 0x003F, 0x00DA);
4036         b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
4037         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
4038         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
4039         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
4040         msleep(1);              /* delay 400usec */
4041
4042         b43_radio_write16(dev, 0x0081,
4043                           (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
4044         msleep(1);              /* delay 400usec */
4045
4046         b43_radio_write16(dev, 0x0005,
4047                           (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
4048         b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
4049         b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
4050         b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
4051         b43_radio_write16(dev, 0x0081,
4052                           (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
4053         b43_radio_write16(dev, 0x0005,
4054                           (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
4055         b43_phy_write(dev, 0x0063, 0xDDC6);
4056         b43_phy_write(dev, 0x0069, 0x07BE);
4057         b43_phy_write(dev, 0x006A, 0x0000);
4058
4059         err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
4060         B43_WARN_ON(err);
4061
4062         msleep(1);
4063 }
4064
4065 static inline u16 freq_r3A_value(u16 frequency)
4066 {
4067         u16 value;
4068
4069         if (frequency < 5091)
4070                 value = 0x0040;
4071         else if (frequency < 5321)
4072                 value = 0x0000;
4073         else if (frequency < 5806)
4074                 value = 0x0080;
4075         else
4076                 value = 0x0040;
4077
4078         return value;
4079 }
4080
4081 void b43_radio_set_tx_iq(struct b43_wldev *dev)
4082 {
4083         static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
4084         static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
4085         u16 tmp = b43_radio_read16(dev, 0x001E);
4086         int i, j;
4087
4088         for (i = 0; i < 5; i++) {
4089                 for (j = 0; j < 5; j++) {
4090                         if (tmp == (data_high[i] << 4 | data_low[j])) {
4091                                 b43_phy_write(dev, 0x0069,
4092                                               (i - j) << 8 | 0x00C0);
4093                                 return;
4094                         }
4095                 }
4096         }
4097 }
4098
4099 int b43_radio_selectchannel(struct b43_wldev *dev,
4100                             u8 channel, int synthetic_pu_workaround)
4101 {
4102         struct b43_phy *phy = &dev->phy;
4103         u16 r8, tmp;
4104         u16 freq;
4105         u16 channelcookie;
4106
4107         if (channel == 0xFF) {
4108                 switch (phy->type) {
4109                 case B43_PHYTYPE_A:
4110                         channel = B43_DEFAULT_CHANNEL_A;
4111                         break;
4112                 case B43_PHYTYPE_B:
4113                 case B43_PHYTYPE_G:
4114                         channel = B43_DEFAULT_CHANNEL_BG;
4115                         break;
4116                 default:
4117                         B43_WARN_ON(1);
4118                 }
4119         }
4120
4121         /* First we set the channel radio code to prevent the
4122          * firmware from sending ghost packets.
4123          */
4124         channelcookie = channel;
4125         if (phy->type == B43_PHYTYPE_A)
4126                 channelcookie |= 0x100;
4127         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
4128
4129         if (phy->type == B43_PHYTYPE_A) {
4130                 if (channel > 200)
4131                         return -EINVAL;
4132                 freq = channel2freq_a(channel);
4133
4134                 r8 = b43_radio_read16(dev, 0x0008);
4135                 b43_write16(dev, 0x03F0, freq);
4136                 b43_radio_write16(dev, 0x0008, r8);
4137
4138                 //TODO: write max channel TX power? to Radio 0x2D
4139                 tmp = b43_radio_read16(dev, 0x002E);
4140                 tmp &= 0x0080;
4141                 //TODO: OR tmp with the Power out estimation for this channel?
4142                 b43_radio_write16(dev, 0x002E, tmp);
4143
4144                 if (freq >= 4920 && freq <= 5500) {
4145                         /*
4146                          * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
4147                          *    = (freq * 0.025862069
4148                          */
4149                         r8 = 3 * freq / 116;    /* is equal to r8 = freq * 0.025862 */
4150                 }
4151                 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
4152                 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
4153                 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
4154                 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
4155                                                 & 0x000F) | (r8 << 4));
4156                 b43_radio_write16(dev, 0x002A, (r8 << 4));
4157                 b43_radio_write16(dev, 0x002B, (r8 << 4));
4158                 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
4159                                                 & 0x00F0) | (r8 << 4));
4160                 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
4161                                                 & 0xFF0F) | 0x00B0);
4162                 b43_radio_write16(dev, 0x0035, 0x00AA);
4163                 b43_radio_write16(dev, 0x0036, 0x0085);
4164                 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
4165                                                 & 0xFF20) |
4166                                   freq_r3A_value(freq));
4167                 b43_radio_write16(dev, 0x003D,
4168                                   b43_radio_read16(dev, 0x003D) & 0x00FF);
4169                 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
4170                                                 & 0xFF7F) | 0x0080);
4171                 b43_radio_write16(dev, 0x0035,
4172                                   b43_radio_read16(dev, 0x0035) & 0xFFEF);
4173                 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
4174                                                 & 0xFFEF) | 0x0010);
4175                 b43_radio_set_tx_iq(dev);
4176                 //TODO: TSSI2dbm workaround
4177                 b43_phy_xmitpower(dev); //FIXME correct?
4178         } else {
4179                 if ((channel < 1) || (channel > 14))
4180                         return -EINVAL;
4181
4182                 if (synthetic_pu_workaround)
4183                         b43_synth_pu_workaround(dev, channel);
4184
4185                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
4186
4187                 if (channel == 14) {
4188                         if (dev->dev->bus->sprom.r1.country_code ==
4189                             SSB_SPROM1CCODE_JAPAN)
4190                                 b43_hf_write(dev,
4191                                              b43_hf_read(dev) & ~B43_HF_ACPR);
4192                         else
4193                                 b43_hf_write(dev,
4194                                              b43_hf_read(dev) | B43_HF_ACPR);
4195                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
4196                                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
4197                                     | (1 << 11));
4198                 } else {
4199                         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
4200                                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
4201                                     & 0xF7BF);
4202                 }
4203         }
4204
4205         phy->channel = channel;
4206         /* Wait for the radio to tune to the channel and stabilize. */
4207         msleep(8);
4208
4209         return 0;
4210 }
4211
4212 /* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
4213 static u16 b43_get_txgain_base_band(u16 txpower)
4214 {
4215         u16 ret;
4216
4217         B43_WARN_ON(txpower > 63);
4218
4219         if (txpower >= 54)
4220                 ret = 2;
4221         else if (txpower >= 49)
4222                 ret = 4;
4223         else if (txpower >= 44)
4224                 ret = 5;
4225         else
4226                 ret = 6;
4227
4228         return ret;
4229 }
4230
4231 /* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
4232 static u16 b43_get_txgain_freq_power_amp(u16 txpower)
4233 {
4234         u16 ret;
4235
4236         B43_WARN_ON(txpower > 63);
4237
4238         if (txpower >= 32)
4239                 ret = 0;
4240         else if (txpower >= 25)
4241                 ret = 1;
4242         else if (txpower >= 20)
4243                 ret = 2;
4244         else if (txpower >= 12)
4245                 ret = 3;
4246         else
4247                 ret = 4;
4248
4249         return ret;
4250 }
4251
4252 /* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
4253 static u16 b43_get_txgain_dac(u16 txpower)
4254 {
4255         u16 ret;
4256
4257         B43_WARN_ON(txpower > 63);
4258
4259         if (txpower >= 54)
4260                 ret = txpower - 53;
4261         else if (txpower >= 49)
4262                 ret = txpower - 42;
4263         else if (txpower >= 44)
4264                 ret = txpower - 37;
4265         else if (txpower >= 32)
4266                 ret = txpower - 32;
4267         else if (txpower >= 25)
4268                 ret = txpower - 20;
4269         else if (txpower >= 20)
4270                 ret = txpower - 13;
4271         else if (txpower >= 12)
4272                 ret = txpower - 8;
4273         else
4274                 ret = txpower;
4275
4276         return ret;
4277 }
4278
4279 static void b43_radio_set_txpower_a(struct b43_wldev *dev, u16 txpower)
4280 {
4281         struct b43_phy *phy = &dev->phy;
4282         u16 pamp, base, dac, t;
4283
4284         txpower = limit_value(txpower, 0, 63);
4285
4286         pamp = b43_get_txgain_freq_power_amp(txpower);
4287         pamp <<= 5;
4288         pamp &= 0x00E0;
4289         b43_phy_write(dev, 0x0019, pamp);
4290
4291         base = b43_get_txgain_base_band(txpower);
4292         base &= 0x000F;
4293         b43_phy_write(dev, 0x0017, base | 0x0020);
4294
4295         t = b43_ofdmtab_read16(dev, 0x3000, 1);
4296         t &= 0x0007;
4297
4298         dac = b43_get_txgain_dac(txpower);
4299         dac <<= 3;
4300         dac |= t;
4301
4302         b43_ofdmtab_write16(dev, 0x3000, 1, dac);
4303
4304         phy->txpwr_offset = txpower;
4305
4306         //TODO: FuncPlaceholder (Adjust BB loft cancel)
4307 }
4308
4309 void b43_radio_turn_on(struct b43_wldev *dev)
4310 {
4311         struct b43_phy *phy = &dev->phy;
4312         int err;
4313         u8 channel;
4314
4315         might_sleep();
4316
4317         if (phy->radio_on)
4318                 return;
4319
4320         switch (phy->type) {
4321         case B43_PHYTYPE_A:
4322                 b43_radio_write16(dev, 0x0004, 0x00C0);
4323                 b43_radio_write16(dev, 0x0005, 0x0008);
4324                 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
4325                 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
4326                 b43_radio_init2060(dev);
4327                 break;
4328         case B43_PHYTYPE_B:
4329         case B43_PHYTYPE_G:
4330                 b43_phy_write(dev, 0x0015, 0x8000);
4331                 b43_phy_write(dev, 0x0015, 0xCC00);
4332                 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
4333                 if (phy->radio_off_context.valid) {
4334                         /* Restore the RFover values. */
4335                         b43_phy_write(dev, B43_PHY_RFOVER,
4336                                       phy->radio_off_context.rfover);
4337                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
4338                                       phy->radio_off_context.rfoverval);
4339                         phy->radio_off_context.valid = 0;
4340                 }
4341                 channel = phy->channel;
4342                 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
4343                 err |= b43_radio_selectchannel(dev, channel, 0);
4344                 B43_WARN_ON(err);
4345                 break;
4346         default:
4347                 B43_WARN_ON(1);
4348         }
4349         phy->radio_on = 1;
4350 }
4351
4352 void b43_radio_turn_off(struct b43_wldev *dev, bool force)
4353 {
4354         struct b43_phy *phy = &dev->phy;
4355
4356         if (!phy->radio_on && !force)
4357                 return;
4358
4359         if (phy->type == B43_PHYTYPE_A) {
4360                 b43_radio_write16(dev, 0x0004, 0x00FF);
4361                 b43_radio_write16(dev, 0x0005, 0x00FB);
4362                 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
4363                 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
4364         }
4365         if (phy->type == B43_PHYTYPE_G && dev->dev->id.revision >= 5) {
4366                 u16 rfover, rfoverval;
4367
4368                 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
4369                 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
4370                 if (!force) {
4371                         phy->radio_off_context.rfover = rfover;
4372                         phy->radio_off_context.rfoverval = rfoverval;
4373                         phy->radio_off_context.valid = 1;
4374                 }
4375                 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
4376                 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
4377         } else
4378                 b43_phy_write(dev, 0x0015, 0xAA00);
4379         phy->radio_on = 0;
4380 }