git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/kernel/head_64.S

   1 /*
   2  *  PowerPC version
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *  Adapted for Power Macintosh by Paul Mackerras.
   8  *  Low-level exception handlers and MMU support
   9  *  rewritten by Paul Mackerras.
  10  *    Copyright (C) 1996 Paul Mackerras.
  11  *
  12  *  Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
  13  *    Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
  14  *
  15  *  This file contains the low-level support and setup for the
  16  *  PowerPC-64 platform, including trap and interrupt dispatch.
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  */
  23
  24 #include <linux/threads.h>
  25 #include <asm/reg.h>
  26 #include <asm/page.h>
  27 #include <asm/mmu.h>
  28 #include <asm/ppc_asm.h>
  29 #include <asm/asm-offsets.h>
  30 #include <asm/bug.h>
  31 #include <asm/cputable.h>
  32 #include <asm/setup.h>
  33 #include <asm/hvcall.h>
  34 #include <asm/iseries/lpar_map.h>
  35 #include <asm/thread_info.h>
  36 #include <asm/firmware.h>
  37
  38 #define DO_SOFT_DISABLE
  39
  40 /*
  41  * We layout physical memory as follows:
  42  * 0x0000 - 0x00ff : Secondary processor spin code
  43  * 0x0100 - 0x2fff : pSeries Interrupt prologs
  44  * 0x3000 - 0x5fff : interrupt support, iSeries and common interrupt prologs
  45  * 0x6000 - 0x6fff : Initial (CPU0) segment table
  46  * 0x7000 - 0x7fff : FWNMI data area
  47  * 0x8000 -        : Early init and support code
  48  */
  49
  50 /*
  51  *   SPRG Usage
  52  *
  53  *   Register   Definition
  54  *
  55  *   SPRG0      reserved for hypervisor
  56  *   SPRG1      temp - used to save gpr
  57  *   SPRG2      temp - used to save gpr
  58  *   SPRG3      virt addr of paca
  59  */
  60
  61 /*
  62  * Entering into this code we make the following assumptions:
  63  *  For pSeries:
  64  *   1. The MMU is off & open firmware is running in real mode.
  65  *   2. The kernel is entered at __start
  66  *
  67  *  For iSeries:
  68  *   1. The MMU is on (as it always is for iSeries)
  69  *   2. The kernel is entered at system_reset_iSeries
  70  */
  71
  72         .text
  73         .globl  _stext
  74 _stext:
  75 _GLOBAL(__start)
  76         /* NOP this out unconditionally */
  77 BEGIN_FTR_SECTION
  78         b       .__start_initialization_multiplatform
  79 END_FTR_SECTION(0, 1)
  80
  81         /* Catch branch to 0 in real mode */
  82         trap
  83
  84         /* Secondary processors spin on this value until it goes to 1. */
  85         .globl  __secondary_hold_spinloop
  86 __secondary_hold_spinloop:
  87         .llong  0x0
  88
  89         /* Secondary processors write this value with their cpu # */
  90         /* after they enter the spin loop immediately below.      */
  91         .globl  __secondary_hold_acknowledge
  92 __secondary_hold_acknowledge:
  93         .llong  0x0
  94
  95 #ifdef CONFIG_PPC_ISERIES
  96         /*
  97          * At offset 0x20, there is a pointer to iSeries LPAR data.
  98          * This is required by the hypervisor
  99          */
 100         . = 0x20
 101         .llong hvReleaseData-KERNELBASE
 102 #endif /* CONFIG_PPC_ISERIES */
 103
 104         . = 0x60
 105 /*
 106  * The following code is used on pSeries to hold secondary processors
 107  * in a spin loop after they have been freed from OpenFirmware, but
 108  * before the bulk of the kernel has been relocated.  This code
 109  * is relocated to physical address 0x60 before prom_init is run.
 110  * All of it must fit below the first exception vector at 0x100.
 111  */
 112 _GLOBAL(__secondary_hold)
 113         mfmsr   r24
 114         ori     r24,r24,MSR_RI
 115         mtmsrd  r24                     /* RI on */
 116
 117         /* Grab our physical cpu number */
 118         mr      r24,r3
 119
 120         /* Tell the master cpu we're here */
 121         /* Relocation is off & we are located at an address less */
 122         /* than 0x100, so only need to grab low order offset.    */
 123         std     r24,__secondary_hold_acknowledge@l(0)
 124         sync
 125
 126         /* All secondary cpus wait here until told to start. */
 127 100:    ld      r4,__secondary_hold_spinloop@l(0)
 128         cmpdi   0,r4,1
 129         bne     100b
 130
 131 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
 132         LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
 133         mtctr   r4
 134         mr      r3,r24
 135         bctr
 136 #else
 137         BUG_OPCODE
 138 #endif
 139
 140 /* This value is used to mark exception frames on the stack. */
 141         .section ".toc","aw"
 142 exception_marker:
 143         .tc     ID_72656773_68657265[TC],0x7265677368657265
 144         .text
 145
 146 /*
 147  * The following macros define the code that appears as
 148  * the prologue to each of the exception handlers.  They
 149  * are split into two parts to allow a single kernel binary
 150  * to be used for pSeries and iSeries.
 151  * LOL.  One day... - paulus
 152  */
 153
 154 /*
 155  * We make as much of the exception code common between native
 156  * exception handlers (including pSeries LPAR) and iSeries LPAR
 157  * implementations as possible.
 158  */
 159
 160 /*
 161  * This is the start of the interrupt handlers for pSeries
 162  * This code runs with relocation off.
 163  */
 164 #define EX_R9           0
 165 #define EX_R10          8
 166 #define EX_R11          16
 167 #define EX_R12          24
 168 #define EX_R13          32
 169 #define EX_SRR0         40
 170 #define EX_DAR          48
 171 #define EX_DSISR        56
 172 #define EX_CCR          60
 173 #define EX_R3           64
 174 #define EX_LR           72
 175
 176 /*
 177  * We're short on space and time in the exception prolog, so we can't
 178  * use the normal SET_REG_IMMEDIATE macro. Normally we just need the
 179  * low halfword of the address, but for Kdump we need the whole low
 180  * word.
 181  */
 182 #ifdef CONFIG_CRASH_DUMP
 183 #define LOAD_HANDLER(reg, label)                                        \
 184         oris    reg,reg,(label)@h;      /* virt addr of handler ... */  \
 185         ori     reg,reg,(label)@l;      /* .. and the rest */
 186 #else
 187 #define LOAD_HANDLER(reg, label)                                        \
 188         ori     reg,reg,(label)@l;      /* virt addr of handler ... */
 189 #endif
 190
 191 /*
 192  * Equal to EXCEPTION_PROLOG_PSERIES, except that it forces 64bit mode.
 193  * The firmware calls the registered system_reset_fwnmi and
 194  * machine_check_fwnmi handlers in 32bit mode if the cpu happens to run
 195  * a 32bit application at the time of the event.
 196  * This firmware bug is present on POWER4 and JS20.
 197  */
 198 #define EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(area, label)               \
 199         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 200         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 201         std     r10,area+EX_R10(r13);                                   \
 202         std     r11,area+EX_R11(r13);                                   \
 203         std     r12,area+EX_R12(r13);                                   \
 204         mfspr   r9,SPRN_SPRG1;                                          \
 205         std     r9,area+EX_R13(r13);                                    \
 206         mfcr    r9;                                                     \
 207         clrrdi  r12,r13,32;             /* get high part of &label */   \
 208         mfmsr   r10;                                                    \
 209         /* force 64bit mode */                                          \
 210         li      r11,5;                  /* MSR_SF_LG|MSR_ISF_LG */      \
 211         rldimi  r10,r11,61,0;           /* insert into top 3 bits */    \
 212         /* done 64bit mode */                                           \
 213         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
 214         LOAD_HANDLER(r12,label)                                         \
 215         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
 216         mtspr   SPRN_SRR0,r12;                                          \
 217         mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
 218         mtspr   SPRN_SRR1,r10;                                          \
 219         rfid;                                                           \
 220         b       .       /* prevent speculative execution */
 221
 222 #define EXCEPTION_PROLOG_PSERIES(area, label)                           \
 223         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 224         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 225         std     r10,area+EX_R10(r13);                                   \
 226         std     r11,area+EX_R11(r13);                                   \
 227         std     r12,area+EX_R12(r13);                                   \
 228         mfspr   r9,SPRN_SPRG1;                                          \
 229         std     r9,area+EX_R13(r13);                                    \
 230         mfcr    r9;                                                     \
 231         clrrdi  r12,r13,32;             /* get high part of &label */   \
 232         mfmsr   r10;                                                    \
 233         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
 234         LOAD_HANDLER(r12,label)                                         \
 235         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
 236         mtspr   SPRN_SRR0,r12;                                          \
 237         mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
 238         mtspr   SPRN_SRR1,r10;                                          \
 239         rfid;                                                           \
 240         b       .       /* prevent speculative execution */
 241
 242 /*
 243  * This is the start of the interrupt handlers for iSeries
 244  * This code runs with relocation on.
 245  */
 246 #define EXCEPTION_PROLOG_ISERIES_1(area)                                \
 247         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 248         std     r9,area+EX_R9(r13);     /* save r9 - r12 */             \
 249         std     r10,area+EX_R10(r13);                                   \
 250         std     r11,area+EX_R11(r13);                                   \
 251         std     r12,area+EX_R12(r13);                                   \
 252         mfspr   r9,SPRN_SPRG1;                                          \
 253         std     r9,area+EX_R13(r13);                                    \
 254         mfcr    r9
 255
 256 #define EXCEPTION_PROLOG_ISERIES_2                                      \
 257         mfmsr   r10;                                                    \
 258         ld      r12,PACALPPACAPTR(r13);                                 \
 259         ld      r11,LPPACASRR0(r12);                                    \
 260         ld      r12,LPPACASRR1(r12);                                    \
 261         ori     r10,r10,MSR_RI;                                         \
 262         mtmsrd  r10,1
 263
 264 /*
 265  * The common exception prolog is used for all except a few exceptions
 266  * such as a segment miss on a kernel address.  We have to be prepared
 267  * to take another exception from the point where we first touch the
 268  * kernel stack onwards.
 269  *
 270  * On entry r13 points to the paca, r9-r13 are saved in the paca,
 271  * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
 272  * SRR1, and relocation is on.
 273  */
 274 #define EXCEPTION_PROLOG_COMMON(n, area)                                   \
 275         andi.   r10,r12,MSR_PR;         /* See if coming from user      */ \
 276         mr      r10,r1;                 /* Save r1                      */ \
 277         subi    r1,r1,INT_FRAME_SIZE;   /* alloc frame on kernel stack  */ \
 278         beq-    1f;                                                        \
 279         ld      r1,PACAKSAVE(r13);      /* kernel stack to use          */ \
 280 1:      cmpdi   cr1,r1,0;               /* check if r1 is in userspace  */ \
 281         bge-    cr1,2f;                 /* abort if it is               */ \
 282         b       3f;                                                        \
 283 2:      li      r1,(n);                 /* will be reloaded later       */ \
 284         sth     r1,PACA_TRAP_SAVE(r13);                                    \
 285         b       bad_stack;                                                 \
 286 3:      std     r9,_CCR(r1);            /* save CR in stackframe        */ \
 287         std     r11,_NIP(r1);           /* save SRR0 in stackframe      */ \
 288         std     r12,_MSR(r1);           /* save SRR1 in stackframe      */ \
 289         std     r10,0(r1);              /* make stack chain pointer     */ \
 290         std     r0,GPR0(r1);            /* save r0 in stackframe        */ \
 291         std     r10,GPR1(r1);           /* save r1 in stackframe        */ \
 292         ACCOUNT_CPU_USER_ENTRY(r9, r10);                                   \
 293         std     r2,GPR2(r1);            /* save r2 in stackframe        */ \
 294         SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe   */ \
 295         SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe    */ \
 296         ld      r9,area+EX_R9(r13);     /* move r9, r10 to stackframe   */ \
 297         ld      r10,area+EX_R10(r13);                                      \
 298         std     r9,GPR9(r1);                                               \
 299         std     r10,GPR10(r1);                                             \
 300         ld      r9,area+EX_R11(r13);    /* move r11 - r13 to stackframe */ \
 301         ld      r10,area+EX_R12(r13);                                      \
 302         ld      r11,area+EX_R13(r13);                                      \
 303         std     r9,GPR11(r1);                                              \
 304         std     r10,GPR12(r1);                                             \
 305         std     r11,GPR13(r1);                                             \
 306         ld      r2,PACATOC(r13);        /* get kernel TOC into r2       */ \
 307         mflr    r9;                     /* save LR in stackframe        */ \
 308         std     r9,_LINK(r1);                                              \
 309         mfctr   r10;                    /* save CTR in stackframe       */ \
 310         std     r10,_CTR(r1);                                              \
 311         lbz     r10,PACASOFTIRQEN(r13);                            \
 312         mfspr   r11,SPRN_XER;           /* save XER in stackframe       */ \
 313         std     r10,SOFTE(r1);                                             \
 314         std     r11,_XER(r1);                                              \
 315         li      r9,(n)+1;                                                  \
 316         std     r9,_TRAP(r1);           /* set trap number              */ \
 317         li      r10,0;                                                     \
 318         ld      r11,exception_marker@toc(r2);                              \
 319         std     r10,RESULT(r1);         /* clear regs->result           */ \
 320         std     r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame      */
 321
 322 /*
 323  * Exception vectors.
 324  */
 325 #define STD_EXCEPTION_PSERIES(n, label)                 \
 326         . = n;                                          \
 327         .globl label##_pSeries;                         \
 328 label##_pSeries:                                        \
 329         HMT_MEDIUM;                                     \
 330         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 331         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 332
 333 #define HSTD_EXCEPTION_PSERIES(n, label)                \
 334         . = n;                                          \
 335         .globl label##_pSeries;                         \
 336 label##_pSeries:                                        \
 337         HMT_MEDIUM;                                     \
 338         mtspr   SPRN_SPRG1,r20;         /* save r20 */  \
 339         mfspr   r20,SPRN_HSRR0;         /* copy HSRR0 to SRR0 */ \
 340         mtspr   SPRN_SRR0,r20;                          \
 341         mfspr   r20,SPRN_HSRR1;         /* copy HSRR0 to SRR0 */ \
 342         mtspr   SPRN_SRR1,r20;                          \
 343         mfspr   r20,SPRN_SPRG1;         /* restore r20 */ \
 344         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 345         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
 346
 347
 348 #define MASKABLE_EXCEPTION_PSERIES(n, label)                            \
 349         . = n;                                                          \
 350         .globl label##_pSeries;                                         \
 351 label##_pSeries:                                                        \
 352         HMT_MEDIUM;                                                     \
 353         mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
 354         mfspr   r13,SPRN_SPRG3;         /* get paca address into r13 */ \
 355         std     r9,PACA_EXGEN+EX_R9(r13);       /* save r9, r10 */      \
 356         std     r10,PACA_EXGEN+EX_R10(r13);                             \
 357         lbz     r10,PACASOFTIRQEN(r13);                                 \
 358         mfcr    r9;                                                     \
 359         cmpwi   r10,0;                                                  \
 360         beq     masked_interrupt;                                       \
 361         mfspr   r10,SPRN_SPRG1;                                         \
 362         std     r10,PACA_EXGEN+EX_R13(r13);                             \
 363         std     r11,PACA_EXGEN+EX_R11(r13);                             \
 364         std     r12,PACA_EXGEN+EX_R12(r13);                             \
 365         clrrdi  r12,r13,32;             /* get high part of &label */   \
 366         mfmsr   r10;                                                    \
 367         mfspr   r11,SPRN_SRR0;          /* save SRR0 */                 \
 368         LOAD_HANDLER(r12,label##_common)                                \
 369         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI;                           \
 370         mtspr   SPRN_SRR0,r12;                                          \
 371         mfspr   r12,SPRN_SRR1;          /* and SRR1 */                  \
 372         mtspr   SPRN_SRR1,r10;                                          \
 373         rfid;                                                           \
 374         b       .       /* prevent speculative execution */
 375
 376 #define STD_EXCEPTION_ISERIES(n, label, area)           \
 377         .globl label##_iSeries;                         \
 378 label##_iSeries:                                        \
 379         HMT_MEDIUM;                                     \
 380         mtspr   SPRN_SPRG1,r13;         /* save r13 */  \
 381         EXCEPTION_PROLOG_ISERIES_1(area);               \
 382         EXCEPTION_PROLOG_ISERIES_2;                     \
 383         b       label##_common
 384
 385 #define MASKABLE_EXCEPTION_ISERIES(n, label)                            \
 386         .globl label##_iSeries;                                         \
 387 label##_iSeries:                                                        \
 388         HMT_MEDIUM;                                                     \
 389         mtspr   SPRN_SPRG1,r13;         /* save r13 */                  \
 390         EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN);                         \
 391         lbz     r10,PACASOFTIRQEN(r13);                                 \
 392         cmpwi   0,r10,0;                                                \
 393         beq-    label##_iSeries_masked;                                 \
 394         EXCEPTION_PROLOG_ISERIES_2;                                     \
 395         b       label##_common;                                         \
 396
 397 #ifdef CONFIG_PPC_ISERIES
 398 #define DISABLE_INTS                            \
 399         li      r11,0;                          \
 400         stb     r11,PACASOFTIRQEN(r13);         \
 401 BEGIN_FW_FTR_SECTION;                           \
 402         stb     r11,PACAHARDIRQEN(r13);         \
 403 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES);   \
 404 BEGIN_FW_FTR_SECTION;                           \
 405         mfmsr   r10;                            \
 406         ori     r10,r10,MSR_EE;                 \
 407         mtmsrd  r10,1;                          \
 408 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
 409
 410 #else
 411 #define DISABLE_INTS                            \
 412         li      r11,0;                          \
 413         stb     r11,PACASOFTIRQEN(r13);         \
 414         stb     r11,PACAHARDIRQEN(r13)
 415
 416 #endif /* CONFIG_PPC_ISERIES */
 417
 418 #define ENABLE_INTS                             \
 419         ld      r12,_MSR(r1);                   \
 420         mfmsr   r11;                            \
 421         rlwimi  r11,r12,0,MSR_EE;               \
 422         mtmsrd  r11,1
 423
 424 #define STD_EXCEPTION_COMMON(trap, label, hdlr)         \
 425         .align  7;                                      \
 426         .globl label##_common;                          \
 427 label##_common:                                         \
 428         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 429         DISABLE_INTS;                                   \
 430         bl      .save_nvgprs;                           \
 431         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 432         bl      hdlr;                                   \
 433         b       .ret_from_except
 434
 435 /*
 436  * Like STD_EXCEPTION_COMMON, but for exceptions that can occur
 437  * in the idle task and therefore need the special idle handling.
 438  */
 439 #define STD_EXCEPTION_COMMON_IDLE(trap, label, hdlr)    \
 440         .align  7;                                      \
 441         .globl label##_common;                          \
 442 label##_common:                                         \
 443         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 444         FINISH_NAP;                                     \
 445         DISABLE_INTS;                                   \
 446         bl      .save_nvgprs;                           \
 447         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 448         bl      hdlr;                                   \
 449         b       .ret_from_except
 450
 451 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr)    \
 452         .align  7;                                      \
 453         .globl label##_common;                          \
 454 label##_common:                                         \
 455         EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN);      \
 456         FINISH_NAP;                                     \
 457         DISABLE_INTS;                                   \
 458         bl      .ppc64_runlatch_on;                     \
 459         addi    r3,r1,STACK_FRAME_OVERHEAD;             \
 460         bl      hdlr;                                   \
 461         b       .ret_from_except_lite
 462
 463 /*
 464  * When the idle code in power4_idle puts the CPU into NAP mode,
 465  * it has to do so in a loop, and relies on the external interrupt
 466  * and decrementer interrupt entry code to get it out of the loop.
 467  * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
 468  * to signal that it is in the loop and needs help to get out.
 469  */
 470 #ifdef CONFIG_PPC_970_NAP
 471 #define FINISH_NAP                              \
 472 BEGIN_FTR_SECTION                               \
 473         clrrdi  r11,r1,THREAD_SHIFT;            \
 474         ld      r9,TI_LOCAL_FLAGS(r11);         \
 475         andi.   r10,r9,_TLF_NAPPING;            \
 476         bnel    power4_fixup_nap;               \
 477 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
 478 #else
 479 #define FINISH_NAP
 480 #endif
 481
 482 /*
 483  * Start of pSeries system interrupt routines
 484  */
 485         . = 0x100
 486         .globl __start_interrupts
 487 __start_interrupts:
 488
 489         STD_EXCEPTION_PSERIES(0x100, system_reset)
 490
 491         . = 0x200
 492 _machine_check_pSeries:
 493         HMT_MEDIUM
 494         mtspr   SPRN_SPRG1,r13          /* save r13 */
 495         EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common)
 496
 497         . = 0x300
 498         .globl data_access_pSeries
 499 data_access_pSeries:
 500         HMT_MEDIUM
 501         mtspr   SPRN_SPRG1,r13
 502 BEGIN_FTR_SECTION
 503         mtspr   SPRN_SPRG2,r12
 504         mfspr   r13,SPRN_DAR
 505         mfspr   r12,SPRN_DSISR
 506         srdi    r13,r13,60
 507         rlwimi  r13,r12,16,0x20
 508         mfcr    r12
 509         cmpwi   r13,0x2c
 510         beq     do_stab_bolted_pSeries
 511         mtcrf   0x80,r12
 512         mfspr   r12,SPRN_SPRG2
 513 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
 514         EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
 515
 516         . = 0x380
 517         .globl data_access_slb_pSeries
 518 data_access_slb_pSeries:
 519         HMT_MEDIUM
 520         mtspr   SPRN_SPRG1,r13
 521         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 522         std     r3,PACA_EXSLB+EX_R3(r13)
 523         mfspr   r3,SPRN_DAR
 524         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
 525         mfcr    r9
 526 #ifdef __DISABLED__
 527         /* Keep that around for when we re-implement dynamic VSIDs */
 528         cmpdi   r3,0
 529         bge     slb_miss_user_pseries
 530 #endif /* __DISABLED__ */
 531         std     r10,PACA_EXSLB+EX_R10(r13)
 532         std     r11,PACA_EXSLB+EX_R11(r13)
 533         std     r12,PACA_EXSLB+EX_R12(r13)
 534         mfspr   r10,SPRN_SPRG1
 535         std     r10,PACA_EXSLB+EX_R13(r13)
 536         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 537         b       .slb_miss_realmode      /* Rel. branch works in real mode */
 538
 539         STD_EXCEPTION_PSERIES(0x400, instruction_access)
 540
 541         . = 0x480
 542         .globl instruction_access_slb_pSeries
 543 instruction_access_slb_pSeries:
 544         HMT_MEDIUM
 545         mtspr   SPRN_SPRG1,r13
 546         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 547         std     r3,PACA_EXSLB+EX_R3(r13)
 548         mfspr   r3,SPRN_SRR0            /* SRR0 is faulting address */
 549         std     r9,PACA_EXSLB+EX_R9(r13)        /* save r9 - r12 */
 550         mfcr    r9
 551 #ifdef __DISABLED__
 552         /* Keep that around for when we re-implement dynamic VSIDs */
 553         cmpdi   r3,0
 554         bge     slb_miss_user_pseries
 555 #endif /* __DISABLED__ */
 556         std     r10,PACA_EXSLB+EX_R10(r13)
 557         std     r11,PACA_EXSLB+EX_R11(r13)
 558         std     r12,PACA_EXSLB+EX_R12(r13)
 559         mfspr   r10,SPRN_SPRG1
 560         std     r10,PACA_EXSLB+EX_R13(r13)
 561         mfspr   r12,SPRN_SRR1           /* and SRR1 */
 562         b       .slb_miss_realmode      /* Rel. branch works in real mode */
 563
 564         MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt)
 565         STD_EXCEPTION_PSERIES(0x600, alignment)
 566         STD_EXCEPTION_PSERIES(0x700, program_check)
 567         STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
 568         MASKABLE_EXCEPTION_PSERIES(0x900, decrementer)
 569         STD_EXCEPTION_PSERIES(0xa00, trap_0a)
 570         STD_EXCEPTION_PSERIES(0xb00, trap_0b)
 571
 572         . = 0xc00
 573         .globl  system_call_pSeries
 574 system_call_pSeries:
 575         HMT_MEDIUM
 576         mr      r9,r13
 577         mfmsr   r10
 578         mfspr   r13,SPRN_SPRG3
 579         mfspr   r11,SPRN_SRR0
 580         clrrdi  r12,r13,32
 581         oris    r12,r12,system_call_common@h
 582         ori     r12,r12,system_call_common@l
 583         mtspr   SPRN_SRR0,r12
 584         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
 585         mfspr   r12,SPRN_SRR1
 586         mtspr   SPRN_SRR1,r10
 587         rfid
 588         b       .       /* prevent speculative execution */
 589
 590         STD_EXCEPTION_PSERIES(0xd00, single_step)
 591         STD_EXCEPTION_PSERIES(0xe00, trap_0e)
 592
 593         /* We need to deal with the Altivec unavailable exception
 594          * here which is at 0xf20, thus in the middle of the
 595          * prolog code of the PerformanceMonitor one. A little
 596          * trickery is thus necessary
 597          */
 598         . = 0xf00
 599         b       performance_monitor_pSeries
 600
 601         STD_EXCEPTION_PSERIES(0xf20, altivec_unavailable)
 602
 603 #ifdef CONFIG_CBE_RAS
 604         HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error)
 605 #endif /* CONFIG_CBE_RAS */
 606         STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
 607 #ifdef CONFIG_CBE_RAS
 608         HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance)
 609 #endif /* CONFIG_CBE_RAS */
 610         STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
 611 #ifdef CONFIG_CBE_RAS
 612         HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal)
 613 #endif /* CONFIG_CBE_RAS */
 614
 615         . = 0x3000
 616
 617 /*** pSeries interrupt support ***/
 618
 619         /* moved from 0xf00 */
 620         STD_EXCEPTION_PSERIES(., performance_monitor)
 621
 622 /*
 623  * An interrupt came in while soft-disabled; clear EE in SRR1,
 624  * clear paca->hard_enabled and return.
 625  */
 626 masked_interrupt:
 627         stb     r10,PACAHARDIRQEN(r13)
 628         mtcrf   0x80,r9
 629         ld      r9,PACA_EXGEN+EX_R9(r13)
 630         mfspr   r10,SPRN_SRR1
 631         rldicl  r10,r10,48,1            /* clear MSR_EE */
 632         rotldi  r10,r10,16
 633         mtspr   SPRN_SRR1,r10
 634         ld      r10,PACA_EXGEN+EX_R10(r13)
 635         mfspr   r13,SPRN_SPRG1
 636         rfid
 637         b       .
 638
 639         .align  7
 640 do_stab_bolted_pSeries:
 641         mtcrf   0x80,r12
 642         mfspr   r12,SPRN_SPRG2
 643         EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
 644
 645 /*
 646  * We have some room here  we use that to put
 647  * the peries slb miss user trampoline code so it's reasonably
 648  * away from slb_miss_user_common to avoid problems with rfid
 649  *
 650  * This is used for when the SLB miss handler has to go virtual,
 651  * which doesn't happen for now anymore but will once we re-implement
 652  * dynamic VSIDs for shared page tables
 653  */
 654 #ifdef __DISABLED__
 655 slb_miss_user_pseries:
 656         std     r10,PACA_EXGEN+EX_R10(r13)
 657         std     r11,PACA_EXGEN+EX_R11(r13)
 658         std     r12,PACA_EXGEN+EX_R12(r13)
 659         mfspr   r10,SPRG1
 660         ld      r11,PACA_EXSLB+EX_R9(r13)
 661         ld      r12,PACA_EXSLB+EX_R3(r13)
 662         std     r10,PACA_EXGEN+EX_R13(r13)
 663         std     r11,PACA_EXGEN+EX_R9(r13)
 664         std     r12,PACA_EXGEN+EX_R3(r13)
 665         clrrdi  r12,r13,32
 666         mfmsr   r10
 667         mfspr   r11,SRR0                        /* save SRR0 */
 668         ori     r12,r12,slb_miss_user_common@l  /* virt addr of handler */
 669         ori     r10,r10,MSR_IR|MSR_DR|MSR_RI
 670         mtspr   SRR0,r12
 671         mfspr   r12,SRR1                        /* and SRR1 */
 672         mtspr   SRR1,r10
 673         rfid
 674         b       .                               /* prevent spec. execution */
 675 #endif /* __DISABLED__ */
 676
 677 /*
 678  * Vectors for the FWNMI option.  Share common code.
 679  */
 680         .globl system_reset_fwnmi
 681       .align 7
 682 system_reset_fwnmi:
 683         HMT_MEDIUM
 684         mtspr   SPRN_SPRG1,r13          /* save r13 */
 685         EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXGEN, system_reset_common)
 686
 687         .globl machine_check_fwnmi
 688       .align 7
 689 machine_check_fwnmi:
 690         HMT_MEDIUM
 691         mtspr   SPRN_SPRG1,r13          /* save r13 */
 692         EXCEPTION_PROLOG_PSERIES_FORCE_64BIT(PACA_EXMC, machine_check_common)
 693
 694 #ifdef CONFIG_PPC_ISERIES
 695 /***  ISeries-LPAR interrupt handlers ***/
 696
 697         STD_EXCEPTION_ISERIES(0x200, machine_check, PACA_EXMC)
 698
 699         .globl data_access_iSeries
 700 data_access_iSeries:
 701         mtspr   SPRN_SPRG1,r13
 702 BEGIN_FTR_SECTION
 703         mtspr   SPRN_SPRG2,r12
 704         mfspr   r13,SPRN_DAR
 705         mfspr   r12,SPRN_DSISR
 706         srdi    r13,r13,60
 707         rlwimi  r13,r12,16,0x20
 708         mfcr    r12
 709         cmpwi   r13,0x2c
 710         beq     .do_stab_bolted_iSeries
 711         mtcrf   0x80,r12
 712         mfspr   r12,SPRN_SPRG2
 713 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
 714         EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
 715         EXCEPTION_PROLOG_ISERIES_2
 716         b       data_access_common
 717
 718 .do_stab_bolted_iSeries:
 719         mtcrf   0x80,r12
 720         mfspr   r12,SPRN_SPRG2
 721         EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
 722         EXCEPTION_PROLOG_ISERIES_2
 723         b       .do_stab_bolted
 724
 725         .globl  data_access_slb_iSeries
 726 data_access_slb_iSeries:
 727         mtspr   SPRN_SPRG1,r13          /* save r13 */
 728         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 729         std     r3,PACA_EXSLB+EX_R3(r13)
 730         mfspr   r3,SPRN_DAR
 731         std     r9,PACA_EXSLB+EX_R9(r13)
 732         mfcr    r9
 733 #ifdef __DISABLED__
 734         cmpdi   r3,0
 735         bge     slb_miss_user_iseries
 736 #endif
 737         std     r10,PACA_EXSLB+EX_R10(r13)
 738         std     r11,PACA_EXSLB+EX_R11(r13)
 739         std     r12,PACA_EXSLB+EX_R12(r13)
 740         mfspr   r10,SPRN_SPRG1
 741         std     r10,PACA_EXSLB+EX_R13(r13)
 742         ld      r12,PACALPPACAPTR(r13)
 743         ld      r12,LPPACASRR1(r12)
 744         b       .slb_miss_realmode
 745
 746         STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN)
 747
 748         .globl  instruction_access_slb_iSeries
 749 instruction_access_slb_iSeries:
 750         mtspr   SPRN_SPRG1,r13          /* save r13 */
 751         mfspr   r13,SPRN_SPRG3          /* get paca address into r13 */
 752         std     r3,PACA_EXSLB+EX_R3(r13)
 753         ld      r3,PACALPPACAPTR(r13)
 754         ld      r3,LPPACASRR0(r3)       /* get SRR0 value */
 755         std     r9,PACA_EXSLB+EX_R9(r13)
 756         mfcr    r9
 757 #ifdef __DISABLED__
 758         cmpdi   r3,0
 759         bge     .slb_miss_user_iseries
 760 #endif
 761         std     r10,PACA_EXSLB+EX_R10(r13)
 762         std     r11,PACA_EXSLB+EX_R11(r13)
 763         std     r12,PACA_EXSLB+EX_R12(r13)
 764         mfspr   r10,SPRN_SPRG1
 765         std     r10,PACA_EXSLB+EX_R13(r13)
 766         ld      r12,PACALPPACAPTR(r13)
 767         ld      r12,LPPACASRR1(r12)
 768         b       .slb_miss_realmode
 769
 770 #ifdef __DISABLED__
 771 slb_miss_user_iseries:
 772         std     r10,PACA_EXGEN+EX_R10(r13)
 773         std     r11,PACA_EXGEN+EX_R11(r13)
 774         std     r12,PACA_EXGEN+EX_R12(r13)
 775         mfspr   r10,SPRG1
 776         ld      r11,PACA_EXSLB+EX_R9(r13)
 777         ld      r12,PACA_EXSLB+EX_R3(r13)
 778         std     r10,PACA_EXGEN+EX_R13(r13)
 779         std     r11,PACA_EXGEN+EX_R9(r13)
 780         std     r12,PACA_EXGEN+EX_R3(r13)
 781         EXCEPTION_PROLOG_ISERIES_2
 782         b       slb_miss_user_common
 783 #endif
 784
 785         MASKABLE_EXCEPTION_ISERIES(0x500, hardware_interrupt)
 786         STD_EXCEPTION_ISERIES(0x600, alignment, PACA_EXGEN)
 787         STD_EXCEPTION_ISERIES(0x700, program_check, PACA_EXGEN)
 788         STD_EXCEPTION_ISERIES(0x800, fp_unavailable, PACA_EXGEN)
 789         MASKABLE_EXCEPTION_ISERIES(0x900, decrementer)
 790         STD_EXCEPTION_ISERIES(0xa00, trap_0a, PACA_EXGEN)
 791         STD_EXCEPTION_ISERIES(0xb00, trap_0b, PACA_EXGEN)
 792
 793         .globl  system_call_iSeries
 794 system_call_iSeries:
 795         mr      r9,r13
 796         mfspr   r13,SPRN_SPRG3
 797         EXCEPTION_PROLOG_ISERIES_2
 798         b       system_call_common
 799
 800         STD_EXCEPTION_ISERIES( 0xd00, single_step, PACA_EXGEN)
 801         STD_EXCEPTION_ISERIES( 0xe00, trap_0e, PACA_EXGEN)
 802         STD_EXCEPTION_ISERIES( 0xf00, performance_monitor, PACA_EXGEN)
 803
 804         .globl system_reset_iSeries
 805 system_reset_iSeries:
 806         mfspr   r13,SPRN_SPRG3          /* Get paca address */
 807         mfmsr   r24
 808         ori     r24,r24,MSR_RI
 809         mtmsrd  r24                     /* RI on */
 810         lhz     r24,PACAPACAINDEX(r13)  /* Get processor # */
 811         cmpwi   0,r24,0                 /* Are we processor 0? */
 812         beq     .__start_initialization_iSeries /* Start up the first processor */
 813         mfspr   r4,SPRN_CTRLF
 814         li      r5,CTRL_RUNLATCH        /* Turn off the run light */
 815         andc    r4,r4,r5
 816         mtspr   SPRN_CTRLT,r4
 817
 818 1:
 819         HMT_LOW
 820 #ifdef CONFIG_SMP
 821         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor
 822                                          * should start */
 823         sync
 824         LOAD_REG_IMMEDIATE(r3,current_set)
 825         sldi    r28,r24,3               /* get current_set[cpu#] */
 826         ldx     r3,r3,r28
 827         addi    r1,r3,THREAD_SIZE
 828         subi    r1,r1,STACK_FRAME_OVERHEAD
 829
 830         cmpwi   0,r23,0
 831         beq     iSeries_secondary_smp_loop      /* Loop until told to go */
 832         bne     __secondary_start               /* Loop until told to go */
 833 iSeries_secondary_smp_loop:
 834         /* Let the Hypervisor know we are alive */
 835         /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
 836         lis     r3,0x8002
 837         rldicr  r3,r3,32,15             /* r0 = (r3 << 32) & 0xffff000000000000 */
 838 #else /* CONFIG_SMP */
 839         /* Yield the processor.  This is required for non-SMP kernels
 840                 which are running on multi-threaded machines. */
 841         lis     r3,0x8000
 842         rldicr  r3,r3,32,15             /* r3 = (r3 << 32) & 0xffff000000000000 */
 843         addi    r3,r3,18                /* r3 = 0x8000000000000012 which is "yield" */
 844         li      r4,0                    /* "yield timed" */
 845         li      r5,-1                   /* "yield forever" */
 846 #endif /* CONFIG_SMP */
 847         li      r0,-1                   /* r0=-1 indicates a Hypervisor call */
 848         sc                              /* Invoke the hypervisor via a system call */
 849         mfspr   r13,SPRN_SPRG3          /* Put r13 back ???? */
 850         b       1b                      /* If SMP not configured, secondaries
 851                                          * loop forever */
 852
 853 decrementer_iSeries_masked:
 854         /* We may not have a valid TOC pointer in here. */
 855         li      r11,1
 856         ld      r12,PACALPPACAPTR(r13)
 857         stb     r11,LPPACADECRINT(r12)
 858         LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
 859         lwz     r12,0(r12)
 860         mtspr   SPRN_DEC,r12
 861         /* fall through */
 862
 863 hardware_interrupt_iSeries_masked:
 864         mtcrf   0x80,r9         /* Restore regs */
 865         ld      r12,PACALPPACAPTR(r13)
 866         ld      r11,LPPACASRR0(r12)
 867         ld      r12,LPPACASRR1(r12)
 868         mtspr   SPRN_SRR0,r11
 869         mtspr   SPRN_SRR1,r12
 870         ld      r9,PACA_EXGEN+EX_R9(r13)
 871         ld      r10,PACA_EXGEN+EX_R10(r13)
 872         ld      r11,PACA_EXGEN+EX_R11(r13)
 873         ld      r12,PACA_EXGEN+EX_R12(r13)
 874         ld      r13,PACA_EXGEN+EX_R13(r13)
 875         rfid
 876         b       .       /* prevent speculative execution */
 877 #endif /* CONFIG_PPC_ISERIES */
 878
 879 /*** Common interrupt handlers ***/
 880
 881         STD_EXCEPTION_COMMON(0x100, system_reset, .system_reset_exception)
 882
 883         /*
 884          * Machine check is different because we use a different
 885          * save area: PACA_EXMC instead of PACA_EXGEN.
 886          */
 887         .align  7
 888         .globl machine_check_common
 889 machine_check_common:
 890         EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
 891         FINISH_NAP
 892         DISABLE_INTS
 893         bl      .save_nvgprs
 894         addi    r3,r1,STACK_FRAME_OVERHEAD
 895         bl      .machine_check_exception
 896         b       .ret_from_except
 897
 898         STD_EXCEPTION_COMMON_LITE(0x900, decrementer, .timer_interrupt)
 899         STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
 900         STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
 901         STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
 902         STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
 903         STD_EXCEPTION_COMMON_IDLE(0xf00, performance_monitor, .performance_monitor_exception)
 904         STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
 905 #ifdef CONFIG_ALTIVEC
 906         STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
 907 #else
 908         STD_EXCEPTION_COMMON(0x1700, altivec_assist, .unknown_exception)
 909 #endif
 910 #ifdef CONFIG_CBE_RAS
 911         STD_EXCEPTION_COMMON(0x1200, cbe_system_error, .cbe_system_error_exception)
 912         STD_EXCEPTION_COMMON(0x1600, cbe_maintenance, .cbe_maintenance_exception)
 913         STD_EXCEPTION_COMMON(0x1800, cbe_thermal, .cbe_thermal_exception)
 914 #endif /* CONFIG_CBE_RAS */
 915
 916 /*
 917  * Here we have detected that the kernel stack pointer is bad.
 918  * R9 contains the saved CR, r13 points to the paca,
 919  * r10 contains the (bad) kernel stack pointer,
 920  * r11 and r12 contain the saved SRR0 and SRR1.
 921  * We switch to using an emergency stack, save the registers there,
 922  * and call kernel_bad_stack(), which panics.
 923  */
 924 bad_stack:
 925         ld      r1,PACAEMERGSP(r13)
 926         subi    r1,r1,64+INT_FRAME_SIZE
 927         std     r9,_CCR(r1)
 928         std     r10,GPR1(r1)
 929         std     r11,_NIP(r1)
 930         std     r12,_MSR(r1)
 931         mfspr   r11,SPRN_DAR
 932         mfspr   r12,SPRN_DSISR
 933         std     r11,_DAR(r1)
 934         std     r12,_DSISR(r1)
 935         mflr    r10
 936         mfctr   r11
 937         mfxer   r12
 938         std     r10,_LINK(r1)
 939         std     r11,_CTR(r1)
 940         std     r12,_XER(r1)
 941         SAVE_GPR(0,r1)
 942         SAVE_GPR(2,r1)
 943         SAVE_4GPRS(3,r1)
 944         SAVE_2GPRS(7,r1)
 945         SAVE_10GPRS(12,r1)
 946         SAVE_10GPRS(22,r1)
 947         lhz     r12,PACA_TRAP_SAVE(r13)
 948         std     r12,_TRAP(r1)
 949         addi    r11,r1,INT_FRAME_SIZE
 950         std     r11,0(r1)
 951         li      r12,0
 952         std     r12,0(r11)
 953         ld      r2,PACATOC(r13)
 954 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
 955         bl      .kernel_bad_stack
 956         b       1b
 957
 958 /*
 959  * Return from an exception with minimal checks.
 960  * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
 961  * If interrupts have been enabled, or anything has been
 962  * done that might have changed the scheduling status of
 963  * any task or sent any task a signal, you should use
 964  * ret_from_except or ret_from_except_lite instead of this.
 965  */
 966 fast_exc_return_irq:                    /* restores irq state too */
 967         ld      r3,SOFTE(r1)
 968         ld      r12,_MSR(r1)
 969         stb     r3,PACASOFTIRQEN(r13)   /* restore paca->soft_enabled */
 970         rldicl  r4,r12,49,63            /* get MSR_EE to LSB */
 971         stb     r4,PACAHARDIRQEN(r13)   /* restore paca->hard_enabled */
 972         b       1f
 973
 974         .globl  fast_exception_return
 975 fast_exception_return:
 976         ld      r12,_MSR(r1)
 977 1:      ld      r11,_NIP(r1)
 978         andi.   r3,r12,MSR_RI           /* check if RI is set */
 979         beq-    unrecov_fer
 980
 981 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 982         andi.   r3,r12,MSR_PR
 983         beq     2f
 984         ACCOUNT_CPU_USER_EXIT(r3, r4)
 985 2:
 986 #endif
 987
 988         ld      r3,_CCR(r1)
 989         ld      r4,_LINK(r1)
 990         ld      r5,_CTR(r1)
 991         ld      r6,_XER(r1)
 992         mtcr    r3
 993         mtlr    r4
 994         mtctr   r5
 995         mtxer   r6
 996         REST_GPR(0, r1)
 997         REST_8GPRS(2, r1)
 998
 999         mfmsr   r10
1000         rldicl  r10,r10,48,1            /* clear EE */
1001         rldicr  r10,r10,16,61           /* clear RI (LE is 0 already) */
1002         mtmsrd  r10,1
1003
1004         mtspr   SPRN_SRR1,r12
1005         mtspr   SPRN_SRR0,r11
1006         REST_4GPRS(10, r1)
1007         ld      r1,GPR1(r1)
1008         rfid
1009         b       .       /* prevent speculative execution */
1010
1011 unrecov_fer:
1012         bl      .save_nvgprs
1013 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1014         bl      .unrecoverable_exception
1015         b       1b
1016
1017 /*
1018  * Here r13 points to the paca, r9 contains the saved CR,
1019  * SRR0 and SRR1 are saved in r11 and r12,
1020  * r9 - r13 are saved in paca->exgen.
1021  */
1022         .align  7
1023         .globl data_access_common
1024 data_access_common:
1025         mfspr   r10,SPRN_DAR
1026         std     r10,PACA_EXGEN+EX_DAR(r13)
1027         mfspr   r10,SPRN_DSISR
1028         stw     r10,PACA_EXGEN+EX_DSISR(r13)
1029         EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
1030         ld      r3,PACA_EXGEN+EX_DAR(r13)
1031         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
1032         li      r5,0x300
1033         b       .do_hash_page           /* Try to handle as hpte fault */
1034
1035         .align  7
1036         .globl instruction_access_common
1037 instruction_access_common:
1038         EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
1039         ld      r3,_NIP(r1)
1040         andis.  r4,r12,0x5820
1041         li      r5,0x400
1042         b       .do_hash_page           /* Try to handle as hpte fault */
1043
1044 /*
1045  * Here is the common SLB miss user that is used when going to virtual
1046  * mode for SLB misses, that is currently not used
1047  */
1048 #ifdef __DISABLED__
1049         .align  7
1050         .globl  slb_miss_user_common
1051 slb_miss_user_common:
1052         mflr    r10
1053         std     r3,PACA_EXGEN+EX_DAR(r13)
1054         stw     r9,PACA_EXGEN+EX_CCR(r13)
1055         std     r10,PACA_EXGEN+EX_LR(r13)
1056         std     r11,PACA_EXGEN+EX_SRR0(r13)
1057         bl      .slb_allocate_user
1058
1059         ld      r10,PACA_EXGEN+EX_LR(r13)
1060         ld      r3,PACA_EXGEN+EX_R3(r13)
1061         lwz     r9,PACA_EXGEN+EX_CCR(r13)
1062         ld      r11,PACA_EXGEN+EX_SRR0(r13)
1063         mtlr    r10
1064         beq-    slb_miss_fault
1065
1066         andi.   r10,r12,MSR_RI          /* check for unrecoverable exception */
1067         beq-    unrecov_user_slb
1068         mfmsr   r10
1069
1070 .machine push
1071 .machine "power4"
1072         mtcrf   0x80,r9
1073 .machine pop
1074
1075         clrrdi  r10,r10,2               /* clear RI before setting SRR0/1 */
1076         mtmsrd  r10,1
1077
1078         mtspr   SRR0,r11
1079         mtspr   SRR1,r12
1080
1081         ld      r9,PACA_EXGEN+EX_R9(r13)
1082         ld      r10,PACA_EXGEN+EX_R10(r13)
1083         ld      r11,PACA_EXGEN+EX_R11(r13)
1084         ld      r12,PACA_EXGEN+EX_R12(r13)
1085         ld      r13,PACA_EXGEN+EX_R13(r13)
1086         rfid
1087         b       .
1088
1089 slb_miss_fault:
1090         EXCEPTION_PROLOG_COMMON(0x380, PACA_EXGEN)
1091         ld      r4,PACA_EXGEN+EX_DAR(r13)
1092         li      r5,0
1093         std     r4,_DAR(r1)
1094         std     r5,_DSISR(r1)
1095         b       handle_page_fault
1096
1097 unrecov_user_slb:
1098         EXCEPTION_PROLOG_COMMON(0x4200, PACA_EXGEN)
1099         DISABLE_INTS
1100         bl      .save_nvgprs
1101 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1102         bl      .unrecoverable_exception
1103         b       1b
1104
1105 #endif /* __DISABLED__ */
1106
1107
1108 /*
1109  * r13 points to the PACA, r9 contains the saved CR,
1110  * r12 contain the saved SRR1, SRR0 is still ready for return
1111  * r3 has the faulting address
1112  * r9 - r13 are saved in paca->exslb.
1113  * r3 is saved in paca->slb_r3
1114  * We assume we aren't going to take any exceptions during this procedure.
1115  */
1116 _GLOBAL(slb_miss_realmode)
1117         mflr    r10
1118
1119         stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
1120         std     r10,PACA_EXSLB+EX_LR(r13)       /* save LR */
1121
1122         bl      .slb_allocate_realmode
1123
1124         /* All done -- return from exception. */
1125
1126         ld      r10,PACA_EXSLB+EX_LR(r13)
1127         ld      r3,PACA_EXSLB+EX_R3(r13)
1128         lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
1129 #ifdef CONFIG_PPC_ISERIES
1130 BEGIN_FW_FTR_SECTION
1131         ld      r11,PACALPPACAPTR(r13)
1132         ld      r11,LPPACASRR0(r11)             /* get SRR0 value */
1133 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1134 #endif /* CONFIG_PPC_ISERIES */
1135
1136         mtlr    r10
1137
1138         andi.   r10,r12,MSR_RI  /* check for unrecoverable exception */
1139         beq-    unrecov_slb
1140
1141 .machine        push
1142 .machine        "power4"
1143         mtcrf   0x80,r9
1144         mtcrf   0x01,r9         /* slb_allocate uses cr0 and cr7 */
1145 .machine        pop
1146
1147 #ifdef CONFIG_PPC_ISERIES
1148 BEGIN_FW_FTR_SECTION
1149         mtspr   SPRN_SRR0,r11
1150         mtspr   SPRN_SRR1,r12
1151 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1152 #endif /* CONFIG_PPC_ISERIES */
1153         ld      r9,PACA_EXSLB+EX_R9(r13)
1154         ld      r10,PACA_EXSLB+EX_R10(r13)
1155         ld      r11,PACA_EXSLB+EX_R11(r13)
1156         ld      r12,PACA_EXSLB+EX_R12(r13)
1157         ld      r13,PACA_EXSLB+EX_R13(r13)
1158         rfid
1159         b       .       /* prevent speculative execution */
1160
1161 unrecov_slb:
1162         EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1163         DISABLE_INTS
1164         bl      .save_nvgprs
1165 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1166         bl      .unrecoverable_exception
1167         b       1b
1168
1169         .align  7
1170         .globl hardware_interrupt_common
1171         .globl hardware_interrupt_entry
1172 hardware_interrupt_common:
1173         EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
1174         FINISH_NAP
1175 hardware_interrupt_entry:
1176         DISABLE_INTS
1177         bl      .ppc64_runlatch_on
1178         addi    r3,r1,STACK_FRAME_OVERHEAD
1179         bl      .do_IRQ
1180         b       .ret_from_except_lite
1181
1182 #ifdef CONFIG_PPC_970_NAP
1183 power4_fixup_nap:
1184         andc    r9,r9,r10
1185         std     r9,TI_LOCAL_FLAGS(r11)
1186         ld      r10,_LINK(r1)           /* make idle task do the */
1187         std     r10,_NIP(r1)            /* equivalent of a blr */
1188         blr
1189 #endif
1190
1191         .align  7
1192         .globl alignment_common
1193 alignment_common:
1194         mfspr   r10,SPRN_DAR
1195         std     r10,PACA_EXGEN+EX_DAR(r13)
1196         mfspr   r10,SPRN_DSISR
1197         stw     r10,PACA_EXGEN+EX_DSISR(r13)
1198         EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1199         ld      r3,PACA_EXGEN+EX_DAR(r13)
1200         lwz     r4,PACA_EXGEN+EX_DSISR(r13)
1201         std     r3,_DAR(r1)
1202         std     r4,_DSISR(r1)
1203         bl      .save_nvgprs
1204         addi    r3,r1,STACK_FRAME_OVERHEAD
1205         ENABLE_INTS
1206         bl      .alignment_exception
1207         b       .ret_from_except
1208
1209         .align  7
1210         .globl program_check_common
1211 program_check_common:
1212         EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1213         bl      .save_nvgprs
1214         addi    r3,r1,STACK_FRAME_OVERHEAD
1215         ENABLE_INTS
1216         bl      .program_check_exception
1217         b       .ret_from_except
1218
1219         .align  7
1220         .globl fp_unavailable_common
1221 fp_unavailable_common:
1222         EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1223         bne     1f                      /* if from user, just load it up */
1224         bl      .save_nvgprs
1225         addi    r3,r1,STACK_FRAME_OVERHEAD
1226         ENABLE_INTS
1227         bl      .kernel_fp_unavailable_exception
1228         BUG_OPCODE
1229 1:      b       .load_up_fpu
1230
1231         .align  7
1232         .globl altivec_unavailable_common
1233 altivec_unavailable_common:
1234         EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1235 #ifdef CONFIG_ALTIVEC
1236 BEGIN_FTR_SECTION
1237         bne     .load_up_altivec        /* if from user, just load it up */
1238 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1239 #endif
1240         bl      .save_nvgprs
1241         addi    r3,r1,STACK_FRAME_OVERHEAD
1242         ENABLE_INTS
1243         bl      .altivec_unavailable_exception
1244         b       .ret_from_except
1245
1246 #ifdef CONFIG_ALTIVEC
1247 /*
1248  * load_up_altivec(unused, unused, tsk)
1249  * Disable VMX for the task which had it previously,
1250  * and save its vector registers in its thread_struct.
1251  * Enables the VMX for use in the kernel on return.
1252  * On SMP we know the VMX is free, since we give it up every
1253  * switch (ie, no lazy save of the vector registers).
1254  * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1255  */
1256 _STATIC(load_up_altivec)
1257         mfmsr   r5                      /* grab the current MSR */
1258         oris    r5,r5,MSR_VEC@h
1259         mtmsrd  r5                      /* enable use of VMX now */
1260         isync
1261
1262 /*
1263  * For SMP, we don't do lazy VMX switching because it just gets too
1264  * horrendously complex, especially when a task switches from one CPU
1265  * to another.  Instead we call giveup_altvec in switch_to.
1266  * VRSAVE isn't dealt with here, that is done in the normal context
1267  * switch code. Note that we could rely on vrsave value to eventually
1268  * avoid saving all of the VREGs here...
1269  */
1270 #ifndef CONFIG_SMP
1271         ld      r3,last_task_used_altivec@got(r2)
1272         ld      r4,0(r3)
1273         cmpdi   0,r4,0
1274         beq     1f
1275         /* Save VMX state to last_task_used_altivec's THREAD struct */
1276         addi    r4,r4,THREAD
1277         SAVE_32VRS(0,r5,r4)
1278         mfvscr  vr0
1279         li      r10,THREAD_VSCR
1280         stvx    vr0,r10,r4
1281         /* Disable VMX for last_task_used_altivec */
1282         ld      r5,PT_REGS(r4)
1283         ld      r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1284         lis     r6,MSR_VEC@h
1285         andc    r4,r4,r6
1286         std     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1287 1:
1288 #endif /* CONFIG_SMP */
1289         /* Hack: if we get an altivec unavailable trap with VRSAVE
1290          * set to all zeros, we assume this is a broken application
1291          * that fails to set it properly, and thus we switch it to
1292          * all 1's
1293          */
1294         mfspr   r4,SPRN_VRSAVE
1295         cmpdi   0,r4,0
1296         bne+    1f
1297         li      r4,-1
1298         mtspr   SPRN_VRSAVE,r4
1299 1:
1300         /* enable use of VMX after return */
1301         ld      r4,PACACURRENT(r13)
1302         addi    r5,r4,THREAD            /* Get THREAD */
1303         oris    r12,r12,MSR_VEC@h
1304         std     r12,_MSR(r1)
1305         li      r4,1
1306         li      r10,THREAD_VSCR
1307         stw     r4,THREAD_USED_VR(r5)
1308         lvx     vr0,r10,r5
1309         mtvscr  vr0
1310         REST_32VRS(0,r4,r5)
1311 #ifndef CONFIG_SMP
1312         /* Update last_task_used_math to 'current' */
1313         subi    r4,r5,THREAD            /* Back to 'current' */
1314         std     r4,0(r3)
1315 #endif /* CONFIG_SMP */
1316         /* restore registers and return */
1317         b       fast_exception_return
1318 #endif /* CONFIG_ALTIVEC */
1319
1320 /*
1321  * Hash table stuff
1322  */
1323         .align  7
1324 _GLOBAL(do_hash_page)
1325         std     r3,_DAR(r1)
1326         std     r4,_DSISR(r1)
1327
1328         andis.  r0,r4,0xa450            /* weird error? */
1329         bne-    handle_page_fault       /* if not, try to insert a HPTE */
1330 BEGIN_FTR_SECTION
1331         andis.  r0,r4,0x0020            /* Is it a segment table fault? */
1332         bne-    do_ste_alloc            /* If so handle it */
1333 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
1334
1335         /*
1336          * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
1337          * accessing a userspace segment (even from the kernel). We assume
1338          * kernel addresses always have the high bit set.
1339          */
1340         rlwinm  r4,r4,32-25+9,31-9,31-9 /* DSISR_STORE -> _PAGE_RW */
1341         rotldi  r0,r3,15                /* Move high bit into MSR_PR posn */
1342         orc     r0,r12,r0               /* MSR_PR | ~high_bit */
1343         rlwimi  r4,r0,32-13,30,30       /* becomes _PAGE_USER access bit */
1344         ori     r4,r4,1                 /* add _PAGE_PRESENT */
1345         rlwimi  r4,r5,22+2,31-2,31-2    /* Set _PAGE_EXEC if trap is 0x400 */
1346
1347         /*
1348          * On iSeries, we soft-disable interrupts here, then
1349          * hard-enable interrupts so that the hash_page code can spin on
1350          * the hash_table_lock without problems on a shared processor.
1351          */
1352         DISABLE_INTS
1353
1354         /*
1355          * r3 contains the faulting address
1356          * r4 contains the required access permissions
1357          * r5 contains the trap number
1358          *
1359          * at return r3 = 0 for success
1360          */
1361         bl      .hash_page              /* build HPTE if possible */
1362         cmpdi   r3,0                    /* see if hash_page succeeded */
1363
1364 #ifdef DO_SOFT_DISABLE
1365 BEGIN_FW_FTR_SECTION
1366         /*
1367          * If we had interrupts soft-enabled at the point where the
1368          * DSI/ISI occurred, and an interrupt came in during hash_page,
1369          * handle it now.
1370          * We jump to ret_from_except_lite rather than fast_exception_return
1371          * because ret_from_except_lite will check for and handle pending
1372          * interrupts if necessary.
1373          */
1374         beq     13f
1375 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1376 #endif
1377 BEGIN_FW_FTR_SECTION
1378         /*
1379          * Here we have interrupts hard-disabled, so it is sufficient
1380          * to restore paca->{soft,hard}_enable and get out.
1381          */
1382         beq     fast_exc_return_irq     /* Return from exception on success */
1383 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1384
1385         /* For a hash failure, we don't bother re-enabling interrupts */
1386         ble-    12f
1387
1388         /*
1389          * hash_page couldn't handle it, set soft interrupt enable back
1390          * to what it was before the trap.  Note that .local_irq_restore
1391          * handles any interrupts pending at this point.
1392          */
1393         ld      r3,SOFTE(r1)
1394         bl      .local_irq_restore
1395         b       11f
1396
1397 /* Here we have a page fault that hash_page can't handle. */
1398 handle_page_fault:
1399         ENABLE_INTS
1400 11:     ld      r4,_DAR(r1)
1401         ld      r5,_DSISR(r1)
1402         addi    r3,r1,STACK_FRAME_OVERHEAD
1403         bl      .do_page_fault
1404         cmpdi   r3,0
1405         beq+    13f
1406         bl      .save_nvgprs
1407         mr      r5,r3
1408         addi    r3,r1,STACK_FRAME_OVERHEAD
1409         lwz     r4,_DAR(r1)
1410         bl      .bad_page_fault
1411         b       .ret_from_except
1412
1413 13:     b       .ret_from_except_lite
1414
1415 /* We have a page fault that hash_page could handle but HV refused
1416  * the PTE insertion
1417  */
1418 12:     bl      .save_nvgprs
1419         addi    r3,r1,STACK_FRAME_OVERHEAD
1420         lwz     r4,_DAR(r1)
1421         bl      .low_hash_fault
1422         b       .ret_from_except
1423
1424         /* here we have a segment miss */
1425 do_ste_alloc:
1426         bl      .ste_allocate           /* try to insert stab entry */
1427         cmpdi   r3,0
1428         bne-    handle_page_fault
1429         b       fast_exception_return
1430
1431 /*
1432  * r13 points to the PACA, r9 contains the saved CR,
1433  * r11 and r12 contain the saved SRR0 and SRR1.
1434  * r9 - r13 are saved in paca->exslb.
1435  * We assume we aren't going to take any exceptions during this procedure.
1436  * We assume (DAR >> 60) == 0xc.
1437  */
1438         .align  7
1439 _GLOBAL(do_stab_bolted)
1440         stw     r9,PACA_EXSLB+EX_CCR(r13)       /* save CR in exc. frame */
1441         std     r11,PACA_EXSLB+EX_SRR0(r13)     /* save SRR0 in exc. frame */
1442
1443         /* Hash to the primary group */
1444         ld      r10,PACASTABVIRT(r13)
1445         mfspr   r11,SPRN_DAR
1446         srdi    r11,r11,28
1447         rldimi  r10,r11,7,52    /* r10 = first ste of the group */
1448
1449         /* Calculate VSID */
1450         /* This is a kernel address, so protovsid = ESID */
1451         ASM_VSID_SCRAMBLE(r11, r9)
1452         rldic   r9,r11,12,16    /* r9 = vsid << 12 */
1453
1454         /* Search the primary group for a free entry */
1455 1:      ld      r11,0(r10)      /* Test valid bit of the current ste    */
1456         andi.   r11,r11,0x80
1457         beq     2f
1458         addi    r10,r10,16
1459         andi.   r11,r10,0x70
1460         bne     1b
1461
1462         /* Stick for only searching the primary group for now.          */
1463         /* At least for now, we use a very simple random castout scheme */
1464         /* Use the TB as a random number ;  OR in 1 to avoid entry 0    */
1465         mftb    r11
1466         rldic   r11,r11,4,57    /* r11 = (r11 << 4) & 0x70 */
1467         ori     r11,r11,0x10
1468
1469         /* r10 currently points to an ste one past the group of interest */
1470         /* make it point to the randomly selected entry                 */
1471         subi    r10,r10,128
1472         or      r10,r10,r11     /* r10 is the entry to invalidate       */
1473
1474         isync                   /* mark the entry invalid               */
1475         ld      r11,0(r10)
1476         rldicl  r11,r11,56,1    /* clear the valid bit */
1477         rotldi  r11,r11,8
1478         std     r11,0(r10)
1479         sync
1480
1481         clrrdi  r11,r11,28      /* Get the esid part of the ste         */
1482         slbie   r11
1483
1484 2:      std     r9,8(r10)       /* Store the vsid part of the ste       */
1485         eieio
1486
1487         mfspr   r11,SPRN_DAR            /* Get the new esid                     */
1488         clrrdi  r11,r11,28      /* Permits a full 32b of ESID           */
1489         ori     r11,r11,0x90    /* Turn on valid and kp                 */
1490         std     r11,0(r10)      /* Put new entry back into the stab     */
1491
1492         sync
1493
1494         /* All done -- return from exception. */
1495         lwz     r9,PACA_EXSLB+EX_CCR(r13)       /* get saved CR */
1496         ld      r11,PACA_EXSLB+EX_SRR0(r13)     /* get saved SRR0 */
1497
1498         andi.   r10,r12,MSR_RI
1499         beq-    unrecov_slb
1500
1501         mtcrf   0x80,r9                 /* restore CR */
1502
1503         mfmsr   r10
1504         clrrdi  r10,r10,2
1505         mtmsrd  r10,1
1506
1507         mtspr   SPRN_SRR0,r11
1508         mtspr   SPRN_SRR1,r12
1509         ld      r9,PACA_EXSLB+EX_R9(r13)
1510         ld      r10,PACA_EXSLB+EX_R10(r13)
1511         ld      r11,PACA_EXSLB+EX_R11(r13)
1512         ld      r12,PACA_EXSLB+EX_R12(r13)
1513         ld      r13,PACA_EXSLB+EX_R13(r13)
1514         rfid
1515         b       .       /* prevent speculative execution */
1516
1517 /*
1518  * Space for CPU0's segment table.
1519  *
1520  * On iSeries, the hypervisor must fill in at least one entry before
1521  * we get control (with relocate on).  The address is give to the hv
1522  * as a page number (see xLparMap in lpardata.c), so this must be at a
1523  * fixed address (the linker can't compute (u64)&initial_stab >>
1524  * PAGE_SHIFT).
1525  */
1526         . = STAB0_OFFSET        /* 0x6000 */
1527         .globl initial_stab
1528 initial_stab:
1529         .space  4096
1530
1531 /*
1532  * Data area reserved for FWNMI option.
1533  * This address (0x7000) is fixed by the RPA.
1534  */
1535         .= 0x7000
1536         .globl fwnmi_data_area
1537 fwnmi_data_area:
1538
1539         /* iSeries does not use the FWNMI stuff, so it is safe to put
1540          * this here, even if we later allow kernels that will boot on
1541          * both pSeries and iSeries */
1542 #ifdef CONFIG_PPC_ISERIES
1543         . = LPARMAP_PHYS
1544 #include "lparmap.s"
1545 /*
1546  * This ".text" is here for old compilers that generate a trailing
1547  * .note section when compiling .c files to .s
1548  */
1549         .text
1550 #endif /* CONFIG_PPC_ISERIES */
1551
1552         . = 0x8000
1553
1554 /*
1555  * On pSeries and most other platforms, secondary processors spin
1556  * in the following code.
1557  * At entry, r3 = this processor's number (physical cpu id)
1558  */
1559 _GLOBAL(generic_secondary_smp_init)
1560         mr      r24,r3
1561
1562         /* turn on 64-bit mode */
1563         bl      .enable_64b_mode
1564
1565         /* Set up a paca value for this processor. Since we have the
1566          * physical cpu id in r24, we need to search the pacas to find
1567          * which logical id maps to our physical one.
1568          */
1569         LOAD_REG_IMMEDIATE(r13, paca)   /* Get base vaddr of paca array  */
1570         li      r5,0                    /* logical cpu id                */
1571 1:      lhz     r6,PACAHWCPUID(r13)     /* Load HW procid from paca      */
1572         cmpw    r6,r24                  /* Compare to our id             */
1573         beq     2f
1574         addi    r13,r13,PACA_SIZE       /* Loop to next PACA on miss     */
1575         addi    r5,r5,1
1576         cmpwi   r5,NR_CPUS
1577         blt     1b
1578
1579         mr      r3,r24                  /* not found, copy phys to r3    */
1580         b       .kexec_wait             /* next kernel might do better   */
1581
1582 2:      mtspr   SPRN_SPRG3,r13          /* Save vaddr of paca in SPRG3   */
1583         /* From now on, r24 is expected to be logical cpuid */
1584         mr      r24,r5
1585 3:      HMT_LOW
1586         lbz     r23,PACAPROCSTART(r13)  /* Test if this processor should */
1587                                         /* start.                        */
1588         sync
1589
1590 #ifndef CONFIG_SMP
1591         b       3b                      /* Never go on non-SMP           */
1592 #else
1593         cmpwi   0,r23,0
1594         beq     3b                      /* Loop until told to go         */
1595
1596         /* See if we need to call a cpu state restore handler */
1597         LOAD_REG_IMMEDIATE(r23, cur_cpu_spec)
1598         ld      r23,0(r23)
1599         ld      r23,CPU_SPEC_RESTORE(r23)
1600         cmpdi   0,r23,0
1601         beq     4f
1602         ld      r23,0(r23)
1603         mtctr   r23
1604         bctrl
1605
1606 4:      /* Create a temp kernel stack for use before relocation is on.  */
1607         ld      r1,PACAEMERGSP(r13)
1608         subi    r1,r1,STACK_FRAME_OVERHEAD
1609
1610         b       __secondary_start
1611 #endif
1612
1613 #ifdef CONFIG_PPC_ISERIES
1614 _STATIC(__start_initialization_iSeries)
1615         /* Clear out the BSS */
1616         LOAD_REG_IMMEDIATE(r11,__bss_stop)
1617         LOAD_REG_IMMEDIATE(r8,__bss_start)
1618         sub     r11,r11,r8              /* bss size                     */
1619         addi    r11,r11,7               /* round up to an even double word */
1620         rldicl. r11,r11,61,3            /* shift right by 3             */
1621         beq     4f
1622         addi    r8,r8,-8
1623         li      r0,0
1624         mtctr   r11                     /* zero this many doublewords   */
1625 3:      stdu    r0,8(r8)
1626         bdnz    3b
1627 4:
1628         LOAD_REG_IMMEDIATE(r1,init_thread_union)
1629         addi    r1,r1,THREAD_SIZE
1630         li      r0,0
1631         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
1632
1633         LOAD_REG_IMMEDIATE(r2,__toc_start)
1634         addi    r2,r2,0x4000
1635         addi    r2,r2,0x4000
1636
1637         bl      .iSeries_early_setup
1638         bl      .early_setup
1639
1640         /* relocation is on at this point */
1641
1642         b       .start_here_common
1643 #endif /* CONFIG_PPC_ISERIES */
1644
1645
1646 _STATIC(__mmu_off)
1647         mfmsr   r3
1648         andi.   r0,r3,MSR_IR|MSR_DR
1649         beqlr
1650         andc    r3,r3,r0
1651         mtspr   SPRN_SRR0,r4
1652         mtspr   SPRN_SRR1,r3
1653         sync
1654         rfid
1655         b       .       /* prevent speculative execution */
1656
1657
1658 /*
1659  * Here is our main kernel entry point. We support currently 2 kind of entries
1660  * depending on the value of r5.
1661  *
1662  *   r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1663  *                 in r3...r7
1664  *
1665  *   r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1666  *                 DT block, r4 is a physical pointer to the kernel itself
1667  *
1668  */
1669 _GLOBAL(__start_initialization_multiplatform)
1670         /*
1671          * Are we booted from a PROM Of-type client-interface ?
1672          */
1673         cmpldi  cr0,r5,0
1674         bne     .__boot_from_prom               /* yes -> prom */
1675
1676         /* Save parameters */
1677         mr      r31,r3
1678         mr      r30,r4
1679
1680         /* Make sure we are running in 64 bits mode */
1681         bl      .enable_64b_mode
1682
1683         /* Setup some critical 970 SPRs before switching MMU off */
1684         mfspr   r0,SPRN_PVR
1685         srwi    r0,r0,16
1686         cmpwi   r0,0x39         /* 970 */
1687         beq     1f
1688         cmpwi   r0,0x3c         /* 970FX */
1689         beq     1f
1690         cmpwi   r0,0x44         /* 970MP */
1691         beq     1f
1692         cmpwi   r0,0x45         /* 970GX */
1693         bne     2f
1694 1:      bl      .__cpu_preinit_ppc970
1695 2:
1696
1697         /* Switch off MMU if not already */
1698         LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
1699         add     r4,r4,r30
1700         bl      .__mmu_off
1701         b       .__after_prom_start
1702
1703 _STATIC(__boot_from_prom)
1704         /* Save parameters */
1705         mr      r31,r3
1706         mr      r30,r4
1707         mr      r29,r5
1708         mr      r28,r6
1709         mr      r27,r7
1710
1711         /*
1712          * Align the stack to 16-byte boundary
1713          * Depending on the size and layout of the ELF sections in the initial
1714          * boot binary, the stack pointer will be unalignet on PowerMac
1715          */
1716         rldicr  r1,r1,0,59
1717
1718         /* Make sure we are running in 64 bits mode */
1719         bl      .enable_64b_mode
1720
1721         /* put a relocation offset into r3 */
1722         bl      .reloc_offset
1723
1724         LOAD_REG_IMMEDIATE(r2,__toc_start)
1725         addi    r2,r2,0x4000
1726         addi    r2,r2,0x4000
1727
1728         /* Relocate the TOC from a virt addr to a real addr */
1729         add     r2,r2,r3
1730
1731         /* Restore parameters */
1732         mr      r3,r31
1733         mr      r4,r30
1734         mr      r5,r29
1735         mr      r6,r28
1736         mr      r7,r27
1737
1738         /* Do all of the interaction with OF client interface */
1739         bl      .prom_init
1740         /* We never return */
1741         trap
1742
1743 _STATIC(__after_prom_start)
1744
1745 /*
1746  * We need to run with __start at physical address PHYSICAL_START.
1747  * This will leave some code in the first 256B of
1748  * real memory, which are reserved for software use.
1749  * The remainder of the first page is loaded with the fixed
1750  * interrupt vectors.  The next two pages are filled with
1751  * unknown exception placeholders.
1752  *
1753  * Note: This process overwrites the OF exception vectors.
1754  *      r26 == relocation offset
1755  *      r27 == KERNELBASE
1756  */
1757         bl      .reloc_offset
1758         mr      r26,r3
1759         LOAD_REG_IMMEDIATE(r27, KERNELBASE)
1760
1761         LOAD_REG_IMMEDIATE(r3, PHYSICAL_START)  /* target addr */
1762
1763         // XXX FIXME: Use phys returned by OF (r30)
1764         add     r4,r27,r26              /* source addr                   */
1765                                         /* current address of _start     */
1766                                         /*   i.e. where we are running   */
1767                                         /*      the source addr          */
1768
1769         cmpdi   r4,0                    /* In some cases the loader may  */
1770         beq     .start_here_multiplatform /* have already put us at zero */
1771                                         /* so we can skip the copy.      */
1772         LOAD_REG_IMMEDIATE(r5,copy_to_here) /* # bytes of memory to copy */
1773         sub     r5,r5,r27
1774
1775         li      r6,0x100                /* Start offset, the first 0x100 */
1776                                         /* bytes were copied earlier.    */
1777
1778         bl      .copy_and_flush         /* copy the first n bytes        */
1779                                         /* this includes the code being  */
1780                                         /* executed here.                */
1781
1782         LOAD_REG_IMMEDIATE(r0, 4f)      /* Jump to the copy of this code */
1783         mtctr   r0                      /* that we just made/relocated   */
1784         bctr
1785
1786 4:      LOAD_REG_IMMEDIATE(r5,klimit)
1787         add     r5,r5,r26
1788         ld      r5,0(r5)                /* get the value of klimit */
1789         sub     r5,r5,r27
1790         bl      .copy_and_flush         /* copy the rest */
1791         b       .start_here_multiplatform
1792
1793 /*
1794  * Copy routine used to copy the kernel to start at physical address 0
1795  * and flush and invalidate the caches as needed.
1796  * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1797  * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1798  *
1799  * Note: this routine *only* clobbers r0, r6 and lr
1800  */
1801 _GLOBAL(copy_and_flush)
1802         addi    r5,r5,-8
1803         addi    r6,r6,-8
1804 4:      li      r0,8                    /* Use the smallest common      */
1805                                         /* denominator cache line       */
1806                                         /* size.  This results in       */
1807                                         /* extra cache line flushes     */
1808                                         /* but operation is correct.    */
1809                                         /* Can't get cache line size    */
1810                                         /* from NACA as it is being     */
1811                                         /* moved too.                   */
1812
1813         mtctr   r0                      /* put # words/line in ctr      */
1814 3:      addi    r6,r6,8                 /* copy a cache line            */
1815         ldx     r0,r6,r4
1816         stdx    r0,r6,r3
1817         bdnz    3b
1818         dcbst   r6,r3                   /* write it to memory           */
1819         sync
1820         icbi    r6,r3                   /* flush the icache line        */
1821         cmpld   0,r6,r5
1822         blt     4b
1823         sync
1824         addi    r5,r5,8
1825         addi    r6,r6,8
1826         blr
1827
1828 .align 8
1829 copy_to_here:
1830
1831 #ifdef CONFIG_SMP
1832 #ifdef CONFIG_PPC_PMAC
1833 /*
1834  * On PowerMac, secondary processors starts from the reset vector, which
1835  * is temporarily turned into a call to one of the functions below.
1836  */
1837         .section ".text";
1838         .align 2 ;
1839
1840         .globl  __secondary_start_pmac_0
1841 __secondary_start_pmac_0:
1842         /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
1843         li      r24,0
1844         b       1f
1845         li      r24,1
1846         b       1f
1847         li      r24,2
1848         b       1f
1849         li      r24,3
1850 1:
1851
1852 _GLOBAL(pmac_secondary_start)
1853         /* turn on 64-bit mode */
1854         bl      .enable_64b_mode
1855
1856         /* Copy some CPU settings from CPU 0 */
1857         bl      .__restore_cpu_ppc970
1858
1859         /* pSeries do that early though I don't think we really need it */
1860         mfmsr   r3
1861         ori     r3,r3,MSR_RI
1862         mtmsrd  r3                      /* RI on */
1863
1864         /* Set up a paca value for this processor. */
1865         LOAD_REG_IMMEDIATE(r4, paca)    /* Get base vaddr of paca array */
1866         mulli   r13,r24,PACA_SIZE        /* Calculate vaddr of right paca */
1867         add     r13,r13,r4              /* for this processor.          */
1868         mtspr   SPRN_SPRG3,r13           /* Save vaddr of paca in SPRG3 */
1869
1870         /* Create a temp kernel stack for use before relocation is on.  */
1871         ld      r1,PACAEMERGSP(r13)
1872         subi    r1,r1,STACK_FRAME_OVERHEAD
1873
1874         b       __secondary_start
1875
1876 #endif /* CONFIG_PPC_PMAC */
1877
1878 /*
1879  * This function is called after the master CPU has released the
1880  * secondary processors.  The execution environment is relocation off.
1881  * The paca for this processor has the following fields initialized at
1882  * this point:
1883  *   1. Processor number
1884  *   2. Segment table pointer (virtual address)
1885  * On entry the following are set:
1886  *   r1 = stack pointer.  vaddr for iSeries, raddr (temp stack) for pSeries
1887  *   r24   = cpu# (in Linux terms)
1888  *   r13   = paca virtual address
1889  *   SPRG3 = paca virtual address
1890  */
1891 __secondary_start:
1892         /* Set thread priority to MEDIUM */
1893         HMT_MEDIUM
1894
1895         /* Load TOC */
1896         ld      r2,PACATOC(r13)
1897
1898         /* Do early setup for that CPU (stab, slb, hash table pointer) */
1899         bl      .early_setup_secondary
1900
1901         /* Initialize the kernel stack.  Just a repeat for iSeries.      */
1902         LOAD_REG_ADDR(r3, current_set)
1903         sldi    r28,r24,3               /* get current_set[cpu#]         */
1904         ldx     r1,r3,r28
1905         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1906         std     r1,PACAKSAVE(r13)
1907
1908         /* Clear backchain so we get nice backtraces */
1909         li      r7,0
1910         mtlr    r7
1911
1912         /* enable MMU and jump to start_secondary */
1913         LOAD_REG_ADDR(r3, .start_secondary_prolog)
1914         LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
1915 #ifdef CONFIG_PPC_ISERIES
1916 BEGIN_FW_FTR_SECTION
1917         ori     r4,r4,MSR_EE
1918 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
1919 #endif
1920 BEGIN_FW_FTR_SECTION
1921         stb     r7,PACASOFTIRQEN(r13)
1922         stb     r7,PACAHARDIRQEN(r13)
1923 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
1924
1925         mtspr   SPRN_SRR0,r3
1926         mtspr   SPRN_SRR1,r4
1927         rfid
1928         b       .       /* prevent speculative execution */
1929
1930 /*
1931  * Running with relocation on at this point.  All we want to do is
1932  * zero the stack back-chain pointer before going into C code.
1933  */
1934 _GLOBAL(start_secondary_prolog)
1935         li      r3,0
1936         std     r3,0(r1)                /* Zero the stack frame pointer */
1937         bl      .start_secondary
1938         b       .
1939 #endif
1940
1941 /*
1942  * This subroutine clobbers r11 and r12
1943  */
1944 _GLOBAL(enable_64b_mode)
1945         mfmsr   r11                     /* grab the current MSR */
1946         li      r12,1
1947         rldicr  r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1948         or      r11,r11,r12
1949         li      r12,1
1950         rldicr  r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1951         or      r11,r11,r12
1952         mtmsrd  r11
1953         isync
1954         blr
1955
1956 /*
1957  * This is where the main kernel code starts.
1958  */
1959 _STATIC(start_here_multiplatform)
1960         /* get a new offset, now that the kernel has moved. */
1961         bl      .reloc_offset
1962         mr      r26,r3
1963
1964         /* Clear out the BSS. It may have been done in prom_init,
1965          * already but that's irrelevant since prom_init will soon
1966          * be detached from the kernel completely. Besides, we need
1967          * to clear it now for kexec-style entry.
1968          */
1969         LOAD_REG_IMMEDIATE(r11,__bss_stop)
1970         LOAD_REG_IMMEDIATE(r8,__bss_start)
1971         sub     r11,r11,r8              /* bss size                     */
1972         addi    r11,r11,7               /* round up to an even double word */
1973         rldicl. r11,r11,61,3            /* shift right by 3             */
1974         beq     4f
1975         addi    r8,r8,-8
1976         li      r0,0
1977         mtctr   r11                     /* zero this many doublewords   */
1978 3:      stdu    r0,8(r8)
1979         bdnz    3b
1980 4:
1981
1982         mfmsr   r6
1983         ori     r6,r6,MSR_RI
1984         mtmsrd  r6                      /* RI on */
1985
1986         /* The following gets the stack and TOC set up with the regs */
1987         /* pointing to the real addr of the kernel stack.  This is   */
1988         /* all done to support the C function call below which sets  */
1989         /* up the htab.  This is done because we have relocated the  */
1990         /* kernel but are still running in real mode. */
1991
1992         LOAD_REG_IMMEDIATE(r3,init_thread_union)
1993         add     r3,r3,r26
1994
1995         /* set up a stack pointer (physical address) */
1996         addi    r1,r3,THREAD_SIZE
1997         li      r0,0
1998         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
1999
2000         /* set up the TOC (physical address) */
2001         LOAD_REG_IMMEDIATE(r2,__toc_start)
2002         addi    r2,r2,0x4000
2003         addi    r2,r2,0x4000
2004         add     r2,r2,r26
2005
2006         /* Do very early kernel initializations, including initial hash table,
2007          * stab and slb setup before we turn on relocation.     */
2008
2009         /* Restore parameters passed from prom_init/kexec */
2010         mr      r3,r31
2011         bl      .early_setup
2012
2013         LOAD_REG_IMMEDIATE(r3, .start_here_common)
2014         LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
2015         mtspr   SPRN_SRR0,r3
2016         mtspr   SPRN_SRR1,r4
2017         rfid
2018         b       .       /* prevent speculative execution */
2019
2020         /* This is where all platforms converge execution */
2021 _STATIC(start_here_common)
2022         /* relocation is on at this point */
2023
2024         /* The following code sets up the SP and TOC now that we are */
2025         /* running with translation enabled. */
2026
2027         LOAD_REG_IMMEDIATE(r3,init_thread_union)
2028
2029         /* set up the stack */
2030         addi    r1,r3,THREAD_SIZE
2031         li      r0,0
2032         stdu    r0,-STACK_FRAME_OVERHEAD(r1)
2033
2034         /* ptr to current */
2035         LOAD_REG_IMMEDIATE(r4, init_task)
2036         std     r4,PACACURRENT(r13)
2037
2038         /* Load the TOC */
2039         ld      r2,PACATOC(r13)
2040         std     r1,PACAKSAVE(r13)
2041
2042         bl      .setup_system
2043
2044         /* Load up the kernel context */
2045 5:
2046         li      r5,0
2047         stb     r5,PACASOFTIRQEN(r13)   /* Soft Disabled */
2048 #ifdef CONFIG_PPC_ISERIES
2049 BEGIN_FW_FTR_SECTION
2050         mfmsr   r5
2051         ori     r5,r5,MSR_EE            /* Hard Enabled */
2052         mtmsrd  r5
2053 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
2054 #endif
2055 BEGIN_FW_FTR_SECTION
2056         stb     r5,PACAHARDIRQEN(r13)
2057 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
2058
2059         bl .start_kernel
2060
2061         /* Not reached */
2062         BUG_OPCODE
2063
2064 /*
2065  * We put a few things here that have to be page-aligned.
2066  * This stuff goes at the beginning of the bss, which is page-aligned.
2067  */
2068         .section ".bss"
2069
2070         .align  PAGE_SHIFT
2071
2072         .globl  empty_zero_page
2073 empty_zero_page:
2074         .space  PAGE_SIZE
2075
2076         .globl  swapper_pg_dir
2077 swapper_pg_dir:
2078         .space  PAGE_SIZE
2079
2080 /*
2081  * This space gets a copy of optional info passed to us by the bootstrap
2082  * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2083  */
2084         .globl  cmd_line
2085 cmd_line:
2086         .space  COMMAND_LINE_SIZE