2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
12 #include <linux/linkage.h>
13 #include <linux/threads.h>
14 #include <linux/init.h>
16 #include <asm/segment.h>
17 #include <asm/pgtable.h>
20 #include <asm/cache.h>
22 /* we are not able to switch in one step to the final KERNEL ADRESS SPACE
23 * because we need identity-mapped pages.
28 .section .bootstrap.text
34 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
35 * and someone has loaded an identity mapped page table
36 * for us. These identity mapped page tables map all of the
37 * kernel pages and possibly all of memory.
39 * %esi holds a physical pointer to real_mode_data.
41 * We come here either directly from a 64bit bootloader, or from
42 * arch/x86_64/boot/compressed/head.S.
44 * We only come here initially at boot nothing else comes here.
46 * Since we may be loaded at an address different from what we were
47 * compiled to run at we first fixup the physical addresses in our page
48 * tables and then reload them.
51 /* Compute the delta between the address I am compiled to run at and the
52 * address I am actually running at.
54 leaq _text(%rip), %rbp
55 subq $_text - __START_KERNEL_map, %rbp
57 /* Is the address not 2M aligned? */
59 andl $~LARGE_PAGE_MASK, %eax
63 /* Is the address too large? */
64 leaq _text(%rip), %rdx
65 movq $PGDIR_SIZE, %rax
69 /* Fixup the physical addresses in the page table
71 addq %rbp, init_level4_pgt + 0(%rip)
72 addq %rbp, init_level4_pgt + (258*8)(%rip)
73 addq %rbp, init_level4_pgt + (511*8)(%rip)
75 addq %rbp, level3_ident_pgt + 0(%rip)
76 addq %rbp, level3_kernel_pgt + (510*8)(%rip)
78 /* Add an Identity mapping if I am above 1G */
79 leaq _text(%rip), %rdi
80 andq $LARGE_PAGE_MASK, %rdi
84 andq $(PTRS_PER_PUD - 1), %rax
87 leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
88 leaq level3_ident_pgt(%rip), %rbx
89 movq %rdx, 0(%rbx, %rax, 8)
93 andq $(PTRS_PER_PMD - 1), %rax
94 leaq __PAGE_KERNEL_LARGE_EXEC(%rdi), %rdx
95 leaq level2_spare_pgt(%rip), %rbx
96 movq %rdx, 0(%rbx, %rax, 8)
99 /* Fixup the kernel text+data virtual addresses
101 leaq level2_kernel_pgt(%rip), %rdi
103 /* See if it is a valid page table entry */
107 /* Go to the next page */
112 /* Fixup phys_base */
113 addq %rbp, phys_base(%rip)
116 addq %rbp, trampoline_level4_pgt + 0(%rip)
117 addq %rbp, trampoline_level4_pgt + (511*8)(%rip)
119 #ifdef CONFIG_ACPI_SLEEP
120 addq %rbp, wakeup_level4_pgt + 0(%rip)
121 addq %rbp, wakeup_level4_pgt + (511*8)(%rip)
124 /* Due to ENTRY(), sometimes the empty space gets filled with
125 * zeros. Better take a jmp than relying on empty space being
126 * filled with 0x90 (nop)
128 jmp secondary_startup_64
129 ENTRY(secondary_startup_64)
131 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
132 * and someone has loaded a mapped page table.
134 * %esi holds a physical pointer to real_mode_data.
136 * We come here either from startup_64 (using physical addresses)
137 * or from trampoline.S (using virtual addresses).
139 * Using virtual addresses from trampoline.S removes the need
140 * to have any identity mapped pages in the kernel page table
141 * after the boot processor executes this code.
144 /* Enable PAE mode and PGE */
150 /* Setup early boot stage 4 level pagetables. */
151 movq $(init_level4_pgt - __START_KERNEL_map), %rax
152 addq phys_base(%rip), %rax
155 /* Ensure I am executing from virtual addresses */
160 /* Check if nx is implemented */
161 movl $0x80000001, %eax
165 /* Setup EFER (Extended Feature Enable Register) */
168 btsl $_EFER_SCE, %eax /* Enable System Call */
169 btl $20,%edi /* No Execute supported? */
172 1: wrmsr /* Make changes effective */
175 #define CR0_PM 1 /* protected mode */
176 #define CR0_MP (1<<1)
177 #define CR0_ET (1<<4)
178 #define CR0_NE (1<<5)
179 #define CR0_WP (1<<16)
180 #define CR0_AM (1<<18)
181 #define CR0_PAGING (1<<31)
182 movl $CR0_PM|CR0_MP|CR0_ET|CR0_NE|CR0_WP|CR0_AM|CR0_PAGING,%eax
183 /* Make changes effective */
186 /* Setup a boot time stack */
187 movq init_rsp(%rip),%rsp
189 /* zero EFLAGS after setting rsp */
194 * We must switch to a new descriptor in kernel space for the GDT
195 * because soon the kernel won't have access anymore to the userspace
196 * addresses where we're currently running on. We have to do that here
197 * because in 32bit we couldn't load a 64bit linear address.
199 lgdt cpu_gdt_descr(%rip)
201 /* set up data segments. actually 0 would do too */
202 movl $__KERNEL_DS,%eax
208 * We don't really need to load %fs or %gs, but load them anyway
209 * to kill any stale realmode selectors. This allows execution
216 * Setup up a dummy PDA. this is just for some early bootup code
217 * that does in_interrupt()
219 movl $MSR_GS_BASE,%ecx
220 movq $empty_zero_page,%rax
225 /* esi is pointer to real mode structure with interesting info.
229 /* Finally jump to run C code and to be on real kernel address
230 * Since we are running on identity-mapped space we have to jump
231 * to the full 64bit address, this is only possible as indirect
232 * jump. In addition we need to ensure %cs is set so we make this
235 movq initial_code(%rip),%rax
236 pushq $0 # fake return address to stop unwinder
237 pushq $__KERNEL_CS # set correct cs
238 pushq %rax # target address in negative space
241 /* SMP bootup changes these two */
245 .quad x86_64_start_kernel
248 .quad init_thread_union+THREAD_SIZE-8
253 ENTRY(early_idt_handler)
254 cmpl $2,early_recursion_flag(%rip)
256 incl early_recursion_flag(%rip)
258 movq 8(%rsp),%rsi # get rip
261 leaq early_idt_msg(%rip),%rdi
263 cmpl $2,early_recursion_flag(%rip)
266 #ifdef CONFIG_KALLSYMS
267 leaq early_idt_ripmsg(%rip),%rdi
268 movq 8(%rsp),%rsi # get rip again
273 early_recursion_flag:
277 .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
283 #define NEXT_PAGE(name) \
287 /* Automate the creation of 1 to 1 mapping pmd entries */
288 #define PMDS(START, PERM, COUNT) \
291 .quad (START) + (i << 21) + (PERM) ; \
296 * This default setting generates an ident mapping at address 0x100000
297 * and a mapping for the kernel that precisely maps virtual address
298 * 0xffffffff80000000 to physical address 0x000000. (always using
299 * 2Mbyte large pages provided by PAE mode)
301 NEXT_PAGE(init_level4_pgt)
302 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
304 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
306 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
307 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
309 NEXT_PAGE(level3_ident_pgt)
310 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
313 NEXT_PAGE(level3_kernel_pgt)
315 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
316 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
319 NEXT_PAGE(level2_ident_pgt)
320 /* Since I easily can, map the first 1G.
321 * Don't set NX because code runs from these pages.
323 PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC, PTRS_PER_PMD)
325 NEXT_PAGE(level2_kernel_pgt)
326 /* 40MB kernel mapping. The kernel code cannot be bigger than that.
327 When you change this change KERNEL_TEXT_SIZE in page.h too. */
328 /* (2^48-(2*1024*1024*1024)-((2^39)*511)-((2^30)*510)) = 0 */
329 PMDS(0x0000000000000000, __PAGE_KERNEL_LARGE_EXEC|_PAGE_GLOBAL,
330 KERNEL_TEXT_SIZE/PMD_SIZE)
331 /* Module mapping starts here */
332 .fill (PTRS_PER_PMD - (KERNEL_TEXT_SIZE/PMD_SIZE)),8,0
334 NEXT_PAGE(level2_spare_pgt)
344 .word gdt_end-cpu_gdt_table-1
355 /* This must match the first entry in level2_kernel_pgt */
356 .quad 0x0000000000000000
358 /* We need valid kernel segments for data and code in long mode too
359 * IRET will check the segment types kkeil 2000/10/28
360 * Also sysret mandates a special GDT layout
363 .section .data.page_aligned, "aw"
366 /* The TLS descriptors are currently at a different place compared to i386.
367 Hopefully nobody expects them at a fixed place (Wine?) */
370 .quad 0x0000000000000000 /* NULL descriptor */
371 .quad 0x00cf9b000000ffff /* __KERNEL32_CS */
372 .quad 0x00af9b000000ffff /* __KERNEL_CS */
373 .quad 0x00cf93000000ffff /* __KERNEL_DS */
374 .quad 0x00cffb000000ffff /* __USER32_CS */
375 .quad 0x00cff3000000ffff /* __USER_DS, __USER32_DS */
376 .quad 0x00affb000000ffff /* __USER_CS */
377 .quad 0x0 /* unused */
380 .quad 0,0,0 /* three TLS descriptors */
381 .quad 0x0000f40000000000 /* node/CPU stored in limit */
383 /* asm/segment.h:GDT_ENTRIES must match this */
384 /* This should be a multiple of the cache line size */
385 /* GDTs of other CPUs are now dynamically allocated */
387 /* zero the remaining page */
388 .fill PAGE_SIZE / 8 - GDT_ENTRIES,8,0
390 .section .bss, "aw", @nobits
391 .align L1_CACHE_BYTES
395 .section .bss.page_aligned, "aw", @nobits
397 ENTRY(empty_zero_page)