Merge phase #2 (PAT updates) of git://git.kernel.org/pub/scm/linux/kernel/git/tip...
[linux-2.6] / arch / arm / mach-pxa / lpd270.c
1 /*
2  * linux/arch/arm/mach-pxa/lpd270.c
3  *
4  * Support for the LogicPD PXA270 Card Engine.
5  * Derived from the mainstone code, which carries these notices:
6  *
7  * Author:      Nicolas Pitre
8  * Created:     Nov 05, 2002
9  * Copyright:   MontaVista Software Inc.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/sysdev.h>
19 #include <linux/interrupt.h>
20 #include <linux/sched.h>
21 #include <linux/bitops.h>
22 #include <linux/fb.h>
23 #include <linux/ioport.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/pwm_backlight.h>
27
28 #include <asm/types.h>
29 #include <asm/setup.h>
30 #include <asm/memory.h>
31 #include <asm/mach-types.h>
32 #include <mach/hardware.h>
33 #include <asm/irq.h>
34 #include <asm/sizes.h>
35
36 #include <asm/mach/arch.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
39 #include <asm/mach/flash.h>
40
41 #include <mach/pxa-regs.h>
42 #include <mach/pxa2xx-regs.h>
43 #include <mach/mfp-pxa27x.h>
44 #include <mach/lpd270.h>
45 #include <mach/audio.h>
46 #include <mach/pxafb.h>
47 #include <mach/mmc.h>
48 #include <mach/irda.h>
49 #include <mach/ohci.h>
50
51 #include "generic.h"
52 #include "devices.h"
53
54 static unsigned long lpd270_pin_config[] __initdata = {
55         /* Chip Selects */
56         GPIO15_nCS_1,   /* Mainboard Flash */
57         GPIO78_nCS_2,   /* CPLD + Ethernet */
58
59         /* LCD - 16bpp Active TFT */
60         GPIO58_LCD_LDD_0,
61         GPIO59_LCD_LDD_1,
62         GPIO60_LCD_LDD_2,
63         GPIO61_LCD_LDD_3,
64         GPIO62_LCD_LDD_4,
65         GPIO63_LCD_LDD_5,
66         GPIO64_LCD_LDD_6,
67         GPIO65_LCD_LDD_7,
68         GPIO66_LCD_LDD_8,
69         GPIO67_LCD_LDD_9,
70         GPIO68_LCD_LDD_10,
71         GPIO69_LCD_LDD_11,
72         GPIO70_LCD_LDD_12,
73         GPIO71_LCD_LDD_13,
74         GPIO72_LCD_LDD_14,
75         GPIO73_LCD_LDD_15,
76         GPIO74_LCD_FCLK,
77         GPIO75_LCD_LCLK,
78         GPIO76_LCD_PCLK,
79         GPIO77_LCD_BIAS,
80         GPIO16_PWM0_OUT,        /* Backlight */
81
82         /* USB Host */
83         GPIO88_USBH1_PWR,
84         GPIO89_USBH1_PEN,
85
86         /* AC97 */
87         GPIO45_AC97_SYSCLK,
88
89         GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
90 };
91
92 static unsigned int lpd270_irq_enabled;
93
94 static void lpd270_mask_irq(unsigned int irq)
95 {
96         int lpd270_irq = irq - LPD270_IRQ(0);
97
98         __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
99
100         lpd270_irq_enabled &= ~(1 << lpd270_irq);
101         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
102 }
103
104 static void lpd270_unmask_irq(unsigned int irq)
105 {
106         int lpd270_irq = irq - LPD270_IRQ(0);
107
108         lpd270_irq_enabled |= 1 << lpd270_irq;
109         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
110 }
111
112 static struct irq_chip lpd270_irq_chip = {
113         .name           = "CPLD",
114         .ack            = lpd270_mask_irq,
115         .mask           = lpd270_mask_irq,
116         .unmask         = lpd270_unmask_irq,
117 };
118
119 static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc)
120 {
121         unsigned long pending;
122
123         pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
124         do {
125                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
126                 if (likely(pending)) {
127                         irq = LPD270_IRQ(0) + __ffs(pending);
128                         generic_handle_irq(irq);
129
130                         pending = __raw_readw(LPD270_INT_STATUS) &
131                                                 lpd270_irq_enabled;
132                 }
133         } while (pending);
134 }
135
136 static void __init lpd270_init_irq(void)
137 {
138         int irq;
139
140         pxa27x_init_irq();
141
142         __raw_writew(0, LPD270_INT_MASK);
143         __raw_writew(0, LPD270_INT_STATUS);
144
145         /* setup extra LogicPD PXA270 irqs */
146         for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
147                 set_irq_chip(irq, &lpd270_irq_chip);
148                 set_irq_handler(irq, handle_level_irq);
149                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
150         }
151         set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
152         set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
153 }
154
155
156 #ifdef CONFIG_PM
157 static int lpd270_irq_resume(struct sys_device *dev)
158 {
159         __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
160         return 0;
161 }
162
163 static struct sysdev_class lpd270_irq_sysclass = {
164         .name = "cpld_irq",
165         .resume = lpd270_irq_resume,
166 };
167
168 static struct sys_device lpd270_irq_device = {
169         .cls = &lpd270_irq_sysclass,
170 };
171
172 static int __init lpd270_irq_device_init(void)
173 {
174         int ret = -ENODEV;
175         if (machine_is_logicpd_pxa270()) {
176                 ret = sysdev_class_register(&lpd270_irq_sysclass);
177                 if (ret == 0)
178                         ret = sysdev_register(&lpd270_irq_device);
179         }
180         return ret;
181 }
182
183 device_initcall(lpd270_irq_device_init);
184 #endif
185
186
187 static struct resource smc91x_resources[] = {
188         [0] = {
189                 .start  = LPD270_ETH_PHYS,
190                 .end    = (LPD270_ETH_PHYS + 0xfffff),
191                 .flags  = IORESOURCE_MEM,
192         },
193         [1] = {
194                 .start  = LPD270_ETHERNET_IRQ,
195                 .end    = LPD270_ETHERNET_IRQ,
196                 .flags  = IORESOURCE_IRQ,
197         },
198 };
199
200 static struct platform_device smc91x_device = {
201         .name           = "smc91x",
202         .id             = 0,
203         .num_resources  = ARRAY_SIZE(smc91x_resources),
204         .resource       = smc91x_resources,
205 };
206
207 static struct resource lpd270_flash_resources[] = {
208         [0] = {
209                 .start  = PXA_CS0_PHYS,
210                 .end    = PXA_CS0_PHYS + SZ_64M - 1,
211                 .flags  = IORESOURCE_MEM,
212         },
213         [1] = {
214                 .start  = PXA_CS1_PHYS,
215                 .end    = PXA_CS1_PHYS + SZ_64M - 1,
216                 .flags  = IORESOURCE_MEM,
217         },
218 };
219
220 static struct mtd_partition lpd270_flash0_partitions[] = {
221         {
222                 .name =         "Bootloader",
223                 .size =         0x00040000,
224                 .offset =       0,
225                 .mask_flags =   MTD_WRITEABLE  /* force read-only */
226         }, {
227                 .name =         "Kernel",
228                 .size =         0x00400000,
229                 .offset =       0x00040000,
230         }, {
231                 .name =         "Filesystem",
232                 .size =         MTDPART_SIZ_FULL,
233                 .offset =       0x00440000
234         },
235 };
236
237 static struct flash_platform_data lpd270_flash_data[2] = {
238         {
239                 .name           = "processor-flash",
240                 .map_name       = "cfi_probe",
241                 .parts          = lpd270_flash0_partitions,
242                 .nr_parts       = ARRAY_SIZE(lpd270_flash0_partitions),
243         }, {
244                 .name           = "mainboard-flash",
245                 .map_name       = "cfi_probe",
246                 .parts          = NULL,
247                 .nr_parts       = 0,
248         }
249 };
250
251 static struct platform_device lpd270_flash_device[2] = {
252         {
253                 .name           = "pxa2xx-flash",
254                 .id             = 0,
255                 .dev = {
256                         .platform_data  = &lpd270_flash_data[0],
257                 },
258                 .resource       = &lpd270_flash_resources[0],
259                 .num_resources  = 1,
260         }, {
261                 .name           = "pxa2xx-flash",
262                 .id             = 1,
263                 .dev = {
264                         .platform_data  = &lpd270_flash_data[1],
265                 },
266                 .resource       = &lpd270_flash_resources[1],
267                 .num_resources  = 1,
268         },
269 };
270
271 static struct platform_pwm_backlight_data lpd270_backlight_data = {
272         .pwm_id         = 0,
273         .max_brightness = 1,
274         .dft_brightness = 1,
275         .pwm_period_ns  = 78770,
276 };
277
278 static struct platform_device lpd270_backlight_device = {
279         .name           = "pwm-backlight",
280         .dev            = {
281                 .parent = &pxa27x_device_pwm0.dev,
282                 .platform_data = &lpd270_backlight_data,
283         },
284 };
285
286 /* 5.7" TFT QVGA (LoLo display number 1) */
287 static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
288         .pixclock               = 150000,
289         .xres                   = 320,
290         .yres                   = 240,
291         .bpp                    = 16,
292         .hsync_len              = 0x14,
293         .left_margin            = 0x28,
294         .right_margin           = 0x0a,
295         .vsync_len              = 0x02,
296         .upper_margin           = 0x08,
297         .lower_margin           = 0x14,
298         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
299 };
300
301 static struct pxafb_mach_info sharp_lq057q3dc02 = {
302         .modes                  = &sharp_lq057q3dc02_mode,
303         .num_modes              = 1,
304         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
305                                   LCD_ALTERNATE_MAPPING,
306 };
307
308 /* 12.1" TFT SVGA (LoLo display number 2) */
309 static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
310         .pixclock               = 50000,
311         .xres                   = 800,
312         .yres                   = 600,
313         .bpp                    = 16,
314         .hsync_len              = 0x05,
315         .left_margin            = 0x52,
316         .right_margin           = 0x05,
317         .vsync_len              = 0x04,
318         .upper_margin           = 0x14,
319         .lower_margin           = 0x0a,
320         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
321 };
322
323 static struct pxafb_mach_info sharp_lq121s1dg31 = {
324         .modes                  = &sharp_lq121s1dg31_mode,
325         .num_modes              = 1,
326         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
327                                   LCD_ALTERNATE_MAPPING,
328 };
329
330 /* 3.6" TFT QVGA (LoLo display number 3) */
331 static struct pxafb_mode_info sharp_lq036q1da01_mode = {
332         .pixclock               = 150000,
333         .xres                   = 320,
334         .yres                   = 240,
335         .bpp                    = 16,
336         .hsync_len              = 0x0e,
337         .left_margin            = 0x04,
338         .right_margin           = 0x0a,
339         .vsync_len              = 0x03,
340         .upper_margin           = 0x03,
341         .lower_margin           = 0x03,
342         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
343 };
344
345 static struct pxafb_mach_info sharp_lq036q1da01 = {
346         .modes                  = &sharp_lq036q1da01_mode,
347         .num_modes              = 1,
348         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
349                                   LCD_ALTERNATE_MAPPING,
350 };
351
352 /* 6.4" TFT VGA (LoLo display number 5) */
353 static struct pxafb_mode_info sharp_lq64d343_mode = {
354         .pixclock               = 25000,
355         .xres                   = 640,
356         .yres                   = 480,
357         .bpp                    = 16,
358         .hsync_len              = 0x31,
359         .left_margin            = 0x89,
360         .right_margin           = 0x19,
361         .vsync_len              = 0x12,
362         .upper_margin           = 0x22,
363         .lower_margin           = 0x00,
364         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
365 };
366
367 static struct pxafb_mach_info sharp_lq64d343 = {
368         .modes                  = &sharp_lq64d343_mode,
369         .num_modes              = 1,
370         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
371                                   LCD_ALTERNATE_MAPPING,
372 };
373
374 /* 10.4" TFT VGA (LoLo display number 7) */
375 static struct pxafb_mode_info sharp_lq10d368_mode = {
376         .pixclock               = 25000,
377         .xres                   = 640,
378         .yres                   = 480,
379         .bpp                    = 16,
380         .hsync_len              = 0x31,
381         .left_margin            = 0x89,
382         .right_margin           = 0x19,
383         .vsync_len              = 0x12,
384         .upper_margin           = 0x22,
385         .lower_margin           = 0x00,
386         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
387 };
388
389 static struct pxafb_mach_info sharp_lq10d368 = {
390         .modes                  = &sharp_lq10d368_mode,
391         .num_modes              = 1,
392         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
393                                   LCD_ALTERNATE_MAPPING,
394 };
395
396 /* 3.5" TFT QVGA (LoLo display number 8) */
397 static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
398         .pixclock               = 150000,
399         .xres                   = 240,
400         .yres                   = 320,
401         .bpp                    = 16,
402         .hsync_len              = 0x0e,
403         .left_margin            = 0x0a,
404         .right_margin           = 0x0a,
405         .vsync_len              = 0x03,
406         .upper_margin           = 0x05,
407         .lower_margin           = 0x14,
408         .sync                   = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
409 };
410
411 static struct pxafb_mach_info sharp_lq035q7db02_20 = {
412         .modes                  = &sharp_lq035q7db02_20_mode,
413         .num_modes              = 1,
414         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
415                                   LCD_ALTERNATE_MAPPING,
416 };
417
418 static struct pxafb_mach_info *lpd270_lcd_to_use;
419
420 static int __init lpd270_set_lcd(char *str)
421 {
422         if (!strnicmp(str, "lq057q3dc02", 11)) {
423                 lpd270_lcd_to_use = &sharp_lq057q3dc02;
424         } else if (!strnicmp(str, "lq121s1dg31", 11)) {
425                 lpd270_lcd_to_use = &sharp_lq121s1dg31;
426         } else if (!strnicmp(str, "lq036q1da01", 11)) {
427                 lpd270_lcd_to_use = &sharp_lq036q1da01;
428         } else if (!strnicmp(str, "lq64d343", 8)) {
429                 lpd270_lcd_to_use = &sharp_lq64d343;
430         } else if (!strnicmp(str, "lq10d368", 8)) {
431                 lpd270_lcd_to_use = &sharp_lq10d368;
432         } else if (!strnicmp(str, "lq035q7db02-20", 14)) {
433                 lpd270_lcd_to_use = &sharp_lq035q7db02_20;
434         } else {
435                 printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
436         }
437
438         return 1;
439 }
440
441 __setup("lcd=", lpd270_set_lcd);
442
443 static struct platform_device *platform_devices[] __initdata = {
444         &smc91x_device,
445         &lpd270_backlight_device,
446         &lpd270_flash_device[0],
447         &lpd270_flash_device[1],
448 };
449
450 static struct pxaohci_platform_data lpd270_ohci_platform_data = {
451         .port_mode      = PMM_PERPORT_MODE,
452         .flags          = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
453 };
454
455 static void __init lpd270_init(void)
456 {
457         pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
458
459         lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
460         lpd270_flash_data[1].width = 4;
461
462         /*
463          * System bus arbiter setting:
464          * - Core_Park
465          * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
466          */
467         ARB_CNTRL = ARB_CORE_PARK | 0x234;
468
469         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
470
471         pxa_set_ac97_info(NULL);
472
473         if (lpd270_lcd_to_use != NULL)
474                 set_pxa_fb_info(lpd270_lcd_to_use);
475
476         pxa_set_ohci_info(&lpd270_ohci_platform_data);
477 }
478
479
480 static struct map_desc lpd270_io_desc[] __initdata = {
481         {
482                 .virtual        = LPD270_CPLD_VIRT,
483                 .pfn            = __phys_to_pfn(LPD270_CPLD_PHYS),
484                 .length         = LPD270_CPLD_SIZE,
485                 .type           = MT_DEVICE,
486         },
487 };
488
489 static void __init lpd270_map_io(void)
490 {
491         pxa_map_io();
492         iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
493
494         /* for use I SRAM as framebuffer.  */
495         PSLR |= 0x00000F04;
496         PCFR  = 0x00000066;
497 }
498
499 MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
500         /* Maintainer: Peter Barada */
501         .phys_io        = 0x40000000,
502         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
503         .boot_params    = 0xa0000100,
504         .map_io         = lpd270_map_io,
505         .init_irq       = lpd270_init_irq,
506         .timer          = &pxa_timer,
507         .init_machine   = lpd270_init,
508 MACHINE_END