git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8548CDS";
  15         compatible = "MPC8548CDS", "MPC85xxCDS";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8548@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       //  33 MHz, from uboot
  31                         bus-frequency = <0>;    // 166 MHz
  32                         clock-frequency = <0>;  // 825 MHz, from uboot
  33                 };
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 reg = <00000000 08000000>;      // 128M at 0x0
  39         };
  40
  41         soc8548@e0000000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 device_type = "soc";
  45                 ranges = <00000000 e0000000 00100000>;
  46                 reg = <e0000000 00001000>;      // CCSRBAR
  47                 bus-frequency = <0>;
  48
  49                 memory-controller@2000 {
  50                         compatible = "fsl,8548-memory-controller";
  51                         reg = <2000 1000>;
  52                         interrupt-parent = <&mpic>;
  53                         interrupts = <12 2>;
  54                 };
  55
  56                 l2-cache-controller@20000 {
  57                         compatible = "fsl,8548-l2-cache-controller";
  58                         reg = <20000 1000>;
  59                         cache-line-size = <20>; // 32 bytes
  60                         cache-size = <80000>;   // L2, 512K
  61                         interrupt-parent = <&mpic>;
  62                         interrupts = <10 2>;
  63                 };
  64
  65                 i2c@3000 {
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68                         cell-index = <0>;
  69                         compatible = "fsl-i2c";
  70                         reg = <3000 100>;
  71                         interrupts = <2b 2>;
  72                         interrupt-parent = <&mpic>;
  73                         dfsrr;
  74                 };
  75
  76                 i2c@3100 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         cell-index = <1>;
  80                         compatible = "fsl-i2c";
  81                         reg = <3100 100>;
  82                         interrupts = <2b 2>;
  83                         interrupt-parent = <&mpic>;
  84                         dfsrr;
  85                 };
  86
  87                 mdio@24520 {
  88                         #address-cells = <1>;
  89                         #size-cells = <0>;
  90                         device_type = "mdio";
  91                         compatible = "gianfar";
  92                         reg = <24520 20>;
  93                         phy0: ethernet-phy@0 {
  94                                 interrupt-parent = <&mpic>;
  95                                 interrupts = <5 1>;
  96                                 reg = <0>;
  97                                 device_type = "ethernet-phy";
  98                         };
  99                         phy1: ethernet-phy@1 {
 100                                 interrupt-parent = <&mpic>;
 101                                 interrupts = <5 1>;
 102                                 reg = <1>;
 103                                 device_type = "ethernet-phy";
 104                         };
 105                         phy2: ethernet-phy@2 {
 106                                 interrupt-parent = <&mpic>;
 107                                 interrupts = <5 1>;
 108                                 reg = <2>;
 109                                 device_type = "ethernet-phy";
 110                         };
 111                         phy3: ethernet-phy@3 {
 112                                 interrupt-parent = <&mpic>;
 113                                 interrupts = <5 1>;
 114                                 reg = <3>;
 115                                 device_type = "ethernet-phy";
 116                         };
 117                 };
 118
 119                 ethernet@24000 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         device_type = "network";
 123                         model = "eTSEC";
 124                         compatible = "gianfar";
 125                         reg = <24000 1000>;
 126                         local-mac-address = [ 00 00 00 00 00 00 ];
 127                         interrupts = <1d 2 1e 2 22 2>;
 128                         interrupt-parent = <&mpic>;
 129                         phy-handle = <&phy0>;
 130                 };
 131
 132                 ethernet@25000 {
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135                         device_type = "network";
 136                         model = "eTSEC";
 137                         compatible = "gianfar";
 138                         reg = <25000 1000>;
 139                         local-mac-address = [ 00 00 00 00 00 00 ];
 140                         interrupts = <23 2 24 2 28 2>;
 141                         interrupt-parent = <&mpic>;
 142                         phy-handle = <&phy1>;
 143                 };
 144
 145 /* eTSEC 3/4 are currently broken
 146                 ethernet@26000 {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         device_type = "network";
 150                         model = "eTSEC";
 151                         compatible = "gianfar";
 152                         reg = <26000 1000>;
 153                         local-mac-address = [ 00 00 00 00 00 00 ];
 154                         interrupts = <1f 2 20 2 21 2>;
 155                         interrupt-parent = <&mpic>;
 156                         phy-handle = <&phy2>;
 157                 };
 158
 159                 ethernet@27000 {
 160                         #address-cells = <1>;
 161                         #size-cells = <0>;
 162                         device_type = "network";
 163                         model = "eTSEC";
 164                         compatible = "gianfar";
 165                         reg = <27000 1000>;
 166                         local-mac-address = [ 00 00 00 00 00 00 ];
 167                         interrupts = <25 2 26 2 27 2>;
 168                         interrupt-parent = <&mpic>;
 169                         phy-handle = <&phy3>;
 170                 };
 171  */
 172
 173                 serial@4500 {
 174                         device_type = "serial";
 175                         compatible = "ns16550";
 176                         reg = <4500 100>;       // reg base, size
 177                         clock-frequency = <0>;  // should we fill in in uboot?
 178                         interrupts = <2a 2>;
 179                         interrupt-parent = <&mpic>;
 180                 };
 181
 182                 serial@4600 {
 183                         device_type = "serial";
 184                         compatible = "ns16550";
 185                         reg = <4600 100>;       // reg base, size
 186                         clock-frequency = <0>;  // should we fill in in uboot?
 187                         interrupts = <2a 2>;
 188                         interrupt-parent = <&mpic>;
 189                 };
 190
 191                 global-utilities@e0000 {        //global utilities reg
 192                         compatible = "fsl,mpc8548-guts";
 193                         reg = <e0000 1000>;
 194                         fsl,has-rstcr;
 195                 };
 196
 197                 mpic: pic@40000 {
 198                         clock-frequency = <0>;
 199                         interrupt-controller;
 200                         #address-cells = <0>;
 201                         #interrupt-cells = <2>;
 202                         reg = <40000 40000>;
 203                         compatible = "chrp,open-pic";
 204                         device_type = "open-pic";
 205                         big-endian;
 206                 };
 207         };
 208
 209         pci@e0008000 {
 210                 interrupt-map-mask = <f800 0 0 7>;
 211                 interrupt-map = <
 212                         /* IDSEL 0x4 (PCIX Slot 2) */
 213                         02000 0 0 1 &mpic 0 1
 214                         02000 0 0 2 &mpic 1 1
 215                         02000 0 0 3 &mpic 2 1
 216                         02000 0 0 4 &mpic 3 1
 217
 218                         /* IDSEL 0x5 (PCIX Slot 3) */
 219                         02800 0 0 1 &mpic 1 1
 220                         02800 0 0 2 &mpic 2 1
 221                         02800 0 0 3 &mpic 3 1
 222                         02800 0 0 4 &mpic 0 1
 223
 224                         /* IDSEL 0x6 (PCIX Slot 4) */
 225                         03000 0 0 1 &mpic 2 1
 226                         03000 0 0 2 &mpic 3 1
 227                         03000 0 0 3 &mpic 0 1
 228                         03000 0 0 4 &mpic 1 1
 229
 230                         /* IDSEL 0x8 (PCIX Slot 5) */
 231                         04000 0 0 1 &mpic 0 1
 232                         04000 0 0 2 &mpic 1 1
 233                         04000 0 0 3 &mpic 2 1
 234                         04000 0 0 4 &mpic 3 1
 235
 236                         /* IDSEL 0xC (Tsi310 bridge) */
 237                         06000 0 0 1 &mpic 0 1
 238                         06000 0 0 2 &mpic 1 1
 239                         06000 0 0 3 &mpic 2 1
 240                         06000 0 0 4 &mpic 3 1
 241
 242                         /* IDSEL 0x14 (Slot 2) */
 243                         0a000 0 0 1 &mpic 0 1
 244                         0a000 0 0 2 &mpic 1 1
 245                         0a000 0 0 3 &mpic 2 1
 246                         0a000 0 0 4 &mpic 3 1
 247
 248                         /* IDSEL 0x15 (Slot 3) */
 249                         0a800 0 0 1 &mpic 1 1
 250                         0a800 0 0 2 &mpic 2 1
 251                         0a800 0 0 3 &mpic 3 1
 252                         0a800 0 0 4 &mpic 0 1
 253
 254                         /* IDSEL 0x16 (Slot 4) */
 255                         0b000 0 0 1 &mpic 2 1
 256                         0b000 0 0 2 &mpic 3 1
 257                         0b000 0 0 3 &mpic 0 1
 258                         0b000 0 0 4 &mpic 1 1
 259
 260                         /* IDSEL 0x18 (Slot 5) */
 261                         0c000 0 0 1 &mpic 0 1
 262                         0c000 0 0 2 &mpic 1 1
 263                         0c000 0 0 3 &mpic 2 1
 264                         0c000 0 0 4 &mpic 3 1
 265
 266                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 267                         0E000 0 0 1 &mpic 0 1
 268                         0E000 0 0 2 &mpic 1 1
 269                         0E000 0 0 3 &mpic 2 1
 270                         0E000 0 0 4 &mpic 3 1>;
 271
 272                 interrupt-parent = <&mpic>;
 273                 interrupts = <18 2>;
 274                 bus-range = <0 0>;
 275                 ranges = <02000000 0 80000000 80000000 0 10000000
 276                           01000000 0 00000000 e2000000 0 00800000>;
 277                 clock-frequency = <3f940aa>;
 278                 #interrupt-cells = <1>;
 279                 #size-cells = <2>;
 280                 #address-cells = <3>;
 281                 reg = <e0008000 1000>;
 282                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 283                 device_type = "pci";
 284
 285                 pci_bridge@1c {
 286                         interrupt-map-mask = <f800 0 0 7>;
 287                         interrupt-map = <
 288
 289                                 /* IDSEL 0x00 (PrPMC Site) */
 290                                 0000 0 0 1 &mpic 0 1
 291                                 0000 0 0 2 &mpic 1 1
 292                                 0000 0 0 3 &mpic 2 1
 293                                 0000 0 0 4 &mpic 3 1
 294
 295                                 /* IDSEL 0x04 (VIA chip) */
 296                                 2000 0 0 1 &mpic 0 1
 297                                 2000 0 0 2 &mpic 1 1
 298                                 2000 0 0 3 &mpic 2 1
 299                                 2000 0 0 4 &mpic 3 1
 300
 301                                 /* IDSEL 0x05 (8139) */
 302                                 2800 0 0 1 &mpic 1 1
 303
 304                                 /* IDSEL 0x06 (Slot 6) */
 305                                 3000 0 0 1 &mpic 2 1
 306                                 3000 0 0 2 &mpic 3 1
 307                                 3000 0 0 3 &mpic 0 1
 308                                 3000 0 0 4 &mpic 1 1
 309
 310                                 /* IDESL 0x07 (Slot 7) */
 311                                 3800 0 0 1 &mpic 3 1
 312                                 3800 0 0 2 &mpic 0 1
 313                                 3800 0 0 3 &mpic 1 1
 314                                 3800 0 0 4 &mpic 2 1>;
 315
 316                         reg = <e000 0 0 0 0>;
 317                         #interrupt-cells = <1>;
 318                         #size-cells = <2>;
 319                         #address-cells = <3>;
 320                         ranges = <02000000 0 80000000
 321                                   02000000 0 80000000
 322                                   0 20000000
 323                                   01000000 0 00000000
 324                                   01000000 0 00000000
 325                                   0 00080000>;
 326                         clock-frequency = <1fca055>;
 327
 328                         isa@4 {
 329                                 device_type = "isa";
 330                                 #interrupt-cells = <2>;
 331                                 #size-cells = <1>;
 332                                 #address-cells = <2>;
 333                                 reg = <2000 0 0 0 0>;
 334                                 ranges = <1 0 01000000 0 0 00001000>;
 335                                 interrupt-parent = <&i8259>;
 336
 337                                 i8259: interrupt-controller@20 {
 338                                         interrupt-controller;
 339                                         device_type = "interrupt-controller";
 340                                         reg = <1 20 2
 341                                                1 a0 2
 342                                                1 4d0 2>;
 343                                         #address-cells = <0>;
 344                                         #interrupt-cells = <2>;
 345                                         compatible = "chrp,iic";
 346                                         interrupts = <0 1>;
 347                                         interrupt-parent = <&mpic>;
 348                                 };
 349
 350                                 rtc@70 {
 351                                         compatible = "pnpPNP,b00";
 352                                         reg = <1 70 2>;
 353                                 };
 354                         };
 355                 };
 356         };
 357
 358         pci@e0009000 {
 359                 interrupt-map-mask = <f800 0 0 7>;
 360                 interrupt-map = <
 361
 362                         /* IDSEL 0x15 */
 363                         a800 0 0 1 &mpic b 1
 364                         a800 0 0 2 &mpic 1 1
 365                         a800 0 0 3 &mpic 2 1
 366                         a800 0 0 4 &mpic 3 1>;
 367
 368                 interrupt-parent = <&mpic>;
 369                 interrupts = <19 2>;
 370                 bus-range = <0 0>;
 371                 ranges = <02000000 0 90000000 90000000 0 10000000
 372                           01000000 0 00000000 e2800000 0 00800000>;
 373                 clock-frequency = <3f940aa>;
 374                 #interrupt-cells = <1>;
 375                 #size-cells = <2>;
 376                 #address-cells = <3>;
 377                 reg = <e0009000 1000>;
 378                 compatible = "fsl,mpc8540-pci";
 379                 device_type = "pci";
 380         };
 381
 382         pcie@e000a000 {
 383                 interrupt-map-mask = <f800 0 0 7>;
 384                 interrupt-map = <
 385
 386                         /* IDSEL 0x0 (PEX) */
 387                         00000 0 0 1 &mpic 0 1
 388                         00000 0 0 2 &mpic 1 1
 389                         00000 0 0 3 &mpic 2 1
 390                         00000 0 0 4 &mpic 3 1>;
 391
 392                 interrupt-parent = <&mpic>;
 393                 interrupts = <1a 2>;
 394                 bus-range = <0 ff>;
 395                 ranges = <02000000 0 a0000000 a0000000 0 20000000
 396                           01000000 0 00000000 e3000000 0 08000000>;
 397                 clock-frequency = <1fca055>;
 398                 #interrupt-cells = <1>;
 399                 #size-cells = <2>;
 400                 #address-cells = <3>;
 401                 reg = <e000a000 1000>;
 402                 compatible = "fsl,mpc8548-pcie";
 403                 device_type = "pci";
 404                 pcie@0 {
 405                         reg = <0 0 0 0 0>;
 406                         #size-cells = <2>;
 407                         #address-cells = <3>;
 408                         device_type = "pci";
 409                         ranges = <02000000 0 a0000000
 410                                   02000000 0 a0000000
 411                                   0 20000000
 412
 413                                   01000000 0 00000000
 414                                   01000000 0 00000000
 415                                   0 08000000>;
 416                 };
 417         };
 418 };