3 * This is a driver for SMSC's 91C9x/91C1xx single-chip Ethernet devices.
5 * Copyright (C) 1996 by Erik Stahlman
6 * Copyright (C) 2001 Standard Microsystems Corporation
7 * Developed by Simple Network Magic Corporation
8 * Copyright (C) 2003 Monta Vista Software, Inc.
9 * Unified SMC91x driver by Nicolas Pitre
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * io = for the base address
28 * nowait = 0 for normal wait states, 1 eliminates additional wait states
31 * Erik Stahlman <erik@vt.edu>
33 * hardware multicast code:
34 * Peter Cammaert <pc@denkart.be>
37 * Daris A Nevil <dnevil@snmc.com>
38 * Nicolas Pitre <nico@cam.org>
39 * Russell King <rmk@arm.linux.org.uk>
42 * 08/20/00 Arnaldo Melo fix kfree(skb) in smc_hardware_send_packet
43 * 12/15/00 Christian Jullien fix "Warning: kfree_skb on hard IRQ"
44 * 03/16/01 Daris A Nevil modified smc9194.c for use with LAN91C111
45 * 08/22/01 Scott Anderson merge changes from smc9194 to smc91111
46 * 08/21/01 Pramod B Bhardwaj added support for RevB of LAN91C111
47 * 12/20/01 Jeff Sutherland initial port to Xscale PXA with DMA support
48 * 04/07/03 Nicolas Pitre unified SMC91x driver, killed irq races,
49 * more bus abstraction, big cleanup, etc.
50 * 29/09/03 Russell King - add driver model support
52 * - convert to use generic MII interface
53 * - add link up/down notification
54 * - don't try to handle full negotiation in
56 * - clean up (and fix stack overrun) in PHY
57 * MII read/write functions
58 * 22/09/04 Nicolas Pitre big update (see commit log for details)
60 static const char version[] =
61 "smc91x.c: v1.1, sep 22 2004 by Nicolas Pitre <nico@cam.org>\n";
69 #include <linux/init.h>
70 #include <linux/module.h>
71 #include <linux/kernel.h>
72 #include <linux/sched.h>
73 #include <linux/slab.h>
74 #include <linux/delay.h>
75 #include <linux/interrupt.h>
76 #include <linux/errno.h>
77 #include <linux/ioport.h>
78 #include <linux/crc32.h>
79 #include <linux/platform_device.h>
80 #include <linux/spinlock.h>
81 #include <linux/ethtool.h>
82 #include <linux/mii.h>
83 #include <linux/workqueue.h>
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
96 static int nowait = SMC_NOWAIT;
97 module_param(nowait, int, 0400);
98 MODULE_PARM_DESC(nowait, "set to 1 for no wait state");
101 * Transmit timeout, default 5 seconds.
103 static int watchdog = 1000;
104 module_param(watchdog, int, 0400);
105 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
107 MODULE_LICENSE("GPL");
108 MODULE_ALIAS("platform:smc91x");
111 * The internal workings of the driver. If you are changing anything
112 * here with the SMC stuff, you should have the datasheet and know
113 * what you are doing.
115 #define CARDNAME "smc91x"
118 * Use power-down feature of the chip
123 * Wait time for memory to be free. This probably shouldn't be
124 * tuned that much, as waiting for this means nothing else happens
127 #define MEMORY_WAIT_TIME 16
130 * The maximum number of processing loops allowed for each call to the
133 #define MAX_IRQ_LOOPS 8
136 * This selects whether TX packets are sent one by one to the SMC91x internal
137 * memory and throttled until transmission completes. This may prevent
138 * RX overruns a litle by keeping much of the memory free for RX packets
139 * but to the expense of reduced TX throughput and increased IRQ overhead.
140 * Note this is not a cure for a too slow data bus or too high IRQ latency.
142 #define THROTTLE_TX_PKTS 0
145 * The MII clock high/low times. 2x this number gives the MII clock period
146 * in microseconds. (was 50, but this gives 6.4ms for each MII transaction!)
151 #define DBG(n, args...) \
153 if (SMC_DEBUG >= (n)) \
157 #define PRINTK(args...) printk(args)
159 #define DBG(n, args...) do { } while(0)
160 #define PRINTK(args...) printk(KERN_DEBUG args)
164 static void PRINT_PKT(u_char *buf, int length)
171 remainder = length % 16;
173 for (i = 0; i < lines ; i ++) {
175 for (cur = 0; cur < 8; cur++) {
179 printk("%02x%02x ", a, b);
183 for (i = 0; i < remainder/2 ; i++) {
187 printk("%02x%02x ", a, b);
192 #define PRINT_PKT(x...) do { } while(0)
196 /* this enables an interrupt in the interrupt mask register */
197 #define SMC_ENABLE_INT(lp, x) do { \
198 unsigned char mask; \
199 spin_lock_irq(&lp->lock); \
200 mask = SMC_GET_INT_MASK(lp); \
202 SMC_SET_INT_MASK(lp, mask); \
203 spin_unlock_irq(&lp->lock); \
206 /* this disables an interrupt from the interrupt mask register */
207 #define SMC_DISABLE_INT(lp, x) do { \
208 unsigned char mask; \
209 spin_lock_irq(&lp->lock); \
210 mask = SMC_GET_INT_MASK(lp); \
212 SMC_SET_INT_MASK(lp, mask); \
213 spin_unlock_irq(&lp->lock); \
217 * Wait while MMU is busy. This is usually in the order of a few nanosecs
218 * if at all, but let's avoid deadlocking the system if the hardware
219 * decides to go south.
221 #define SMC_WAIT_MMU_BUSY(lp) do { \
222 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
223 unsigned long timeout = jiffies + 2; \
224 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
225 if (time_after(jiffies, timeout)) { \
226 printk("%s: timeout %s line %d\n", \
227 dev->name, __FILE__, __LINE__); \
237 * this does a soft reset on the device
239 static void smc_reset(struct net_device *dev)
241 struct smc_local *lp = netdev_priv(dev);
242 void __iomem *ioaddr = lp->base;
243 unsigned int ctl, cfg;
244 struct sk_buff *pending_skb;
246 DBG(2, "%s: %s\n", dev->name, __func__);
248 /* Disable all interrupts, block TX tasklet */
249 spin_lock_irq(&lp->lock);
250 SMC_SELECT_BANK(lp, 2);
251 SMC_SET_INT_MASK(lp, 0);
252 pending_skb = lp->pending_tx_skb;
253 lp->pending_tx_skb = NULL;
254 spin_unlock_irq(&lp->lock);
256 /* free any pending tx skb */
258 dev_kfree_skb(pending_skb);
259 dev->stats.tx_errors++;
260 dev->stats.tx_aborted_errors++;
264 * This resets the registers mostly to defaults, but doesn't
265 * affect EEPROM. That seems unnecessary
267 SMC_SELECT_BANK(lp, 0);
268 SMC_SET_RCR(lp, RCR_SOFTRST);
271 * Setup the Configuration Register
272 * This is necessary because the CONFIG_REG is not affected
275 SMC_SELECT_BANK(lp, 1);
277 cfg = CONFIG_DEFAULT;
280 * Setup for fast accesses if requested. If the card/system
281 * can't handle it then there will be no recovery except for
282 * a hard reset or power cycle
284 if (lp->cfg.flags & SMC91X_NOWAIT)
285 cfg |= CONFIG_NO_WAIT;
288 * Release from possible power-down state
289 * Configuration register is not affected by Soft Reset
291 cfg |= CONFIG_EPH_POWER_EN;
293 SMC_SET_CONFIG(lp, cfg);
295 /* this should pause enough for the chip to be happy */
297 * elaborate? What does the chip _need_? --jgarzik
299 * This seems to be undocumented, but something the original
300 * driver(s) have always done. Suspect undocumented timing
301 * info/determined empirically. --rmk
305 /* Disable transmit and receive functionality */
306 SMC_SELECT_BANK(lp, 0);
307 SMC_SET_RCR(lp, RCR_CLEAR);
308 SMC_SET_TCR(lp, TCR_CLEAR);
310 SMC_SELECT_BANK(lp, 1);
311 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
314 * Set the control register to automatically release successfully
315 * transmitted packets, to make the best use out of our limited
318 if(!THROTTLE_TX_PKTS)
319 ctl |= CTL_AUTO_RELEASE;
321 ctl &= ~CTL_AUTO_RELEASE;
322 SMC_SET_CTL(lp, ctl);
325 SMC_SELECT_BANK(lp, 2);
326 SMC_SET_MMU_CMD(lp, MC_RESET);
327 SMC_WAIT_MMU_BUSY(lp);
331 * Enable Interrupts, Receive, and Transmit
333 static void smc_enable(struct net_device *dev)
335 struct smc_local *lp = netdev_priv(dev);
336 void __iomem *ioaddr = lp->base;
339 DBG(2, "%s: %s\n", dev->name, __func__);
341 /* see the header file for options in TCR/RCR DEFAULT */
342 SMC_SELECT_BANK(lp, 0);
343 SMC_SET_TCR(lp, lp->tcr_cur_mode);
344 SMC_SET_RCR(lp, lp->rcr_cur_mode);
346 SMC_SELECT_BANK(lp, 1);
347 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
349 /* now, enable interrupts */
350 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
351 if (lp->version >= (CHIP_91100 << 4))
353 SMC_SELECT_BANK(lp, 2);
354 SMC_SET_INT_MASK(lp, mask);
357 * From this point the register bank must _NOT_ be switched away
358 * to something else than bank 2 without proper locking against
359 * races with any tasklet or interrupt handlers until smc_shutdown()
360 * or smc_reset() is called.
365 * this puts the device in an inactive state
367 static void smc_shutdown(struct net_device *dev)
369 struct smc_local *lp = netdev_priv(dev);
370 void __iomem *ioaddr = lp->base;
371 struct sk_buff *pending_skb;
373 DBG(2, "%s: %s\n", CARDNAME, __func__);
375 /* no more interrupts for me */
376 spin_lock_irq(&lp->lock);
377 SMC_SELECT_BANK(lp, 2);
378 SMC_SET_INT_MASK(lp, 0);
379 pending_skb = lp->pending_tx_skb;
380 lp->pending_tx_skb = NULL;
381 spin_unlock_irq(&lp->lock);
383 dev_kfree_skb(pending_skb);
385 /* and tell the card to stay away from that nasty outside world */
386 SMC_SELECT_BANK(lp, 0);
387 SMC_SET_RCR(lp, RCR_CLEAR);
388 SMC_SET_TCR(lp, TCR_CLEAR);
391 /* finally, shut the chip down */
392 SMC_SELECT_BANK(lp, 1);
393 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
398 * This is the procedure to handle the receipt of a packet.
400 static inline void smc_rcv(struct net_device *dev)
402 struct smc_local *lp = netdev_priv(dev);
403 void __iomem *ioaddr = lp->base;
404 unsigned int packet_number, status, packet_len;
406 DBG(3, "%s: %s\n", dev->name, __func__);
408 packet_number = SMC_GET_RXFIFO(lp);
409 if (unlikely(packet_number & RXFIFO_REMPTY)) {
410 PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name);
414 /* read from start of packet */
415 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
417 /* First two words are status and packet length */
418 SMC_GET_PKT_HDR(lp, status, packet_len);
419 packet_len &= 0x07ff; /* mask off top bits */
420 DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
421 dev->name, packet_number, status,
422 packet_len, packet_len);
425 if (unlikely(packet_len < 6 || status & RS_ERRORS)) {
426 if (status & RS_TOOLONG && packet_len <= (1514 + 4 + 6)) {
427 /* accept VLAN packets */
428 status &= ~RS_TOOLONG;
431 if (packet_len < 6) {
432 /* bloody hardware */
433 printk(KERN_ERR "%s: fubar (rxlen %u status %x\n",
434 dev->name, packet_len, status);
435 status |= RS_TOOSHORT;
437 SMC_WAIT_MMU_BUSY(lp);
438 SMC_SET_MMU_CMD(lp, MC_RELEASE);
439 dev->stats.rx_errors++;
440 if (status & RS_ALGNERR)
441 dev->stats.rx_frame_errors++;
442 if (status & (RS_TOOSHORT | RS_TOOLONG))
443 dev->stats.rx_length_errors++;
444 if (status & RS_BADCRC)
445 dev->stats.rx_crc_errors++;
449 unsigned int data_len;
451 /* set multicast stats */
452 if (status & RS_MULTICAST)
453 dev->stats.multicast++;
456 * Actual payload is packet_len - 6 (or 5 if odd byte).
457 * We want skb_reserve(2) and the final ctrl word
458 * (2 bytes, possibly containing the payload odd byte).
459 * Furthermore, we add 2 bytes to allow rounding up to
460 * multiple of 4 bytes on 32 bit buses.
461 * Hence packet_len - 6 + 2 + 2 + 2.
463 skb = dev_alloc_skb(packet_len);
464 if (unlikely(skb == NULL)) {
465 printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
467 SMC_WAIT_MMU_BUSY(lp);
468 SMC_SET_MMU_CMD(lp, MC_RELEASE);
469 dev->stats.rx_dropped++;
473 /* Align IP header to 32 bits */
476 /* BUG: the LAN91C111 rev A never sets this bit. Force it. */
477 if (lp->version == 0x90)
478 status |= RS_ODDFRAME;
481 * If odd length: packet_len - 5,
482 * otherwise packet_len - 6.
483 * With the trailing ctrl byte it's packet_len - 4.
485 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
486 data = skb_put(skb, data_len);
487 SMC_PULL_DATA(lp, data, packet_len - 4);
489 SMC_WAIT_MMU_BUSY(lp);
490 SMC_SET_MMU_CMD(lp, MC_RELEASE);
492 PRINT_PKT(data, packet_len - 4);
494 skb->protocol = eth_type_trans(skb, dev);
496 dev->stats.rx_packets++;
497 dev->stats.rx_bytes += data_len;
503 * On SMP we have the following problem:
505 * A = smc_hardware_send_pkt()
506 * B = smc_hard_start_xmit()
507 * C = smc_interrupt()
509 * A and B can never be executed simultaneously. However, at least on UP,
510 * it is possible (and even desirable) for C to interrupt execution of
511 * A or B in order to have better RX reliability and avoid overruns.
512 * C, just like A and B, must have exclusive access to the chip and
513 * each of them must lock against any other concurrent access.
514 * Unfortunately this is not possible to have C suspend execution of A or
515 * B taking place on another CPU. On UP this is no an issue since A and B
516 * are run from softirq context and C from hard IRQ context, and there is
517 * no other CPU where concurrent access can happen.
518 * If ever there is a way to force at least B and C to always be executed
519 * on the same CPU then we could use read/write locks to protect against
520 * any other concurrent access and C would always interrupt B. But life
521 * isn't that easy in a SMP world...
523 #define smc_special_trylock(lock) \
526 local_irq_disable(); \
527 __ret = spin_trylock(lock); \
529 local_irq_enable(); \
532 #define smc_special_lock(lock) spin_lock_irq(lock)
533 #define smc_special_unlock(lock) spin_unlock_irq(lock)
535 #define smc_special_trylock(lock) (1)
536 #define smc_special_lock(lock) do { } while (0)
537 #define smc_special_unlock(lock) do { } while (0)
541 * This is called to actually send a packet to the chip.
543 static void smc_hardware_send_pkt(unsigned long data)
545 struct net_device *dev = (struct net_device *)data;
546 struct smc_local *lp = netdev_priv(dev);
547 void __iomem *ioaddr = lp->base;
549 unsigned int packet_no, len;
552 DBG(3, "%s: %s\n", dev->name, __func__);
554 if (!smc_special_trylock(&lp->lock)) {
555 netif_stop_queue(dev);
556 tasklet_schedule(&lp->tx_task);
560 skb = lp->pending_tx_skb;
561 if (unlikely(!skb)) {
562 smc_special_unlock(&lp->lock);
565 lp->pending_tx_skb = NULL;
567 packet_no = SMC_GET_AR(lp);
568 if (unlikely(packet_no & AR_FAILED)) {
569 printk("%s: Memory allocation failed.\n", dev->name);
570 dev->stats.tx_errors++;
571 dev->stats.tx_fifo_errors++;
572 smc_special_unlock(&lp->lock);
576 /* point to the beginning of the packet */
577 SMC_SET_PN(lp, packet_no);
578 SMC_SET_PTR(lp, PTR_AUTOINC);
582 DBG(2, "%s: TX PNR 0x%x LENGTH 0x%04x (%d) BUF 0x%p\n",
583 dev->name, packet_no, len, len, buf);
587 * Send the packet length (+6 for status words, length, and ctl.
588 * The card will pad to 64 bytes with zeroes if packet is too small.
590 SMC_PUT_PKT_HDR(lp, 0, len + 6);
592 /* send the actual data */
593 SMC_PUSH_DATA(lp, buf, len & ~1);
595 /* Send final ctl word with the last byte if there is one */
596 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
599 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
600 * have the effect of having at most one packet queued for TX
601 * in the chip's memory at all time.
603 * If THROTTLE_TX_PKTS is not set then the queue is stopped only
604 * when memory allocation (MC_ALLOC) does not succeed right away.
606 if (THROTTLE_TX_PKTS)
607 netif_stop_queue(dev);
609 /* queue the packet for TX */
610 SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
611 smc_special_unlock(&lp->lock);
613 dev->trans_start = jiffies;
614 dev->stats.tx_packets++;
615 dev->stats.tx_bytes += len;
617 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
619 done: if (!THROTTLE_TX_PKTS)
620 netif_wake_queue(dev);
626 * Since I am not sure if I will have enough room in the chip's ram
627 * to store the packet, I call this routine which either sends it
628 * now, or set the card to generates an interrupt when ready
631 static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
633 struct smc_local *lp = netdev_priv(dev);
634 void __iomem *ioaddr = lp->base;
635 unsigned int numPages, poll_count, status;
637 DBG(3, "%s: %s\n", dev->name, __func__);
639 BUG_ON(lp->pending_tx_skb != NULL);
642 * The MMU wants the number of pages to be the number of 256 bytes
643 * 'pages', minus 1 (since a packet can't ever have 0 pages :))
645 * The 91C111 ignores the size bits, but earlier models don't.
647 * Pkt size for allocating is data length +6 (for additional status
648 * words, length and ctl)
650 * If odd size then last byte is included in ctl word.
652 numPages = ((skb->len & ~1) + (6 - 1)) >> 8;
653 if (unlikely(numPages > 7)) {
654 printk("%s: Far too big packet error.\n", dev->name);
655 dev->stats.tx_errors++;
656 dev->stats.tx_dropped++;
661 smc_special_lock(&lp->lock);
663 /* now, try to allocate the memory */
664 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
667 * Poll the chip for a short amount of time in case the
668 * allocation succeeds quickly.
670 poll_count = MEMORY_WAIT_TIME;
672 status = SMC_GET_INT(lp);
673 if (status & IM_ALLOC_INT) {
674 SMC_ACK_INT(lp, IM_ALLOC_INT);
677 } while (--poll_count);
679 smc_special_unlock(&lp->lock);
681 lp->pending_tx_skb = skb;
683 /* oh well, wait until the chip finds memory later */
684 netif_stop_queue(dev);
685 DBG(2, "%s: TX memory allocation deferred.\n", dev->name);
686 SMC_ENABLE_INT(lp, IM_ALLOC_INT);
689 * Allocation succeeded: push packet to the chip's own memory
692 smc_hardware_send_pkt((unsigned long)dev);
699 * This handles a TX interrupt, which is only called when:
700 * - a TX error occurred, or
701 * - CTL_AUTO_RELEASE is not set and TX of a packet completed.
703 static void smc_tx(struct net_device *dev)
705 struct smc_local *lp = netdev_priv(dev);
706 void __iomem *ioaddr = lp->base;
707 unsigned int saved_packet, packet_no, tx_status, pkt_len;
709 DBG(3, "%s: %s\n", dev->name, __func__);
711 /* If the TX FIFO is empty then nothing to do */
712 packet_no = SMC_GET_TXFIFO(lp);
713 if (unlikely(packet_no & TXFIFO_TEMPTY)) {
714 PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
718 /* select packet to read from */
719 saved_packet = SMC_GET_PN(lp);
720 SMC_SET_PN(lp, packet_no);
722 /* read the first word (status word) from this packet */
723 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
724 SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
725 DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
726 dev->name, tx_status, packet_no);
728 if (!(tx_status & ES_TX_SUC))
729 dev->stats.tx_errors++;
731 if (tx_status & ES_LOSTCARR)
732 dev->stats.tx_carrier_errors++;
734 if (tx_status & (ES_LATCOL | ES_16COL)) {
735 PRINTK("%s: %s occurred on last xmit\n", dev->name,
736 (tx_status & ES_LATCOL) ?
737 "late collision" : "too many collisions");
738 dev->stats.tx_window_errors++;
739 if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
740 printk(KERN_INFO "%s: unexpectedly large number of "
741 "bad collisions. Please check duplex "
742 "setting.\n", dev->name);
746 /* kill the packet */
747 SMC_WAIT_MMU_BUSY(lp);
748 SMC_SET_MMU_CMD(lp, MC_FREEPKT);
750 /* Don't restore Packet Number Reg until busy bit is cleared */
751 SMC_WAIT_MMU_BUSY(lp);
752 SMC_SET_PN(lp, saved_packet);
754 /* re-enable transmit */
755 SMC_SELECT_BANK(lp, 0);
756 SMC_SET_TCR(lp, lp->tcr_cur_mode);
757 SMC_SELECT_BANK(lp, 2);
761 /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
763 static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
765 struct smc_local *lp = netdev_priv(dev);
766 void __iomem *ioaddr = lp->base;
767 unsigned int mii_reg, mask;
769 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
772 for (mask = 1 << (bits - 1); mask; mask >>= 1) {
778 SMC_SET_MII(lp, mii_reg);
780 SMC_SET_MII(lp, mii_reg | MII_MCLK);
785 static unsigned int smc_mii_in(struct net_device *dev, int bits)
787 struct smc_local *lp = netdev_priv(dev);
788 void __iomem *ioaddr = lp->base;
789 unsigned int mii_reg, mask, val;
791 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
792 SMC_SET_MII(lp, mii_reg);
794 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
795 if (SMC_GET_MII(lp) & MII_MDI)
798 SMC_SET_MII(lp, mii_reg);
800 SMC_SET_MII(lp, mii_reg | MII_MCLK);
808 * Reads a register from the MII Management serial interface
810 static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
812 struct smc_local *lp = netdev_priv(dev);
813 void __iomem *ioaddr = lp->base;
814 unsigned int phydata;
816 SMC_SELECT_BANK(lp, 3);
819 smc_mii_out(dev, 0xffffffff, 32);
821 /* Start code (01) + read (10) + phyaddr + phyreg */
822 smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
824 /* Turnaround (2bits) + phydata */
825 phydata = smc_mii_in(dev, 18);
827 /* Return to idle state */
828 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
830 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
831 __func__, phyaddr, phyreg, phydata);
833 SMC_SELECT_BANK(lp, 2);
838 * Writes a register to the MII Management serial interface
840 static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
843 struct smc_local *lp = netdev_priv(dev);
844 void __iomem *ioaddr = lp->base;
846 SMC_SELECT_BANK(lp, 3);
849 smc_mii_out(dev, 0xffffffff, 32);
851 /* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
852 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
854 /* Return to idle state */
855 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
857 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
858 __func__, phyaddr, phyreg, phydata);
860 SMC_SELECT_BANK(lp, 2);
864 * Finds and reports the PHY address
866 static void smc_phy_detect(struct net_device *dev)
868 struct smc_local *lp = netdev_priv(dev);
871 DBG(2, "%s: %s\n", dev->name, __func__);
876 * Scan all 32 PHY addresses if necessary, starting at
877 * PHY#1 to PHY#31, and then PHY#0 last.
879 for (phyaddr = 1; phyaddr < 33; ++phyaddr) {
880 unsigned int id1, id2;
882 /* Read the PHY identifiers */
883 id1 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID1);
884 id2 = smc_phy_read(dev, phyaddr & 31, MII_PHYSID2);
886 DBG(3, "%s: phy_id1=0x%x, phy_id2=0x%x\n",
887 dev->name, id1, id2);
889 /* Make sure it is a valid identifier */
890 if (id1 != 0x0000 && id1 != 0xffff && id1 != 0x8000 &&
891 id2 != 0x0000 && id2 != 0xffff && id2 != 0x8000) {
892 /* Save the PHY's address */
893 lp->mii.phy_id = phyaddr & 31;
894 lp->phy_type = id1 << 16 | id2;
901 * Sets the PHY to a configuration as determined by the user
903 static int smc_phy_fixed(struct net_device *dev)
905 struct smc_local *lp = netdev_priv(dev);
906 void __iomem *ioaddr = lp->base;
907 int phyaddr = lp->mii.phy_id;
910 DBG(3, "%s: %s\n", dev->name, __func__);
912 /* Enter Link Disable state */
913 cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
914 cfg1 |= PHY_CFG1_LNKDIS;
915 smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
918 * Set our fixed capabilities
919 * Disable auto-negotiation
924 bmcr |= BMCR_FULLDPLX;
926 if (lp->ctl_rspeed == 100)
927 bmcr |= BMCR_SPEED100;
929 /* Write our capabilities to the phy control register */
930 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
932 /* Re-Configure the Receive/Phy Control register */
933 SMC_SELECT_BANK(lp, 0);
934 SMC_SET_RPC(lp, lp->rpc_cur_mode);
935 SMC_SELECT_BANK(lp, 2);
941 * smc_phy_reset - reset the phy
945 * Issue a software reset for the specified PHY and
946 * wait up to 100ms for the reset to complete. We should
947 * not access the PHY for 50ms after issuing the reset.
949 * The time to wait appears to be dependent on the PHY.
951 * Must be called with lp->lock locked.
953 static int smc_phy_reset(struct net_device *dev, int phy)
955 struct smc_local *lp = netdev_priv(dev);
959 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
961 for (timeout = 2; timeout; timeout--) {
962 spin_unlock_irq(&lp->lock);
964 spin_lock_irq(&lp->lock);
966 bmcr = smc_phy_read(dev, phy, MII_BMCR);
967 if (!(bmcr & BMCR_RESET))
971 return bmcr & BMCR_RESET;
975 * smc_phy_powerdown - powerdown phy
978 * Power down the specified PHY
980 static void smc_phy_powerdown(struct net_device *dev)
982 struct smc_local *lp = netdev_priv(dev);
984 int phy = lp->mii.phy_id;
986 if (lp->phy_type == 0)
989 /* We need to ensure that no calls to smc_phy_configure are
992 cancel_work_sync(&lp->phy_configure);
994 bmcr = smc_phy_read(dev, phy, MII_BMCR);
995 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
999 * smc_phy_check_media - check the media status and adjust TCR
1001 * @init: set true for initialisation
1003 * Select duplex mode depending on negotiation state. This
1004 * also updates our carrier state.
1006 static void smc_phy_check_media(struct net_device *dev, int init)
1008 struct smc_local *lp = netdev_priv(dev);
1009 void __iomem *ioaddr = lp->base;
1011 if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
1012 /* duplex state has changed */
1013 if (lp->mii.full_duplex) {
1014 lp->tcr_cur_mode |= TCR_SWFDUP;
1016 lp->tcr_cur_mode &= ~TCR_SWFDUP;
1019 SMC_SELECT_BANK(lp, 0);
1020 SMC_SET_TCR(lp, lp->tcr_cur_mode);
1025 * Configures the specified PHY through the MII management interface
1026 * using Autonegotiation.
1027 * Calls smc_phy_fixed() if the user has requested a certain config.
1028 * If RPC ANEG bit is set, the media selection is dependent purely on
1029 * the selection by the MII (either in the MII BMCR reg or the result
1030 * of autonegotiation.) If the RPC ANEG bit is cleared, the selection
1031 * is controlled by the RPC SPEED and RPC DPLX bits.
1033 static void smc_phy_configure(struct work_struct *work)
1035 struct smc_local *lp =
1036 container_of(work, struct smc_local, phy_configure);
1037 struct net_device *dev = lp->dev;
1038 void __iomem *ioaddr = lp->base;
1039 int phyaddr = lp->mii.phy_id;
1040 int my_phy_caps; /* My PHY capabilities */
1041 int my_ad_caps; /* My Advertised capabilities */
1044 DBG(3, "%s:smc_program_phy()\n", dev->name);
1046 spin_lock_irq(&lp->lock);
1049 * We should not be called if phy_type is zero.
1051 if (lp->phy_type == 0)
1052 goto smc_phy_configure_exit;
1054 if (smc_phy_reset(dev, phyaddr)) {
1055 printk("%s: PHY reset timed out\n", dev->name);
1056 goto smc_phy_configure_exit;
1060 * Enable PHY Interrupts (for register 18)
1061 * Interrupts listed here are disabled
1063 smc_phy_write(dev, phyaddr, PHY_MASK_REG,
1064 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
1065 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
1066 PHY_INT_SPDDET | PHY_INT_DPLXDET);
1068 /* Configure the Receive/Phy Control register */
1069 SMC_SELECT_BANK(lp, 0);
1070 SMC_SET_RPC(lp, lp->rpc_cur_mode);
1072 /* If the user requested no auto neg, then go set his request */
1073 if (lp->mii.force_media) {
1075 goto smc_phy_configure_exit;
1078 /* Copy our capabilities from MII_BMSR to MII_ADVERTISE */
1079 my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
1081 if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
1082 printk(KERN_INFO "Auto negotiation NOT supported\n");
1084 goto smc_phy_configure_exit;
1087 my_ad_caps = ADVERTISE_CSMA; /* I am CSMA capable */
1089 if (my_phy_caps & BMSR_100BASE4)
1090 my_ad_caps |= ADVERTISE_100BASE4;
1091 if (my_phy_caps & BMSR_100FULL)
1092 my_ad_caps |= ADVERTISE_100FULL;
1093 if (my_phy_caps & BMSR_100HALF)
1094 my_ad_caps |= ADVERTISE_100HALF;
1095 if (my_phy_caps & BMSR_10FULL)
1096 my_ad_caps |= ADVERTISE_10FULL;
1097 if (my_phy_caps & BMSR_10HALF)
1098 my_ad_caps |= ADVERTISE_10HALF;
1100 /* Disable capabilities not selected by our user */
1101 if (lp->ctl_rspeed != 100)
1102 my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
1104 if (!lp->ctl_rfduplx)
1105 my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
1107 /* Update our Auto-Neg Advertisement Register */
1108 smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
1109 lp->mii.advertising = my_ad_caps;
1112 * Read the register back. Without this, it appears that when
1113 * auto-negotiation is restarted, sometimes it isn't ready and
1114 * the link does not come up.
1116 status = smc_phy_read(dev, phyaddr, MII_ADVERTISE);
1118 DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps);
1119 DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps);
1121 /* Restart auto-negotiation process in order to advertise my caps */
1122 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1124 smc_phy_check_media(dev, 1);
1126 smc_phy_configure_exit:
1127 SMC_SELECT_BANK(lp, 2);
1128 spin_unlock_irq(&lp->lock);
1134 * Purpose: Handle interrupts relating to PHY register 18. This is
1135 * called from the "hard" interrupt handler under our private spinlock.
1137 static void smc_phy_interrupt(struct net_device *dev)
1139 struct smc_local *lp = netdev_priv(dev);
1140 int phyaddr = lp->mii.phy_id;
1143 DBG(2, "%s: %s\n", dev->name, __func__);
1145 if (lp->phy_type == 0)
1149 smc_phy_check_media(dev, 0);
1151 /* Read PHY Register 18, Status Output */
1152 phy18 = smc_phy_read(dev, phyaddr, PHY_INT_REG);
1153 if ((phy18 & PHY_INT_INT) == 0)
1158 /*--- END PHY CONTROL AND CONFIGURATION-------------------------------------*/
1160 static void smc_10bt_check_media(struct net_device *dev, int init)
1162 struct smc_local *lp = netdev_priv(dev);
1163 void __iomem *ioaddr = lp->base;
1164 unsigned int old_carrier, new_carrier;
1166 old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1168 SMC_SELECT_BANK(lp, 0);
1169 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
1170 SMC_SELECT_BANK(lp, 2);
1172 if (init || (old_carrier != new_carrier)) {
1174 netif_carrier_off(dev);
1176 netif_carrier_on(dev);
1178 if (netif_msg_link(lp))
1179 printk(KERN_INFO "%s: link %s\n", dev->name,
1180 new_carrier ? "up" : "down");
1184 static void smc_eph_interrupt(struct net_device *dev)
1186 struct smc_local *lp = netdev_priv(dev);
1187 void __iomem *ioaddr = lp->base;
1190 smc_10bt_check_media(dev, 0);
1192 SMC_SELECT_BANK(lp, 1);
1193 ctl = SMC_GET_CTL(lp);
1194 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
1195 SMC_SET_CTL(lp, ctl);
1196 SMC_SELECT_BANK(lp, 2);
1200 * This is the main routine of the driver, to handle the device when
1201 * it needs some attention.
1203 static irqreturn_t smc_interrupt(int irq, void *dev_id)
1205 struct net_device *dev = dev_id;
1206 struct smc_local *lp = netdev_priv(dev);
1207 void __iomem *ioaddr = lp->base;
1208 int status, mask, timeout, card_stats;
1211 DBG(3, "%s: %s\n", dev->name, __func__);
1213 spin_lock(&lp->lock);
1215 /* A preamble may be used when there is a potential race
1216 * between the interruptible transmit functions and this
1218 SMC_INTERRUPT_PREAMBLE;
1220 saved_pointer = SMC_GET_PTR(lp);
1221 mask = SMC_GET_INT_MASK(lp);
1222 SMC_SET_INT_MASK(lp, 0);
1224 /* set a timeout value, so I don't stay here forever */
1225 timeout = MAX_IRQ_LOOPS;
1228 status = SMC_GET_INT(lp);
1230 DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
1231 dev->name, status, mask,
1232 ({ int meminfo; SMC_SELECT_BANK(lp, 0);
1233 meminfo = SMC_GET_MIR(lp);
1234 SMC_SELECT_BANK(lp, 2); meminfo; }),
1241 if (status & IM_TX_INT) {
1242 /* do this before RX as it will free memory quickly */
1243 DBG(3, "%s: TX int\n", dev->name);
1245 SMC_ACK_INT(lp, IM_TX_INT);
1246 if (THROTTLE_TX_PKTS)
1247 netif_wake_queue(dev);
1248 } else if (status & IM_RCV_INT) {
1249 DBG(3, "%s: RX irq\n", dev->name);
1251 } else if (status & IM_ALLOC_INT) {
1252 DBG(3, "%s: Allocation irq\n", dev->name);
1253 tasklet_hi_schedule(&lp->tx_task);
1254 mask &= ~IM_ALLOC_INT;
1255 } else if (status & IM_TX_EMPTY_INT) {
1256 DBG(3, "%s: TX empty\n", dev->name);
1257 mask &= ~IM_TX_EMPTY_INT;
1260 SMC_SELECT_BANK(lp, 0);
1261 card_stats = SMC_GET_COUNTER(lp);
1262 SMC_SELECT_BANK(lp, 2);
1264 /* single collisions */
1265 dev->stats.collisions += card_stats & 0xF;
1268 /* multiple collisions */
1269 dev->stats.collisions += card_stats & 0xF;
1270 } else if (status & IM_RX_OVRN_INT) {
1271 DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name,
1272 ({ int eph_st; SMC_SELECT_BANK(lp, 0);
1273 eph_st = SMC_GET_EPH_STATUS(lp);
1274 SMC_SELECT_BANK(lp, 2); eph_st; }));
1275 SMC_ACK_INT(lp, IM_RX_OVRN_INT);
1276 dev->stats.rx_errors++;
1277 dev->stats.rx_fifo_errors++;
1278 } else if (status & IM_EPH_INT) {
1279 smc_eph_interrupt(dev);
1280 } else if (status & IM_MDINT) {
1281 SMC_ACK_INT(lp, IM_MDINT);
1282 smc_phy_interrupt(dev);
1283 } else if (status & IM_ERCV_INT) {
1284 SMC_ACK_INT(lp, IM_ERCV_INT);
1285 PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name);
1287 } while (--timeout);
1289 /* restore register states */
1290 SMC_SET_PTR(lp, saved_pointer);
1291 SMC_SET_INT_MASK(lp, mask);
1292 spin_unlock(&lp->lock);
1294 #ifndef CONFIG_NET_POLL_CONTROLLER
1295 if (timeout == MAX_IRQ_LOOPS)
1296 PRINTK("%s: spurious interrupt (mask = 0x%02x)\n",
1299 DBG(3, "%s: Interrupt done (%d loops)\n",
1300 dev->name, MAX_IRQ_LOOPS - timeout);
1303 * We return IRQ_HANDLED unconditionally here even if there was
1304 * nothing to do. There is a possibility that a packet might
1305 * get enqueued into the chip right after TX_EMPTY_INT is raised
1306 * but just before the CPU acknowledges the IRQ.
1307 * Better take an unneeded IRQ in some occasions than complexifying
1308 * the code for all cases.
1313 #ifdef CONFIG_NET_POLL_CONTROLLER
1315 * Polling receive - used by netconsole and other diagnostic tools
1316 * to allow network i/o with interrupts disabled.
1318 static void smc_poll_controller(struct net_device *dev)
1320 disable_irq(dev->irq);
1321 smc_interrupt(dev->irq, dev);
1322 enable_irq(dev->irq);
1326 /* Our watchdog timed out. Called by the networking layer */
1327 static void smc_timeout(struct net_device *dev)
1329 struct smc_local *lp = netdev_priv(dev);
1330 void __iomem *ioaddr = lp->base;
1331 int status, mask, eph_st, meminfo, fifo;
1333 DBG(2, "%s: %s\n", dev->name, __func__);
1335 spin_lock_irq(&lp->lock);
1336 status = SMC_GET_INT(lp);
1337 mask = SMC_GET_INT_MASK(lp);
1338 fifo = SMC_GET_FIFO(lp);
1339 SMC_SELECT_BANK(lp, 0);
1340 eph_st = SMC_GET_EPH_STATUS(lp);
1341 meminfo = SMC_GET_MIR(lp);
1342 SMC_SELECT_BANK(lp, 2);
1343 spin_unlock_irq(&lp->lock);
1344 PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x "
1345 "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
1346 dev->name, status, mask, meminfo, fifo, eph_st );
1352 * Reconfiguring the PHY doesn't seem like a bad idea here, but
1353 * smc_phy_configure() calls msleep() which calls schedule_timeout()
1354 * which calls schedule(). Hence we use a work queue.
1356 if (lp->phy_type != 0)
1357 schedule_work(&lp->phy_configure);
1359 /* We can accept TX packets again */
1360 dev->trans_start = jiffies;
1361 netif_wake_queue(dev);
1365 * This routine will, depending on the values passed to it,
1366 * either make it accept multicast packets, go into
1367 * promiscuous mode (for TCPDUMP and cousins) or accept
1368 * a select set of multicast packets
1370 static void smc_set_multicast_list(struct net_device *dev)
1372 struct smc_local *lp = netdev_priv(dev);
1373 void __iomem *ioaddr = lp->base;
1374 unsigned char multicast_table[8];
1375 int update_multicast = 0;
1377 DBG(2, "%s: %s\n", dev->name, __func__);
1379 if (dev->flags & IFF_PROMISC) {
1380 DBG(2, "%s: RCR_PRMS\n", dev->name);
1381 lp->rcr_cur_mode |= RCR_PRMS;
1384 /* BUG? I never disable promiscuous mode if multicasting was turned on.
1385 Now, I turn off promiscuous mode, but I don't do anything to multicasting
1386 when promiscuous mode is turned on.
1390 * Here, I am setting this to accept all multicast packets.
1391 * I don't need to zero the multicast table, because the flag is
1392 * checked before the table is
1394 else if (dev->flags & IFF_ALLMULTI || dev->mc_count > 16) {
1395 DBG(2, "%s: RCR_ALMUL\n", dev->name);
1396 lp->rcr_cur_mode |= RCR_ALMUL;
1400 * This sets the internal hardware table to filter out unwanted
1401 * multicast packets before they take up memory.
1403 * The SMC chip uses a hash table where the high 6 bits of the CRC of
1404 * address are the offset into the table. If that bit is 1, then the
1405 * multicast packet is accepted. Otherwise, it's dropped silently.
1407 * To use the 6 bits as an offset into the table, the high 3 bits are
1408 * the number of the 8 bit register, while the low 3 bits are the bit
1409 * within that register.
1411 else if (dev->mc_count) {
1413 struct dev_mc_list *cur_addr;
1415 /* table for flipping the order of 3 bits */
1416 static const unsigned char invert3[] = {0, 4, 2, 6, 1, 5, 3, 7};
1418 /* start with a table of all zeros: reject all */
1419 memset(multicast_table, 0, sizeof(multicast_table));
1421 cur_addr = dev->mc_list;
1422 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
1425 /* do we have a pointer here? */
1428 /* make sure this is a multicast address -
1429 shouldn't this be a given if we have it here ? */
1430 if (!(*cur_addr->dmi_addr & 1))
1433 /* only use the low order bits */
1434 position = crc32_le(~0, cur_addr->dmi_addr, 6) & 0x3f;
1436 /* do some messy swapping to put the bit in the right spot */
1437 multicast_table[invert3[position&7]] |=
1438 (1<<invert3[(position>>3)&7]);
1441 /* be sure I get rid of flags I might have set */
1442 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1444 /* now, the table can be loaded into the chipset */
1445 update_multicast = 1;
1447 DBG(2, "%s: ~(RCR_PRMS|RCR_ALMUL)\n", dev->name);
1448 lp->rcr_cur_mode &= ~(RCR_PRMS | RCR_ALMUL);
1451 * since I'm disabling all multicast entirely, I need to
1452 * clear the multicast list
1454 memset(multicast_table, 0, sizeof(multicast_table));
1455 update_multicast = 1;
1458 spin_lock_irq(&lp->lock);
1459 SMC_SELECT_BANK(lp, 0);
1460 SMC_SET_RCR(lp, lp->rcr_cur_mode);
1461 if (update_multicast) {
1462 SMC_SELECT_BANK(lp, 3);
1463 SMC_SET_MCAST(lp, multicast_table);
1465 SMC_SELECT_BANK(lp, 2);
1466 spin_unlock_irq(&lp->lock);
1471 * Open and Initialize the board
1473 * Set up everything, reset the card, etc..
1476 smc_open(struct net_device *dev)
1478 struct smc_local *lp = netdev_priv(dev);
1480 DBG(2, "%s: %s\n", dev->name, __func__);
1483 * Check that the address is valid. If its not, refuse
1484 * to bring the device up. The user must specify an
1485 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1487 if (!is_valid_ether_addr(dev->dev_addr)) {
1488 PRINTK("%s: no valid ethernet hw addr\n", __func__);
1492 /* Setup the default Register Modes */
1493 lp->tcr_cur_mode = TCR_DEFAULT;
1494 lp->rcr_cur_mode = RCR_DEFAULT;
1495 lp->rpc_cur_mode = RPC_DEFAULT |
1496 lp->cfg.leda << RPC_LSXA_SHFT |
1497 lp->cfg.ledb << RPC_LSXB_SHFT;
1500 * If we are not using a MII interface, we need to
1501 * monitor our own carrier signal to detect faults.
1503 if (lp->phy_type == 0)
1504 lp->tcr_cur_mode |= TCR_MON_CSN;
1506 /* reset the hardware */
1510 /* Configure the PHY, initialize the link state */
1511 if (lp->phy_type != 0)
1512 smc_phy_configure(&lp->phy_configure);
1514 spin_lock_irq(&lp->lock);
1515 smc_10bt_check_media(dev, 1);
1516 spin_unlock_irq(&lp->lock);
1519 netif_start_queue(dev);
1526 * this makes the board clean up everything that it can
1527 * and not talk to the outside world. Caused by
1528 * an 'ifconfig ethX down'
1530 static int smc_close(struct net_device *dev)
1532 struct smc_local *lp = netdev_priv(dev);
1534 DBG(2, "%s: %s\n", dev->name, __func__);
1536 netif_stop_queue(dev);
1537 netif_carrier_off(dev);
1539 /* clear everything */
1541 tasklet_kill(&lp->tx_task);
1542 smc_phy_powerdown(dev);
1550 smc_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1552 struct smc_local *lp = netdev_priv(dev);
1558 if (lp->phy_type != 0) {
1559 spin_lock_irq(&lp->lock);
1560 ret = mii_ethtool_gset(&lp->mii, cmd);
1561 spin_unlock_irq(&lp->lock);
1563 cmd->supported = SUPPORTED_10baseT_Half |
1564 SUPPORTED_10baseT_Full |
1565 SUPPORTED_TP | SUPPORTED_AUI;
1567 if (lp->ctl_rspeed == 10)
1568 cmd->speed = SPEED_10;
1569 else if (lp->ctl_rspeed == 100)
1570 cmd->speed = SPEED_100;
1572 cmd->autoneg = AUTONEG_DISABLE;
1573 cmd->transceiver = XCVR_INTERNAL;
1575 cmd->duplex = lp->tcr_cur_mode & TCR_SWFDUP ? DUPLEX_FULL : DUPLEX_HALF;
1584 smc_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
1586 struct smc_local *lp = netdev_priv(dev);
1589 if (lp->phy_type != 0) {
1590 spin_lock_irq(&lp->lock);
1591 ret = mii_ethtool_sset(&lp->mii, cmd);
1592 spin_unlock_irq(&lp->lock);
1594 if (cmd->autoneg != AUTONEG_DISABLE ||
1595 cmd->speed != SPEED_10 ||
1596 (cmd->duplex != DUPLEX_HALF && cmd->duplex != DUPLEX_FULL) ||
1597 (cmd->port != PORT_TP && cmd->port != PORT_AUI))
1600 // lp->port = cmd->port;
1601 lp->ctl_rfduplx = cmd->duplex == DUPLEX_FULL;
1603 // if (netif_running(dev))
1604 // smc_set_port(dev);
1613 smc_ethtool_getdrvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1615 strncpy(info->driver, CARDNAME, sizeof(info->driver));
1616 strncpy(info->version, version, sizeof(info->version));
1617 strncpy(info->bus_info, dev_name(dev->dev.parent), sizeof(info->bus_info));
1620 static int smc_ethtool_nwayreset(struct net_device *dev)
1622 struct smc_local *lp = netdev_priv(dev);
1625 if (lp->phy_type != 0) {
1626 spin_lock_irq(&lp->lock);
1627 ret = mii_nway_restart(&lp->mii);
1628 spin_unlock_irq(&lp->lock);
1634 static u32 smc_ethtool_getmsglevel(struct net_device *dev)
1636 struct smc_local *lp = netdev_priv(dev);
1637 return lp->msg_enable;
1640 static void smc_ethtool_setmsglevel(struct net_device *dev, u32 level)
1642 struct smc_local *lp = netdev_priv(dev);
1643 lp->msg_enable = level;
1646 static int smc_write_eeprom_word(struct net_device *dev, u16 addr, u16 word)
1649 struct smc_local *lp = netdev_priv(dev);
1650 void __iomem *ioaddr = lp->base;
1652 spin_lock_irq(&lp->lock);
1653 /* load word into GP register */
1654 SMC_SELECT_BANK(lp, 1);
1655 SMC_SET_GP(lp, word);
1656 /* set the address to put the data in EEPROM */
1657 SMC_SELECT_BANK(lp, 2);
1658 SMC_SET_PTR(lp, addr);
1659 /* tell it to write */
1660 SMC_SELECT_BANK(lp, 1);
1661 ctl = SMC_GET_CTL(lp);
1662 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_STORE));
1663 /* wait for it to finish */
1666 } while (SMC_GET_CTL(lp) & CTL_STORE);
1668 SMC_SET_CTL(lp, ctl);
1669 SMC_SELECT_BANK(lp, 2);
1670 spin_unlock_irq(&lp->lock);
1674 static int smc_read_eeprom_word(struct net_device *dev, u16 addr, u16 *word)
1677 struct smc_local *lp = netdev_priv(dev);
1678 void __iomem *ioaddr = lp->base;
1680 spin_lock_irq(&lp->lock);
1681 /* set the EEPROM address to get the data from */
1682 SMC_SELECT_BANK(lp, 2);
1683 SMC_SET_PTR(lp, addr | PTR_READ);
1684 /* tell it to load */
1685 SMC_SELECT_BANK(lp, 1);
1686 SMC_SET_GP(lp, 0xffff); /* init to known */
1687 ctl = SMC_GET_CTL(lp);
1688 SMC_SET_CTL(lp, ctl | (CTL_EEPROM_SELECT | CTL_RELOAD));
1689 /* wait for it to finish */
1692 } while (SMC_GET_CTL(lp) & CTL_RELOAD);
1693 /* read word from GP register */
1694 *word = SMC_GET_GP(lp);
1696 SMC_SET_CTL(lp, ctl);
1697 SMC_SELECT_BANK(lp, 2);
1698 spin_unlock_irq(&lp->lock);
1702 static int smc_ethtool_geteeprom_len(struct net_device *dev)
1707 static int smc_ethtool_geteeprom(struct net_device *dev,
1708 struct ethtool_eeprom *eeprom, u8 *data)
1713 DBG(1, "Reading %d bytes at %d(0x%x)\n",
1714 eeprom->len, eeprom->offset, eeprom->offset);
1715 imax = smc_ethtool_geteeprom_len(dev);
1716 for (i = 0; i < eeprom->len; i += 2) {
1719 int offset = i + eeprom->offset;
1722 ret = smc_read_eeprom_word(dev, offset >> 1, &wbuf);
1725 DBG(2, "Read 0x%x from 0x%x\n", wbuf, offset >> 1);
1726 data[i] = (wbuf >> 8) & 0xff;
1727 data[i+1] = wbuf & 0xff;
1732 static int smc_ethtool_seteeprom(struct net_device *dev,
1733 struct ethtool_eeprom *eeprom, u8 *data)
1738 DBG(1, "Writing %d bytes to %d(0x%x)\n",
1739 eeprom->len, eeprom->offset, eeprom->offset);
1740 imax = smc_ethtool_geteeprom_len(dev);
1741 for (i = 0; i < eeprom->len; i += 2) {
1744 int offset = i + eeprom->offset;
1747 wbuf = (data[i] << 8) | data[i + 1];
1748 DBG(2, "Writing 0x%x to 0x%x\n", wbuf, offset >> 1);
1749 ret = smc_write_eeprom_word(dev, offset >> 1, wbuf);
1757 static const struct ethtool_ops smc_ethtool_ops = {
1758 .get_settings = smc_ethtool_getsettings,
1759 .set_settings = smc_ethtool_setsettings,
1760 .get_drvinfo = smc_ethtool_getdrvinfo,
1762 .get_msglevel = smc_ethtool_getmsglevel,
1763 .set_msglevel = smc_ethtool_setmsglevel,
1764 .nway_reset = smc_ethtool_nwayreset,
1765 .get_link = ethtool_op_get_link,
1766 .get_eeprom_len = smc_ethtool_geteeprom_len,
1767 .get_eeprom = smc_ethtool_geteeprom,
1768 .set_eeprom = smc_ethtool_seteeprom,
1771 static const struct net_device_ops smc_netdev_ops = {
1772 .ndo_open = smc_open,
1773 .ndo_stop = smc_close,
1774 .ndo_start_xmit = smc_hard_start_xmit,
1775 .ndo_tx_timeout = smc_timeout,
1776 .ndo_set_multicast_list = smc_set_multicast_list,
1777 .ndo_validate_addr = eth_validate_addr,
1778 .ndo_set_mac_address = eth_mac_addr,
1779 #ifdef CONFIG_NET_POLL_CONTROLLER
1780 .ndo_poll_controller = smc_poll_controller,
1787 * This routine has a simple purpose -- make the SMC chip generate an
1788 * interrupt, so an auto-detect routine can detect it, and find the IRQ,
1791 * does this still work?
1793 * I just deleted auto_irq.c, since it was never built...
1796 static int __devinit smc_findirq(struct smc_local *lp)
1798 void __iomem *ioaddr = lp->base;
1800 unsigned long cookie;
1802 DBG(2, "%s: %s\n", CARDNAME, __func__);
1804 cookie = probe_irq_on();
1807 * What I try to do here is trigger an ALLOC_INT. This is done
1808 * by allocating a small chunk of memory, which will give an interrupt
1811 /* enable ALLOCation interrupts ONLY */
1812 SMC_SELECT_BANK(lp, 2);
1813 SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
1816 * Allocate 512 bytes of memory. Note that the chip was just
1817 * reset so all the memory is available
1819 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
1822 * Wait until positive that the interrupt has been generated
1827 int_status = SMC_GET_INT(lp);
1828 if (int_status & IM_ALLOC_INT)
1829 break; /* got the interrupt */
1830 } while (--timeout);
1833 * there is really nothing that I can do here if timeout fails,
1834 * as autoirq_report will return a 0 anyway, which is what I
1835 * want in this case. Plus, the clean up is needed in both
1839 /* and disable all interrupts again */
1840 SMC_SET_INT_MASK(lp, 0);
1842 /* and return what I found */
1843 return probe_irq_off(cookie);
1847 * Function: smc_probe(unsigned long ioaddr)
1850 * Tests to see if a given ioaddr points to an SMC91x chip.
1851 * Returns a 0 on success
1854 * (1) see if the high byte of BANK_SELECT is 0x33
1855 * (2) compare the ioaddr with the base register's address
1856 * (3) see if I recognize the chip ID in the appropriate register
1858 * Here I do typical initialization tasks.
1860 * o Initialize the structure if needed
1861 * o print out my vanity message if not done so already
1862 * o print out what type of hardware is detected
1863 * o print out the ethernet address
1865 * o set up my private data
1866 * o configure the dev structure with my subroutines
1867 * o actually GRAB the irq.
1870 static int __devinit smc_probe(struct net_device *dev, void __iomem *ioaddr,
1871 unsigned long irq_flags)
1873 struct smc_local *lp = netdev_priv(dev);
1874 static int version_printed = 0;
1876 unsigned int val, revision_register;
1877 const char *version_string;
1879 DBG(2, "%s: %s\n", CARDNAME, __func__);
1881 /* First, see if the high byte is 0x33 */
1882 val = SMC_CURRENT_BANK(lp);
1883 DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val);
1884 if ((val & 0xFF00) != 0x3300) {
1885 if ((val & 0xFF) == 0x33) {
1887 "%s: Detected possible byte-swapped interface"
1888 " at IOADDR %p\n", CARDNAME, ioaddr);
1895 * The above MIGHT indicate a device, but I need to write to
1896 * further test this.
1898 SMC_SELECT_BANK(lp, 0);
1899 val = SMC_CURRENT_BANK(lp);
1900 if ((val & 0xFF00) != 0x3300) {
1906 * well, we've already written once, so hopefully another
1907 * time won't hurt. This time, I need to switch the bank
1908 * register to bank 1, so I can access the base address
1911 SMC_SELECT_BANK(lp, 1);
1912 val = SMC_GET_BASE(lp);
1913 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1914 if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1915 printk("%s: IOADDR %p doesn't match configuration (%x).\n",
1916 CARDNAME, ioaddr, val);
1920 * check if the revision register is something that I
1921 * recognize. These might need to be added to later,
1922 * as future revisions could be added.
1924 SMC_SELECT_BANK(lp, 3);
1925 revision_register = SMC_GET_REV(lp);
1926 DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
1927 version_string = chip_ids[ (revision_register >> 4) & 0xF];
1928 if (!version_string || (revision_register & 0xff00) != 0x3300) {
1929 /* I don't recognize this chip, so... */
1930 printk("%s: IO %p: Unrecognized revision register 0x%04x"
1931 ", Contact author.\n", CARDNAME,
1932 ioaddr, revision_register);
1938 /* At this point I'll assume that the chip is an SMC91x. */
1939 if (version_printed++ == 0)
1940 printk("%s", version);
1942 /* fill in some of the fields */
1943 dev->base_addr = (unsigned long)ioaddr;
1945 lp->version = revision_register & 0xff;
1946 spin_lock_init(&lp->lock);
1948 /* Get the MAC address */
1949 SMC_SELECT_BANK(lp, 1);
1950 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1952 /* now, reset the chip, and put it into a known state */
1956 * If dev->irq is 0, then the device has to be banged on to see
1959 * This banging doesn't always detect the IRQ, for unknown reasons.
1960 * a workaround is to reset the chip and try again.
1962 * Interestingly, the DOS packet driver *SETS* the IRQ on the card to
1963 * be what is requested on the command line. I don't do that, mostly
1964 * because the card that I have uses a non-standard method of accessing
1965 * the IRQs, and because this _should_ work in most configurations.
1967 * Specifying an IRQ is done with the assumption that the user knows
1968 * what (s)he is doing. No checking is done!!!!
1975 dev->irq = smc_findirq(lp);
1978 /* kick the card and try again */
1982 if (dev->irq == 0) {
1983 printk("%s: Couldn't autodetect your IRQ. Use irq=xx.\n",
1988 dev->irq = irq_canonicalize(dev->irq);
1990 /* Fill in the fields of the device structure with ethernet values. */
1993 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1994 dev->netdev_ops = &smc_netdev_ops;
1995 dev->ethtool_ops = &smc_ethtool_ops;
1997 tasklet_init(&lp->tx_task, smc_hardware_send_pkt, (unsigned long)dev);
1998 INIT_WORK(&lp->phy_configure, smc_phy_configure);
2000 lp->mii.phy_id_mask = 0x1f;
2001 lp->mii.reg_num_mask = 0x1f;
2002 lp->mii.force_media = 0;
2003 lp->mii.full_duplex = 0;
2005 lp->mii.mdio_read = smc_phy_read;
2006 lp->mii.mdio_write = smc_phy_write;
2009 * Locate the phy, if any.
2011 if (lp->version >= (CHIP_91100 << 4))
2012 smc_phy_detect(dev);
2014 /* then shut everything down to save power */
2016 smc_phy_powerdown(dev);
2018 /* Set default parameters */
2019 lp->msg_enable = NETIF_MSG_LINK;
2020 lp->ctl_rfduplx = 0;
2021 lp->ctl_rspeed = 10;
2023 if (lp->version >= (CHIP_91100 << 4)) {
2024 lp->ctl_rfduplx = 1;
2025 lp->ctl_rspeed = 100;
2029 retval = request_irq(dev->irq, &smc_interrupt, irq_flags, dev->name, dev);
2033 #ifdef CONFIG_ARCH_PXA
2034 # ifdef SMC_USE_PXA_DMA
2035 lp->cfg.flags |= SMC91X_USE_DMA;
2037 if (lp->cfg.flags & SMC91X_USE_DMA) {
2038 int dma = pxa_request_dma(dev->name, DMA_PRIO_LOW,
2039 smc_pxa_dma_irq, NULL);
2045 retval = register_netdev(dev);
2047 /* now, print out the card info, in a short format.. */
2048 printk("%s: %s (rev %d) at %p IRQ %d",
2049 dev->name, version_string, revision_register & 0x0f,
2050 lp->base, dev->irq);
2052 if (dev->dma != (unsigned char)-1)
2053 printk(" DMA %d", dev->dma);
2056 lp->cfg.flags & SMC91X_NOWAIT ? " [nowait]" : "",
2057 THROTTLE_TX_PKTS ? " [throttle_tx]" : "");
2059 if (!is_valid_ether_addr(dev->dev_addr)) {
2060 printk("%s: Invalid ethernet MAC address. Please "
2061 "set using ifconfig\n", dev->name);
2063 /* Print the Ethernet address */
2064 printk("%s: Ethernet addr: %pM\n",
2065 dev->name, dev->dev_addr);
2068 if (lp->phy_type == 0) {
2069 PRINTK("%s: No PHY found\n", dev->name);
2070 } else if ((lp->phy_type & 0xfffffff0) == 0x0016f840) {
2071 PRINTK("%s: PHY LAN83C183 (LAN91C111 Internal)\n", dev->name);
2072 } else if ((lp->phy_type & 0xfffffff0) == 0x02821c50) {
2073 PRINTK("%s: PHY LAN83C180\n", dev->name);
2078 #ifdef CONFIG_ARCH_PXA
2079 if (retval && dev->dma != (unsigned char)-1)
2080 pxa_free_dma(dev->dma);
2085 static int smc_enable_device(struct platform_device *pdev)
2087 struct net_device *ndev = platform_get_drvdata(pdev);
2088 struct smc_local *lp = netdev_priv(ndev);
2089 unsigned long flags;
2090 unsigned char ecor, ecsr;
2092 struct resource * res;
2094 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2099 * Map the attribute space. This is overkill, but clean.
2101 addr = ioremap(res->start, ATTRIB_SIZE);
2106 * Reset the device. We must disable IRQs around this
2107 * since a reset causes the IRQ line become active.
2109 local_irq_save(flags);
2110 ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
2111 writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
2112 readb(addr + (ECOR << SMC_IO_SHIFT));
2115 * Wait 100us for the chip to reset.
2120 * The device will ignore all writes to the enable bit while
2121 * reset is asserted, even if the reset bit is cleared in the
2122 * same write. Must clear reset first, then enable the device.
2124 writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
2125 writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
2128 * Set the appropriate byte/word mode.
2130 ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
2133 writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
2134 local_irq_restore(flags);
2139 * Wait for the chip to wake up. We could poll the control
2140 * register in the main register space, but that isn't mapped
2141 * yet. We know this is going to take 750us.
2148 static int smc_request_attrib(struct platform_device *pdev,
2149 struct net_device *ndev)
2151 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2152 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2157 if (!request_mem_region(res->start, ATTRIB_SIZE, CARDNAME))
2163 static void smc_release_attrib(struct platform_device *pdev,
2164 struct net_device *ndev)
2166 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-attrib");
2167 struct smc_local *lp __maybe_unused = netdev_priv(ndev);
2170 release_mem_region(res->start, ATTRIB_SIZE);
2173 static inline void smc_request_datacs(struct platform_device *pdev, struct net_device *ndev)
2175 if (SMC_CAN_USE_DATACS) {
2176 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2177 struct smc_local *lp = netdev_priv(ndev);
2182 if(!request_mem_region(res->start, SMC_DATA_EXTENT, CARDNAME)) {
2183 printk(KERN_INFO "%s: failed to request datacs memory region.\n", CARDNAME);
2187 lp->datacs = ioremap(res->start, SMC_DATA_EXTENT);
2191 static void smc_release_datacs(struct platform_device *pdev, struct net_device *ndev)
2193 if (SMC_CAN_USE_DATACS) {
2194 struct smc_local *lp = netdev_priv(ndev);
2195 struct resource * res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-data32");
2198 iounmap(lp->datacs);
2203 release_mem_region(res->start, SMC_DATA_EXTENT);
2210 * dev->base_addr == 0, try to find all possible locations
2211 * dev->base_addr > 0x1ff, this is the address to check
2212 * dev->base_addr == <anything else>, return failure code
2215 * 0 --> there is a device
2216 * anything else, error
2218 static int __devinit smc_drv_probe(struct platform_device *pdev)
2220 struct smc91x_platdata *pd = pdev->dev.platform_data;
2221 struct smc_local *lp;
2222 struct net_device *ndev;
2223 struct resource *res, *ires;
2224 unsigned int __iomem *addr;
2225 unsigned long irq_flags = SMC_IRQ_FLAGS;
2228 ndev = alloc_etherdev(sizeof(struct smc_local));
2230 printk("%s: could not allocate device.\n", CARDNAME);
2234 SET_NETDEV_DEV(ndev, &pdev->dev);
2236 /* get configuration from platform data, only allow use of
2237 * bus width if both SMC_CAN_USE_xxx and SMC91X_USE_xxx are set.
2240 lp = netdev_priv(ndev);
2243 memcpy(&lp->cfg, pd, sizeof(lp->cfg));
2244 lp->io_shift = SMC91X_IO_SHIFT(lp->cfg.flags);
2246 lp->cfg.flags |= (SMC_CAN_USE_8BIT) ? SMC91X_USE_8BIT : 0;
2247 lp->cfg.flags |= (SMC_CAN_USE_16BIT) ? SMC91X_USE_16BIT : 0;
2248 lp->cfg.flags |= (SMC_CAN_USE_32BIT) ? SMC91X_USE_32BIT : 0;
2249 lp->cfg.flags |= (nowait) ? SMC91X_NOWAIT : 0;
2252 if (!lp->cfg.leda && !lp->cfg.ledb) {
2253 lp->cfg.leda = RPC_LSA_DEFAULT;
2254 lp->cfg.ledb = RPC_LSB_DEFAULT;
2257 ndev->dma = (unsigned char)-1;
2259 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2264 goto out_free_netdev;
2268 if (!request_mem_region(res->start, SMC_IO_EXTENT, CARDNAME)) {
2270 goto out_free_netdev;
2273 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2276 goto out_release_io;
2279 ndev->irq = ires->start;
2281 if (ires->flags & IRQF_TRIGGER_MASK)
2282 irq_flags = ires->flags & IRQF_TRIGGER_MASK;
2284 ret = smc_request_attrib(pdev, ndev);
2286 goto out_release_io;
2287 #if defined(CONFIG_SA1100_ASSABET)
2288 NCR_0 |= NCR_ENET_OSC_EN;
2290 platform_set_drvdata(pdev, ndev);
2291 ret = smc_enable_device(pdev);
2293 goto out_release_attrib;
2295 addr = ioremap(res->start, SMC_IO_EXTENT);
2298 goto out_release_attrib;
2301 #ifdef CONFIG_ARCH_PXA
2303 struct smc_local *lp = netdev_priv(ndev);
2304 lp->device = &pdev->dev;
2305 lp->physaddr = res->start;
2309 ret = smc_probe(ndev, addr, irq_flags);
2313 smc_request_datacs(pdev, ndev);
2318 platform_set_drvdata(pdev, NULL);
2321 smc_release_attrib(pdev, ndev);
2323 release_mem_region(res->start, SMC_IO_EXTENT);
2327 printk("%s: not found (%d).\n", CARDNAME, ret);
2332 static int __devexit smc_drv_remove(struct platform_device *pdev)
2334 struct net_device *ndev = platform_get_drvdata(pdev);
2335 struct smc_local *lp = netdev_priv(ndev);
2336 struct resource *res;
2338 platform_set_drvdata(pdev, NULL);
2340 unregister_netdev(ndev);
2342 free_irq(ndev->irq, ndev);
2344 #ifdef CONFIG_ARCH_PXA
2345 if (ndev->dma != (unsigned char)-1)
2346 pxa_free_dma(ndev->dma);
2350 smc_release_datacs(pdev,ndev);
2351 smc_release_attrib(pdev,ndev);
2353 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "smc91x-regs");
2355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2356 release_mem_region(res->start, SMC_IO_EXTENT);
2363 static int smc_drv_suspend(struct platform_device *dev, pm_message_t state)
2365 struct net_device *ndev = platform_get_drvdata(dev);
2368 if (netif_running(ndev)) {
2369 netif_device_detach(ndev);
2371 smc_phy_powerdown(ndev);
2377 static int smc_drv_resume(struct platform_device *dev)
2379 struct net_device *ndev = platform_get_drvdata(dev);
2382 struct smc_local *lp = netdev_priv(ndev);
2383 smc_enable_device(dev);
2384 if (netif_running(ndev)) {
2387 if (lp->phy_type != 0)
2388 smc_phy_configure(&lp->phy_configure);
2389 netif_device_attach(ndev);
2395 static struct platform_driver smc_driver = {
2396 .probe = smc_drv_probe,
2397 .remove = __devexit_p(smc_drv_remove),
2398 .suspend = smc_drv_suspend,
2399 .resume = smc_drv_resume,
2402 .owner = THIS_MODULE,
2406 static int __init smc_init(void)
2408 return platform_driver_register(&smc_driver);
2411 static void __exit smc_cleanup(void)
2413 platform_driver_unregister(&smc_driver);
2416 module_init(smc_init);
2417 module_exit(smc_cleanup);