git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_iba6110.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * This file contains all of the code that is specific to the InfiniPath
  36  * HT chip.
  37  */
  38
  39 #include <linux/vmalloc.h>
  40 #include <linux/pci.h>
  41 #include <linux/delay.h>
  42 #include <linux/htirq.h>
  43
  44 #include "ipath_kernel.h"
  45 #include "ipath_registers.h"
  46
  47 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
  48
  49
  50 /*
  51  * This lists the InfiniPath registers, in the actual chip layout.
  52  * This structure should never be directly accessed.
  53  *
  54  * The names are in InterCap form because they're taken straight from
  55  * the chip specification.  Since they're only used in this file, they
  56  * don't pollute the rest of the source.
  57 */
  58
  59 struct _infinipath_do_not_use_kernel_regs {
  60         unsigned long long Revision;
  61         unsigned long long Control;
  62         unsigned long long PageAlign;
  63         unsigned long long PortCnt;
  64         unsigned long long DebugPortSelect;
  65         unsigned long long DebugPort;
  66         unsigned long long SendRegBase;
  67         unsigned long long UserRegBase;
  68         unsigned long long CounterRegBase;
  69         unsigned long long Scratch;
  70         unsigned long long ReservedMisc1;
  71         unsigned long long InterruptConfig;
  72         unsigned long long IntBlocked;
  73         unsigned long long IntMask;
  74         unsigned long long IntStatus;
  75         unsigned long long IntClear;
  76         unsigned long long ErrorMask;
  77         unsigned long long ErrorStatus;
  78         unsigned long long ErrorClear;
  79         unsigned long long HwErrMask;
  80         unsigned long long HwErrStatus;
  81         unsigned long long HwErrClear;
  82         unsigned long long HwDiagCtrl;
  83         unsigned long long MDIO;
  84         unsigned long long IBCStatus;
  85         unsigned long long IBCCtrl;
  86         unsigned long long ExtStatus;
  87         unsigned long long ExtCtrl;
  88         unsigned long long GPIOOut;
  89         unsigned long long GPIOMask;
  90         unsigned long long GPIOStatus;
  91         unsigned long long GPIOClear;
  92         unsigned long long RcvCtrl;
  93         unsigned long long RcvBTHQP;
  94         unsigned long long RcvHdrSize;
  95         unsigned long long RcvHdrCnt;
  96         unsigned long long RcvHdrEntSize;
  97         unsigned long long RcvTIDBase;
  98         unsigned long long RcvTIDCnt;
  99         unsigned long long RcvEgrBase;
 100         unsigned long long RcvEgrCnt;
 101         unsigned long long RcvBufBase;
 102         unsigned long long RcvBufSize;
 103         unsigned long long RxIntMemBase;
 104         unsigned long long RxIntMemSize;
 105         unsigned long long RcvPartitionKey;
 106         unsigned long long ReservedRcv[10];
 107         unsigned long long SendCtrl;
 108         unsigned long long SendPIOBufBase;
 109         unsigned long long SendPIOSize;
 110         unsigned long long SendPIOBufCnt;
 111         unsigned long long SendPIOAvailAddr;
 112         unsigned long long TxIntMemBase;
 113         unsigned long long TxIntMemSize;
 114         unsigned long long ReservedSend[9];
 115         unsigned long long SendBufferError;
 116         unsigned long long SendBufferErrorCONT1;
 117         unsigned long long SendBufferErrorCONT2;
 118         unsigned long long SendBufferErrorCONT3;
 119         unsigned long long ReservedSBE[4];
 120         unsigned long long RcvHdrAddr0;
 121         unsigned long long RcvHdrAddr1;
 122         unsigned long long RcvHdrAddr2;
 123         unsigned long long RcvHdrAddr3;
 124         unsigned long long RcvHdrAddr4;
 125         unsigned long long RcvHdrAddr5;
 126         unsigned long long RcvHdrAddr6;
 127         unsigned long long RcvHdrAddr7;
 128         unsigned long long RcvHdrAddr8;
 129         unsigned long long ReservedRHA[7];
 130         unsigned long long RcvHdrTailAddr0;
 131         unsigned long long RcvHdrTailAddr1;
 132         unsigned long long RcvHdrTailAddr2;
 133         unsigned long long RcvHdrTailAddr3;
 134         unsigned long long RcvHdrTailAddr4;
 135         unsigned long long RcvHdrTailAddr5;
 136         unsigned long long RcvHdrTailAddr6;
 137         unsigned long long RcvHdrTailAddr7;
 138         unsigned long long RcvHdrTailAddr8;
 139         unsigned long long ReservedRHTA[7];
 140         unsigned long long Sync;        /* Software only */
 141         unsigned long long Dump;        /* Software only */
 142         unsigned long long SimVer;      /* Software only */
 143         unsigned long long ReservedSW[5];
 144         unsigned long long SerdesConfig0;
 145         unsigned long long SerdesConfig1;
 146         unsigned long long SerdesStatus;
 147         unsigned long long XGXSConfig;
 148         unsigned long long ReservedSW2[4];
 149 };
 150
 151 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 152     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 153 #define IPATH_CREG_OFFSET(field) (offsetof( \
 154     struct infinipath_counters, field) / sizeof(u64))
 155
 156 static const struct ipath_kregs ipath_ht_kregs = {
 157         .kr_control = IPATH_KREG_OFFSET(Control),
 158         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 159         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 160         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 161         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 162         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 163         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 164         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 165         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 166         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 167         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 168         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 169         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 170         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 171         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 172         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 173         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 174         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 175         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 176         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 177         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 178         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 179         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 180         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 181         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 182         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 183         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 184         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 185         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 186         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 187         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 188         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 189         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 190         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 191         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 192         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 193         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 194         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 195         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 196         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 197         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 198         .kr_revision = IPATH_KREG_OFFSET(Revision),
 199         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 200         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 201         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 202         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 203         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 204         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 205         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 206         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 207         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 208         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 209         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 210         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 211         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 212         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 213         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 214         /*
 215          * These should not be used directly via ipath_write_kreg64(),
 216          * use them with ipath_write_kreg64_port(),
 217          */
 218         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 219         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 220 };
 221
 222 static const struct ipath_cregs ipath_ht_cregs = {
 223         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 224         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 225         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 226         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 227         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 228         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 229         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 230         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 231         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 232         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 233         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 234         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 235         /* calc from Reg_CounterRegBase + offset */
 236         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 237         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 238         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 239         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 240         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 241         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 242         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 243         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 244         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 245         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 246         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 247         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 248         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 249         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 250         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 251         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 252         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 253         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 254         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 255         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 256         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 257 };
 258
 259 /* kr_intstatus, kr_intclear, kr_intmask bits */
 260 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
 261 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
 262
 263 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 264 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 265 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 266 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 267 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 268 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 269 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 270 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 271 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 272 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 273 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 274 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 275 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 276 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 277 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 278 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 279 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 280 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 281 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 282 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 283 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 284
 285 /* kr_extstatus bits */
 286 #define INFINIPATH_EXTS_FREQSEL 0x2
 287 #define INFINIPATH_EXTS_SERDESSEL 0x4
 288 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 289 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 290
 291
 292 /* TID entries (memory), HT-only */
 293 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
 294 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
 295 #define INFINIPATH_RT_ADDR_SHIFT 0
 296 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
 297 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
 298
 299 /*
 300  * masks and bits that are different in different chips, or present only
 301  * in one
 302  */
 303 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 304     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 305 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 306     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 307
 308 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 309     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 310 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 311     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 312 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 313     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 314 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 315     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 316
 317 #define _IPATH_GPIO_SDA_NUM 1
 318 #define _IPATH_GPIO_SCL_NUM 0
 319
 320 #define IPATH_GPIO_SDA \
 321         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 322 #define IPATH_GPIO_SCL \
 323         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 324
 325 /* keep the code below somewhat more readonable; not used elsewhere */
 326 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 327                                 infinipath_hwe_htclnkabyte1crcerr)
 328 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 329                                 infinipath_hwe_htclnkbbyte1crcerr)
 330 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 331                                 infinipath_hwe_htclnkbbyte0crcerr)
 332 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 333                                 infinipath_hwe_htclnkbbyte1crcerr)
 334
 335 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 336                           char *msg, size_t msgl)
 337 {
 338         char bitsmsg[64];
 339         ipath_err_t crcbits = hwerrs &
 340                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 341         /* don't check if 8bit HT */
 342         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 343                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 344         /* don't check if 8bit HT */
 345         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 346                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 347         /*
 348          * we'll want to ignore link errors on link that is
 349          * not in use, if any.  For now, complain about both
 350          */
 351         if (crcbits) {
 352                 u16 ctrl0, ctrl1;
 353                 snprintf(bitsmsg, sizeof bitsmsg,
 354                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
 355                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 356                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 357                                     ? "1 (B)" : "0+1 (A+B)"),
 358                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 359                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 360                             "0+1"), (unsigned long long) crcbits);
 361                 strlcat(msg, bitsmsg, msgl);
 362
 363                 /*
 364                  * print extra info for debugging.  slave/primary
 365                  * config word 4, 8 (link control 0, 1)
 366                  */
 367
 368                 if (pci_read_config_word(dd->pcidev,
 369                                          dd->ipath_ht_slave_off + 0x4,
 370                                          &ctrl0))
 371                         dev_info(&dd->pcidev->dev, "Couldn't read "
 372                                  "linkctrl0 of slave/primary "
 373                                  "config block\n");
 374                 else if (!(ctrl0 & 1 << 6))
 375                         /* not if EOC bit set */
 376                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 377                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 378                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 379                                   "");
 380                 if (pci_read_config_word(dd->pcidev,
 381                                          dd->ipath_ht_slave_off + 0x8,
 382                                          &ctrl1))
 383                         dev_info(&dd->pcidev->dev, "Couldn't read "
 384                                  "linkctrl1 of slave/primary "
 385                                  "config block\n");
 386                 else if (!(ctrl1 & 1 << 6))
 387                         /* not if EOC bit set */
 388                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 389                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 390                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 391                                   "");
 392
 393                 /* disable until driver reloaded */
 394                 dd->ipath_hwerrmask &= ~crcbits;
 395                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 396                                  dd->ipath_hwerrmask);
 397                 ipath_dbg("HT crc errs: %s\n", msg);
 398         } else
 399                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 400                           "not in use\n", (unsigned long long)
 401                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 402                                      _IPATH_HTLINK1_CRCBITS)));
 403 }
 404
 405 /* 6110 specific hardware errors... */
 406 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
 407         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
 408         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
 409         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
 410         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
 411         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
 412         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
 413         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 414         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 415 };
 416
 417 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 418                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 419                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 420 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
 421                           << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
 422
 423 static int ipath_ht_txe_recover(struct ipath_devdata *);
 424
 425 /**
 426  * ipath_ht_handle_hwerrors - display hardware errors.
 427  * @dd: the infinipath device
 428  * @msg: the output buffer
 429  * @msgl: the size of the output buffer
 430  *
 431  * Use same msg buffer as regular errors to avoid excessive stack
 432  * use.  Most hardware errors are catastrophic, but for right now,
 433  * we'll print them and continue.  We reuse the same message buffer as
 434  * ipath_handle_errors() to avoid excessive stack usage.
 435  */
 436 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 437                                      size_t msgl)
 438 {
 439         ipath_err_t hwerrs;
 440         u32 bits, ctrl;
 441         int isfatal = 0;
 442         char bitsmsg[64];
 443         int log_idx;
 444
 445         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 446
 447         if (!hwerrs) {
 448                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 449                 /*
 450                  * better than printing cofusing messages
 451                  * This seems to be related to clearing the crc error, or
 452                  * the pll error during init.
 453                  */
 454                 goto bail;
 455         } else if (hwerrs == -1LL) {
 456                 ipath_dev_err(dd, "Read of hardware error status failed "
 457                               "(all bits set); ignoring\n");
 458                 goto bail;
 459         }
 460         ipath_stats.sps_hwerrs++;
 461
 462         /* Always clear the error status register, except MEMBISTFAIL,
 463          * regardless of whether we continue or stop using the chip.
 464          * We want that set so we know it failed, even across driver reload.
 465          * We'll still ignore it in the hwerrmask.  We do this partly for
 466          * diagnostics, but also for support */
 467         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 468                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 469
 470         hwerrs &= dd->ipath_hwerrmask;
 471
 472         /* We log some errors to EEPROM, check if we have any of those. */
 473         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 474                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 475                         ipath_inc_eeprom_err(dd, log_idx, 1);
 476
 477         /*
 478          * make sure we get this much out, unless told to be quiet,
 479          * it's a parity error we may recover from,
 480          * or it's occurred within the last 5 seconds
 481          */
 482         if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
 483                 RXE_EAGER_PARITY)) ||
 484                 (ipath_debug & __IPATH_VERBDBG))
 485                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 486                          "(cleared)\n", (unsigned long long) hwerrs);
 487         dd->ipath_lasthwerror |= hwerrs;
 488
 489         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 490                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 491                               "%llx set\n", (unsigned long long)
 492                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 493
 494         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 495         if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
 496                 /*
 497                  * parity errors in send memory are recoverable,
 498                  * just cancel the send (if indicated in * sendbuffererror),
 499                  * count the occurrence, unfreeze (if no other handled
 500                  * hardware error bits are set), and continue. They can
 501                  * occur if a processor speculative read is done to the PIO
 502                  * buffer while we are sending a packet, for example.
 503                  */
 504                 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
 505                         hwerrs &= ~TXE_PIO_PARITY;
 506                 if (hwerrs & RXE_EAGER_PARITY)
 507                         ipath_dev_err(dd, "RXE parity, Eager TID error is not "
 508                                 "recoverable\n");
 509                 if (!hwerrs) {
 510                         ipath_dbg("Clearing freezemode on ignored or "
 511                                   "recovered hardware error\n");
 512                         ipath_clear_freeze(dd);
 513                 }
 514         }
 515
 516         *msg = '\0';
 517
 518         /*
 519          * may someday want to decode into which bits are which
 520          * functional area for parity errors, etc.
 521          */
 522         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 523                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 524                 bits = (u32) ((hwerrs >>
 525                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 526                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 527                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 528                          bits);
 529                 strlcat(msg, bitsmsg, msgl);
 530         }
 531
 532         ipath_format_hwerrors(hwerrs,
 533                               ipath_6110_hwerror_msgs,
 534                               sizeof(ipath_6110_hwerror_msgs) /
 535                               sizeof(ipath_6110_hwerror_msgs[0]),
 536                               msg, msgl);
 537
 538         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 539                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 540
 541         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 542                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 543                         msgl);
 544                 /* ignore from now on, so disable until driver reloaded */
 545                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 546                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 547                                  dd->ipath_hwerrmask);
 548         }
 549 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 550                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 551                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 552                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 553                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 554                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 555
 556         if (hwerrs & _IPATH_PLL_FAIL) {
 557                 snprintf(bitsmsg, sizeof bitsmsg,
 558                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 559                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 560                 strlcat(msg, bitsmsg, msgl);
 561                 /* ignore from now on, so disable until driver reloaded */
 562                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 563                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 564                                  dd->ipath_hwerrmask);
 565         }
 566
 567         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 568                 /*
 569                  * If it occurs, it is left masked since the eternal
 570                  * interface is unused
 571                  */
 572                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 573                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 574                                  dd->ipath_hwerrmask);
 575         }
 576
 577         if (hwerrs) {
 578                 /*
 579                  * if any set that we aren't ignoring; only
 580                  * make the complaint once, in case it's stuck
 581                  * or recurring, and we get here multiple
 582                  * times.
 583                  * force link down, so switch knows, and
 584                  * LEDs are turned off
 585                  */
 586                 if (dd->ipath_flags & IPATH_INITTED) {
 587                         ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 588                         ipath_setup_ht_setextled(dd,
 589                                 INFINIPATH_IBCS_L_STATE_DOWN,
 590                                 INFINIPATH_IBCS_LT_STATE_DISABLED);
 591                         ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 592                                           "mode), no longer usable, SN %.16s\n",
 593                                           dd->ipath_serial);
 594                         isfatal = 1;
 595                 }
 596                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 597                 /* mark as having had error */
 598                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 599                 /*
 600                  * mark as not usable, at a minimum until driver
 601                  * is reloaded, probably until reboot, since no
 602                  * other reset is possible.
 603                  */
 604                 dd->ipath_flags &= ~IPATH_INITTED;
 605         }
 606         else
 607                 *msg = 0; /* recovered from all of them */
 608         if (*msg)
 609                 ipath_dev_err(dd, "%s hardware error\n", msg);
 610         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 611                 /*
 612                  * for status file; if no trailing brace is copied,
 613                  * we'll know it was truncated.
 614                  */
 615                 snprintf(dd->ipath_freezemsg,
 616                          dd->ipath_freezelen, "{%s}", msg);
 617
 618 bail:;
 619 }
 620
 621 /**
 622  * ipath_ht_boardname - fill in the board name
 623  * @dd: the infinipath device
 624  * @name: the output buffer
 625  * @namelen: the size of the output buffer
 626  *
 627  * fill in the board name, based on the board revision register
 628  */
 629 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 630                               size_t namelen)
 631 {
 632         char *n = NULL;
 633         u8 boardrev = dd->ipath_boardrev;
 634         int ret = 0;
 635
 636         switch (boardrev) {
 637         case 5:
 638                 /*
 639                  * original production board; two production levels, with
 640                  * different serial number ranges.   See ipath_ht_early_init() for
 641                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 642                  * Original 112* serial number is no longer supported.
 643                  */
 644                 n = "InfiniPath_QHT7040";
 645                 break;
 646         case 7:
 647                 /* small form factor production board */
 648                 n = "InfiniPath_QHT7140";
 649                 break;
 650         default:                /* don't know, just print the number */
 651                 ipath_dev_err(dd, "Don't yet know about board "
 652                               "with ID %u\n", boardrev);
 653                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
 654                          boardrev);
 655                 ret = 1;
 656                 break;
 657         }
 658         if (n)
 659                 snprintf(name, namelen, "%s", n);
 660
 661         if (ret) {
 662                 ipath_dev_err(dd, "Unsupported InfiniPath board %s!\n", name);
 663                 goto bail;
 664         }
 665         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
 666                 dd->ipath_minrev > 4)) {
 667                 /*
 668                  * This version of the driver only supports Rev 3.2 - 3.4
 669                  */
 670                 ipath_dev_err(dd,
 671                               "Unsupported InfiniPath hardware revision %u.%u!\n",
 672                               dd->ipath_majrev, dd->ipath_minrev);
 673                 ret = 1;
 674                 goto bail;
 675         }
 676         /*
 677          * pkt/word counters are 32 bit, and therefore wrap fast enough
 678          * that we snapshot them from a timer, and maintain 64 bit shadow
 679          * copies
 680          */
 681         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 682         dd->ipath_flags |= IPATH_GPIO_INTR;
 683         if (dd->ipath_htspeed != 800)
 684                 ipath_dev_err(dd,
 685                               "Incorrectly configured for HT @ %uMHz\n",
 686                               dd->ipath_htspeed);
 687         ret = 0;
 688
 689 bail:
 690         return ret;
 691 }
 692
 693 static void ipath_check_htlink(struct ipath_devdata *dd)
 694 {
 695         u8 linkerr, link_off, i;
 696
 697         for (i = 0; i < 2; i++) {
 698                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 699                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 700                         dev_info(&dd->pcidev->dev, "Couldn't read "
 701                                  "linkerror%d of HT slave/primary block\n",
 702                                  i);
 703                 else if (linkerr & 0xf0) {
 704                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 705                                    "clearing\n", linkerr >> 4, i);
 706                         /*
 707                          * writing the linkerr bits that are set should
 708                          * clear them
 709                          */
 710                         if (pci_write_config_byte(dd->pcidev, link_off,
 711                                                   linkerr))
 712                                 ipath_dbg("Failed write to clear HT "
 713                                           "linkerror%d\n", i);
 714                         if (pci_read_config_byte(dd->pcidev, link_off,
 715                                                  &linkerr))
 716                                 dev_info(&dd->pcidev->dev,
 717                                          "Couldn't reread linkerror%d of "
 718                                          "HT slave/primary block\n", i);
 719                         else if (linkerr & 0xf0)
 720                                 dev_info(&dd->pcidev->dev,
 721                                          "HT linkerror%d bits 0x%x "
 722                                          "couldn't be cleared\n",
 723                                          i, linkerr >> 4);
 724                 }
 725         }
 726 }
 727
 728 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 729 {
 730         ipath_dbg("No reset possible for this InfiniPath hardware\n");
 731         return 0;
 732 }
 733
 734 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 735 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 736
 737 /*
 738  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 739  * errors.  We only bother to do this at load time, because it's OK if
 740  * it happened before we were loaded (first time after boot/reset),
 741  * but any time after that, it's fatal anyway.  Also need to not check
 742  * for for upper byte errors if we are in 8 bit mode, so figure out
 743  * our width.  For now, at least, also complain if it's 8 bit.
 744  */
 745 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 746                              int pos, u8 cap_type)
 747 {
 748         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 749         u16 linkctrl = 0;
 750         int i;
 751
 752         dd->ipath_ht_slave_off = pos;
 753         /* command word, master_host bit */
 754         /* master host || slave */
 755         if ((cap_type >> 2) & 1)
 756                 link_a_b_off = 4;
 757         else
 758                 link_a_b_off = 0;
 759         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 760                    link_a_b_off ? 1 : 0,
 761                    link_a_b_off ? 'B' : 'A');
 762
 763         link_a_b_off += pos;
 764
 765         /*
 766          * check both link control registers; clear both HT CRC sets if
 767          * necessary.
 768          */
 769         for (i = 0; i < 2; i++) {
 770                 link_off = pos + i * 4 + 0x4;
 771                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 772                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 773                                       "register\n", i);
 774                 else if (linkctrl & (0xf << 8)) {
 775                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 776                                    "bits %x\n", i, linkctrl & (0xf << 8));
 777                         /*
 778                          * now write them back to clear the error.
 779                          */
 780                         pci_write_config_byte(pdev, link_off,
 781                                               linkctrl & (0xf << 8));
 782                 }
 783         }
 784
 785         /*
 786          * As with HT CRC bits, same for protocol errors that might occur
 787          * during boot.
 788          */
 789         for (i = 0; i < 2; i++) {
 790                 link_off = pos + i * 4 + 0xd;
 791                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 792                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 793                                  "of HT slave/primary block\n", i);
 794                 else if (linkerr & 0xf0) {
 795                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 796                                    "clearing\n", linkerr >> 4, i);
 797                         /*
 798                          * writing the linkerr bits that are set will clear
 799                          * them
 800                          */
 801                         if (pci_write_config_byte
 802                             (pdev, link_off, linkerr))
 803                                 ipath_dbg("Failed write to clear HT "
 804                                           "linkerror%d\n", i);
 805                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 806                                 dev_info(&pdev->dev, "Couldn't reread "
 807                                          "linkerror%d of HT slave/primary "
 808                                          "block\n", i);
 809                         else if (linkerr & 0xf0)
 810                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 811                                          "0x%x couldn't be cleared\n",
 812                                          i, linkerr >> 4);
 813                 }
 814         }
 815
 816         /*
 817          * this is just for our link to the host, not devices connected
 818          * through tunnel.
 819          */
 820
 821         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 822                 ipath_dev_err(dd, "Couldn't read HT link width "
 823                               "config register\n");
 824         else {
 825                 u32 width;
 826                 switch (linkwidth & 7) {
 827                 case 5:
 828                         width = 4;
 829                         break;
 830                 case 4:
 831                         width = 2;
 832                         break;
 833                 case 3:
 834                         width = 32;
 835                         break;
 836                 case 1:
 837                         width = 16;
 838                         break;
 839                 case 0:
 840                 default:        /* if wrong, assume 8 bit */
 841                         width = 8;
 842                         break;
 843                 }
 844
 845                 dd->ipath_htwidth = width;
 846
 847                 if (linkwidth != 0x11) {
 848                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 849                                       "(%x)\n", linkwidth);
 850                         if (!(linkwidth & 0xf)) {
 851                                 ipath_dbg("Will ignore HT lane1 errors\n");
 852                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 853                         }
 854                 }
 855         }
 856
 857         /*
 858          * this is just for our link to the host, not devices connected
 859          * through tunnel.
 860          */
 861         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 862                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 863                               "config register\n");
 864         else {
 865                 u32 speed;
 866                 switch (linkwidth & 0xf) {
 867                 case 6:
 868                         speed = 1000;
 869                         break;
 870                 case 5:
 871                         speed = 800;
 872                         break;
 873                 case 4:
 874                         speed = 600;
 875                         break;
 876                 case 3:
 877                         speed = 500;
 878                         break;
 879                 case 2:
 880                         speed = 400;
 881                         break;
 882                 case 1:
 883                         speed = 300;
 884                         break;
 885                 default:
 886                         /*
 887                          * assume reserved and vendor-specific are 200...
 888                          */
 889                 case 0:
 890                         speed = 200;
 891                         break;
 892                 }
 893                 dd->ipath_htspeed = speed;
 894         }
 895 }
 896
 897 static int ipath_ht_intconfig(struct ipath_devdata *dd)
 898 {
 899         int ret;
 900
 901         if (dd->ipath_intconfig) {
 902                 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
 903                                  dd->ipath_intconfig);  /* interrupt address */
 904                 ret = 0;
 905         } else {
 906                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
 907                               "interrupt address\n");
 908                 ret = -EINVAL;
 909         }
 910
 911         return ret;
 912 }
 913
 914 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
 915                                 struct ht_irq_msg *msg)
 916 {
 917         struct ipath_devdata *dd = pci_get_drvdata(dev);
 918         u64 prev_intconfig = dd->ipath_intconfig;
 919
 920         dd->ipath_intconfig = msg->address_lo;
 921         dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
 922
 923         /*
 924          * If the previous value of dd->ipath_intconfig is zero, we're
 925          * getting configured for the first time, and must not program the
 926          * intconfig register here (it will be programmed later, when the
 927          * hardware is ready).  Otherwise, we should.
 928          */
 929         if (prev_intconfig)
 930                 ipath_ht_intconfig(dd);
 931 }
 932
 933 /**
 934  * ipath_setup_ht_config - setup the interruptconfig register
 935  * @dd: the infinipath device
 936  * @pdev: the PCI device
 937  *
 938  * setup the interruptconfig register from the HT config info.
 939  * Also clear CRC errors in HT linkcontrol, if necessary.
 940  * This is done only for the real hardware.  It is done before
 941  * chip address space is initted, so can't touch infinipath registers
 942  */
 943 static int ipath_setup_ht_config(struct ipath_devdata *dd,
 944                                  struct pci_dev *pdev)
 945 {
 946         int pos, ret;
 947
 948         ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
 949         if (ret < 0) {
 950                 ipath_dev_err(dd, "Couldn't create interrupt handler: "
 951                               "err %d\n", ret);
 952                 goto bail;
 953         }
 954         dd->ipath_irq = ret;
 955         ret = 0;
 956
 957         /*
 958          * Handle clearing CRC errors in linkctrl register if necessary.  We
 959          * do this early, before we ever enable errors or hardware errors,
 960          * mostly to avoid causing the chip to enter freeze mode.
 961          */
 962         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
 963         if (!pos) {
 964                 ipath_dev_err(dd, "Couldn't find HyperTransport "
 965                               "capability; no interrupts\n");
 966                 ret = -ENODEV;
 967                 goto bail;
 968         }
 969         do {
 970                 u8 cap_type;
 971
 972                 /* the HT capability type byte is 3 bytes after the
 973                  * capability byte.
 974                  */
 975                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
 976                         dev_info(&pdev->dev, "Couldn't read config "
 977                                  "command @ %d\n", pos);
 978                         continue;
 979                 }
 980                 if (!(cap_type & 0xE0))
 981                         slave_or_pri_blk(dd, pdev, pos, cap_type);
 982         } while ((pos = pci_find_next_capability(pdev, pos,
 983                                                  PCI_CAP_ID_HT)));
 984
 985 bail:
 986         return ret;
 987 }
 988
 989 /**
 990  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
 991  * @dd: the infinipath device
 992  *
 993  * Called during driver unload.
 994  * This is currently a nop for the HT chip, not for all chips
 995  */
 996 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
 997 {
 998 }
 999
1000 /**
1001  * ipath_setup_ht_setextled - set the state of the two external LEDs
1002  * @dd: the infinipath device
1003  * @lst: the L state
1004  * @ltst: the LT state
1005  *
1006  * Set the state of the two external LEDs, to indicate physical and
1007  * logical state of IB link.   For this chip (at least with recommended
1008  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1009  * (logical state)
1010  *
1011  * Note:  We try to match the Mellanox HCA LED behavior as best
1012  * we can.  Green indicates physical link state is OK (something is
1013  * plugged in, and we can train).
1014  * Amber indicates the link is logically up (ACTIVE).
1015  * Mellanox further blinks the amber LED to indicate data packet
1016  * activity, but we have no hardware support for that, so it would
1017  * require waking up every 10-20 msecs and checking the counters
1018  * on the chip, and then turning the LED off if appropriate.  That's
1019  * visible overhead, so not something we will do.
1020  *
1021  */
1022 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1023                                      u64 lst, u64 ltst)
1024 {
1025         u64 extctl;
1026         unsigned long flags = 0;
1027
1028         /* the diags use the LED to indicate diag info, so we leave
1029          * the external LED alone when the diags are running */
1030         if (ipath_diag_inuse)
1031                 return;
1032
1033         /* Allow override of LED display for, e.g. Locating system in rack */
1034         if (dd->ipath_led_override) {
1035                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1036                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
1037                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
1038                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1039                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
1040                         : INFINIPATH_IBCS_L_STATE_DOWN;
1041         }
1042
1043         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1044         /*
1045          * start by setting both LED control bits to off, then turn
1046          * on the appropriate bit(s).
1047          */
1048         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1049                 /*
1050                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1051                  * is inverted,  because it is normally used to indicate
1052                  * a hardware fault at reset, if there were errors
1053                  */
1054                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1055                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1056                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1057                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1058                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1059                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1060         }
1061         else {
1062                 extctl = dd->ipath_extctrl &
1063                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1064                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1065                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1066                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1067                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1068                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1069         }
1070         dd->ipath_extctrl = extctl;
1071         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1072         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1073 }
1074
1075 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1076 {
1077         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1078         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1079         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1080         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1081
1082         dd->ipath_i_bitsextant =
1083                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1084                 (INFINIPATH_I_RCVAVAIL_MASK <<
1085                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1086                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1087                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1088
1089         dd->ipath_e_bitsextant =
1090                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1091                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1092                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1093                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1094                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1095                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1096                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1097                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1098                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1099                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1100                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1101                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1102                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1103                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1104                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1105                 INFINIPATH_E_HARDWARE;
1106
1107         dd->ipath_hwe_bitsextant =
1108                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1109                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1110                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1111                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1112                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1113                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1114                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1115                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1116                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1117                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1118                 INFINIPATH_HWE_HTCMISCERR4 |
1119                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1120                 INFINIPATH_HWE_HTCMISCERR7 |
1121                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1122                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1123                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1124                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1125                 INFINIPATH_HWE_MEMBISTFAILED |
1126                 INFINIPATH_HWE_COREPLL_FBSLIP |
1127                 INFINIPATH_HWE_COREPLL_RFSLIP |
1128                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1129                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1130                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1131                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1132                 INFINIPATH_HWE_SERDESPLLFAILED |
1133                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1134                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1135
1136         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1137         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1138
1139         /*
1140          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1141          * 2 is Some Misc, 3 is reserved for future.
1142          */
1143         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1144                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1145                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1146
1147         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1148                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1149                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1150
1151         dd->ipath_eep_st_masks[2].errs_to_log =
1152                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1153
1154 }
1155
1156 /**
1157  * ipath_ht_init_hwerrors - enable hardware errors
1158  * @dd: the infinipath device
1159  *
1160  * now that we have finished initializing everything that might reasonably
1161  * cause a hardware error, and cleared those errors bits as they occur,
1162  * we can enable hardware errors in the mask (potentially enabling
1163  * freeze mode), and enable hardware errors as errors (along with
1164  * everything else) in errormask
1165  */
1166 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1167 {
1168         ipath_err_t val;
1169         u64 extsval;
1170
1171         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1172
1173         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1174                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1175         if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1176                 ipath_dbg("MemBIST corrected\n");
1177
1178         ipath_check_htlink(dd);
1179
1180         /* barring bugs, all hwerrors become interrupts, which can */
1181         val = -1LL;
1182         /* don't look at crc lane1 if 8 bit */
1183         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1184                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1185         /* don't look at crc lane1 if 8 bit */
1186         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1187                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1188
1189         /*
1190          * disable RXDSYNCMEMPARITY because external serdes is unused,
1191          * and therefore the logic will never be used or initialized,
1192          * and uninitialized state will normally result in this error
1193          * being asserted.  Similarly for the external serdess pll
1194          * lock signal.
1195          */
1196         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1197                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1198
1199         /*
1200          * Disable MISCERR4 because of an inversion in the HT core
1201          * logic checking for errors that cause this bit to be set.
1202          * The errata can also cause the protocol error bit to be set
1203          * in the HT config space linkerror register(s).
1204          */
1205         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1206
1207         /*
1208          * PLL ignored because MDIO interface has a logic problem
1209          * for reads, on Comstock and Ponderosa.  BRINGUP
1210          */
1211         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1212                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1213         dd->ipath_hwerrmask = val;
1214 }
1215
1216 /**
1217  * ipath_ht_bringup_serdes - bring up the serdes
1218  * @dd: the infinipath device
1219  */
1220 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1221 {
1222         u64 val, config1;
1223         int ret = 0, change = 0;
1224
1225         ipath_dbg("Trying to bringup serdes\n");
1226
1227         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1228             INFINIPATH_HWE_SERDESPLLFAILED)
1229         {
1230                 ipath_dbg("At start, serdes PLL failed bit set in "
1231                           "hwerrstatus, clearing and continuing\n");
1232                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1233                                  INFINIPATH_HWE_SERDESPLLFAILED);
1234         }
1235
1236         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1237         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1238
1239         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1240                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1241                    (unsigned long long) val, (unsigned long long) config1,
1242                    (unsigned long long)
1243                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1244                    (unsigned long long)
1245                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1246
1247         /* force reset on */
1248         val |= INFINIPATH_SERDC0_RESET_PLL
1249                 /* | INFINIPATH_SERDC0_RESET_MASK */
1250                 ;
1251         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1252         udelay(15);             /* need pll reset set at least for a bit */
1253
1254         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1255                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1256                 /* set lane resets, and tx idle, during pll reset */
1257                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1258                         INFINIPATH_SERDC0_TXIDLE;
1259                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1260                            "%llx)\n", (unsigned long long) val2);
1261                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1262                                  val2);
1263                 /*
1264                  * be sure chip saw it
1265                  */
1266                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1267                 /*
1268                  * need pll reset clear at least 11 usec before lane
1269                  * resets cleared; give it a few more
1270                  */
1271                 udelay(15);
1272                 val = val2;     /* for check below */
1273         }
1274
1275         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1276                    INFINIPATH_SERDC0_RESET_MASK |
1277                    INFINIPATH_SERDC0_TXIDLE)) {
1278                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1279                          INFINIPATH_SERDC0_RESET_MASK |
1280                          INFINIPATH_SERDC0_TXIDLE);
1281                 /* clear them */
1282                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1283                                  val);
1284         }
1285
1286         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1287         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1288              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1289                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1290                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1291                 /*
1292                  * we use address 3
1293                  */
1294                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1295                 change = 1;
1296         }
1297         if (val & INFINIPATH_XGXS_RESET) {
1298                 /* normally true after boot */
1299                 val &= ~INFINIPATH_XGXS_RESET;
1300                 change = 1;
1301         }
1302         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1303              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1304                 /* need to compensate for Tx inversion in partner */
1305                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1306                          INFINIPATH_XGXS_RX_POL_SHIFT);
1307                 val |= dd->ipath_rx_pol_inv <<
1308                         INFINIPATH_XGXS_RX_POL_SHIFT;
1309                 change = 1;
1310         }
1311         if (change)
1312                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1313
1314         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1315
1316         /* clear current and de-emphasis bits */
1317         config1 &= ~0x0ffffffff00ULL;
1318         /* set current to 20ma */
1319         config1 |= 0x00000000000ULL;
1320         /* set de-emphasis to -5.68dB */
1321         config1 |= 0x0cccc000000ULL;
1322         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1323
1324         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1325                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1326                    (unsigned long long) val, (unsigned long long) config1,
1327                    (unsigned long long)
1328                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1329                    (unsigned long long)
1330                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1331
1332         if (!ipath_waitfor_mdio_cmdready(dd)) {
1333                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1334                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1335                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1336                                                 0));
1337                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1338                                            IPATH_MDIO_DATAVALID, &val))
1339                         ipath_dbg("Never got MDIO data for XGXS status "
1340                                   "read\n");
1341                 else
1342                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1343                                    "'bank' 31 %x\n", (u32) val);
1344         } else
1345                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1346
1347         return ret;             /* for now, say we always succeeded */
1348 }
1349
1350 /**
1351  * ipath_ht_quiet_serdes - set serdes to txidle
1352  * @dd: the infinipath device
1353  * driver is being unloaded
1354  */
1355 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1356 {
1357         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1358
1359         val |= INFINIPATH_SERDC0_TXIDLE;
1360         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1361                   (unsigned long long) val);
1362         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1363 }
1364
1365 /**
1366  * ipath_pe_put_tid - write a TID in chip
1367  * @dd: the infinipath device
1368  * @tidptr: pointer to the expected TID (in chip) to udpate
1369  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1370  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1371  *
1372  * This exists as a separate routine to allow for special locking etc.
1373  * It's used for both the full cleanup on exit, as well as the normal
1374  * setup and teardown.
1375  */
1376 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1377                              u64 __iomem *tidptr, u32 type,
1378                              unsigned long pa)
1379 {
1380         if (!dd->ipath_kregbase)
1381                 return;
1382
1383         if (pa != dd->ipath_tidinvalid) {
1384                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1385                         dev_info(&dd->pcidev->dev,
1386                                  "physaddr %lx has more than "
1387                                  "40 bits, using only 40!!!\n", pa);
1388                         pa &= INFINIPATH_RT_ADDR_MASK;
1389                 }
1390                 if (type == RCVHQ_RCV_TYPE_EAGER)
1391                         pa |= dd->ipath_tidtemplate;
1392                 else {
1393                         /* in words (fixed, full page).  */
1394                         u64 lenvalid = PAGE_SIZE >> 2;
1395                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1396                         pa |= lenvalid | INFINIPATH_RT_VALID;
1397                 }
1398         }
1399         writeq(pa, tidptr);
1400 }
1401
1402
1403 /**
1404  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1405  * @dd: the infinipath device
1406  * @port: the port
1407  *
1408  * Used from ipath_close(), and at chip initialization.
1409  */
1410 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1411 {
1412         u64 __iomem *tidbase;
1413         int i;
1414
1415         if (!dd->ipath_kregbase)
1416                 return;
1417
1418         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1419
1420         /*
1421          * need to invalidate all of the expected TID entries for this
1422          * port, so we don't have valid entries that might somehow get
1423          * used (early in next use of this port, or through some bug)
1424          */
1425         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1426                                    dd->ipath_rcvtidbase +
1427                                    port * dd->ipath_rcvtidcnt *
1428                                    sizeof(*tidbase));
1429         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1430                 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1431                                  dd->ipath_tidinvalid);
1432
1433         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1434                                    dd->ipath_rcvegrbase +
1435                                    port * dd->ipath_rcvegrcnt *
1436                                    sizeof(*tidbase));
1437
1438         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1439                 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1440                                  dd->ipath_tidinvalid);
1441 }
1442
1443 /**
1444  * ipath_ht_tidtemplate - setup constants for TID updates
1445  * @dd: the infinipath device
1446  *
1447  * We setup stuff that we use a lot, to avoid calculating each time
1448  */
1449 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1450 {
1451         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1452         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1453         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1454
1455         /*
1456          * work around chip errata bug 7358, by marking invalid tids
1457          * as having max length
1458          */
1459         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1460                 INFINIPATH_RT_BUFSIZE_SHIFT;
1461 }
1462
1463 static int ipath_ht_early_init(struct ipath_devdata *dd)
1464 {
1465         u32 __iomem *piobuf;
1466         u32 pioincr, val32;
1467         int i;
1468
1469         /*
1470          * one cache line; long IB headers will spill over into received
1471          * buffer
1472          */
1473         dd->ipath_rcvhdrentsize = 16;
1474         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1475
1476         /*
1477          * For HT, we allocate a somewhat overly large eager buffer,
1478          * such that we can guarantee that we can receive the largest
1479          * packet that we can send out.  To truly support a 4KB MTU,
1480          * we need to bump this to a large value.  To date, other than
1481          * testing, we have never encountered an HCA that can really
1482          * send 4KB MTU packets, so we do not handle that (we'll get
1483          * errors interrupts if we ever see one).
1484          */
1485         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1486
1487         /*
1488          * the min() check here is currently a nop, but it may not
1489          * always be, depending on just how we do ipath_rcvegrbufsize
1490          */
1491         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1492                                  dd->ipath_rcvegrbufsize);
1493         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1494         ipath_ht_tidtemplate(dd);
1495
1496         /*
1497          * zero all the TID entries at startup.  We do this for sanity,
1498          * in case of a previous driver crash of some kind, and also
1499          * because the chip powers up with these memories in an unknown
1500          * state.  Use portcnt, not cfgports, since this is for the
1501          * full chip, not for current (possibly different) configuration
1502          * value.
1503          * Chip Errata bug 6447
1504          */
1505         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1506                 ipath_ht_clear_tids(dd, val32);
1507
1508         /*
1509          * write the pbc of each buffer, to be sure it's initialized, then
1510          * cancel all the buffers, and also abort any packets that might
1511          * have been in flight for some reason (the latter is for driver
1512          * unload/reload, but isn't a bad idea at first init).  PIO send
1513          * isn't enabled at this point, so there is no danger of sending
1514          * these out on the wire.
1515          * Chip Errata bug 6610
1516          */
1517         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1518                                   dd->ipath_piobufbase);
1519         pioincr = dd->ipath_palign / sizeof(*piobuf);
1520         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1521                 /*
1522                  * reasonable word count, just to init pbc
1523                  */
1524                 writel(16, piobuf);
1525                 piobuf += pioincr;
1526         }
1527
1528         ipath_get_eeprom_info(dd);
1529         if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1530                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1531                 /*
1532                  * Later production QHT7040 has same changes as QHT7140, so
1533                  * can use GPIO interrupts.  They have serial #'s starting
1534                  * with 128, rather than 112.
1535                  */
1536                 if (dd->ipath_serial[0] == '1' &&
1537                     dd->ipath_serial[1] == '2' &&
1538                     dd->ipath_serial[2] == '8')
1539                         dd->ipath_flags |= IPATH_GPIO_INTR;
1540                 else {
1541                         ipath_dev_err(dd, "Unsupported InfiniPath board "
1542                                 "(serial number %.16s)!\n",
1543                                 dd->ipath_serial);
1544                         return 1;
1545                 }
1546         }
1547
1548         if (dd->ipath_minrev >= 4) {
1549                 /* Rev4+ reports extra errors via internal GPIO pins */
1550                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
1551                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
1552                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
1553                                  dd->ipath_gpio_mask);
1554         }
1555
1556         return 0;
1557 }
1558
1559
1560 static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1561 {
1562         int cnt = ++ipath_stats.sps_txeparity;
1563         if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1564                 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1565                         ipath_dev_err(dd,
1566                                 "Too many attempts to recover from "
1567                                 "TXE parity, giving up\n");
1568                 return 0;
1569         }
1570         dev_info(&dd->pcidev->dev,
1571                 "Recovering from TXE PIO parity error\n");
1572         return 1;
1573 }
1574
1575
1576 /**
1577  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1578  * @dd: the infinipath device
1579  * @kbase: ipath_base_info pointer
1580  *
1581  * We set the PCIE flag because the lower bandwidth on PCIe vs
1582  * HyperTransport can affect some user packet algorithms.
1583  */
1584 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1585 {
1586         struct ipath_base_info *kinfo = kbase;
1587
1588         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1589                 IPATH_RUNTIME_PIO_REGSWAPPED;
1590
1591         if (pd->port_dd->ipath_minrev < 4)
1592                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_RCVHDR_COPY;
1593
1594         return 0;
1595 }
1596
1597 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1598 {
1599         free_irq(dd->ipath_irq, dd);
1600         ht_destroy_irq(dd->ipath_irq);
1601         dd->ipath_irq = 0;
1602         dd->ipath_intconfig = 0;
1603 }
1604
1605 /**
1606  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1607  * @dd: the infinipath device
1608  *
1609  * This is global, and is called directly at init to set up the
1610  * chip-specific function pointers for later use.
1611  */
1612 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1613 {
1614         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1615         dd->ipath_f_bus = ipath_setup_ht_config;
1616         dd->ipath_f_reset = ipath_setup_ht_reset;
1617         dd->ipath_f_get_boardname = ipath_ht_boardname;
1618         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1619         dd->ipath_f_early_init = ipath_ht_early_init;
1620         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1621         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1622         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1623         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1624         dd->ipath_f_put_tid = ipath_ht_put_tid;
1625         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1626         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1627         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1628         dd->ipath_f_free_irq = ipath_ht_free_irq;
1629
1630         /*
1631          * initialize chip-specific variables
1632          */
1633         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1634
1635         /*
1636          * setup the register offsets, since they are different for each
1637          * chip
1638          */
1639         dd->ipath_kregs = &ipath_ht_kregs;
1640         dd->ipath_cregs = &ipath_ht_cregs;
1641
1642         /*
1643          * do very early init that is needed before ipath_f_bus is
1644          * called
1645          */
1646         ipath_init_ht_variables(dd);
1647 }