2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef __AMD_IOMMU_TYPES_H__
21 #define __AMD_IOMMU_TYPES_H__
23 #include <linux/types.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
28 * some size calculation constants
30 #define DEV_TABLE_ENTRY_SIZE 32
31 #define ALIAS_TABLE_ENTRY_SIZE 2
32 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
35 #define LOW_U32(x) ((x) & ((1ULL << 32)-1))
37 /* Length of the MMIO region for the AMD IOMMU */
38 #define MMIO_REGION_LENGTH 0x4000
40 /* Capability offsets used by the driver */
41 #define MMIO_CAP_HDR_OFFSET 0x00
42 #define MMIO_RANGE_OFFSET 0x0c
44 /* Masks, shifts and macros to parse the device range capability */
45 #define MMIO_RANGE_LD_MASK 0xff000000
46 #define MMIO_RANGE_FD_MASK 0x00ff0000
47 #define MMIO_RANGE_BUS_MASK 0x0000ff00
48 #define MMIO_RANGE_LD_SHIFT 24
49 #define MMIO_RANGE_FD_SHIFT 16
50 #define MMIO_RANGE_BUS_SHIFT 8
51 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
52 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
53 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
55 /* Flag masks for the AMD IOMMU exclusion range */
56 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
57 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
59 /* Used offsets into the MMIO space */
60 #define MMIO_DEV_TABLE_OFFSET 0x0000
61 #define MMIO_CMD_BUF_OFFSET 0x0008
62 #define MMIO_EVT_BUF_OFFSET 0x0010
63 #define MMIO_CONTROL_OFFSET 0x0018
64 #define MMIO_EXCL_BASE_OFFSET 0x0020
65 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
66 #define MMIO_CMD_HEAD_OFFSET 0x2000
67 #define MMIO_CMD_TAIL_OFFSET 0x2008
68 #define MMIO_EVT_HEAD_OFFSET 0x2010
69 #define MMIO_EVT_TAIL_OFFSET 0x2018
70 #define MMIO_STATUS_OFFSET 0x2020
72 /* feature control bits */
73 #define CONTROL_IOMMU_EN 0x00ULL
74 #define CONTROL_HT_TUN_EN 0x01ULL
75 #define CONTROL_EVT_LOG_EN 0x02ULL
76 #define CONTROL_EVT_INT_EN 0x03ULL
77 #define CONTROL_COMWAIT_EN 0x04ULL
78 #define CONTROL_PASSPW_EN 0x08ULL
79 #define CONTROL_RESPASSPW_EN 0x09ULL
80 #define CONTROL_COHERENT_EN 0x0aULL
81 #define CONTROL_ISOC_EN 0x0bULL
82 #define CONTROL_CMDBUF_EN 0x0cULL
83 #define CONTROL_PPFLOG_EN 0x0dULL
84 #define CONTROL_PPFINT_EN 0x0eULL
86 /* command specific defines */
87 #define CMD_COMPL_WAIT 0x01
88 #define CMD_INV_DEV_ENTRY 0x02
89 #define CMD_INV_IOMMU_PAGES 0x03
91 #define CMD_COMPL_WAIT_STORE_MASK 0x01
92 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
93 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
95 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
97 /* macros and definitions for device table entries */
98 #define DEV_ENTRY_VALID 0x00
99 #define DEV_ENTRY_TRANSLATION 0x01
100 #define DEV_ENTRY_IR 0x3d
101 #define DEV_ENTRY_IW 0x3e
102 #define DEV_ENTRY_EX 0x67
103 #define DEV_ENTRY_SYSMGT1 0x68
104 #define DEV_ENTRY_SYSMGT2 0x69
105 #define DEV_ENTRY_INIT_PASS 0xb8
106 #define DEV_ENTRY_EINT_PASS 0xb9
107 #define DEV_ENTRY_NMI_PASS 0xba
108 #define DEV_ENTRY_LINT0_PASS 0xbe
109 #define DEV_ENTRY_LINT1_PASS 0xbf
111 /* constants to configure the command buffer */
112 #define CMD_BUFFER_SIZE 8192
113 #define CMD_BUFFER_ENTRIES 512
114 #define MMIO_CMD_SIZE_SHIFT 56
115 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
117 #define PAGE_MODE_1_LEVEL 0x01
118 #define PAGE_MODE_2_LEVEL 0x02
119 #define PAGE_MODE_3_LEVEL 0x03
121 #define IOMMU_PDE_NL_0 0x000ULL
122 #define IOMMU_PDE_NL_1 0x200ULL
123 #define IOMMU_PDE_NL_2 0x400ULL
124 #define IOMMU_PDE_NL_3 0x600ULL
126 #define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
127 #define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
128 #define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
130 #define IOMMU_MAP_SIZE_L1 (1ULL << 21)
131 #define IOMMU_MAP_SIZE_L2 (1ULL << 30)
132 #define IOMMU_MAP_SIZE_L3 (1ULL << 39)
134 #define IOMMU_PTE_P (1ULL << 0)
135 #define IOMMU_PTE_U (1ULL << 59)
136 #define IOMMU_PTE_FC (1ULL << 60)
137 #define IOMMU_PTE_IR (1ULL << 61)
138 #define IOMMU_PTE_IW (1ULL << 62)
140 #define IOMMU_L1_PDE(address) \
141 ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
142 #define IOMMU_L2_PDE(address) \
143 ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
145 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
146 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
147 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
148 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
150 #define IOMMU_PROT_MASK 0x03
151 #define IOMMU_PROT_IR 0x01
152 #define IOMMU_PROT_IW 0x02
154 /* IOMMU capabilities */
155 #define IOMMU_CAP_IOTLB 24
156 #define IOMMU_CAP_NPCACHE 26
158 #define MAX_DOMAIN_ID 65536
161 * This structure contains generic data for IOMMU protection domains
162 * independent of their use.
164 struct protection_domain {
165 spinlock_t lock; /* mostly used to lock the page table*/
166 u16 id; /* the domain id written to the device table */
167 int mode; /* paging mode (0-6 levels) */
168 u64 *pt_root; /* page table root pointer */
169 void *priv; /* private data */
173 * Data container for a dma_ops specific protection domain
175 struct dma_ops_domain {
176 struct list_head list;
178 /* generic protection domain information */
179 struct protection_domain domain;
181 /* size of the aperture for the mappings */
182 unsigned long aperture_size;
184 /* address we start to search for free addresses */
185 unsigned long next_bit;
187 /* address allocation bitmap */
188 unsigned long *bitmap;
191 * Array of PTE pages for the aperture. In this array we save all the
192 * leaf pages of the domain page table used for the aperture. This way
193 * we don't need to walk the page table to find a specific PTE. We can
194 * just calculate its address in constant time.
200 * Structure where we save information about one hardware AMD IOMMU in the
204 struct list_head list;
206 /* locks the accesses to the hardware */
209 /* device id of this IOMMU */
212 * Capability pointer. There could be more than one IOMMU per PCI
213 * device function if there are more than one AMD IOMMU capability
218 /* physical address of MMIO space */
220 /* virtual address of MMIO space */
223 /* capabilities of that IOMMU read from ACPI */
226 /* first device this IOMMU handles. read from PCI */
228 /* last device this IOMMU handles. read from PCI */
231 /* start of exclusion range of that IOMMU */
233 /* length of exclusion range of that IOMMU */
234 u64 exclusion_length;
236 /* command buffer virtual address */
238 /* size of command buffer */
241 /* if one, we need to send a completion wait command */
244 /* default dma_ops domain for that IOMMU */
245 struct dma_ops_domain *default_dom;
249 * List with all IOMMUs in the system. This list is not locked because it is
250 * only written and read at driver initialization or suspend time
252 extern struct list_head amd_iommu_list;
255 * Structure defining one entry in the device table
257 struct dev_table_entry {
262 * One entry for unity mappings parsed out of the ACPI table.
264 struct unity_map_entry {
265 struct list_head list;
267 /* starting device id this entry is used for (including) */
269 /* end device id this entry is used for (including) */
272 /* start address to unity map (including) */
274 /* end address to unity map (including) */
277 /* required protection */
282 * List of all unity mappings. It is not locked because as runtime it is only
283 * read. It is created at ACPI table parsing time.
285 extern struct list_head amd_iommu_unity_map;
288 * Data structures for device handling
292 * Device table used by hardware. Read and write accesses by software are
293 * locked with the amd_iommu_pd_table lock.
295 extern struct dev_table_entry *amd_iommu_dev_table;
298 * Alias table to find requestor ids to device ids. Not locked because only
301 extern u16 *amd_iommu_alias_table;
304 * Reverse lookup table to find the IOMMU which translates a specific device.
306 extern struct amd_iommu **amd_iommu_rlookup_table;
308 /* size of the dma_ops aperture as power of 2 */
309 extern unsigned amd_iommu_aperture_order;
311 /* largest PCI device id we expect translation requests for */
312 extern u16 amd_iommu_last_bdf;
314 /* data structures for protection domain handling */
315 extern struct protection_domain **amd_iommu_pd_table;
317 /* allocation bitmap for domain ids */
318 extern unsigned long *amd_iommu_pd_alloc_bitmap;
320 /* will be 1 if device isolation is enabled */
321 extern int amd_iommu_isolate;
323 /* takes a PCI device id and prints it out in a readable form */
324 static inline void print_devid(u16 devid, int nl)
326 int bus = devid >> 8;
327 int dev = devid >> 3 & 0x1f;
328 int fn = devid & 0x07;
330 printk("%02x:%02x.%x", bus, dev, fn);
335 /* takes bus and device/function and returns the device id
336 * FIXME: should that be in generic PCI code? */
337 static inline u16 calc_devid(u8 bus, u8 devfn)
339 return (((u16)bus) << 8) | devfn;