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   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995 Waldorf GmbH
   7  * Copyright (C) 1994 - 2000 Ralf Baechle
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
  10  *      Author: Maciej W. Rozycki <macro@mips.com>
  11  */
  12 #ifndef _ASM_IO_H
  13 #define _ASM_IO_H
  14
  15 #include <linux/config.h>
  16 #include <linux/compiler.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19
  20 #include <asm/addrspace.h>
  21 #include <asm/bug.h>
  22 #include <asm/byteorder.h>
  23 #include <asm/cpu.h>
  24 #include <asm/cpu-features.h>
  25 #include <asm/page.h>
  26 #include <asm/pgtable-bits.h>
  27 #include <asm/processor.h>
  28 #include <asm/string.h>
  29
  30 #include <mangle-port.h>
  31
  32 /*
  33  * Slowdown I/O port space accesses for antique hardware.
  34  */
  35 #undef CONF_SLOWDOWN_IO
  36
  37 /*
  38  * Raw operations are never swapped in software.  OTOH values that raw
  39  * operations are working on may or may not have been swapped by the bus
  40  * hardware.  An example use would be for flash memory that's used for
  41  * execute in place.
  42  */
  43 # define __raw_ioswabb(x)       (x)
  44 # define __raw_ioswabw(x)       (x)
  45 # define __raw_ioswabl(x)       (x)
  46 # define __raw_ioswabq(x)       (x)
  47 # define ____raw_ioswabq(x)     (x)
  48
  49 /*
  50  * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
  51  * less sane hardware forces software to fiddle with this...
  52  *
  53  * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
  54  * you can't have the numerical value of data and byte addresses within
  55  * multibyte quantities both preserved at the same time.  Hence two
  56  * variations of functions: non-prefixed ones that preserve the value
  57  * and prefixed ones that preserve byte addresses.  The latters are
  58  * typically used for moving raw data between a peripheral and memory (cf.
  59  * string I/O functions), hence the "mem_" prefix.
  60  */
  61 #if defined(CONFIG_SWAP_IO_SPACE)
  62
  63 # define ioswabb(x)             (x)
  64 # define mem_ioswabb(x)         (x)
  65 # ifdef CONFIG_SGI_IP22
  66 /*
  67  * IP22 seems braindead enough to swap 16bits values in hardware, but
  68  * not 32bits.  Go figure... Can't tell without documentation.
  69  */
  70 #  define ioswabw(x)            (x)
  71 #  define mem_ioswabw(x)        le16_to_cpu(x)
  72 # else
  73 #  define ioswabw(x)            le16_to_cpu(x)
  74 #  define mem_ioswabw(x)        (x)
  75 # endif
  76 # define ioswabl(x)             le32_to_cpu(x)
  77 # define mem_ioswabl(x)         (x)
  78 # define ioswabq(x)             le64_to_cpu(x)
  79 # define mem_ioswabq(x)         (x)
  80
  81 #else
  82
  83 # define ioswabb(x)             (x)
  84 # define mem_ioswabb(x)         (x)
  85 # define ioswabw(x)             (x)
  86 # define mem_ioswabw(x)         cpu_to_le16(x)
  87 # define ioswabl(x)             (x)
  88 # define mem_ioswabl(x)         cpu_to_le32(x)
  89 # define ioswabq(x)             (x)
  90 # define mem_ioswabq(x)         cpu_to_le32(x)
  91
  92 #endif
  93
  94 #define IO_SPACE_LIMIT 0xffff
  95
  96 /*
  97  * On MIPS I/O ports are memory mapped, so we access them using normal
  98  * load/store instructions. mips_io_port_base is the virtual address to
  99  * which all ports are being mapped.  For sake of efficiency some code
 100  * assumes that this is an address that can be loaded with a single lui
 101  * instruction, so the lower 16 bits must be zero.  Should be true on
 102  * on any sane architecture; generic code does not use this assumption.
 103  */
 104 extern const unsigned long mips_io_port_base;
 105
 106 #define set_io_port_base(base)  \
 107         do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
 108
 109 /*
 110  * Thanks to James van Artsdalen for a better timing-fix than
 111  * the two short jumps: using outb's to a nonexistent port seems
 112  * to guarantee better timings even on fast machines.
 113  *
 114  * On the other hand, I'd like to be sure of a non-existent port:
 115  * I feel a bit unsafe about using 0x80 (should be safe, though)
 116  *
 117  *              Linus
 118  *
 119  */
 120
 121 #define __SLOW_DOWN_IO \
 122         __asm__ __volatile__( \
 123                 "sb\t$0,0x80(%0)" \
 124                 : : "r" (mips_io_port_base));
 125
 126 #ifdef CONF_SLOWDOWN_IO
 127 #ifdef REALLY_SLOW_IO
 128 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
 129 #else
 130 #define SLOW_DOWN_IO __SLOW_DOWN_IO
 131 #endif
 132 #else
 133 #define SLOW_DOWN_IO
 134 #endif
 135
 136 /*
 137  *     virt_to_phys    -       map virtual addresses to physical
 138  *     @address: address to remap
 139  *
 140  *     The returned physical address is the physical (CPU) mapping for
 141  *     the memory address given. It is only valid to use this function on
 142  *     addresses directly mapped or allocated via kmalloc.
 143  *
 144  *     This function does not give bus mappings for DMA transfers. In
 145  *     almost all conceivable cases a device driver should not be using
 146  *     this function
 147  */
 148 static inline unsigned long virt_to_phys(volatile void * address)
 149 {
 150         return (unsigned long)address - PAGE_OFFSET;
 151 }
 152
 153 /*
 154  *     phys_to_virt    -       map physical address to virtual
 155  *     @address: address to remap
 156  *
 157  *     The returned virtual address is a current CPU mapping for
 158  *     the memory address given. It is only valid to use this function on
 159  *     addresses that have a kernel mapping
 160  *
 161  *     This function does not handle bus mappings for DMA transfers. In
 162  *     almost all conceivable cases a device driver should not be using
 163  *     this function
 164  */
 165 static inline void * phys_to_virt(unsigned long address)
 166 {
 167         return (void *)(address + PAGE_OFFSET);
 168 }
 169
 170 /*
 171  * ISA I/O bus memory addresses are 1:1 with the physical address.
 172  */
 173 static inline unsigned long isa_virt_to_bus(volatile void * address)
 174 {
 175         return (unsigned long)address - PAGE_OFFSET;
 176 }
 177
 178 static inline void * isa_bus_to_virt(unsigned long address)
 179 {
 180         return (void *)(address + PAGE_OFFSET);
 181 }
 182
 183 #define isa_page_to_bus page_to_phys
 184
 185 /*
 186  * However PCI ones are not necessarily 1:1 and therefore these interfaces
 187  * are forbidden in portable PCI drivers.
 188  *
 189  * Allow them for x86 for legacy drivers, though.
 190  */
 191 #define virt_to_bus virt_to_phys
 192 #define bus_to_virt phys_to_virt
 193
 194 /*
 195  * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
 196  * for the processor.  This implies the assumption that there is only
 197  * one of these busses.
 198  */
 199 extern unsigned long isa_slot_offset;
 200
 201 /*
 202  * Change "struct page" to physical address.
 203  */
 204 #define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 205
 206 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
 207 extern void __iounmap(volatile void __iomem *addr);
 208
 209 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
 210         unsigned long flags)
 211 {
 212         if (cpu_has_64bit_addresses) {
 213                 u64 base = UNCAC_BASE;
 214
 215                 /*
 216                  * R10000 supports a 2 bit uncached attribute therefore
 217                  * UNCAC_BASE may not equal IO_BASE.
 218                  */
 219                 if (flags == _CACHE_UNCACHED)
 220                         base = (u64) IO_BASE;
 221                 return (void __iomem *) (unsigned long) (base + offset);
 222         }
 223
 224         return __ioremap(offset, size, flags);
 225 }
 226
 227 /*
 228  * ioremap     -   map bus memory into CPU space
 229  * @offset:    bus address of the memory
 230  * @size:      size of the resource to map
 231  *
 232  * ioremap performs a platform specific sequence of operations to
 233  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 234  * writew/writel functions and the other mmio helpers. The returned
 235  * address is not guaranteed to be usable directly as a virtual
 236  * address.
 237  */
 238 #define ioremap(offset, size)                                           \
 239         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 240
 241 /*
 242  * ioremap_nocache     -   map bus memory into CPU space
 243  * @offset:    bus address of the memory
 244  * @size:      size of the resource to map
 245  *
 246  * ioremap_nocache performs a platform specific sequence of operations to
 247  * make bus memory CPU accessible via the readb/readw/readl/writeb/
 248  * writew/writel functions and the other mmio helpers. The returned
 249  * address is not guaranteed to be usable directly as a virtual
 250  * address.
 251  *
 252  * This version of ioremap ensures that the memory is marked uncachable
 253  * on the CPU as well as honouring existing caching rules from things like
 254  * the PCI bus. Note that there are other caches and buffers on many
 255  * busses. In paticular driver authors should read up on PCI writes
 256  *
 257  * It's useful if some control registers are in such an area and
 258  * write combining or read caching is not desirable:
 259  */
 260 #define ioremap_nocache(offset, size)                                   \
 261         __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 262
 263 /*
 264  * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
 265  * requests a cachable mapping, ioremap_uncached_accelerated requests a
 266  * mapping using the uncached accelerated mode which isn't supported on
 267  * all processors.
 268  */
 269 #define ioremap_cacheable_cow(offset, size)                             \
 270         __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
 271 #define ioremap_uncached_accelerated(offset, size)                      \
 272         __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
 273
 274 static inline void iounmap(volatile void __iomem *addr)
 275 {
 276         if (cpu_has_64bit_addresses)
 277                 return;
 278
 279         __iounmap(addr);
 280 }
 281
 282
 283 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
 284                                                                         \
 285 static inline void pfx##write##bwlq(type val,                           \
 286                                     volatile void __iomem *mem)         \
 287 {                                                                       \
 288         volatile type *__mem;                                           \
 289         type __val;                                                     \
 290                                                                         \
 291         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 292                                                                         \
 293         __val = pfx##ioswab##bwlq(val);                                 \
 294                                                                         \
 295         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 296                 *__mem = __val;                                         \
 297         else if (cpu_has_64bits) {                                      \
 298                 unsigned long __flags;                                  \
 299                 type __tmp;                                             \
 300                                                                         \
 301                 if (irq)                                                \
 302                         local_irq_save(__flags);                        \
 303                 __asm__ __volatile__(                                   \
 304                         ".set   mips3"          "\t\t# __writeq""\n\t"  \
 305                         "dsll32 %L0, %L0, 0"                    "\n\t"  \
 306                         "dsrl32 %L0, %L0, 0"                    "\n\t"  \
 307                         "dsll32 %M0, %M0, 0"                    "\n\t"  \
 308                         "or     %L0, %L0, %M0"                  "\n\t"  \
 309                         "sd     %L0, %2"                        "\n\t"  \
 310                         ".set   mips0"                          "\n"    \
 311                         : "=r" (__tmp)                                  \
 312                         : "0" (__val), "m" (*__mem));                   \
 313                 if (irq)                                                \
 314                         local_irq_restore(__flags);                     \
 315         } else                                                          \
 316                 BUG();                                                  \
 317 }                                                                       \
 318                                                                         \
 319 static inline type pfx##read##bwlq(volatile void __iomem *mem)          \
 320 {                                                                       \
 321         volatile type *__mem;                                           \
 322         type __val;                                                     \
 323                                                                         \
 324         __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
 325                                                                         \
 326         if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
 327                 __val = *__mem;                                         \
 328         else if (cpu_has_64bits) {                                      \
 329                 unsigned long __flags;                                  \
 330                                                                         \
 331                 if (irq)                                                \
 332                         local_irq_save(__flags);                        \
 333                 __asm__ __volatile__(                                   \
 334                         ".set   mips3"          "\t\t# __readq" "\n\t"  \
 335                         "ld     %L0, %1"                        "\n\t"  \
 336                         "dsra32 %M0, %L0, 0"                    "\n\t"  \
 337                         "sll    %L0, %L0, 0"                    "\n\t"  \
 338                         ".set   mips0"                          "\n"    \
 339                         : "=r" (__val)                                  \
 340                         : "m" (*__mem));                                \
 341                 if (irq)                                                \
 342                         local_irq_restore(__flags);                     \
 343         } else {                                                        \
 344                 __val = 0;                                              \
 345                 BUG();                                                  \
 346         }                                                               \
 347                                                                         \
 348         return pfx##ioswab##bwlq(__val);                                \
 349 }
 350
 351 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
 352                                                                         \
 353 static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
 354 {                                                                       \
 355         volatile type *__addr;                                          \
 356         type __val;                                                     \
 357                                                                         \
 358         port = __swizzle_addr_##bwlq(port);                             \
 359         __addr = (void *)(mips_io_port_base + port);                    \
 360                                                                         \
 361         __val = pfx##ioswab##bwlq(val);                                 \
 362                                                                         \
 363         if (sizeof(type) != sizeof(u64)) {                              \
 364                 *__addr = __val;                                        \
 365                 slow;                                                   \
 366         } else                                                          \
 367                 BUILD_BUG();                                            \
 368 }                                                                       \
 369                                                                         \
 370 static inline type pfx##in##bwlq##p(unsigned long port)                 \
 371 {                                                                       \
 372         volatile type *__addr;                                          \
 373         type __val;                                                     \
 374                                                                         \
 375         port = __swizzle_addr_##bwlq(port);                             \
 376         __addr = (void *)(mips_io_port_base + port);                    \
 377                                                                         \
 378         if (sizeof(type) != sizeof(u64)) {                              \
 379                 __val = *__addr;                                        \
 380                 slow;                                                   \
 381         } else {                                                        \
 382                 __val = 0;                                              \
 383                 BUILD_BUG();                                            \
 384         }                                                               \
 385                                                                         \
 386         return pfx##ioswab##bwlq(__val);                                \
 387 }
 388
 389 #define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
 390                                                                         \
 391 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
 392
 393 #define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
 394                                                                         \
 395 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                               \
 396 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
 397
 398 #define BUILDIO(bwlq, type)                                             \
 399                                                                         \
 400 __BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
 401 __BUILD_MEMORY_PFX(, bwlq, type)                                        \
 402 __BUILD_MEMORY_PFX(mem_, bwlq, type)                                    \
 403 __BUILD_IOPORT_PFX(, bwlq, type)                                        \
 404 __BUILD_IOPORT_PFX(mem_, bwlq, type)
 405
 406 #define __BUILDIO(bwlq, type)                                           \
 407                                                                         \
 408 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
 409
 410 BUILDIO(b, u8)
 411 BUILDIO(w, u16)
 412 BUILDIO(l, u32)
 413 BUILDIO(q, u64)
 414
 415 __BUILDIO(q, u64)
 416
 417 #define readb_relaxed                   readb
 418 #define readw_relaxed                   readw
 419 #define readl_relaxed                   readl
 420 #define readq_relaxed                   readq
 421
 422 /*
 423  * Some code tests for these symbols
 424  */
 425 #define readq                           readq
 426 #define writeq                          writeq
 427
 428 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
 429                                                                         \
 430 static inline void writes##bwlq(volatile void __iomem *mem, void *addr, \
 431                                 unsigned int count)                     \
 432 {                                                                       \
 433         volatile type *__addr = addr;                                   \
 434                                                                         \
 435         while (count--) {                                               \
 436                 mem_write##bwlq(*__addr, mem);                          \
 437                 __addr++;                                               \
 438         }                                                               \
 439 }                                                                       \
 440                                                                         \
 441 static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
 442                                unsigned int count)                      \
 443 {                                                                       \
 444         volatile type *__addr = addr;                                   \
 445                                                                         \
 446         while (count--) {                                               \
 447                 *__addr = mem_read##bwlq(mem);                          \
 448                 __addr++;                                               \
 449         }                                                               \
 450 }
 451
 452 #define __BUILD_IOPORT_STRING(bwlq, type)                               \
 453                                                                         \
 454 static inline void outs##bwlq(unsigned long port, const void *addr,     \
 455                               unsigned int count)                       \
 456 {                                                                       \
 457         const volatile type *__addr = addr;                             \
 458                                                                         \
 459         while (count--) {                                               \
 460                 mem_out##bwlq(*__addr, port);                           \
 461                 __addr++;                                               \
 462         }                                                               \
 463 }                                                                       \
 464                                                                         \
 465 static inline void ins##bwlq(unsigned long port, void *addr,            \
 466                              unsigned int count)                        \
 467 {                                                                       \
 468         volatile type *__addr = addr;                                   \
 469                                                                         \
 470         while (count--) {                                               \
 471                 *__addr = mem_in##bwlq(port);                           \
 472                 __addr++;                                               \
 473         }                                                               \
 474 }
 475
 476 #define BUILDSTRING(bwlq, type)                                         \
 477                                                                         \
 478 __BUILD_MEMORY_STRING(bwlq, type)                                       \
 479 __BUILD_IOPORT_STRING(bwlq, type)
 480
 481 BUILDSTRING(b, u8)
 482 BUILDSTRING(w, u16)
 483 BUILDSTRING(l, u32)
 484 BUILDSTRING(q, u64)
 485
 486
 487 /* Depends on MIPS II instruction set */
 488 #define mmiowb() asm volatile ("sync" ::: "memory")
 489
 490 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
 491 {
 492         memset((void __force *) addr, val, count);
 493 }
 494 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
 495 {
 496         memcpy(dst, (void __force *) src, count);
 497 }
 498 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
 499 {
 500         memcpy((void __force *) dst, src, count);
 501 }
 502
 503 /*
 504  * Memory Mapped I/O
 505  */
 506 #define ioread8(addr)           readb(addr)
 507 #define ioread16(addr)          readw(addr)
 508 #define ioread32(addr)          readl(addr)
 509
 510 #define iowrite8(b,addr)        writeb(b,addr)
 511 #define iowrite16(w,addr)       writew(w,addr)
 512 #define iowrite32(l,addr)       writel(l,addr)
 513
 514 #define ioread8_rep(a,b,c)      readsb(a,b,c)
 515 #define ioread16_rep(a,b,c)     readsw(a,b,c)
 516 #define ioread32_rep(a,b,c)     readsl(a,b,c)
 517
 518 #define iowrite8_rep(a,b,c)     writesb(a,b,c)
 519 #define iowrite16_rep(a,b,c)    writesw(a,b,c)
 520 #define iowrite32_rep(a,b,c)    writesl(a,b,c)
 521
 522 /* Create a virtual mapping cookie for an IO port range */
 523 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 524 extern void ioport_unmap(void __iomem *);
 525
 526 /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
 527 struct pci_dev;
 528 extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 529 extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
 530
 531 /*
 532  * ISA space is 'always mapped' on currently supported MIPS systems, no need
 533  * to explicitly ioremap() it. The fact that the ISA IO space is mapped
 534  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
 535  * are physical addresses. The following constant pointer can be
 536  * used as the IO-area pointer (it can be iounmapped as well, so the
 537  * analogy with PCI is quite large):
 538  */
 539 #define __ISA_IO_base ((char *)(isa_slot_offset))
 540
 541 #define isa_readb(a)            readb(__ISA_IO_base + (a))
 542 #define isa_readw(a)            readw(__ISA_IO_base + (a))
 543 #define isa_readl(a)            readl(__ISA_IO_base + (a))
 544 #define isa_readq(a)            readq(__ISA_IO_base + (a))
 545 #define isa_writeb(b,a)         writeb(b,__ISA_IO_base + (a))
 546 #define isa_writew(w,a)         writew(w,__ISA_IO_base + (a))
 547 #define isa_writel(l,a)         writel(l,__ISA_IO_base + (a))
 548 #define isa_writeq(q,a)         writeq(q,__ISA_IO_base + (a))
 549 #define isa_memset_io(a,b,c)    memset_io(__ISA_IO_base + (a),(b),(c))
 550 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
 551 #define isa_memcpy_toio(a,b,c)  memcpy_toio(__ISA_IO_base + (a),(b),(c))
 552
 553 /*
 554  * We don't have csum_partial_copy_fromio() yet, so we cheat here and
 555  * just copy it. The net code will then do the checksum later.
 556  */
 557 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
 558 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
 559
 560 /*
 561  *     check_signature         -       find BIOS signatures
 562  *     @io_addr: mmio address to check
 563  *     @signature:  signature block
 564  *     @length: length of signature
 565  *
 566  *     Perform a signature comparison with the mmio address io_addr. This
 567  *     address should have been obtained by ioremap.
 568  *     Returns 1 on a match.
 569  */
 570 static inline int check_signature(char __iomem *io_addr,
 571         const unsigned char *signature, int length)
 572 {
 573         int retval = 0;
 574         do {
 575                 if (readb(io_addr) != *signature)
 576                         goto out;
 577                 io_addr++;
 578                 signature++;
 579                 length--;
 580         } while (length);
 581         retval = 1;
 582 out:
 583         return retval;
 584 }
 585
 586 /*
 587  * The caches on some architectures aren't dma-coherent and have need to
 588  * handle this in software.  There are three types of operations that
 589  * can be applied to dma buffers.
 590  *
 591  *  - dma_cache_wback_inv(start, size) makes caches and coherent by
 592  *    writing the content of the caches back to memory, if necessary.
 593  *    The function also invalidates the affected part of the caches as
 594  *    necessary before DMA transfers from outside to memory.
 595  *  - dma_cache_wback(start, size) makes caches and coherent by
 596  *    writing the content of the caches back to memory, if necessary.
 597  *    The function also invalidates the affected part of the caches as
 598  *    necessary before DMA transfers from outside to memory.
 599  *  - dma_cache_inv(start, size) invalidates the affected parts of the
 600  *    caches.  Dirty lines of the caches may be written back or simply
 601  *    be discarded.  This operation is necessary before dma operations
 602  *    to the memory.
 603  */
 604 #ifdef CONFIG_DMA_NONCOHERENT
 605
 606 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
 607 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
 608 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 609
 610 #define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start,size)
 611 #define dma_cache_wback(start, size)            _dma_cache_wback(start,size)
 612 #define dma_cache_inv(start, size)              _dma_cache_inv(start,size)
 613
 614 #else /* Sane hardware */
 615
 616 #define dma_cache_wback_inv(start,size) \
 617         do { (void) (start); (void) (size); } while (0)
 618 #define dma_cache_wback(start,size)     \
 619         do { (void) (start); (void) (size); } while (0)
 620 #define dma_cache_inv(start,size)       \
 621         do { (void) (start); (void) (size); } while (0)
 622
 623 #endif /* CONFIG_DMA_NONCOHERENT */
 624
 625 /*
 626  * Read a 32-bit register that requires a 64-bit read cycle on the bus.
 627  * Avoid interrupt mucking, just adjust the address for 4-byte access.
 628  * Assume the addresses are 8-byte aligned.
 629  */
 630 #ifdef __MIPSEB__
 631 #define __CSR_32_ADJUST 4
 632 #else
 633 #define __CSR_32_ADJUST 0
 634 #endif
 635
 636 #define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
 637 #define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
 638
 639 /*
 640  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 641  * access
 642  */
 643 #define xlate_dev_mem_ptr(p)    __va(p)
 644
 645 /*
 646  * Convert a virtual cached pointer to an uncached pointer
 647  */
 648 #define xlate_dev_kmem_ptr(p)   p
 649
 650 #endif /* _ASM_IO_H */