git.oblomov.eu Git - linux-2.6/blob - arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/thread_info.h>
   8 #include <linux/module.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/pgtable.h>
  12 #include <asm/msr.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/ds.h>
  15 #include <asm/bugs.h>
  16
  17 #ifdef CONFIG_X86_64
  18 #include <asm/topology.h>
  19 #include <asm/numa_64.h>
  20 #endif
  21
  22 #include "cpu.h"
  23
  24 #ifdef CONFIG_X86_LOCAL_APIC
  25 #include <asm/mpspec.h>
  26 #include <asm/apic.h>
  27 #endif
  28
  29 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  30 {
  31         /* Unmask CPUID levels if masked: */
  32         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
  33                 u64 misc_enable;
  34
  35                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  36
  37                 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
  38                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
  39                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  40                         c->cpuid_level = cpuid_eax(0);
  41                 }
  42         }
  43
  44         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  45                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  46                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  47
  48 #ifdef CONFIG_X86_64
  49         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  50 #else
  51         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  52         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  53                 c->x86_cache_alignment = 128;
  54 #endif
  55
  56         /*
  57          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
  58          * with P/T states and does not stop in deep C-states
  59          */
  60         if (c->x86_power & (1 << 8)) {
  61                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  62                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
  63         }
  64
  65         /*
  66          * There is a known erratum on Pentium III and Core Solo
  67          * and Core Duo CPUs.
  68          * " Page with PAT set to WC while associated MTRR is UC
  69          *   may consolidate to UC "
  70          * Because of this erratum, it is better to stick with
  71          * setting WC in MTRR rather than using PAT on these CPUs.
  72          *
  73          * Enable PAT WC only on P4, Core 2 or later CPUs.
  74          */
  75         if (c->x86 == 6 && c->x86_model < 15)
  76                 clear_cpu_cap(c, X86_FEATURE_PAT);
  77 }
  78
  79 #ifdef CONFIG_X86_32
  80 /*
  81  *      Early probe support logic for ppro memory erratum #50
  82  *
  83  *      This is called before we do cpu ident work
  84  */
  85
  86 int __cpuinit ppro_with_ram_bug(void)
  87 {
  88         /* Uses data from early_cpu_detect now */
  89         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  90             boot_cpu_data.x86 == 6 &&
  91             boot_cpu_data.x86_model == 1 &&
  92             boot_cpu_data.x86_mask < 8) {
  93                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  94                 return 1;
  95         }
  96         return 0;
  97 }
  98
  99 #ifdef CONFIG_X86_F00F_BUG
 100 static void __cpuinit trap_init_f00f_bug(void)
 101 {
 102         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
 103
 104         /*
 105          * Update the IDT descriptor and reload the IDT so that
 106          * it uses the read-only mapped virtual address.
 107          */
 108         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
 109         load_idt(&idt_descr);
 110 }
 111 #endif
 112
 113 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 114 {
 115         unsigned long lo, hi;
 116
 117 #ifdef CONFIG_X86_F00F_BUG
 118         /*
 119          * All current models of Pentium and Pentium with MMX technology CPUs
 120          * have the F0 0F bug, which lets nonprivileged users lock up the system.
 121          * Note that the workaround only should be initialized once...
 122          */
 123         c->f00f_bug = 0;
 124         if (!paravirt_enabled() && c->x86 == 5) {
 125                 static int f00f_workaround_enabled;
 126
 127                 c->f00f_bug = 1;
 128                 if (!f00f_workaround_enabled) {
 129                         trap_init_f00f_bug();
 130                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 131                         f00f_workaround_enabled = 1;
 132                 }
 133         }
 134 #endif
 135
 136         /*
 137          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 138          * model 3 mask 3
 139          */
 140         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 141                 clear_cpu_cap(c, X86_FEATURE_SEP);
 142
 143         /*
 144          * P4 Xeon errata 037 workaround.
 145          * Hardware prefetcher may cause stale data to be loaded into the cache.
 146          */
 147         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 148                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 149                 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
 150                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 151                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 152                         lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
 153                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
 154                 }
 155         }
 156
 157         /*
 158          * See if we have a good local APIC by checking for buggy Pentia,
 159          * i.e. all B steppings and the C2 stepping of P54C when using their
 160          * integrated APIC (see 11AP erratum in "Pentium Processor
 161          * Specification Update").
 162          */
 163         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 164             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 165                 set_cpu_cap(c, X86_FEATURE_11AP);
 166
 167
 168 #ifdef CONFIG_X86_INTEL_USERCOPY
 169         /*
 170          * Set up the preferred alignment for movsl bulk memory moves
 171          */
 172         switch (c->x86) {
 173         case 4:         /* 486: untested */
 174                 break;
 175         case 5:         /* Old Pentia: untested */
 176                 break;
 177         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 178                 movsl_mask.mask = 7;
 179                 break;
 180         case 15:        /* P4 is OK down to 8-byte alignment */
 181                 movsl_mask.mask = 7;
 182                 break;
 183         }
 184 #endif
 185
 186 #ifdef CONFIG_X86_NUMAQ
 187         numaq_tsc_disable();
 188 #endif
 189 }
 190 #else
 191 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 192 {
 193 }
 194 #endif
 195
 196 static void __cpuinit srat_detect_node(void)
 197 {
 198 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 199         unsigned node;
 200         int cpu = smp_processor_id();
 201         int apicid = hard_smp_processor_id();
 202
 203         /* Don't do the funky fallback heuristics the AMD version employs
 204            for now. */
 205         node = apicid_to_node[apicid];
 206         if (node == NUMA_NO_NODE || !node_online(node))
 207                 node = first_node(node_online_map);
 208         numa_set_node(cpu, node);
 209
 210         printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
 211 #endif
 212 }
 213
 214 /*
 215  * find out the number of processor cores on the die
 216  */
 217 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 218 {
 219         unsigned int eax, ebx, ecx, edx;
 220
 221         if (c->cpuid_level < 4)
 222                 return 1;
 223
 224         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
 225         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
 226         if (eax & 0x1f)
 227                 return ((eax >> 26) + 1);
 228         else
 229                 return 1;
 230 }
 231
 232 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 233 {
 234         /* Intel VMX MSR indicated features */
 235 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
 236 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
 237 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
 238 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
 239 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
 240 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
 241
 242         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 243
 244         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 245         clear_cpu_cap(c, X86_FEATURE_VNMI);
 246         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 247         clear_cpu_cap(c, X86_FEATURE_EPT);
 248         clear_cpu_cap(c, X86_FEATURE_VPID);
 249
 250         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 251         msr_ctl = vmx_msr_high | vmx_msr_low;
 252         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 253                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 254         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 255                 set_cpu_cap(c, X86_FEATURE_VNMI);
 256         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 257                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 258                       vmx_msr_low, vmx_msr_high);
 259                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 260                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 261                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 262                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 263                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 264                         set_cpu_cap(c, X86_FEATURE_EPT);
 265                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 266                         set_cpu_cap(c, X86_FEATURE_VPID);
 267         }
 268 }
 269
 270 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 271 {
 272         unsigned int l2 = 0;
 273
 274         early_init_intel(c);
 275
 276         intel_workarounds(c);
 277
 278         /*
 279          * Detect the extended topology information if available. This
 280          * will reinitialise the initial_apicid which will be used
 281          * in init_intel_cacheinfo()
 282          */
 283         detect_extended_topology(c);
 284
 285         l2 = init_intel_cacheinfo(c);
 286         if (c->cpuid_level > 9) {
 287                 unsigned eax = cpuid_eax(10);
 288                 /* Check for version and the number of counters */
 289                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 290                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 291         }
 292
 293         if (cpu_has_xmm2)
 294                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 295         if (cpu_has_ds) {
 296                 unsigned int l1;
 297                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 298                 if (!(l1 & (1<<11)))
 299                         set_cpu_cap(c, X86_FEATURE_BTS);
 300                 if (!(l1 & (1<<12)))
 301                         set_cpu_cap(c, X86_FEATURE_PEBS);
 302                 ds_init_intel(c);
 303         }
 304
 305         if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
 306                 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
 307
 308 #ifdef CONFIG_X86_64
 309         if (c->x86 == 15)
 310                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 311         if (c->x86 == 6)
 312                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 313 #else
 314         /*
 315          * Names for the Pentium II/Celeron processors
 316          * detectable only by also checking the cache size.
 317          * Dixon is NOT a Celeron.
 318          */
 319         if (c->x86 == 6) {
 320                 char *p = NULL;
 321
 322                 switch (c->x86_model) {
 323                 case 5:
 324                         if (c->x86_mask == 0) {
 325                                 if (l2 == 0)
 326                                         p = "Celeron (Covington)";
 327                                 else if (l2 == 256)
 328                                         p = "Mobile Pentium II (Dixon)";
 329                         }
 330                         break;
 331
 332                 case 6:
 333                         if (l2 == 128)
 334                                 p = "Celeron (Mendocino)";
 335                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 336                                 p = "Celeron-A";
 337                         break;
 338
 339                 case 8:
 340                         if (l2 == 128)
 341                                 p = "Celeron (Coppermine)";
 342                         break;
 343                 }
 344
 345                 if (p)
 346                         strcpy(c->x86_model_id, p);
 347         }
 348
 349         if (c->x86 == 15)
 350                 set_cpu_cap(c, X86_FEATURE_P4);
 351         if (c->x86 == 6)
 352                 set_cpu_cap(c, X86_FEATURE_P3);
 353 #endif
 354
 355         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 356                 /*
 357                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 358                  * detection.
 359                  */
 360                 c->x86_max_cores = intel_num_cpu_cores(c);
 361 #ifdef CONFIG_X86_32
 362                 detect_ht(c);
 363 #endif
 364         }
 365
 366         /* Work around errata */
 367         srat_detect_node();
 368
 369         if (cpu_has(c, X86_FEATURE_VMX))
 370                 detect_vmx_virtcap(c);
 371 }
 372
 373 #ifdef CONFIG_X86_32
 374 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 375 {
 376         /*
 377          * Intel PIII Tualatin. This comes in two flavours.
 378          * One has 256kb of cache, the other 512. We have no way
 379          * to determine which, so we use a boottime override
 380          * for the 512kb model, and assume 256 otherwise.
 381          */
 382         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 383                 size = 256;
 384         return size;
 385 }
 386 #endif
 387
 388 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
 389         .c_vendor       = "Intel",
 390         .c_ident        = { "GenuineIntel" },
 391 #ifdef CONFIG_X86_32
 392         .c_models = {
 393                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 394                   {
 395                           [0] = "486 DX-25/33",
 396                           [1] = "486 DX-50",
 397                           [2] = "486 SX",
 398                           [3] = "486 DX/2",
 399                           [4] = "486 SL",
 400                           [5] = "486 SX/2",
 401                           [7] = "486 DX/2-WB",
 402                           [8] = "486 DX/4",
 403                           [9] = "486 DX/4-WB"
 404                   }
 405                 },
 406                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 407                   {
 408                           [0] = "Pentium 60/66 A-step",
 409                           [1] = "Pentium 60/66",
 410                           [2] = "Pentium 75 - 200",
 411                           [3] = "OverDrive PODP5V83",
 412                           [4] = "Pentium MMX",
 413                           [7] = "Mobile Pentium 75 - 200",
 414                           [8] = "Mobile Pentium MMX"
 415                   }
 416                 },
 417                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 418                   {
 419                           [0] = "Pentium Pro A-step",
 420                           [1] = "Pentium Pro",
 421                           [3] = "Pentium II (Klamath)",
 422                           [4] = "Pentium II (Deschutes)",
 423                           [5] = "Pentium II (Deschutes)",
 424                           [6] = "Mobile Pentium II",
 425                           [7] = "Pentium III (Katmai)",
 426                           [8] = "Pentium III (Coppermine)",
 427                           [10] = "Pentium III (Cascades)",
 428                           [11] = "Pentium III (Tualatin)",
 429                   }
 430                 },
 431                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 432                   {
 433                           [0] = "Pentium 4 (Unknown)",
 434                           [1] = "Pentium 4 (Willamette)",
 435                           [2] = "Pentium 4 (Northwood)",
 436                           [4] = "Pentium 4 (Foster)",
 437                           [5] = "Pentium 4 (Foster)",
 438                   }
 439                 },
 440         },
 441         .c_size_cache   = intel_size_cache,
 442 #endif
 443         .c_early_init   = early_init_intel,
 444         .c_init         = init_intel,
 445         .c_x86_vendor   = X86_VENDOR_INTEL,
 446 };
 447
 448 cpu_dev_register(intel_cpu_dev);
 449