[PATCH] jiffies_64 cleanup
[linux-2.6] / arch / m32r / kernel / setup_usrv.c
1 /*
2  *  linux/arch/m32r/kernel/setup_usrv.c
3  *
4  *  Setup routines for MITSUBISHI uServer
5  *
6  *  Copyright (c) 2001, 2002, 2003  Hiroyuki Kondo, Hirokazu Takata,
7  *                                  Hitoshi Yamamoto
8  */
9
10 #include <linux/config.h>
11 #include <linux/irq.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14
15 #include <asm/system.h>
16 #include <asm/m32r.h>
17 #include <asm/io.h>
18
19 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
20
21 #if !defined(CONFIG_SMP)
22 typedef struct {
23         unsigned long icucr;    /* ICU Control Register */
24 } icu_data_t;
25 #endif /* CONFIG_SMP */
26
27 icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
28
29 static void disable_mappi_irq(unsigned int irq)
30 {
31         unsigned long port, data;
32
33         port = irq2port(irq);
34         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
35         outl(data, port);
36 }
37
38 static void enable_mappi_irq(unsigned int irq)
39 {
40         unsigned long port, data;
41
42         port = irq2port(irq);
43         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
44         outl(data, port);
45 }
46
47 static void mask_and_ack_mappi(unsigned int irq)
48 {
49         disable_mappi_irq(irq);
50 }
51
52 static void end_mappi_irq(unsigned int irq)
53 {
54         enable_mappi_irq(irq);
55 }
56
57 static unsigned int startup_mappi_irq(unsigned int irq)
58 {
59         enable_mappi_irq(irq);
60         return 0;
61 }
62
63 static void shutdown_mappi_irq(unsigned int irq)
64 {
65         unsigned long port;
66
67         port = irq2port(irq);
68         outl(M32R_ICUCR_ILEVEL7, port);
69 }
70
71 static struct hw_interrupt_type mappi_irq_type =
72 {
73         .typename = "M32700-IRQ",
74         .startup = startup_mappi_irq,
75         .shutdown = shutdown_mappi_irq,
76         .enable = enable_mappi_irq,
77         .disable = disable_mappi_irq,
78         .ack = mask_and_ack_mappi,
79         .end = end_mappi_irq
80 };
81
82 /*
83  * Interrupt Control Unit of PLD on M32700UT (Level 2)
84  */
85 #define irq2pldirq(x)           ((x) - M32700UT_PLD_IRQ_BASE)
86 #define pldirq2port(x)          (unsigned long)((int)PLD_ICUCR1 + \
87                                  (((x) - 1) * sizeof(unsigned short)))
88
89 typedef struct {
90         unsigned short icucr;  /* ICU Control Register */
91 } pld_icu_data_t;
92
93 static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
94
95 static void disable_m32700ut_pld_irq(unsigned int irq)
96 {
97         unsigned long port, data;
98         unsigned int pldirq;
99
100         pldirq = irq2pldirq(irq);
101         port = pldirq2port(pldirq);
102         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
103         outw(data, port);
104 }
105
106 static void enable_m32700ut_pld_irq(unsigned int irq)
107 {
108         unsigned long port, data;
109         unsigned int pldirq;
110
111         pldirq = irq2pldirq(irq);
112         port = pldirq2port(pldirq);
113         data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
114         outw(data, port);
115 }
116
117 static void mask_and_ack_m32700ut_pld(unsigned int irq)
118 {
119         disable_m32700ut_pld_irq(irq);
120 }
121
122 static void end_m32700ut_pld_irq(unsigned int irq)
123 {
124         enable_m32700ut_pld_irq(irq);
125         end_mappi_irq(M32R_IRQ_INT1);
126 }
127
128 static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
129 {
130         enable_m32700ut_pld_irq(irq);
131         return 0;
132 }
133
134 static void shutdown_m32700ut_pld_irq(unsigned int irq)
135 {
136         unsigned long port;
137         unsigned int pldirq;
138
139         pldirq = irq2pldirq(irq);
140         port = pldirq2port(pldirq);
141         outw(PLD_ICUCR_ILEVEL7, port);
142 }
143
144 static struct hw_interrupt_type m32700ut_pld_irq_type =
145 {
146         .typename = "USRV-PLD-IRQ",
147         .startup = startup_m32700ut_pld_irq,
148         .shutdown = shutdown_m32700ut_pld_irq,
149         .enable = enable_m32700ut_pld_irq,
150         .disable = disable_m32700ut_pld_irq,
151         .ack = mask_and_ack_m32700ut_pld,
152         .end = end_m32700ut_pld_irq
153 };
154
155 void __init init_IRQ(void)
156 {
157         static int once = 0;
158         int i;
159
160         if (once)
161                 return;
162         else
163                 once++;
164
165         /* MFT2 : system timer */
166         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
167         irq_desc[M32R_IRQ_MFT2].handler = &mappi_irq_type;
168         irq_desc[M32R_IRQ_MFT2].action = 0;
169         irq_desc[M32R_IRQ_MFT2].depth = 1;
170         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
171         disable_mappi_irq(M32R_IRQ_MFT2);
172
173 #if defined(CONFIG_SERIAL_M32R_SIO)
174         /* SIO0_R : uart receive data */
175         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
176         irq_desc[M32R_IRQ_SIO0_R].handler = &mappi_irq_type;
177         irq_desc[M32R_IRQ_SIO0_R].action = 0;
178         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
179         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
180         disable_mappi_irq(M32R_IRQ_SIO0_R);
181
182         /* SIO0_S : uart send data */
183         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
184         irq_desc[M32R_IRQ_SIO0_S].handler = &mappi_irq_type;
185         irq_desc[M32R_IRQ_SIO0_S].action = 0;
186         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
187         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
188         disable_mappi_irq(M32R_IRQ_SIO0_S);
189
190         /* SIO1_R : uart receive data */
191         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
192         irq_desc[M32R_IRQ_SIO1_R].handler = &mappi_irq_type;
193         irq_desc[M32R_IRQ_SIO1_R].action = 0;
194         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
195         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
196         disable_mappi_irq(M32R_IRQ_SIO1_R);
197
198         /* SIO1_S : uart send data */
199         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
200         irq_desc[M32R_IRQ_SIO1_S].handler = &mappi_irq_type;
201         irq_desc[M32R_IRQ_SIO1_S].action = 0;
202         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
203         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
204         disable_mappi_irq(M32R_IRQ_SIO1_S);
205 #endif  /* CONFIG_SERIAL_M32R_SIO */
206
207         /* INT#67-#71: CFC#0 IREQ on PLD */
208         for (i = 0 ; i < CONFIG_CFC_NUM ; i++ ) {
209                 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED;
210                 irq_desc[PLD_IRQ_CF0 + i].handler = &m32700ut_pld_irq_type;
211                 irq_desc[PLD_IRQ_CF0 + i].action = 0;
212                 irq_desc[PLD_IRQ_CF0 + i].depth = 1;    /* disable nested irq */
213                 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
214                         = PLD_ICUCR_ISMOD01;    /* 'L' level sense */
215                 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
216         }
217
218 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
219         /* INT#76: 16552D#0 IREQ on PLD */
220         irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED;
221         irq_desc[PLD_IRQ_UART0].handler = &m32700ut_pld_irq_type;
222         irq_desc[PLD_IRQ_UART0].action = 0;
223         irq_desc[PLD_IRQ_UART0].depth = 1;      /* disable nested irq */
224         pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
225                 = PLD_ICUCR_ISMOD03;    /* 'H' level sense */
226         disable_m32700ut_pld_irq(PLD_IRQ_UART0);
227
228         /* INT#77: 16552D#1 IREQ on PLD */
229         irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED;
230         irq_desc[PLD_IRQ_UART1].handler = &m32700ut_pld_irq_type;
231         irq_desc[PLD_IRQ_UART1].action = 0;
232         irq_desc[PLD_IRQ_UART1].depth = 1;      /* disable nested irq */
233         pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
234                 = PLD_ICUCR_ISMOD03;    /* 'H' level sense */
235         disable_m32700ut_pld_irq(PLD_IRQ_UART1);
236 #endif  /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
237
238 #if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
239         /* INT#80: AK4524 IREQ on PLD */
240         irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED;
241         irq_desc[PLD_IRQ_SNDINT].handler = &m32700ut_pld_irq_type;
242         irq_desc[PLD_IRQ_SNDINT].action = 0;
243         irq_desc[PLD_IRQ_SNDINT].depth = 1;     /* disable nested irq */
244         pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
245                 = PLD_ICUCR_ISMOD01;    /* 'L' level sense */
246         disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
247 #endif  /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
248
249         /*
250          * INT1# is used for UART, MMC, CF Controller in FPGA.
251          * We enable it here.
252          */
253         icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
254         enable_mappi_irq(M32R_IRQ_INT1);
255 }
256