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   1 /*
   2  * arch/ppc/platforms/4xx/yucca.h
   3  *
   4  * Yucca board definitions
   5  *
   6  * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
   7  *
   8  * Copyright 2004-2005 MontaVista Software Inc.
   9  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  *
  16  */
  17
  18 #ifdef __KERNEL__
  19 #ifndef __ASM_YUCCA_H__
  20 #define __ASM_YUCCA_H__
  21
  22 #include <linux/config.h>
  23 #include <platforms/4xx/ppc440spe.h>
  24
  25 /* F/W TLB mapping used in bootloader glue to reset EMAC */
  26 #define PPC44x_EMAC0_MR0        0xa0000800
  27
  28 /* Location of MAC addresses in PIBS image */
  29 #define PIBS_FLASH_BASE         0xffe00000
  30 #define PIBS_MAC_BASE           (PIBS_FLASH_BASE+0x1b0400)
  31
  32 /* External timer clock frequency */
  33 #define YUCCA_TMR_CLK           25000000
  34
  35 /*
  36  * FPGA registers
  37  */
  38 #define YUCCA_FPGA_REG_BASE                     0x00000004e2000000ULL
  39 #define YUCCA_FPGA_REG_SIZE                     0x24
  40
  41 #define FPGA_REG1A                              0x1a
  42
  43 #define FPGA_REG1A_PE0_GLED                     0x8000
  44 #define FPGA_REG1A_PE1_GLED                     0x4000
  45 #define FPGA_REG1A_PE2_GLED                     0x2000
  46 #define FPGA_REG1A_PE0_YLED                     0x1000
  47 #define FPGA_REG1A_PE1_YLED                     0x0800
  48 #define FPGA_REG1A_PE2_YLED                     0x0400
  49 #define FPGA_REG1A_PE0_PWRON                    0x0200
  50 #define FPGA_REG1A_PE1_PWRON                    0x0100
  51 #define FPGA_REG1A_PE2_PWRON                    0x0080
  52 #define FPGA_REG1A_PE0_REFCLK_ENABLE            0x0040
  53 #define FPGA_REG1A_PE1_REFCLK_ENABLE            0x0020
  54 #define FPGA_REG1A_PE2_REFCLK_ENABLE            0x0010
  55 #define FPGA_REG1A_PE_SPREAD0                   0x0008
  56 #define FPGA_REG1A_PE_SPREAD1                   0x0004
  57 #define FPGA_REG1A_PE_SELSOURCE_0               0x0002
  58 #define FPGA_REG1A_PE_SELSOURCE_1               0x0001
  59
  60 #define FPGA_REG1C                              0x1c
  61
  62 #define FPGA_REG1C_PE0_ROOTPOINT                0x8000
  63 #define FPGA_REG1C_PE1_ENDPOINT                 0x4000
  64 #define FPGA_REG1C_PE2_ENDPOINT                 0x2000
  65 #define FPGA_REG1C_PE0_PRSNT                    0x1000
  66 #define FPGA_REG1C_PE1_PRSNT                    0x0800
  67 #define FPGA_REG1C_PE2_PRSNT                    0x0400
  68 #define FPGA_REG1C_PE0_WAKE                     0x0080
  69 #define FPGA_REG1C_PE1_WAKE                     0x0040
  70 #define FPGA_REG1C_PE2_WAKE                     0x0020
  71 #define FPGA_REG1C_PE0_PERST                    0x0010
  72 #define FPGA_REG1C_PE1_PERST                    0x0008
  73 #define FPGA_REG1C_PE2_PERST                    0x0004
  74
  75 /*
  76  * Serial port defines
  77  */
  78 #define RS_TABLE_SIZE   3
  79
  80 /* PIBS defined UART mappings, used before early_serial_setup */
  81 #define UART0_IO_BASE   0xa0000200
  82 #define UART1_IO_BASE   0xa0000300
  83 #define UART2_IO_BASE   0xa0000600
  84
  85 #define BASE_BAUD       11059200
  86 #define STD_UART_OP(num)                                        \
  87         { 0, BASE_BAUD, 0, UART##num##_INT,                     \
  88                 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
  89                 iomem_base: (void*)UART##num##_IO_BASE,         \
  90                 io_type: SERIAL_IO_MEM},
  91
  92 #define SERIAL_PORT_DFNS        \
  93         STD_UART_OP(0)          \
  94         STD_UART_OP(1)          \
  95         STD_UART_OP(2)
  96
  97 /* PCI support */
  98 #define YUCCA_PCIX_LOWER_IO     0x00000000
  99 #define YUCCA_PCIX_UPPER_IO     0x0000ffff
 100 #define YUCCA_PCIX_LOWER_MEM    0x80000000
 101 #define YUCCA_PCIX_UPPER_MEM    0x8fffffff
 102 #define YUCCA_PCIE_LOWER_MEM    0x90000000
 103 #define YUCCA_PCIE_MEM_SIZE     0x10000000
 104
 105 #define YUCCA_PCIX_MEM_SIZE     0x10000000
 106 #define YUCCA_PCIX_MEM_OFFSET   0x00000000
 107 #define YUCCA_PCIE_MEM_SIZE     0x10000000
 108 #define YUCCA_PCIE_MEM_OFFSET   0x00000000
 109
 110 #endif                          /* __ASM_YUCCA_H__ */
 111 #endif                          /* __KERNEL__ */