2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/tcp.h>
36 #include <linux/udp.h>
37 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
54 * The first part is the high level driver of the gigE ethernet ports.
60 #define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61 #define HW_IP_ALIGN 2 /* hw aligns IP header */
62 #define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
63 #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
65 #define INT_UNMASK_ALL 0x0007ffff
66 #define INT_UNMASK_ALL_EXT 0x0011ffff
67 #define INT_MASK_ALL 0x00000000
68 #define INT_MASK_ALL_EXT 0x00000000
69 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
72 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
75 #define MAX_DESCS_PER_SKB 1
78 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79 #define PHY_WAIT_MICRO_SECONDS 10
81 /* Static function declarations */
82 static int eth_port_link_is_up(unsigned int eth_port_num);
83 static void eth_port_uc_addr_get(struct net_device *dev,
84 unsigned char *MacAddr);
85 static void eth_port_set_multicast_list(struct net_device *);
86 static int mv643xx_eth_open(struct net_device *);
87 static int mv643xx_eth_stop(struct net_device *);
88 static int mv643xx_eth_change_mtu(struct net_device *, int);
89 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
90 static void eth_port_init_mac_tables(unsigned int eth_port_num);
92 static int mv643xx_poll(struct net_device *dev, int *budget);
94 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
95 static int ethernet_phy_detect(unsigned int eth_port_num);
96 static struct ethtool_ops mv643xx_ethtool_ops;
98 static char mv643xx_driver_name[] = "mv643xx_eth";
99 static char mv643xx_driver_version[] = "1.0";
101 static void __iomem *mv643xx_eth_shared_base;
103 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
104 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
106 static inline u32 mv_read(int offset)
108 void __iomem *reg_base;
110 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
112 return readl(reg_base + offset);
115 static inline void mv_write(int offset, u32 data)
117 void __iomem *reg_base;
119 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
120 writel(data, reg_base + offset);
124 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
126 * Input : pointer to ethernet interface network device structure
128 * Output : 0 upon success, -EINVAL upon failure
130 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
132 if ((new_mtu > 9500) || (new_mtu < 64))
137 * Stop then re-open the interface. This will allocate RX skb's with
139 * There is a possible danger that the open will not successed, due
140 * to memory is full, which might fail the open function.
142 if (netif_running(dev)) {
143 mv643xx_eth_stop(dev);
144 if (mv643xx_eth_open(dev))
146 "%s: Fatal error on opening device\n",
154 * mv643xx_eth_rx_task
156 * Fills / refills RX queue on a certain gigabit ethernet port
158 * Input : pointer to ethernet interface network device structure
161 static void mv643xx_eth_rx_task(void *data)
163 struct net_device *dev = (struct net_device *)data;
164 struct mv643xx_private *mp = netdev_priv(dev);
165 struct pkt_info pkt_info;
169 if (test_and_set_bit(0, &mp->rx_task_busy))
170 panic("%s: Error in test_set_bit / clear_bit", dev->name);
172 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
173 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
177 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
179 skb_reserve(skb, DMA_ALIGN - unaligned);
180 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
181 pkt_info.byte_cnt = RX_SKB_SIZE;
182 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
184 pkt_info.return_info = skb;
185 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
187 "%s: Error allocating RX Ring\n", dev->name);
190 skb_reserve(skb, HW_IP_ALIGN);
192 clear_bit(0, &mp->rx_task_busy);
194 * If RX ring is empty of SKB, set a timer to try allocating
195 * again in a later time .
197 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
198 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
200 mp->timeout.expires = jiffies + (HZ / 10);
201 add_timer(&mp->timeout);
202 mp->rx_timer_flag = 1;
204 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
206 /* Return interrupts */
207 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
214 * mv643xx_eth_rx_task_timer_wrapper
216 * Timer routine to wake up RX queue filling task. This function is
217 * used only in case the RX queue is empty, and all alloc_skb has
218 * failed (due to out of memory event).
220 * Input : pointer to ethernet interface network device structure
223 static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
225 struct net_device *dev = (struct net_device *)data;
226 struct mv643xx_private *mp = netdev_priv(dev);
228 mp->rx_timer_flag = 0;
229 mv643xx_eth_rx_task((void *)data);
233 * mv643xx_eth_update_mac_address
235 * Update the MAC address of the port in the address table
237 * Input : pointer to ethernet interface network device structure
240 static void mv643xx_eth_update_mac_address(struct net_device *dev)
242 struct mv643xx_private *mp = netdev_priv(dev);
243 unsigned int port_num = mp->port_num;
245 eth_port_init_mac_tables(port_num);
246 eth_port_uc_addr_set(port_num, dev->dev_addr);
250 * mv643xx_eth_set_rx_mode
252 * Change from promiscuos to regular rx mode
254 * Input : pointer to ethernet interface network device structure
257 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
259 struct mv643xx_private *mp = netdev_priv(dev);
261 if (dev->flags & IFF_PROMISC)
262 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
264 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
266 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
268 eth_port_set_multicast_list(dev);
272 * mv643xx_eth_set_mac_address
274 * Change the interface's mac address.
275 * No special hardware thing should be done because interface is always
276 * put in promiscuous mode.
278 * Input : pointer to ethernet interface network device structure and
279 * a pointer to the designated entry to be added to the cache.
280 * Output : zero upon success, negative upon failure
282 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
286 for (i = 0; i < 6; i++)
287 /* +2 is for the offset of the HW addr type */
288 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
289 mv643xx_eth_update_mac_address(dev);
294 * mv643xx_eth_tx_timeout
296 * Called upon a timeout on transmitting a packet
298 * Input : pointer to ethernet interface network device structure.
301 static void mv643xx_eth_tx_timeout(struct net_device *dev)
303 struct mv643xx_private *mp = netdev_priv(dev);
305 printk(KERN_INFO "%s: TX timeout ", dev->name);
307 /* Do the reset outside of interrupt context */
308 schedule_work(&mp->tx_timeout_task);
312 * mv643xx_eth_tx_timeout_task
314 * Actual routine to reset the adapter when a timeout on Tx has occurred
316 static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
318 struct mv643xx_private *mp = netdev_priv(dev);
320 netif_device_detach(dev);
321 eth_port_reset(mp->port_num);
323 netif_device_attach(dev);
327 * mv643xx_eth_free_tx_queue
329 * Input : dev - a pointer to the required interface
331 * Output : 0 if was able to release skb , nonzero otherwise
333 static int mv643xx_eth_free_tx_queue(struct net_device *dev,
334 unsigned int eth_int_cause_ext)
336 struct mv643xx_private *mp = netdev_priv(dev);
337 struct net_device_stats *stats = &mp->stats;
338 struct pkt_info pkt_info;
341 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
344 /* Check only queue 0 */
345 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
346 if (pkt_info.cmd_sts & BIT0) {
347 printk("%s: Error in TX\n", dev->name);
351 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
352 dma_unmap_single(NULL, pkt_info.buf_ptr,
356 dma_unmap_page(NULL, pkt_info.buf_ptr,
360 if (pkt_info.return_info) {
361 dev_kfree_skb_irq(pkt_info.return_info);
370 * mv643xx_eth_receive
372 * This function is forward packets that are received from the port's
373 * queues toward kernel core or FastRoute them to another interface.
375 * Input : dev - a pointer to the required interface
376 * max - maximum number to receive (0 means unlimted)
378 * Output : number of served packets
381 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
383 static int mv643xx_eth_receive_queue(struct net_device *dev)
386 struct mv643xx_private *mp = netdev_priv(dev);
387 struct net_device_stats *stats = &mp->stats;
388 unsigned int received_packets = 0;
390 struct pkt_info pkt_info;
393 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
395 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
400 /* Update statistics. Note byte count includes 4 byte CRC count */
402 stats->rx_bytes += pkt_info.byte_cnt;
403 skb = pkt_info.return_info;
405 * In case received a packet without first / last bits on OR
406 * the error summary bit is on, the packets needs to be dropeed.
408 if (((pkt_info.cmd_sts
409 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
410 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
411 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
413 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
414 ETH_RX_LAST_DESC)) !=
415 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
418 "%s: Received packet spread "
419 "on multiple descriptors\n",
422 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
425 dev_kfree_skb_irq(skb);
428 * The -4 is for the CRC in the trailer of the
431 skb_put(skb, pkt_info.byte_cnt - 4);
434 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
435 skb->ip_summed = CHECKSUM_UNNECESSARY;
437 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
439 skb->protocol = eth_type_trans(skb, dev);
441 netif_receive_skb(skb);
446 dev->last_rx = jiffies;
449 return received_packets;
453 * mv643xx_eth_int_handler
455 * Main interrupt handler for the gigbit ethernet ports
457 * Input : irq - irq number (not used)
458 * dev_id - a pointer to the required interface's data structure
463 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
464 struct pt_regs *regs)
466 struct net_device *dev = (struct net_device *)dev_id;
467 struct mv643xx_private *mp = netdev_priv(dev);
468 u32 eth_int_cause, eth_int_cause_ext = 0;
469 unsigned int port_num = mp->port_num;
471 /* Read interrupt cause registers */
472 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
475 if (eth_int_cause & BIT1)
476 eth_int_cause_ext = mv_read(
477 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
481 if (!(eth_int_cause & 0x0007fffd)) {
482 /* Dont ack the Rx interrupt */
485 * Clear specific ethernet port intrerrupt registers by
486 * acknowleding relevant bits.
488 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
490 if (eth_int_cause_ext != 0x0)
491 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
492 (port_num), ~eth_int_cause_ext);
494 /* UDP change : We may need this */
495 if ((eth_int_cause_ext & 0x0000ffff) &&
496 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
497 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
498 netif_wake_queue(dev);
501 if (netif_rx_schedule_prep(dev)) {
502 /* Mask all the interrupts */
503 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
505 /* wait for previous write to complete */
506 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
507 __netif_rx_schedule(dev);
510 if (eth_int_cause & (BIT2 | BIT11))
511 mv643xx_eth_receive_queue(dev, 0);
514 * After forwarded received packets to upper layer, add a task
515 * in an interrupts enabled context that refills the RX ring
518 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
519 /* Mask all interrupts on ethernet port */
520 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
522 /* wait for previous write to take effect */
523 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
525 queue_task(&mp->rx_task, &tq_immediate);
526 mark_bh(IMMEDIATE_BH);
528 mp->rx_task.func(dev);
532 /* PHY status changed */
533 if (eth_int_cause_ext & (BIT16 | BIT20)) {
534 if (eth_port_link_is_up(port_num)) {
535 netif_carrier_on(dev);
536 netif_wake_queue(dev);
538 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
541 netif_carrier_off(dev);
542 netif_stop_queue(dev);
547 * If no real interrupt occured, exit.
548 * This can happen when using gigE interrupt coalescing mechanism.
550 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
559 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
562 * This routine sets the RX coalescing interrupt mechanism parameter.
563 * This parameter is a timeout counter, that counts in 64 t_clk
564 * chunks ; that when timeout event occurs a maskable interrupt
566 * The parameter is calculated using the tClk of the MV-643xx chip
567 * , and the required delay of the interrupt in usec.
570 * unsigned int eth_port_num Ethernet port number
571 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
572 * unsigned int delay Delay in usec
575 * Interrupt coalescing mechanism value is set in MV-643xx chip.
578 * The interrupt coalescing value set in the gigE port.
581 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
582 unsigned int t_clk, unsigned int delay)
584 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
586 /* Set RX Coalescing mechanism */
587 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
588 ((coal & 0x3fff) << 8) |
589 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
597 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
600 * This routine sets the TX coalescing interrupt mechanism parameter.
601 * This parameter is a timeout counter, that counts in 64 t_clk
602 * chunks ; that when timeout event occurs a maskable interrupt
604 * The parameter is calculated using the t_cLK frequency of the
605 * MV-643xx chip and the required delay in the interrupt in uSec
608 * unsigned int eth_port_num Ethernet port number
609 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
610 * unsigned int delay Delay in uSeconds
613 * Interrupt coalescing mechanism value is set in MV-643xx chip.
616 * The interrupt coalescing value set in the gigE port.
619 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
620 unsigned int t_clk, unsigned int delay)
623 coal = ((t_clk / 1000000) * delay) / 64;
624 /* Set TX Coalescing mechanism */
625 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
631 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
634 * This function prepares a Rx chained list of descriptors and packet
635 * buffers in a form of a ring. The routine must be called after port
636 * initialization routine and before port start routine.
637 * The Ethernet SDMA engine uses CPU bus addresses to access the various
638 * devices in the system (i.e. DRAM). This function uses the ethernet
639 * struct 'virtual to physical' routine (set by the user) to set the ring
640 * with physical addresses.
643 * struct mv643xx_private *mp Ethernet Port Control srtuct.
646 * The routine updates the Ethernet port control struct with information
647 * regarding the Rx descriptors and buffers.
652 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
654 volatile struct eth_rx_desc *p_rx_desc;
655 int rx_desc_num = mp->rx_ring_size;
658 /* initialize the next_desc_ptr links in the Rx descriptors ring */
659 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
660 for (i = 0; i < rx_desc_num; i++) {
661 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
662 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
665 /* Save Rx desc pointer to driver struct. */
666 mp->rx_curr_desc_q = 0;
667 mp->rx_used_desc_q = 0;
669 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
671 /* Add the queue to the list of RX queues of this port */
672 mp->port_rx_queue_command |= 1;
676 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
679 * This function prepares a Tx chained list of descriptors and packet
680 * buffers in a form of a ring. The routine must be called after port
681 * initialization routine and before port start routine.
682 * The Ethernet SDMA engine uses CPU bus addresses to access the various
683 * devices in the system (i.e. DRAM). This function uses the ethernet
684 * struct 'virtual to physical' routine (set by the user) to set the ring
685 * with physical addresses.
688 * struct mv643xx_private *mp Ethernet Port Control srtuct.
691 * The routine updates the Ethernet port control struct with information
692 * regarding the Tx descriptors and buffers.
697 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
699 int tx_desc_num = mp->tx_ring_size;
700 struct eth_tx_desc *p_tx_desc;
703 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
704 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
705 for (i = 0; i < tx_desc_num; i++) {
706 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
707 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
710 mp->tx_curr_desc_q = 0;
711 mp->tx_used_desc_q = 0;
712 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
713 mp->tx_first_desc_q = 0;
716 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
718 /* Add the queue to the list of Tx queues of this port */
719 mp->port_tx_queue_command |= 1;
725 * This function is called when openning the network device. The function
726 * should initialize all the hardware, initialize cyclic Rx/Tx
727 * descriptors chain and buffers and allocate an IRQ to the network
730 * Input : a pointer to the network device structure
732 * Output : zero of success , nonzero if fails.
735 static int mv643xx_eth_open(struct net_device *dev)
737 struct mv643xx_private *mp = netdev_priv(dev);
738 unsigned int port_num = mp->port_num;
742 err = request_irq(dev->irq, mv643xx_eth_int_handler,
743 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
745 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
751 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
755 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
757 memset(&mp->timeout, 0, sizeof(struct timer_list));
758 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
759 mp->timeout.data = (unsigned long)dev;
761 mp->rx_task_busy = 0;
762 mp->rx_timer_flag = 0;
764 /* Allocate RX and TX skb rings */
765 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
768 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
772 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
775 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
777 goto out_free_rx_skb;
780 /* Allocate TX ring */
781 mp->tx_ring_skbs = 0;
782 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
783 mp->tx_desc_area_size = size;
785 if (mp->tx_sram_size) {
786 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
788 mp->tx_desc_dma = mp->tx_sram_addr;
790 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
794 if (!mp->p_tx_desc_area) {
795 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
798 goto out_free_tx_skb;
800 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
801 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
803 ether_init_tx_desc_ring(mp);
805 /* Allocate RX ring */
806 mp->rx_ring_skbs = 0;
807 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
808 mp->rx_desc_area_size = size;
810 if (mp->rx_sram_size) {
811 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
813 mp->rx_desc_dma = mp->rx_sram_addr;
815 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
819 if (!mp->p_rx_desc_area) {
820 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
822 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
824 if (mp->rx_sram_size)
825 iounmap(mp->p_tx_desc_area);
827 dma_free_coherent(NULL, mp->tx_desc_area_size,
828 mp->p_tx_desc_area, mp->tx_desc_dma);
830 goto out_free_tx_skb;
832 memset((void *)mp->p_rx_desc_area, 0, size);
834 ether_init_rx_desc_ring(mp);
836 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
840 /* Interrupt Coalescing */
844 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
848 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
850 /* Clear any pending ethernet port interrupts */
851 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
852 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
854 /* Unmask phy and link status changes interrupts */
855 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
858 /* Unmask RX buffer and TX end interrupt */
859 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
867 free_irq(dev->irq, dev);
872 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
874 struct mv643xx_private *mp = netdev_priv(dev);
875 unsigned int port_num = mp->port_num;
880 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
882 /* Free outstanding skb's on TX rings */
883 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
884 skb = mp->tx_skb[curr];
886 mp->tx_ring_skbs -= skb_shinfo(skb)->nr_frags;
891 if (mp->tx_ring_skbs)
892 printk("%s: Error on Tx descriptor free - could not free %d"
893 " descriptors\n", dev->name, mp->tx_ring_skbs);
896 if (mp->tx_sram_size)
897 iounmap(mp->p_tx_desc_area);
899 dma_free_coherent(NULL, mp->tx_desc_area_size,
900 mp->p_tx_desc_area, mp->tx_desc_dma);
903 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
905 struct mv643xx_private *mp = netdev_priv(dev);
906 unsigned int port_num = mp->port_num;
910 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
912 /* Free preallocated skb's on RX rings */
913 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
914 if (mp->rx_skb[curr]) {
915 dev_kfree_skb(mp->rx_skb[curr]);
920 if (mp->rx_ring_skbs)
922 "%s: Error in freeing Rx Ring. %d skb's still"
923 " stuck in RX Ring - ignoring them\n", dev->name,
926 if (mp->rx_sram_size)
927 iounmap(mp->p_rx_desc_area);
929 dma_free_coherent(NULL, mp->rx_desc_area_size,
930 mp->p_rx_desc_area, mp->rx_desc_dma);
936 * This function is used when closing the network device.
937 * It updates the hardware,
938 * release all memory that holds buffers and descriptors and release the IRQ.
939 * Input : a pointer to the device structure
940 * Output : zero if success , nonzero if fails
943 static int mv643xx_eth_stop(struct net_device *dev)
945 struct mv643xx_private *mp = netdev_priv(dev);
946 unsigned int port_num = mp->port_num;
948 /* Mask all interrupts on ethernet port */
949 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
950 /* wait for previous write to complete */
951 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
954 netif_poll_disable(dev);
956 netif_carrier_off(dev);
957 netif_stop_queue(dev);
959 eth_port_reset(mp->port_num);
961 mv643xx_eth_free_tx_rings(dev);
962 mv643xx_eth_free_rx_rings(dev);
965 netif_poll_enable(dev);
968 free_irq(dev->irq, dev);
974 static void mv643xx_tx(struct net_device *dev)
976 struct mv643xx_private *mp = netdev_priv(dev);
977 struct pkt_info pkt_info;
979 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
980 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
981 dma_unmap_single(NULL, pkt_info.buf_ptr,
985 dma_unmap_page(NULL, pkt_info.buf_ptr,
989 if (pkt_info.return_info)
990 dev_kfree_skb_irq(pkt_info.return_info);
993 if (netif_queue_stopped(dev) &&
994 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
995 netif_wake_queue(dev);
1001 * This function is used in case of NAPI
1003 static int mv643xx_poll(struct net_device *dev, int *budget)
1005 struct mv643xx_private *mp = netdev_priv(dev);
1006 int done = 1, orig_budget, work_done;
1007 unsigned int port_num = mp->port_num;
1009 #ifdef MV643XX_TX_FAST_REFILL
1010 if (++mp->tx_clean_threshold > 5) {
1012 mp->tx_clean_threshold = 0;
1016 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1017 != (u32) mp->rx_used_desc_q) {
1018 orig_budget = *budget;
1019 if (orig_budget > dev->quota)
1020 orig_budget = dev->quota;
1021 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1022 mp->rx_task.func(dev);
1023 *budget -= work_done;
1024 dev->quota -= work_done;
1025 if (work_done >= orig_budget)
1030 netif_rx_complete(dev);
1031 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1032 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1033 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1037 return done ? 0 : 1;
1041 /* Hardware can't handle unaligned fragments smaller than 9 bytes.
1042 * This helper function detects that case.
1045 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1050 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1051 fragp = &skb_shinfo(skb)->frags[frag];
1052 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1060 * mv643xx_eth_start_xmit
1062 * This function is queues a packet in the Tx descriptor for
1065 * Input : skb - a pointer to socket buffer
1066 * dev - a pointer to the required port
1068 * Output : zero upon success
1070 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1072 struct mv643xx_private *mp = netdev_priv(dev);
1073 struct net_device_stats *stats = &mp->stats;
1074 ETH_FUNC_RET_STATUS status;
1075 unsigned long flags;
1076 struct pkt_info pkt_info;
1078 if (netif_queue_stopped(dev)) {
1080 "%s: Tried sending packet when interface is stopped\n",
1085 /* This is a hard error, log it. */
1086 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1087 (skb_shinfo(skb)->nr_frags + 1)) {
1088 netif_stop_queue(dev);
1090 "%s: Bug in mv643xx_eth - Trying to transmit when"
1091 " queue full !\n", dev->name);
1095 /* Paranoid check - this shouldn't happen */
1097 stats->tx_dropped++;
1098 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1102 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1103 if (has_tiny_unaligned_frags(skb)) {
1104 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1105 stats->tx_dropped++;
1106 printk(KERN_DEBUG "%s: failed to linearize tiny "
1107 "unaligned fragment\n", dev->name);
1112 spin_lock_irqsave(&mp->lock, flags);
1114 if (!skb_shinfo(skb)->nr_frags) {
1115 if (skb->ip_summed != CHECKSUM_HW) {
1116 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1117 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
1120 5 << ETH_TX_IHL_SHIFT;
1121 pkt_info.l4i_chk = 0;
1123 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
1126 ETH_GEN_TCP_UDP_CHECKSUM |
1127 ETH_GEN_IP_V_4_CHECKSUM |
1128 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1129 /* CPU already calculated pseudo header checksum. */
1130 if ((skb->protocol == ETH_P_IP) &&
1131 (skb->nh.iph->protocol == IPPROTO_UDP) ) {
1132 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1133 pkt_info.l4i_chk = skb->h.uh->check;
1134 } else if ((skb->protocol == ETH_P_IP) &&
1135 (skb->nh.iph->protocol == IPPROTO_TCP))
1136 pkt_info.l4i_chk = skb->h.th->check;
1139 "%s: chksum proto != IPv4 TCP or UDP\n",
1141 spin_unlock_irqrestore(&mp->lock, flags);
1145 pkt_info.byte_cnt = skb->len;
1146 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1148 pkt_info.return_info = skb;
1149 status = eth_port_send(mp, &pkt_info);
1150 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1151 printk(KERN_ERR "%s: Error on transmitting packet\n",
1153 stats->tx_bytes += pkt_info.byte_cnt;
1157 /* first frag which is skb header */
1158 pkt_info.byte_cnt = skb_headlen(skb);
1159 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1162 pkt_info.l4i_chk = 0;
1163 pkt_info.return_info = 0;
1165 if (skb->ip_summed != CHECKSUM_HW)
1166 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1167 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1168 5 << ETH_TX_IHL_SHIFT;
1170 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1171 ETH_GEN_TCP_UDP_CHECKSUM |
1172 ETH_GEN_IP_V_4_CHECKSUM |
1173 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1174 /* CPU already calculated pseudo header checksum. */
1175 if ((skb->protocol == ETH_P_IP) &&
1176 (skb->nh.iph->protocol == IPPROTO_UDP)) {
1177 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1178 pkt_info.l4i_chk = skb->h.uh->check;
1179 } else if ((skb->protocol == ETH_P_IP) &&
1180 (skb->nh.iph->protocol == IPPROTO_TCP))
1181 pkt_info.l4i_chk = skb->h.th->check;
1184 "%s: chksum proto != IPv4 TCP or UDP\n",
1186 spin_unlock_irqrestore(&mp->lock, flags);
1191 status = eth_port_send(mp, &pkt_info);
1192 if (status != ETH_OK) {
1193 if ((status == ETH_ERROR))
1195 "%s: Error on transmitting packet\n",
1197 if (status == ETH_QUEUE_FULL)
1198 printk("Error on Queue Full \n");
1199 if (status == ETH_QUEUE_LAST_RESOURCE)
1200 printk("Tx resource error \n");
1202 stats->tx_bytes += pkt_info.byte_cnt;
1204 /* Check for the remaining frags */
1205 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1206 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1207 pkt_info.l4i_chk = 0x0000;
1208 pkt_info.cmd_sts = 0x00000000;
1210 /* Last Frag enables interrupt and frees the skb */
1211 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1212 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1214 pkt_info.return_info = skb;
1216 pkt_info.return_info = 0;
1218 pkt_info.l4i_chk = 0;
1219 pkt_info.byte_cnt = this_frag->size;
1221 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1222 this_frag->page_offset,
1226 status = eth_port_send(mp, &pkt_info);
1228 if (status != ETH_OK) {
1229 if ((status == ETH_ERROR))
1230 printk(KERN_ERR "%s: Error on "
1231 "transmitting packet\n",
1234 if (status == ETH_QUEUE_LAST_RESOURCE)
1235 printk("Tx resource error \n");
1237 if (status == ETH_QUEUE_FULL)
1238 printk("Queue is full \n");
1240 stats->tx_bytes += pkt_info.byte_cnt;
1244 spin_lock_irqsave(&mp->lock, flags);
1246 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1248 pkt_info.l4i_chk = 0;
1249 pkt_info.byte_cnt = skb->len;
1250 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1252 pkt_info.return_info = skb;
1253 status = eth_port_send(mp, &pkt_info);
1254 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1255 printk(KERN_ERR "%s: Error on transmitting packet\n",
1257 stats->tx_bytes += pkt_info.byte_cnt;
1260 /* Check if TX queue can handle another skb. If not, then
1261 * signal higher layers to stop requesting TX
1263 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1265 * Stop getting skb's from upper layers.
1266 * Getting skb's from upper layers will be enabled again after
1267 * packets are released.
1269 netif_stop_queue(dev);
1271 /* Update statistics and start of transmittion time */
1272 stats->tx_packets++;
1273 dev->trans_start = jiffies;
1275 spin_unlock_irqrestore(&mp->lock, flags);
1277 return 0; /* success */
1281 * mv643xx_eth_get_stats
1283 * Returns a pointer to the interface statistics.
1285 * Input : dev - a pointer to the required interface
1287 * Output : a pointer to the interface's statistics
1290 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1292 struct mv643xx_private *mp = netdev_priv(dev);
1297 #ifdef CONFIG_NET_POLL_CONTROLLER
1298 static void mv643xx_netpoll(struct net_device *netdev)
1300 struct mv643xx_private *mp = netdev_priv(netdev);
1301 int port_num = mp->port_num;
1303 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_MASK_ALL);
1304 /* wait for previous write to complete */
1305 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num));
1307 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1309 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), INT_UNMASK_ALL);
1316 * First function called after registering the network device.
1317 * It's purpose is to initialize the device as an ethernet device,
1318 * fill the ethernet device structure with pointers * to functions,
1319 * and set the MAC address of the interface
1321 * Input : struct device *
1322 * Output : -ENOMEM if failed , 0 if success
1324 static int mv643xx_eth_probe(struct platform_device *pdev)
1326 struct mv643xx_eth_platform_data *pd;
1327 int port_num = pdev->id;
1328 struct mv643xx_private *mp;
1329 struct net_device *dev;
1331 struct resource *res;
1334 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1338 platform_set_drvdata(pdev, dev);
1340 mp = netdev_priv(dev);
1342 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1344 dev->irq = res->start;
1346 mp->port_num = port_num;
1348 dev->open = mv643xx_eth_open;
1349 dev->stop = mv643xx_eth_stop;
1350 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1351 dev->get_stats = mv643xx_eth_get_stats;
1352 dev->set_mac_address = mv643xx_eth_set_mac_address;
1353 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1355 /* No need to Tx Timeout */
1356 dev->tx_timeout = mv643xx_eth_tx_timeout;
1358 dev->poll = mv643xx_poll;
1362 #ifdef CONFIG_NET_POLL_CONTROLLER
1363 dev->poll_controller = mv643xx_netpoll;
1366 dev->watchdog_timeo = 2 * HZ;
1367 dev->tx_queue_len = mp->tx_ring_size;
1369 dev->change_mtu = mv643xx_eth_change_mtu;
1370 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1372 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1373 #ifdef MAX_SKB_FRAGS
1375 * Zero copy can only work if we use Discovery II memory. Else, we will
1376 * have to map the buffers to ISA memory which is only 16 MB
1378 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1382 /* Configure the timeout task */
1383 INIT_WORK(&mp->tx_timeout_task,
1384 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1386 spin_lock_init(&mp->lock);
1388 /* set default config values */
1389 eth_port_uc_addr_get(dev, dev->dev_addr);
1390 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1391 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1392 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1393 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1394 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1395 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1397 pd = pdev->dev.platform_data;
1399 if (pd->mac_addr != NULL)
1400 memcpy(dev->dev_addr, pd->mac_addr, 6);
1402 if (pd->phy_addr || pd->force_phy_addr)
1403 ethernet_phy_set(port_num, pd->phy_addr);
1405 if (pd->port_config || pd->force_port_config)
1406 mp->port_config = pd->port_config;
1408 if (pd->port_config_extend || pd->force_port_config_extend)
1409 mp->port_config_extend = pd->port_config_extend;
1411 if (pd->port_sdma_config || pd->force_port_sdma_config)
1412 mp->port_sdma_config = pd->port_sdma_config;
1414 if (pd->port_serial_control || pd->force_port_serial_control)
1415 mp->port_serial_control = pd->port_serial_control;
1417 if (pd->rx_queue_size)
1418 mp->rx_ring_size = pd->rx_queue_size;
1420 if (pd->tx_queue_size)
1421 mp->tx_ring_size = pd->tx_queue_size;
1423 if (pd->tx_sram_size) {
1424 mp->tx_sram_size = pd->tx_sram_size;
1425 mp->tx_sram_addr = pd->tx_sram_addr;
1428 if (pd->rx_sram_size) {
1429 mp->rx_sram_size = pd->rx_sram_size;
1430 mp->rx_sram_addr = pd->rx_sram_addr;
1434 err = ethernet_phy_detect(port_num);
1436 pr_debug("MV643xx ethernet port %d: "
1437 "No PHY detected at addr %d\n",
1438 port_num, ethernet_phy_get(port_num));
1442 err = register_netdev(dev);
1448 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1449 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1451 if (dev->features & NETIF_F_SG)
1452 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1454 if (dev->features & NETIF_F_IP_CSUM)
1455 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1458 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1459 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1463 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1468 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1471 if (mp->tx_sram_size > 0)
1472 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1482 static int mv643xx_eth_remove(struct platform_device *pdev)
1484 struct net_device *dev = platform_get_drvdata(pdev);
1486 unregister_netdev(dev);
1487 flush_scheduled_work();
1490 platform_set_drvdata(pdev, NULL);
1494 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1496 struct resource *res;
1498 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1500 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1504 mv643xx_eth_shared_base = ioremap(res->start,
1505 MV643XX_ETH_SHARED_REGS_SIZE);
1506 if (mv643xx_eth_shared_base == NULL)
1513 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1515 iounmap(mv643xx_eth_shared_base);
1516 mv643xx_eth_shared_base = NULL;
1521 static struct platform_driver mv643xx_eth_driver = {
1522 .probe = mv643xx_eth_probe,
1523 .remove = mv643xx_eth_remove,
1525 .name = MV643XX_ETH_NAME,
1529 static struct platform_driver mv643xx_eth_shared_driver = {
1530 .probe = mv643xx_eth_shared_probe,
1531 .remove = mv643xx_eth_shared_remove,
1533 .name = MV643XX_ETH_SHARED_NAME,
1538 * mv643xx_init_module
1540 * Registers the network drivers into the Linux kernel
1546 static int __init mv643xx_init_module(void)
1550 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1552 rc = platform_driver_register(&mv643xx_eth_driver);
1554 platform_driver_unregister(&mv643xx_eth_shared_driver);
1560 * mv643xx_cleanup_module
1562 * Registers the network drivers into the Linux kernel
1568 static void __exit mv643xx_cleanup_module(void)
1570 platform_driver_unregister(&mv643xx_eth_driver);
1571 platform_driver_unregister(&mv643xx_eth_shared_driver);
1574 module_init(mv643xx_init_module);
1575 module_exit(mv643xx_cleanup_module);
1577 MODULE_LICENSE("GPL");
1578 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1579 " and Dale Farnsworth");
1580 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1583 * The second part is the low level driver of the gigE ethernet ports.
1587 * Marvell's Gigabit Ethernet controller low level driver
1590 * This file introduce low level API to Marvell's Gigabit Ethernet
1591 * controller. This Gigabit Ethernet Controller driver API controls
1592 * 1) Operations (i.e. port init, start, reset etc').
1593 * 2) Data flow (i.e. port send, receive etc').
1594 * Each Gigabit Ethernet port is controlled via
1595 * struct mv643xx_private.
1596 * This struct includes user configuration information as well as
1597 * driver internal data needed for its operations.
1599 * Supported Features:
1600 * - This low level driver is OS independent. Allocating memory for
1601 * the descriptor rings and buffers are not within the scope of
1603 * - The user is free from Rx/Tx queue managing.
1604 * - This low level driver introduce functionality API that enable
1605 * the to operate Marvell's Gigabit Ethernet Controller in a
1607 * - Simple Gigabit Ethernet port operation API.
1608 * - Simple Gigabit Ethernet port data flow API.
1609 * - Data flow and operation API support per queue functionality.
1610 * - Support cached descriptors for better performance.
1611 * - Enable access to all four DRAM banks and internal SRAM memory
1613 * - PHY access and control API.
1614 * - Port control register configuration API.
1615 * - Full control over Unicast and Multicast MAC configurations.
1619 * Initialization phase
1620 * This phase complete the initialization of the the
1621 * mv643xx_private struct.
1622 * User information regarding port configuration has to be set
1623 * prior to calling the port initialization routine.
1625 * In this phase any port Tx/Rx activity is halted, MIB counters
1626 * are cleared, PHY address is set according to user parameter and
1627 * access to DRAM and internal SRAM memory spaces.
1629 * Driver ring initialization
1630 * Allocating memory for the descriptor rings and buffers is not
1631 * within the scope of this driver. Thus, the user is required to
1632 * allocate memory for the descriptors ring and buffers. Those
1633 * memory parameters are used by the Rx and Tx ring initialization
1634 * routines in order to curve the descriptor linked list in a form
1636 * Note: Pay special attention to alignment issues when using
1637 * cached descriptors/buffers. In this phase the driver store
1638 * information in the mv643xx_private struct regarding each queue
1642 * This phase prepares the Ethernet port for Rx and Tx activity.
1643 * It uses the information stored in the mv643xx_private struct to
1644 * initialize the various port registers.
1647 * All packet references to/from the driver are done using
1649 * This struct is a unified struct used with Rx and Tx operations.
1650 * This way the user is not required to be familiar with neither
1651 * Tx nor Rx descriptors structures.
1652 * The driver's descriptors rings are management by indexes.
1653 * Those indexes controls the ring resources and used to indicate
1654 * a SW resource error:
1656 * This index points to the current available resource for use. For
1657 * example in Rx process this index will point to the descriptor
1658 * that will be passed to the user upon calling the receive
1659 * routine. In Tx process, this index will point to the descriptor
1660 * that will be assigned with the user packet info and transmitted.
1662 * This index points to the descriptor that need to restore its
1663 * resources. For example in Rx process, using the Rx buffer return
1664 * API will attach the buffer returned in packet info to the
1665 * descriptor pointed by 'used'. In Tx process, using the Tx
1666 * descriptor return will merely return the user packet info with
1667 * the command status of the transmitted buffer pointed by the
1668 * 'used' index. Nevertheless, it is essential to use this routine
1669 * to update the 'used' index.
1671 * This index supports Tx Scatter-Gather. It points to the first
1672 * descriptor of a packet assembled of multiple buffers. For
1673 * example when in middle of Such packet we have a Tx resource
1674 * error the 'curr' index get the value of 'first' to indicate
1675 * that the ring returned to its state before trying to transmit
1678 * Receive operation:
1679 * The eth_port_receive API set the packet information struct,
1680 * passed by the caller, with received information from the
1681 * 'current' SDMA descriptor.
1682 * It is the user responsibility to return this resource back
1683 * to the Rx descriptor ring to enable the reuse of this source.
1684 * Return Rx resource is done using the eth_rx_return_buff API.
1686 * Transmit operation:
1687 * The eth_port_send API supports Scatter-Gather which enables to
1688 * send a packet spanned over multiple buffers. This means that
1689 * for each packet info structure given by the user and put into
1690 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1691 * bit will be set in the packet info command status field. This
1692 * API also consider restriction regarding buffer alignments and
1694 * The user must return a Tx resource after ensuring the buffer
1695 * has been transmitted to enable the Tx ring indexes to update.
1698 * This device is on-board. No jumper diagram is necessary.
1700 * EXTERNAL INTERFACE
1702 * Prior to calling the initialization routine eth_port_init() the user
1703 * must set the following fields under mv643xx_private struct:
1704 * port_num User Ethernet port number.
1705 * port_config User port configuration value.
1706 * port_config_extend User port config extend value.
1707 * port_sdma_config User port SDMA config value.
1708 * port_serial_control User port serial control value.
1710 * This driver data flow is done using the struct pkt_info which
1711 * is a unified struct for Rx and Tx operations:
1713 * byte_cnt Tx/Rx descriptor buffer byte count.
1714 * l4i_chk CPU provided TCP Checksum. For Tx operation
1716 * cmd_sts Tx/Rx descriptor command status.
1717 * buf_ptr Tx/Rx descriptor buffer pointer.
1718 * return_info Tx/Rx user resource return information.
1722 /* SDMA command macros */
1723 #define ETH_ENABLE_TX_QUEUE(eth_port) \
1724 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1729 static int ethernet_phy_get(unsigned int eth_port_num);
1730 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1732 /* Ethernet Port routines */
1733 static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1737 * eth_port_init - Initialize the Ethernet port driver
1740 * This function prepares the ethernet port to start its activity:
1741 * 1) Completes the ethernet port driver struct initialization toward port
1743 * 2) Resets the device to a quiescent state in case of warm reboot.
1744 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1745 * 4) Clean MAC tables. The reset status of those tables is unknown.
1746 * 5) Set PHY address.
1747 * Note: Call this routine prior to eth_port_start routine and after
1748 * setting user values in the user fields of Ethernet port control
1752 * struct mv643xx_private *mp Ethernet port control struct
1760 static void eth_port_init(struct mv643xx_private *mp)
1762 mp->port_rx_queue_command = 0;
1763 mp->port_tx_queue_command = 0;
1765 mp->rx_resource_err = 0;
1766 mp->tx_resource_err = 0;
1768 eth_port_reset(mp->port_num);
1770 eth_port_init_mac_tables(mp->port_num);
1772 ethernet_phy_reset(mp->port_num);
1776 * eth_port_start - Start the Ethernet port activity.
1779 * This routine prepares the Ethernet port for Rx and Tx activity:
1780 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1781 * has been initialized a descriptor's ring (using
1782 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1783 * 2. Initialize and enable the Ethernet configuration port by writing to
1784 * the port's configuration and command registers.
1785 * 3. Initialize and enable the SDMA by writing to the SDMA's
1786 * configuration and command registers. After completing these steps,
1787 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1789 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1790 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1791 * and ether_init_rx_desc_ring for Rx queues).
1794 * dev - a pointer to the required interface
1797 * Ethernet port is ready to receive and transmit.
1802 static void eth_port_start(struct net_device *dev)
1804 struct mv643xx_private *mp = netdev_priv(dev);
1805 unsigned int port_num = mp->port_num;
1806 int tx_curr_desc, rx_curr_desc;
1808 /* Assignment of Tx CTRP of given queue */
1809 tx_curr_desc = mp->tx_curr_desc_q;
1810 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1811 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1813 /* Assignment of Rx CRDP of given queue */
1814 rx_curr_desc = mp->rx_curr_desc_q;
1815 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1816 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1818 /* Add the assigned Ethernet address to the port's address table */
1819 eth_port_uc_addr_set(port_num, dev->dev_addr);
1821 /* Assign port configuration and command. */
1822 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1824 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1825 mp->port_config_extend);
1828 /* Increase the Rx side buffer size if supporting GigE */
1829 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1830 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1831 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1833 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1834 mp->port_serial_control);
1836 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1837 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1838 MV643XX_ETH_SERIAL_PORT_ENABLE);
1840 /* Assign port SDMA configuration */
1841 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1842 mp->port_sdma_config);
1844 /* Enable port Rx. */
1845 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1846 mp->port_rx_queue_command);
1848 /* Disable port bandwidth limits by clearing MTU register */
1849 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1853 * eth_port_uc_addr_set - This function Set the port Unicast address.
1856 * This function Set the port Ethernet MAC address.
1859 * unsigned int eth_port_num Port number.
1860 * char * p_addr Address to be set
1863 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1864 * To set the unicast table with the proper information.
1870 static void eth_port_uc_addr_set(unsigned int eth_port_num,
1871 unsigned char *p_addr)
1876 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1877 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1880 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1881 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1883 /* Accept frames of this address */
1884 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1890 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1891 * (MAC address) from the ethernet hw registers.
1894 * This function retrieves the port Ethernet MAC address.
1897 * unsigned int eth_port_num Port number.
1898 * char *MacAddr pointer where the MAC address is stored
1901 * Copy the MAC address to the location pointed to by MacAddr
1907 static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1909 struct mv643xx_private *mp = netdev_priv(dev);
1913 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1914 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1916 p_addr[0] = (mac_h >> 24) & 0xff;
1917 p_addr[1] = (mac_h >> 16) & 0xff;
1918 p_addr[2] = (mac_h >> 8) & 0xff;
1919 p_addr[3] = mac_h & 0xff;
1920 p_addr[4] = (mac_l >> 8) & 0xff;
1921 p_addr[5] = mac_l & 0xff;
1925 * eth_port_uc_addr - This function Set the port unicast address table
1928 * This function locates the proper entry in the Unicast table for the
1929 * specified MAC nibble and sets its properties according to function
1933 * unsigned int eth_port_num Port number.
1934 * unsigned char uc_nibble Unicast MAC Address last nibble.
1935 * int option 0 = Add, 1 = remove address.
1938 * This function add/removes MAC addresses from the port unicast address
1942 * true is output succeeded.
1943 * false if option parameter is invalid.
1946 static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1949 unsigned int unicast_reg;
1950 unsigned int tbl_offset;
1951 unsigned int reg_offset;
1953 /* Locate the Unicast table entry */
1954 uc_nibble = (0xf & uc_nibble);
1955 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1956 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1959 case REJECT_MAC_ADDR:
1960 /* Clear accepts frame bit at given unicast DA table entry */
1961 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1962 (eth_port_num) + tbl_offset));
1964 unicast_reg &= (0x0E << (8 * reg_offset));
1966 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1967 (eth_port_num) + tbl_offset), unicast_reg);
1970 case ACCEPT_MAC_ADDR:
1971 /* Set accepts frame bit at unicast DA filter table entry */
1973 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1974 (eth_port_num) + tbl_offset));
1976 unicast_reg |= (0x01 << (8 * reg_offset));
1978 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
1979 (eth_port_num) + tbl_offset), unicast_reg);
1991 * The entries in each table are indexed by a hash of a packet's MAC
1992 * address. One bit in each entry determines whether the packet is
1993 * accepted. There are 4 entries (each 8 bits wide) in each register
1994 * of the table. The bits in each entry are defined as follows:
1995 * 0 Accept=1, Drop=0
1996 * 3-1 Queue (ETH_Q0=0)
1999 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2001 unsigned int table_reg;
2002 unsigned int tbl_offset;
2003 unsigned int reg_offset;
2005 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2006 reg_offset = entry % 4; /* Entry offset within the register */
2008 /* Set "accepts frame bit" at specified table entry */
2009 table_reg = mv_read(table + tbl_offset);
2010 table_reg |= 0x01 << (8 * reg_offset);
2011 mv_write(table + tbl_offset, table_reg);
2015 * eth_port_mc_addr - Multicast address settings.
2017 * The MV device supports multicast using two tables:
2018 * 1) Special Multicast Table for MAC addresses of the form
2019 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2020 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2021 * Table entries in the DA-Filter table.
2022 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2023 * is used as an index to the Other Multicast Table entries in the
2024 * DA-Filter table. This function calculates the CRC-8bit value.
2025 * In either case, eth_port_set_filter_table_entry() is then called
2026 * to set to set the actual table entry.
2028 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2032 unsigned char crc_result = 0;
2038 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2039 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2040 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2042 eth_port_set_filter_table_entry(table, p_addr[5]);
2046 /* Calculate CRC-8 out of the given address */
2047 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2048 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2049 (p_addr[4] << 8) | (p_addr[5] << 0);
2051 for (i = 0; i < 32; i++)
2052 mac_array[i] = (mac_l >> i) & 0x1;
2053 for (i = 32; i < 48; i++)
2054 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2056 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2057 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2058 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2059 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2060 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2062 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2063 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2064 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2065 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2066 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2067 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2068 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2070 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2071 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2072 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2073 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2074 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2075 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2077 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2078 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2079 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2080 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2081 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2082 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2084 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2085 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2086 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2087 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2088 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2089 mac_array[3] ^ mac_array[2];
2091 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2092 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2093 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2094 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2095 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2096 mac_array[4] ^ mac_array[3];
2098 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2099 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2100 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2101 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2102 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2105 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2106 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2107 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2108 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2109 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2111 for (i = 0; i < 8; i++)
2112 crc_result = crc_result | (crc[i] << i);
2114 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2115 eth_port_set_filter_table_entry(table, crc_result);
2119 * Set the entire multicast list based on dev->mc_list.
2121 static void eth_port_set_multicast_list(struct net_device *dev)
2124 struct dev_mc_list *mc_list;
2127 struct mv643xx_private *mp = netdev_priv(dev);
2128 unsigned int eth_port_num = mp->port_num;
2130 /* If the device is in promiscuous mode or in all multicast mode,
2131 * we will fully populate both multicast tables with accept.
2132 * This is guaranteed to yield a match on all multicast addresses...
2134 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2135 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2136 /* Set all entries in DA filter special multicast
2138 * Set for ETH_Q0 for now
2140 * 0 Accept=1, Drop=0
2141 * 3-1 Queue ETH_Q0=0
2144 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2146 /* Set all entries in DA filter other multicast
2148 * Set for ETH_Q0 for now
2150 * 0 Accept=1, Drop=0
2151 * 3-1 Queue ETH_Q0=0
2154 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2159 /* We will clear out multicast tables every time we get the list.
2160 * Then add the entire new list...
2162 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2163 /* Clear DA filter special multicast table (Ex_dFSMT) */
2164 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2165 (eth_port_num) + table_index, 0);
2167 /* Clear DA filter other multicast table (Ex_dFOMT) */
2168 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2169 (eth_port_num) + table_index, 0);
2172 /* Get pointer to net_device multicast list and add each one... */
2173 for (i = 0, mc_list = dev->mc_list;
2174 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2175 i++, mc_list = mc_list->next)
2176 if (mc_list->dmi_addrlen == 6)
2177 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2181 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2184 * Go through all the DA filter tables (Unicast, Special Multicast &
2185 * Other Multicast) and set each entry to 0.
2188 * unsigned int eth_port_num Ethernet Port number.
2191 * Multicast and Unicast packets are rejected.
2196 static void eth_port_init_mac_tables(unsigned int eth_port_num)
2200 /* Clear DA filter unicast table (Ex_dFUT) */
2201 for (table_index = 0; table_index <= 0xC; table_index += 4)
2202 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2203 (eth_port_num) + table_index), 0);
2205 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2206 /* Clear DA filter special multicast table (Ex_dFSMT) */
2207 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2208 (eth_port_num) + table_index, 0);
2209 /* Clear DA filter other multicast table (Ex_dFOMT) */
2210 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2211 (eth_port_num) + table_index, 0);
2216 * eth_clear_mib_counters - Clear all MIB counters
2219 * This function clears all MIB counters of a specific ethernet port.
2220 * A read from the MIB counter will reset the counter.
2223 * unsigned int eth_port_num Ethernet Port number.
2226 * After reading all MIB counters, the counters resets.
2229 * MIB counter value.
2232 static void eth_clear_mib_counters(unsigned int eth_port_num)
2236 /* Perform dummy reads from MIB counters */
2237 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2239 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2242 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2244 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2247 static void eth_update_mib_counters(struct mv643xx_private *mp)
2249 struct mv643xx_mib_counters *p = &mp->mib_counters;
2252 p->good_octets_received +=
2253 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2254 p->good_octets_received +=
2255 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2257 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2258 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2260 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2262 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2263 p->good_octets_sent +=
2264 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2266 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2267 offset <= ETH_MIB_LATE_COLLISION;
2269 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2273 * ethernet_phy_detect - Detect whether a phy is present
2276 * This function tests whether there is a PHY present on
2277 * the specified port.
2280 * unsigned int eth_port_num Ethernet Port number.
2287 * -ENODEV on failure
2290 static int ethernet_phy_detect(unsigned int port_num)
2292 unsigned int phy_reg_data0;
2295 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2296 auto_neg = phy_reg_data0 & 0x1000;
2297 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2298 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2300 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2301 if ((phy_reg_data0 & 0x1000) == auto_neg)
2302 return -ENODEV; /* change didn't take */
2304 phy_reg_data0 ^= 0x1000;
2305 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2310 * ethernet_phy_get - Get the ethernet port PHY address.
2313 * This routine returns the given ethernet port PHY address.
2316 * unsigned int eth_port_num Ethernet Port number.
2325 static int ethernet_phy_get(unsigned int eth_port_num)
2327 unsigned int reg_data;
2329 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2331 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2335 * ethernet_phy_set - Set the ethernet port PHY address.
2338 * This routine sets the given ethernet port PHY address.
2341 * unsigned int eth_port_num Ethernet Port number.
2342 * int phy_addr PHY address.
2351 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2354 int addr_shift = 5 * eth_port_num;
2356 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2357 reg_data &= ~(0x1f << addr_shift);
2358 reg_data |= (phy_addr & 0x1f) << addr_shift;
2359 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2363 * ethernet_phy_reset - Reset Ethernet port PHY.
2366 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2369 * unsigned int eth_port_num Ethernet Port number.
2378 static void ethernet_phy_reset(unsigned int eth_port_num)
2380 unsigned int phy_reg_data;
2383 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2384 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2385 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2389 * eth_port_reset - Reset Ethernet port
2392 * This routine resets the chip by aborting any SDMA engine activity and
2393 * clearing the MIB counters. The Receiver and the Transmit unit are in
2394 * idle state after this command is performed and the port is disabled.
2397 * unsigned int eth_port_num Ethernet Port number.
2400 * Channel activity is halted.
2406 static void eth_port_reset(unsigned int port_num)
2408 unsigned int reg_data;
2410 /* Stop Tx port activity. Check port Tx activity. */
2411 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2413 if (reg_data & 0xFF) {
2414 /* Issue stop command for active channels only */
2415 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2418 /* Wait for all Tx activity to terminate. */
2419 /* Check port cause register that all Tx queues are stopped */
2420 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2425 /* Stop Rx port activity. Check port Rx activity. */
2426 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2428 if (reg_data & 0xFF) {
2429 /* Issue stop command for active channels only */
2430 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2433 /* Wait for all Rx activity to terminate. */
2434 /* Check port cause register that all Rx queues are stopped */
2435 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2440 /* Clear all MIB counters */
2441 eth_clear_mib_counters(port_num);
2443 /* Reset the Enable bit in the Configuration Register */
2444 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2445 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2446 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2450 static int eth_port_autoneg_supported(unsigned int eth_port_num)
2452 unsigned int phy_reg_data0;
2454 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2456 return phy_reg_data0 & 0x1000;
2459 static int eth_port_link_is_up(unsigned int eth_port_num)
2461 unsigned int phy_reg_data1;
2463 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2465 if (eth_port_autoneg_supported(eth_port_num)) {
2466 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2468 } else if (phy_reg_data1 & 0x4) /* link up */
2475 * eth_port_read_smi_reg - Read PHY registers
2478 * This routine utilize the SMI interface to interact with the PHY in
2479 * order to perform PHY register read.
2482 * unsigned int port_num Ethernet Port number.
2483 * unsigned int phy_reg PHY register address offset.
2484 * unsigned int *value Register value buffer.
2487 * Write the value of a specified PHY register into given buffer.
2490 * false if the PHY is busy or read data is not in valid state.
2494 static void eth_port_read_smi_reg(unsigned int port_num,
2495 unsigned int phy_reg, unsigned int *value)
2497 int phy_addr = ethernet_phy_get(port_num);
2498 unsigned long flags;
2501 /* the SMI register is a shared resource */
2502 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2504 /* wait for the SMI register to become available */
2505 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2506 if (i == PHY_WAIT_ITERATIONS) {
2507 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2510 udelay(PHY_WAIT_MICRO_SECONDS);
2513 mv_write(MV643XX_ETH_SMI_REG,
2514 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2516 /* now wait for the data to be valid */
2517 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2518 if (i == PHY_WAIT_ITERATIONS) {
2519 printk("mv643xx PHY read timeout, port %d\n", port_num);
2522 udelay(PHY_WAIT_MICRO_SECONDS);
2525 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2527 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2531 * eth_port_write_smi_reg - Write to PHY registers
2534 * This routine utilize the SMI interface to interact with the PHY in
2535 * order to perform writes to PHY registers.
2538 * unsigned int eth_port_num Ethernet Port number.
2539 * unsigned int phy_reg PHY register address offset.
2540 * unsigned int value Register value.
2543 * Write the given value to the specified PHY register.
2546 * false if the PHY is busy.
2550 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2551 unsigned int phy_reg, unsigned int value)
2555 unsigned long flags;
2557 phy_addr = ethernet_phy_get(eth_port_num);
2559 /* the SMI register is a shared resource */
2560 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2562 /* wait for the SMI register to become available */
2563 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2564 if (i == PHY_WAIT_ITERATIONS) {
2565 printk("mv643xx PHY busy timeout, port %d\n",
2569 udelay(PHY_WAIT_MICRO_SECONDS);
2572 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2573 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2575 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2579 * eth_port_send - Send an Ethernet packet
2582 * This routine send a given packet described by p_pktinfo parameter. It
2583 * supports transmitting of a packet spaned over multiple buffers. The
2584 * routine updates 'curr' and 'first' indexes according to the packet
2585 * segment passed to the routine. In case the packet segment is first,
2586 * the 'first' index is update. In any case, the 'curr' index is updated.
2587 * If the routine get into Tx resource error it assigns 'curr' index as
2588 * 'first'. This way the function can abort Tx process of multiple
2589 * descriptors per packet.
2592 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2593 * struct pkt_info *p_pkt_info User packet buffer.
2596 * Tx ring 'curr' and 'first' indexes are updated.
2599 * ETH_QUEUE_FULL in case of Tx resource error.
2600 * ETH_ERROR in case the routine can not access Tx desc ring.
2601 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2605 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2607 * Modified to include the first descriptor pointer in case of SG
2609 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2610 struct pkt_info *p_pkt_info)
2612 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2613 struct eth_tx_desc *current_descriptor;
2614 struct eth_tx_desc *first_descriptor;
2617 /* Do not process Tx ring in case of Tx ring resource error */
2618 if (mp->tx_resource_err)
2619 return ETH_QUEUE_FULL;
2622 * The hardware requires that each buffer that is <= 8 bytes
2623 * in length must be aligned on an 8 byte boundary.
2625 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2627 "mv643xx_eth port %d: packet size <= 8 problem\n",
2633 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2635 /* Get the Tx Desc ring indexes */
2636 tx_desc_curr = mp->tx_curr_desc_q;
2637 tx_desc_used = mp->tx_used_desc_q;
2639 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2641 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2643 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2644 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2645 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2646 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2648 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2649 ETH_BUFFER_OWNED_BY_DMA;
2650 if (command & ETH_TX_FIRST_DESC) {
2651 tx_first_desc = tx_desc_curr;
2652 mp->tx_first_desc_q = tx_first_desc;
2653 first_descriptor = current_descriptor;
2654 mp->tx_first_command = command;
2656 tx_first_desc = mp->tx_first_desc_q;
2657 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2658 BUG_ON(first_descriptor == NULL);
2659 current_descriptor->cmd_sts = command;
2662 if (command & ETH_TX_LAST_DESC) {
2664 first_descriptor->cmd_sts = mp->tx_first_command;
2667 ETH_ENABLE_TX_QUEUE(mp->port_num);
2670 * Finish Tx packet. Update first desc in case of Tx resource
2672 tx_first_desc = tx_next_desc;
2673 mp->tx_first_desc_q = tx_first_desc;
2676 /* Check for ring index overlap in the Tx desc ring */
2677 if (tx_next_desc == tx_desc_used) {
2678 mp->tx_resource_err = 1;
2679 mp->tx_curr_desc_q = tx_first_desc;
2681 return ETH_QUEUE_LAST_RESOURCE;
2684 mp->tx_curr_desc_q = tx_next_desc;
2689 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2690 struct pkt_info *p_pkt_info)
2694 struct eth_tx_desc *current_descriptor;
2695 unsigned int command_status;
2697 /* Do not process Tx ring in case of Tx ring resource error */
2698 if (mp->tx_resource_err)
2699 return ETH_QUEUE_FULL;
2702 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2704 /* Get the Tx Desc ring indexes */
2705 tx_desc_curr = mp->tx_curr_desc_q;
2706 tx_desc_used = mp->tx_used_desc_q;
2707 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2709 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2710 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2711 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2712 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2714 /* Set last desc with DMA ownership and interrupt enable. */
2716 current_descriptor->cmd_sts = command_status |
2717 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2720 ETH_ENABLE_TX_QUEUE(mp->port_num);
2722 /* Finish Tx packet. Update first desc in case of Tx resource error */
2723 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2725 /* Update the current descriptor */
2726 mp->tx_curr_desc_q = tx_desc_curr;
2728 /* Check for ring index overlap in the Tx desc ring */
2729 if (tx_desc_curr == tx_desc_used) {
2730 mp->tx_resource_err = 1;
2731 return ETH_QUEUE_LAST_RESOURCE;
2739 * eth_tx_return_desc - Free all used Tx descriptors
2742 * This routine returns the transmitted packet information to the caller.
2743 * It uses the 'first' index to support Tx desc return in case a transmit
2744 * of a packet spanned over multiple buffer still in process.
2745 * In case the Tx queue was in "resource error" condition, where there are
2746 * no available Tx resources, the function resets the resource error flag.
2749 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2750 * struct pkt_info *p_pkt_info User packet buffer.
2753 * Tx ring 'first' and 'used' indexes are updated.
2757 * ETH_ERROR otherwise.
2760 static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2761 struct pkt_info *p_pkt_info)
2765 struct eth_tx_desc *p_tx_desc_used;
2766 unsigned int command_status;
2767 unsigned long flags;
2770 spin_lock_irqsave(&mp->lock, flags);
2772 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2773 tx_busy_desc = mp->tx_first_desc_q;
2775 tx_busy_desc = mp->tx_curr_desc_q;
2778 /* Get the Tx Desc ring indexes */
2779 tx_desc_used = mp->tx_used_desc_q;
2781 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2784 if (p_tx_desc_used == NULL) {
2789 /* Stop release. About to overlap the current available Tx descriptor */
2790 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err) {
2795 command_status = p_tx_desc_used->cmd_sts;
2797 /* Still transmitting... */
2798 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2803 /* Pass the packet information to the caller */
2804 p_pkt_info->cmd_sts = command_status;
2805 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2806 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2807 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
2808 mp->tx_skb[tx_desc_used] = NULL;
2810 /* Update the next descriptor to release. */
2811 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2813 /* Any Tx return cancels the Tx resource error status */
2814 mp->tx_resource_err = 0;
2816 BUG_ON(mp->tx_ring_skbs == 0);
2820 spin_unlock_irqrestore(&mp->lock, flags);
2826 * eth_port_receive - Get received information from Rx ring.
2829 * This routine returns the received data to the caller. There is no
2830 * data copying during routine operation. All information is returned
2831 * using pointer to packet information struct passed from the caller.
2832 * If the routine exhausts Rx ring resources then the resource error flag
2836 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2837 * struct pkt_info *p_pkt_info User packet buffer.
2840 * Rx ring current and used indexes are updated.
2843 * ETH_ERROR in case the routine can not access Rx desc ring.
2844 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2845 * ETH_END_OF_JOB if there is no received data.
2848 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2849 struct pkt_info *p_pkt_info)
2851 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2852 volatile struct eth_rx_desc *p_rx_desc;
2853 unsigned int command_status;
2854 unsigned long flags;
2856 /* Do not process Rx ring in case of Rx ring resource error */
2857 if (mp->rx_resource_err)
2858 return ETH_QUEUE_FULL;
2860 spin_lock_irqsave(&mp->lock, flags);
2862 /* Get the Rx Desc ring 'curr and 'used' indexes */
2863 rx_curr_desc = mp->rx_curr_desc_q;
2864 rx_used_desc = mp->rx_used_desc_q;
2866 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2868 /* The following parameters are used to save readings from memory */
2869 command_status = p_rx_desc->cmd_sts;
2872 /* Nothing to receive... */
2873 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2874 spin_unlock_irqrestore(&mp->lock, flags);
2875 return ETH_END_OF_JOB;
2878 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2879 p_pkt_info->cmd_sts = command_status;
2880 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2881 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2882 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2885 * Clean the return info field to indicate that the
2886 * packet has been moved to the upper layers
2888 mp->rx_skb[rx_curr_desc] = NULL;
2890 /* Update current index in data structure */
2891 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2892 mp->rx_curr_desc_q = rx_next_curr_desc;
2894 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2895 if (rx_next_curr_desc == rx_used_desc)
2896 mp->rx_resource_err = 1;
2898 spin_unlock_irqrestore(&mp->lock, flags);
2904 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2907 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2908 * next 'used' descriptor and attached the returned buffer to it.
2909 * In case the Rx ring was in "resource error" condition, where there are
2910 * no available Rx resources, the function resets the resource error flag.
2913 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2914 * struct pkt_info *p_pkt_info Information on returned buffer.
2917 * New available Rx resource in Rx descriptor ring.
2920 * ETH_ERROR in case the routine can not access Rx desc ring.
2923 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2924 struct pkt_info *p_pkt_info)
2926 int used_rx_desc; /* Where to return Rx resource */
2927 volatile struct eth_rx_desc *p_used_rx_desc;
2928 unsigned long flags;
2930 spin_lock_irqsave(&mp->lock, flags);
2932 /* Get 'used' Rx descriptor */
2933 used_rx_desc = mp->rx_used_desc_q;
2934 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2936 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2937 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2938 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2940 /* Flush the write pipe */
2942 /* Return the descriptor to DMA ownership */
2944 p_used_rx_desc->cmd_sts =
2945 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2948 /* Move the used descriptor pointer to the next descriptor */
2949 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
2951 /* Any Rx return cancels the Rx resource error status */
2952 mp->rx_resource_err = 0;
2954 spin_unlock_irqrestore(&mp->lock, flags);
2959 /************* Begin ethtool support *************************/
2961 struct mv643xx_stats {
2962 char stat_string[ETH_GSTRING_LEN];
2967 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2968 offsetof(struct mv643xx_private, m)
2970 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
2971 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
2972 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
2973 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
2974 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
2975 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
2976 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
2977 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
2978 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
2979 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
2980 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
2981 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
2982 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
2983 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
2984 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
2985 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
2986 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
2987 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
2988 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
2989 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
2990 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
2991 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
2992 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
2993 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
2994 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
2995 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
2996 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
2997 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
2998 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
2999 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3000 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3001 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3002 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3003 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3004 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3005 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3006 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3007 { "collision", MV643XX_STAT(mib_counters.collision) },
3008 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3011 #define MV643XX_STATS_LEN \
3012 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
3015 mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
3017 struct mv643xx_private *mp = netdev->priv;
3018 int port_num = mp->port_num;
3019 int autoneg = eth_port_autoneg_supported(port_num);
3022 int half_duplex = 0;
3023 int full_duplex = 0;
3029 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
3030 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
3032 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
3035 ecmd->supported = SUPPORTED_10baseT_Half;
3037 ecmd->supported = (SUPPORTED_10baseT_Half |
3038 SUPPORTED_10baseT_Full |
3039 SUPPORTED_100baseT_Half |
3040 SUPPORTED_100baseT_Full |
3041 SUPPORTED_1000baseT_Full |
3042 (autoneg ? SUPPORTED_Autoneg : 0) |
3045 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
3046 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
3048 ecmd->advertising = ADVERTISED_TP;
3051 ecmd->advertising |= ADVERTISED_Autoneg;
3057 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
3068 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
3070 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
3076 if (speed_10 & half_duplex)
3077 ecmd->advertising |= ADVERTISED_10baseT_Half;
3078 if (speed_10 & full_duplex)
3079 ecmd->advertising |= ADVERTISED_10baseT_Full;
3080 if (speed_100 & half_duplex)
3081 ecmd->advertising |= ADVERTISED_100baseT_Half;
3082 if (speed_100 & full_duplex)
3083 ecmd->advertising |= ADVERTISED_100baseT_Full;
3085 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3089 ecmd->port = PORT_TP;
3090 ecmd->phy_address = ethernet_phy_get(port_num);
3092 ecmd->transceiver = XCVR_EXTERNAL;
3094 if (netif_carrier_ok(netdev)) {
3096 ecmd->speed = SPEED_10;
3098 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
3099 ecmd->speed = SPEED_1000;
3100 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
3101 ecmd->speed = SPEED_100;
3103 ecmd->speed = SPEED_10;
3106 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
3107 ecmd->duplex = DUPLEX_FULL;
3109 ecmd->duplex = DUPLEX_HALF;
3115 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3119 static void mv643xx_get_drvinfo(struct net_device *netdev,
3120 struct ethtool_drvinfo *drvinfo)
3122 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3123 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3124 strncpy(drvinfo->fw_version, "N/A", 32);
3125 strncpy(drvinfo->bus_info, "mv643xx", 32);
3126 drvinfo->n_stats = MV643XX_STATS_LEN;
3129 static int mv643xx_get_stats_count(struct net_device *netdev)
3131 return MV643XX_STATS_LEN;
3134 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
3135 struct ethtool_stats *stats, uint64_t *data)
3137 struct mv643xx_private *mp = netdev->priv;
3140 eth_update_mib_counters(mp);
3142 for (i = 0; i < MV643XX_STATS_LEN; i++) {
3143 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3144 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3145 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3149 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3156 for (i=0; i < MV643XX_STATS_LEN; i++) {
3157 memcpy(data + i * ETH_GSTRING_LEN,
3158 mv643xx_gstrings_stats[i].stat_string,
3165 static struct ethtool_ops mv643xx_ethtool_ops = {
3166 .get_settings = mv643xx_get_settings,
3167 .get_drvinfo = mv643xx_get_drvinfo,
3168 .get_link = ethtool_op_get_link,
3169 .get_sg = ethtool_op_get_sg,
3170 .set_sg = ethtool_op_set_sg,
3171 .get_strings = mv643xx_get_strings,
3172 .get_stats_count = mv643xx_get_stats_count,
3173 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3176 /************* End ethtool support *************************/