Merge branch 'master' into 85xx
[linux-2.6] / drivers / char / drm / via_dma.c
1 /* via_dma.c -- DMA support for the VIA Unichrome/Pro
2  *
3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4  * All Rights Reserved.
5  *
6  * Copyright 2004 Digeo, Inc., Palo Alto, CA, U.S.A.
7  * All Rights Reserved.
8  *
9  * Copyright 2004 The Unichrome project.
10  * All Rights Reserved.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a
13  * copy of this software and associated documentation files (the "Software"),
14  * to deal in the Software without restriction, including without limitation
15  * the rights to use, copy, modify, merge, publish, distribute, sub license,
16  * and/or sell copies of the Software, and to permit persons to whom the
17  * Software is furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice (including the
20  * next paragraph) shall be included in all copies or substantial portions
21  * of the Software.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
26  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
27  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
28  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
29  * USE OR OTHER DEALINGS IN THE SOFTWARE.
30  *
31  * Authors:
32  *    Tungsten Graphics,
33  *    Erdi Chen,
34  *    Thomas Hellstrom.
35  */
36
37 #include "drmP.h"
38 #include "drm.h"
39 #include "via_drm.h"
40 #include "via_drv.h"
41 #include "via_3d_reg.h"
42
43 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
44 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
45
46 /* defines for VIA 3D registers */
47 #define VIA_REG_STATUS          0x400
48 #define VIA_REG_TRANSET         0x43C
49 #define VIA_REG_TRANSPACE       0x440
50
51 /* VIA_REG_STATUS(0x400): Engine Status */
52 #define VIA_CMD_RGTR_BUSY       0x00000080      /* Command Regulator is busy */
53 #define VIA_2D_ENG_BUSY         0x00000001      /* 2D Engine is busy */
54 #define VIA_3D_ENG_BUSY         0x00000002      /* 3D Engine is busy */
55 #define VIA_VR_QUEUE_BUSY       0x00020000      /* Virtual Queue is busy */
56
57 #define SetReg2DAGP(nReg, nData) {                              \
58         *((uint32_t *)(vb)) = ((nReg) >> 2) | HALCYON_HEADER1;  \
59         *((uint32_t *)(vb) + 1) = (nData);                      \
60         vb = ((uint32_t *)vb) + 2;                              \
61         dev_priv->dma_low +=8;                                  \
62 }
63
64 #define via_flush_write_combine() DRM_MEMORYBARRIER()
65
66 #define VIA_OUT_RING_QW(w1,w2)                  \
67         *vb++ = (w1);                           \
68         *vb++ = (w2);                           \
69         dev_priv->dma_low += 8;
70
71 static void via_cmdbuf_start(drm_via_private_t * dev_priv);
72 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
73 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
74 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
75 static int via_wait_idle(drm_via_private_t * dev_priv);
76 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords);
77
78 /*
79  * Free space in command buffer.
80  */
81
82 static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv)
83 {
84         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
85         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
86
87         return ((hw_addr <= dev_priv->dma_low) ?
88                 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) :
89                 (hw_addr - dev_priv->dma_low));
90 }
91
92 /*
93  * How much does the command regulator lag behind?
94  */
95
96 static uint32_t via_cmdbuf_lag(drm_via_private_t * dev_priv)
97 {
98         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
99         uint32_t hw_addr = *(dev_priv->hw_addr_ptr) - agp_base;
100
101         return ((hw_addr <= dev_priv->dma_low) ?
102                 (dev_priv->dma_low - hw_addr) :
103                 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr));
104 }
105
106 /*
107  * Check that the given size fits in the buffer, otherwise wait.
108  */
109
110 static inline int
111 via_cmdbuf_wait(drm_via_private_t * dev_priv, unsigned int size)
112 {
113         uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
114         uint32_t cur_addr, hw_addr, next_addr;
115         volatile uint32_t *hw_addr_ptr;
116         uint32_t count;
117         hw_addr_ptr = dev_priv->hw_addr_ptr;
118         cur_addr = dev_priv->dma_low;
119         next_addr = cur_addr + size + 512 * 1024;
120         count = 1000000;
121         do {
122                 hw_addr = *hw_addr_ptr - agp_base;
123                 if (count-- == 0) {
124                         DRM_ERROR
125                             ("via_cmdbuf_wait timed out hw %x cur_addr %x next_addr %x\n",
126                              hw_addr, cur_addr, next_addr);
127                         return -1;
128                 }
129         } while ((cur_addr < hw_addr) && (next_addr >= hw_addr));
130         return 0;
131 }
132
133 /*
134  * Checks whether buffer head has reach the end. Rewind the ring buffer
135  * when necessary.
136  *
137  * Returns virtual pointer to ring buffer.
138  */
139
140 static inline uint32_t *via_check_dma(drm_via_private_t * dev_priv,
141                                       unsigned int size)
142 {
143         if ((dev_priv->dma_low + size + 4 * CMDBUF_ALIGNMENT_SIZE) >
144             dev_priv->dma_high) {
145                 via_cmdbuf_rewind(dev_priv);
146         }
147         if (via_cmdbuf_wait(dev_priv, size) != 0) {
148                 return NULL;
149         }
150
151         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
152 }
153
154 int via_dma_cleanup(drm_device_t * dev)
155 {
156         if (dev->dev_private) {
157                 drm_via_private_t *dev_priv =
158                     (drm_via_private_t *) dev->dev_private;
159
160                 if (dev_priv->ring.virtual_start) {
161                         via_cmdbuf_reset(dev_priv);
162
163                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
164                         dev_priv->ring.virtual_start = NULL;
165                 }
166
167         }
168
169         return 0;
170 }
171
172 static int via_initialize(drm_device_t * dev,
173                           drm_via_private_t * dev_priv,
174                           drm_via_dma_init_t * init)
175 {
176         if (!dev_priv || !dev_priv->mmio) {
177                 DRM_ERROR("via_dma_init called before via_map_init\n");
178                 return DRM_ERR(EFAULT);
179         }
180
181         if (dev_priv->ring.virtual_start != NULL) {
182                 DRM_ERROR("%s called again without calling cleanup\n",
183                           __FUNCTION__);
184                 return DRM_ERR(EFAULT);
185         }
186
187         if (!dev->agp || !dev->agp->base) {
188                 DRM_ERROR("%s called with no agp memory available\n",
189                           __FUNCTION__);
190                 return DRM_ERR(EFAULT);
191         }
192
193         if (dev_priv->chipset == VIA_DX9_0) {
194                 DRM_ERROR("AGP DMA is not supported on this chip\n");
195                 return DRM_ERR(EINVAL);
196         }
197
198         dev_priv->ring.map.offset = dev->agp->base + init->offset;
199         dev_priv->ring.map.size = init->size;
200         dev_priv->ring.map.type = 0;
201         dev_priv->ring.map.flags = 0;
202         dev_priv->ring.map.mtrr = 0;
203
204         drm_core_ioremap(&dev_priv->ring.map, dev);
205
206         if (dev_priv->ring.map.handle == NULL) {
207                 via_dma_cleanup(dev);
208                 DRM_ERROR("can not ioremap virtual address for"
209                           " ring buffer\n");
210                 return DRM_ERR(ENOMEM);
211         }
212
213         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
214
215         dev_priv->dma_ptr = dev_priv->ring.virtual_start;
216         dev_priv->dma_low = 0;
217         dev_priv->dma_high = init->size;
218         dev_priv->dma_wrap = init->size;
219         dev_priv->dma_offset = init->offset;
220         dev_priv->last_pause_ptr = NULL;
221         dev_priv->hw_addr_ptr =
222                 (volatile uint32_t *)((char *)dev_priv->mmio->handle +
223                 init->reg_pause_addr);
224
225         via_cmdbuf_start(dev_priv);
226
227         return 0;
228 }
229
230 static int via_dma_init(DRM_IOCTL_ARGS)
231 {
232         DRM_DEVICE;
233         drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private;
234         drm_via_dma_init_t init;
235         int retcode = 0;
236
237         DRM_COPY_FROM_USER_IOCTL(init, (drm_via_dma_init_t __user *) data,
238                                  sizeof(init));
239
240         switch (init.func) {
241         case VIA_INIT_DMA:
242                 if (!DRM_SUSER(DRM_CURPROC))
243                         retcode = DRM_ERR(EPERM);
244                 else
245                         retcode = via_initialize(dev, dev_priv, &init);
246                 break;
247         case VIA_CLEANUP_DMA:
248                 if (!DRM_SUSER(DRM_CURPROC))
249                         retcode = DRM_ERR(EPERM);
250                 else
251                         retcode = via_dma_cleanup(dev);
252                 break;
253         case VIA_DMA_INITIALIZED:
254                 retcode = (dev_priv->ring.virtual_start != NULL) ?
255                     0 : DRM_ERR(EFAULT);
256                 break;
257         default:
258                 retcode = DRM_ERR(EINVAL);
259                 break;
260         }
261
262         return retcode;
263 }
264
265 static int via_dispatch_cmdbuffer(drm_device_t * dev, drm_via_cmdbuffer_t * cmd)
266 {
267         drm_via_private_t *dev_priv;
268         uint32_t *vb;
269         int ret;
270
271         dev_priv = (drm_via_private_t *) dev->dev_private;
272
273         if (dev_priv->ring.virtual_start == NULL) {
274                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
275                           __FUNCTION__);
276                 return DRM_ERR(EFAULT);
277         }
278
279         if (cmd->size > VIA_PCI_BUF_SIZE) {
280                 return DRM_ERR(ENOMEM);
281         }
282
283         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
284                 return DRM_ERR(EFAULT);
285
286         /*
287          * Running this function on AGP memory is dead slow. Therefore
288          * we run it on a temporary cacheable system memory buffer and
289          * copy it to AGP memory when ready.
290          */
291
292         if ((ret =
293              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
294                                        cmd->size, dev, 1))) {
295                 return ret;
296         }
297
298         vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);
299         if (vb == NULL) {
300                 return DRM_ERR(EAGAIN);
301         }
302
303         memcpy(vb, dev_priv->pci_buf, cmd->size);
304
305         dev_priv->dma_low += cmd->size;
306
307         /*
308          * Small submissions somehow stalls the CPU. (AGP cache effects?)
309          * pad to greater size.
310          */
311
312         if (cmd->size < 0x100)
313                 via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);
314         via_cmdbuf_pause(dev_priv);
315
316         return 0;
317 }
318
319 int via_driver_dma_quiescent(drm_device_t * dev)
320 {
321         drm_via_private_t *dev_priv = dev->dev_private;
322
323         if (!via_wait_idle(dev_priv)) {
324                 return DRM_ERR(EBUSY);
325         }
326         return 0;
327 }
328
329 static int via_flush_ioctl(DRM_IOCTL_ARGS)
330 {
331         DRM_DEVICE;
332
333         LOCK_TEST_WITH_RETURN(dev, filp);
334
335         return via_driver_dma_quiescent(dev);
336 }
337
338 static int via_cmdbuffer(DRM_IOCTL_ARGS)
339 {
340         DRM_DEVICE;
341         drm_via_cmdbuffer_t cmdbuf;
342         int ret;
343
344         LOCK_TEST_WITH_RETURN(dev, filp);
345
346         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
347                                  sizeof(cmdbuf));
348
349         DRM_DEBUG("via cmdbuffer, buf %p size %lu\n", cmdbuf.buf, cmdbuf.size);
350
351         ret = via_dispatch_cmdbuffer(dev, &cmdbuf);
352         if (ret) {
353                 return ret;
354         }
355
356         return 0;
357 }
358
359 static int via_dispatch_pci_cmdbuffer(drm_device_t * dev,
360                                       drm_via_cmdbuffer_t * cmd)
361 {
362         drm_via_private_t *dev_priv = dev->dev_private;
363         int ret;
364
365         if (cmd->size > VIA_PCI_BUF_SIZE) {
366                 return DRM_ERR(ENOMEM);
367         }
368         if (DRM_COPY_FROM_USER(dev_priv->pci_buf, cmd->buf, cmd->size))
369                 return DRM_ERR(EFAULT);
370
371         if ((ret =
372              via_verify_command_stream((uint32_t *) dev_priv->pci_buf,
373                                        cmd->size, dev, 0))) {
374                 return ret;
375         }
376
377         ret =
378             via_parse_command_stream(dev, (const uint32_t *)dev_priv->pci_buf,
379                                      cmd->size);
380         return ret;
381 }
382
383 static int via_pci_cmdbuffer(DRM_IOCTL_ARGS)
384 {
385         DRM_DEVICE;
386         drm_via_cmdbuffer_t cmdbuf;
387         int ret;
388
389         LOCK_TEST_WITH_RETURN(dev, filp);
390
391         DRM_COPY_FROM_USER_IOCTL(cmdbuf, (drm_via_cmdbuffer_t __user *) data,
392                                  sizeof(cmdbuf));
393
394         DRM_DEBUG("via_pci_cmdbuffer, buf %p size %lu\n", cmdbuf.buf,
395                   cmdbuf.size);
396
397         ret = via_dispatch_pci_cmdbuffer(dev, &cmdbuf);
398         if (ret) {
399                 return ret;
400         }
401
402         return 0;
403 }
404
405 static inline uint32_t *via_align_buffer(drm_via_private_t * dev_priv,
406                                          uint32_t * vb, int qw_count)
407 {
408         for (; qw_count > 0; --qw_count) {
409                 VIA_OUT_RING_QW(HC_DUMMY, HC_DUMMY);
410         }
411         return vb;
412 }
413
414 /*
415  * This function is used internally by ring buffer mangement code.
416  *
417  * Returns virtual pointer to ring buffer.
418  */
419 static inline uint32_t *via_get_dma(drm_via_private_t * dev_priv)
420 {
421         return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low);
422 }
423
424 /*
425  * Hooks a segment of data into the tail of the ring-buffer by
426  * modifying the pause address stored in the buffer itself. If
427  * the regulator has already paused, restart it.
428  */
429 static int via_hook_segment(drm_via_private_t * dev_priv,
430                             uint32_t pause_addr_hi, uint32_t pause_addr_lo,
431                             int no_pci_fire)
432 {
433         int paused, count;
434         volatile uint32_t *paused_at = dev_priv->last_pause_ptr;
435
436         via_flush_write_combine();
437         while (!*(via_get_dma(dev_priv) - 1)) ;
438         *dev_priv->last_pause_ptr = pause_addr_lo;
439         via_flush_write_combine();
440
441         /*
442          * The below statement is inserted to really force the flush.
443          * Not sure it is needed.
444          */
445
446         while (!*dev_priv->last_pause_ptr) ;
447         dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1;
448         while (!*dev_priv->last_pause_ptr) ;
449
450         paused = 0;
451         count = 20;
452
453         while (!(paused = (VIA_READ(0x41c) & 0x80000000)) && count--) ;
454         if ((count <= 8) && (count >= 0)) {
455                 uint32_t rgtr, ptr;
456                 rgtr = *(dev_priv->hw_addr_ptr);
457                 ptr = ((volatile char *)dev_priv->last_pause_ptr -
458                       dev_priv->dma_ptr) + dev_priv->dma_offset +
459                       (uint32_t) dev_priv->agpAddr + 4 - CMDBUF_ALIGNMENT_SIZE;
460                 if (rgtr <= ptr) {
461                         DRM_ERROR
462                             ("Command regulator\npaused at count %d, address %x, "
463                              "while current pause address is %x.\n"
464                              "Please mail this message to "
465                              "<unichrome-devel@lists.sourceforge.net>\n", count,
466                              rgtr, ptr);
467                 }
468         }
469
470         if (paused && !no_pci_fire) {
471                 uint32_t rgtr, ptr;
472                 uint32_t ptr_low;
473
474                 count = 1000000;
475                 while ((VIA_READ(VIA_REG_STATUS) & VIA_CMD_RGTR_BUSY)
476                        && count--) ;
477
478                 rgtr = *(dev_priv->hw_addr_ptr);
479                 ptr = ((volatile char *)paused_at - dev_priv->dma_ptr) +
480                     dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4;
481
482                 ptr_low = (ptr > 3 * CMDBUF_ALIGNMENT_SIZE) ?
483                     ptr - 3 * CMDBUF_ALIGNMENT_SIZE : 0;
484                 if (rgtr <= ptr && rgtr >= ptr_low) {
485                         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
486                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
487                         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
488                         VIA_READ(VIA_REG_TRANSPACE);
489                 }
490         }
491         return paused;
492 }
493
494 static int via_wait_idle(drm_via_private_t * dev_priv)
495 {
496         int count = 10000000;
497         while (count-- && (VIA_READ(VIA_REG_STATUS) &
498                            (VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY |
499                             VIA_3D_ENG_BUSY))) ;
500         return count;
501 }
502
503 static uint32_t *via_align_cmd(drm_via_private_t * dev_priv, uint32_t cmd_type,
504                                uint32_t addr, uint32_t * cmd_addr_hi,
505                                uint32_t * cmd_addr_lo, int skip_wait)
506 {
507         uint32_t agp_base;
508         uint32_t cmd_addr, addr_lo, addr_hi;
509         uint32_t *vb;
510         uint32_t qw_pad_count;
511
512         if (!skip_wait)
513                 via_cmdbuf_wait(dev_priv, 2 * CMDBUF_ALIGNMENT_SIZE);
514
515         vb = via_get_dma(dev_priv);
516         VIA_OUT_RING_QW(HC_HEADER2 | ((VIA_REG_TRANSET >> 2) << 12) |
517                         (VIA_REG_TRANSPACE >> 2), HC_ParaType_PreCR << 16);
518         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
519         qw_pad_count = (CMDBUF_ALIGNMENT_SIZE >> 3) -
520             ((dev_priv->dma_low & CMDBUF_ALIGNMENT_MASK) >> 3);
521
522         cmd_addr = (addr) ? addr :
523             agp_base + dev_priv->dma_low - 8 + (qw_pad_count << 3);
524         addr_lo = ((HC_SubA_HAGPBpL << 24) | (cmd_type & HC_HAGPBpID_MASK) |
525                    (cmd_addr & HC_HAGPBpL_MASK));
526         addr_hi = ((HC_SubA_HAGPBpH << 24) | (cmd_addr >> 24));
527
528         vb = via_align_buffer(dev_priv, vb, qw_pad_count - 1);
529         VIA_OUT_RING_QW(*cmd_addr_hi = addr_hi, *cmd_addr_lo = addr_lo);
530         return vb;
531 }
532
533 static void via_cmdbuf_start(drm_via_private_t * dev_priv)
534 {
535         uint32_t pause_addr_lo, pause_addr_hi;
536         uint32_t start_addr, start_addr_lo;
537         uint32_t end_addr, end_addr_lo;
538         uint32_t command;
539         uint32_t agp_base;
540
541         dev_priv->dma_low = 0;
542
543         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
544         start_addr = agp_base;
545         end_addr = agp_base + dev_priv->dma_high;
546
547         start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));
548         end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));
549         command = ((HC_SubA_HAGPCMNT << 24) | (start_addr >> 24) |
550                    ((end_addr & 0xff000000) >> 16));
551
552         dev_priv->last_pause_ptr =
553             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,
554                           &pause_addr_hi, &pause_addr_lo, 1) - 1;
555
556         via_flush_write_combine();
557         while (!*dev_priv->last_pause_ptr) ;
558
559         VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16));
560         VIA_WRITE(VIA_REG_TRANSPACE, command);
561         VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo);
562         VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo);
563
564         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
565         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
566         DRM_WRITEMEMORYBARRIER();
567         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
568         VIA_READ(VIA_REG_TRANSPACE);
569 }
570
571 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords)
572 {
573         uint32_t *vb;
574
575         via_cmdbuf_wait(dev_priv, qwords + 2);
576         vb = via_get_dma(dev_priv);
577         VIA_OUT_RING_QW(HC_HEADER2, HC_ParaType_NotTex << 16);
578         via_align_buffer(dev_priv, vb, qwords);
579 }
580
581 static inline void via_dummy_bitblt(drm_via_private_t * dev_priv)
582 {
583         uint32_t *vb = via_get_dma(dev_priv);
584         SetReg2DAGP(0x0C, (0 | (0 << 16)));
585         SetReg2DAGP(0x10, 0 | (0 << 16));
586         SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);
587 }
588
589 static void via_cmdbuf_jump(drm_via_private_t * dev_priv)
590 {
591         uint32_t agp_base;
592         uint32_t pause_addr_lo, pause_addr_hi;
593         uint32_t jump_addr_lo, jump_addr_hi;
594         volatile uint32_t *last_pause_ptr;
595         uint32_t dma_low_save1, dma_low_save2;
596
597         agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr;
598         via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,
599                       &jump_addr_lo, 0);
600
601         dev_priv->dma_wrap = dev_priv->dma_low;
602
603         /*
604          * Wrap command buffer to the beginning.
605          */
606
607         dev_priv->dma_low = 0;
608         if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0) {
609                 DRM_ERROR("via_cmdbuf_jump failed\n");
610         }
611
612         via_dummy_bitblt(dev_priv);
613         via_dummy_bitblt(dev_priv);
614
615         last_pause_ptr =
616             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
617                           &pause_addr_lo, 0) - 1;
618         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
619                       &pause_addr_lo, 0);
620
621         *last_pause_ptr = pause_addr_lo;
622         dma_low_save1 = dev_priv->dma_low;
623
624         /*
625          * Now, set a trap that will pause the regulator if it tries to rerun the old
626          * command buffer. (Which may happen if via_hook_segment detecs a command regulator pause
627          * and reissues the jump command over PCI, while the regulator has already taken the jump
628          * and actually paused at the current buffer end).
629          * There appears to be no other way to detect this condition, since the hw_addr_pointer
630          * does not seem to get updated immediately when a jump occurs.
631          */
632
633         last_pause_ptr =
634             via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
635                           &pause_addr_lo, 0) - 1;
636         via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,
637                       &pause_addr_lo, 0);
638         *last_pause_ptr = pause_addr_lo;
639
640         dma_low_save2 = dev_priv->dma_low;
641         dev_priv->dma_low = dma_low_save1;
642         via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);
643         dev_priv->dma_low = dma_low_save2;
644         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
645 }
646
647 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv)
648 {
649         via_cmdbuf_jump(dev_priv);
650 }
651
652 static void via_cmdbuf_flush(drm_via_private_t * dev_priv, uint32_t cmd_type)
653 {
654         uint32_t pause_addr_lo, pause_addr_hi;
655
656         via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);
657         via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);
658 }
659
660 static void via_cmdbuf_pause(drm_via_private_t * dev_priv)
661 {
662         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_PAUSE);
663 }
664
665 static void via_cmdbuf_reset(drm_via_private_t * dev_priv)
666 {
667         via_cmdbuf_flush(dev_priv, HC_HAGPBpID_STOP);
668         via_wait_idle(dev_priv);
669 }
670
671 /*
672  * User interface to the space and lag functions.
673  */
674
675 static int via_cmdbuf_size(DRM_IOCTL_ARGS)
676 {
677         DRM_DEVICE;
678         drm_via_cmdbuf_size_t d_siz;
679         int ret = 0;
680         uint32_t tmp_size, count;
681         drm_via_private_t *dev_priv;
682
683         DRM_DEBUG("via cmdbuf_size\n");
684         LOCK_TEST_WITH_RETURN(dev, filp);
685
686         dev_priv = (drm_via_private_t *) dev->dev_private;
687
688         if (dev_priv->ring.virtual_start == NULL) {
689                 DRM_ERROR("%s called without initializing AGP ring buffer.\n",
690                           __FUNCTION__);
691                 return DRM_ERR(EFAULT);
692         }
693
694         DRM_COPY_FROM_USER_IOCTL(d_siz, (drm_via_cmdbuf_size_t __user *) data,
695                                  sizeof(d_siz));
696
697         count = 1000000;
698         tmp_size = d_siz.size;
699         switch (d_siz.func) {
700         case VIA_CMDBUF_SPACE:
701                 while (((tmp_size = via_cmdbuf_space(dev_priv)) < d_siz.size)
702                        && count--) {
703                         if (!d_siz.wait) {
704                                 break;
705                         }
706                 }
707                 if (!count) {
708                         DRM_ERROR("VIA_CMDBUF_SPACE timed out.\n");
709                         ret = DRM_ERR(EAGAIN);
710                 }
711                 break;
712         case VIA_CMDBUF_LAG:
713                 while (((tmp_size = via_cmdbuf_lag(dev_priv)) > d_siz.size)
714                        && count--) {
715                         if (!d_siz.wait) {
716                                 break;
717                         }
718                 }
719                 if (!count) {
720                         DRM_ERROR("VIA_CMDBUF_LAG timed out.\n");
721                         ret = DRM_ERR(EAGAIN);
722                 }
723                 break;
724         default:
725                 ret = DRM_ERR(EFAULT);
726         }
727         d_siz.size = tmp_size;
728
729         DRM_COPY_TO_USER_IOCTL((drm_via_cmdbuf_size_t __user *) data, d_siz,
730                                sizeof(d_siz));
731         return ret;
732 }
733
734 drm_ioctl_desc_t via_ioctls[] = {
735         [DRM_IOCTL_NR(DRM_VIA_ALLOCMEM)] = {via_mem_alloc, DRM_AUTH},
736         [DRM_IOCTL_NR(DRM_VIA_FREEMEM)] = {via_mem_free, DRM_AUTH},
737         [DRM_IOCTL_NR(DRM_VIA_AGP_INIT)] = {via_agp_init, DRM_AUTH|DRM_MASTER},
738         [DRM_IOCTL_NR(DRM_VIA_FB_INIT)] = {via_fb_init, DRM_AUTH|DRM_MASTER},
739         [DRM_IOCTL_NR(DRM_VIA_MAP_INIT)] = {via_map_init, DRM_AUTH|DRM_MASTER},
740         [DRM_IOCTL_NR(DRM_VIA_DEC_FUTEX)] = {via_decoder_futex, DRM_AUTH},
741         [DRM_IOCTL_NR(DRM_VIA_DMA_INIT)] = {via_dma_init, DRM_AUTH},
742         [DRM_IOCTL_NR(DRM_VIA_CMDBUFFER)] = {via_cmdbuffer, DRM_AUTH},
743         [DRM_IOCTL_NR(DRM_VIA_FLUSH)] = {via_flush_ioctl, DRM_AUTH},
744         [DRM_IOCTL_NR(DRM_VIA_PCICMD)] = {via_pci_cmdbuffer, DRM_AUTH},
745         [DRM_IOCTL_NR(DRM_VIA_CMDBUF_SIZE)] = {via_cmdbuf_size, DRM_AUTH},
746         [DRM_IOCTL_NR(DRM_VIA_WAIT_IRQ)] = {via_wait_irq, DRM_AUTH},
747         [DRM_IOCTL_NR(DRM_VIA_DMA_BLIT)] = {via_dma_blit, DRM_AUTH},
748         [DRM_IOCTL_NR(DRM_VIA_BLIT_SYNC)] = {via_dma_blit_sync, DRM_AUTH}
749 };
750
751 int via_max_ioctl = DRM_ARRAY_SIZE(via_ioctls);