2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
9 * Copyright (C) 1999 by Ralf Baechle
11 #ifndef _ASM_SN_SN0_ADDRS_H
12 #define _ASM_SN_SN0_ADDRS_H
14 #include <linux/config.h>
17 * SN0 (on a T5) Address map
19 * This file contains a set of definitions and macros which are used
20 * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
21 * and UNCAC) used by the SN0 architecture. It also contains addresses
22 * for "major" statically locatable PROM/Kernel data structures, such as
23 * the partition table, the configuration data structure, etc.
24 * We make an implicit assumption that the processor using this file
25 * follows the R10K's provisions for specifying uncached attributes;
26 * should this change, the base registers may very well become processor-
29 * For more information on the address spaces, see the "Local Resources"
30 * chapter of the Hub specification.
32 * NOTE: This header file is included both by C and by assembler source
33 * files. Please bracket any language-dependent definitions
38 * Some of the macros here need to be casted to appropriate types when used
39 * from C. They definitely must not be casted from assembly language so we
40 * use some new ANSI preprocessor stuff to paste these on where needed.
44 * The following couple of definitions will eventually need to be variables,
45 * since the amount of address space assigned to each node depends on
46 * whether the system is running in N-mode (more nodes with less memory)
47 * or M-mode (fewer nodes with more memory). We expect that it will
48 * be a while before we need to make this decision dynamically, though,
49 * so for now we just use defines bracketed by an ifdef.
52 #ifdef CONFIG_SGI_SN0_N_MODE
54 #define NODE_SIZE_BITS 31
55 #define BWIN_SIZE_BITS 28
58 #define NASID_BITMASK (0x1ffLL)
60 #define NASID_META_BITS 5
61 #define NASID_LOCAL_BITS 4
63 #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
64 #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
66 #else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
68 #define NODE_SIZE_BITS 32
69 #define BWIN_SIZE_BITS 29
71 #define NASID_BITMASK (0xffLL)
74 #define NASID_META_BITS 4
75 #define NASID_LOCAL_BITS 4
77 #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
78 #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
80 #endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
82 #define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
84 #define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT)
85 #define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
86 NASID_SHFT) & NASID_BITMASK)
88 #if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
90 #define NODE_SWIN_BASE(nasid, widget) \
91 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
92 : RAW_NODE_SWIN_BASE(nasid, widget))
93 #else /* __ASSEMBLY__ || _STANDALONE */
94 #define NODE_SWIN_BASE(nasid, widget) \
95 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
96 #endif /* __ASSEMBLY__ || _STANDALONE */
99 * The following definitions pertain to the IO special address
100 * space. They define the location of the big and little windows
104 #define BWIN_INDEX_BITS 3
105 #define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS)
106 #define BWIN_SIZEMASK (BWIN_SIZE - 1)
107 #define BWIN_WIDGET_MASK 0x7
108 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
109 #define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
110 (UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
112 #define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
113 #define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
115 * Verify if addr belongs to large window address of node with "nasid"
118 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
124 #define NODE_BWIN_ADDR(nasid, addr) \
125 (((addr) >= NODE_BWIN_BASE0(nasid)) && \
126 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
130 * The following define the major position-independent aliases used
132 * CALIAS -- Varies in size, points to the first n bytes of memory
133 * on the reader's node.
136 #define CALIAS_BASE CAC_BASE
140 #define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \
141 ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
143 #define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
145 /* Turn on sable logging for the processors whose bits are set. */
146 #define SABLE_LOG_TRIGGER(_map)
149 #define KERN_NMI_ADDR(nasid, slice) \
150 TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \
151 (IP27_NMI_KREGS_CPU_SIZE * (slice)))
152 #endif /* !__ASSEMBLY__ */
156 #define MISC_PROM_BASE PHYS_TO_K0(0x01300000)
157 #define MISC_PROM_SIZE 0x200000
159 #define DIAG_BASE PHYS_TO_K0(0x01500000)
160 #define DIAG_SIZE 0x300000
162 #define ROUTE_BASE PHYS_TO_K0(0x01800000)
163 #define ROUTE_SIZE 0x200000
165 #define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000)
166 #define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000)
167 #define IP27PROM_CORP_MAX 32
168 #define IP27PROM_CORP PHYS_TO_K0(0x01800000)
169 #define IP27PROM_CORP_SIZE 0x10000
170 #define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000)
171 #define IP27PROM_CORP_STKSIZE 0x2000
172 #define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000)
173 #define IP27PROM_DECOMP_SIZE 0xfff00
175 #define IP27PROM_BASE PHYS_TO_K0(0x01a00000)
176 #define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000)
177 #define IP27PROM_SIZE_MAX 0x100000
179 #define IP27PROM_PCFG PHYS_TO_K0(0x01b00000)
180 #define IP27PROM_PCFG_SIZE 0xd0000
181 #define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000)
182 #define IP27PROM_ERRDMP_SIZE 0xf000
184 #define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000)
185 #define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000)
186 #define IP27PROM_CONSOLE_SIZE 0x200
187 #define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200)
188 #define IP27PROM_NETUART_SIZE 0x100
189 #define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300)
190 #define IP27PROM_UNUSED1_SIZE 0x500
191 #define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800)
192 #define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00)
193 #define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000)
194 #define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000)
195 #define IP27PROM_STACK_SHFT 16
196 #define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT)
197 #define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000)
199 #define SLAVESTACK_BASE PHYS_TO_K0(0x01580000)
200 #define SLAVESTACK_SIZE 0x40000
202 #define ENETBUFS_BASE PHYS_TO_K0(0x01f80000)
203 #define ENETBUFS_SIZE 0x20000
205 #define IO6PROM_BASE PHYS_TO_K0(0x01c00000)
206 #define IO6PROM_SIZE 0x400000
207 #define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000)
208 #define IO6DPROM_BASE PHYS_TO_K0(0x01c00000)
209 #define IO6DPROM_SIZE 0x200000
211 #define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000)
212 #define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000)
214 #define IP27PROM_INT_LAUNCH 10 /* and 11 */
215 #define IP27PROM_INT_NETUART 12 /* through 17 */
220 * needed by symmon so it needs to be outside #if PROM
222 #define IP27PROM_ELSC_SHFT 10
223 #define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT)
226 * This address is used by IO6PROM to build MemoryDescriptors of
227 * free memory. This address is important since unix gets loaded
228 * at this address, and this memory has to be FREE if unix is to
232 #define FREEMEM_BASE PHYS_TO_K0(0x2000000)
234 #define IO6PROM_STACK_SHFT 14 /* stack per cpu */
235 #define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT)
241 #define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000)
242 #define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008)
243 #define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010)
244 #define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018)
245 #define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020)
246 #define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028)
247 #define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030)
248 #define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038)
249 #define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040)
250 #define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048)
252 #define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */
253 #define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */
254 #define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */
255 #define KL_I2C_REG MD_UREG0_0 /* I2C reg */
259 /* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
260 * CACHE_ERR_SP_PTR could either contain an address to the stack, or
261 * the stack could start at CACHE_ERR_SP_PTR
263 #if defined (HUB_ERR_STS_WAR)
264 #define CACHE_ERR_EFRAME 0x480
265 #else /* HUB_ERR_STS_WAR */
266 #define CACHE_ERR_EFRAME 0x400
267 #endif /* HUB_ERR_STS_WAR */
269 #define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE)
270 #define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */
271 #define CACHE_ERR_IBASE_PTR (0x1000 - 40)
272 #define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16)
273 #define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
275 #endif /* !__ASSEMBLY__ */
282 * The PROM needs to pass the device base address and the
283 * device pci cfg space address to the device drivers during
284 * install. The COMPONENT->Key field is used for this purpose.
285 * Macros needed by SN0 device drivers to convert the
286 * COMPONENT->Key field to the respective base address.
287 * Key field looks as follows:
289 * +----------------------------------------------------+
290 * |devnasid | widget |pciid |hubwidid|hstnasid | adap |
291 * | 2 | 1 | 1 | 1 | 2 | 1 |
292 * +----------------------------------------------------+
296 * These are used by standalone drivers till the io infrastructure
302 #define uchar unsigned char
304 #define KEY_DEVNASID_SHFT 48
305 #define KEY_WIDID_SHFT 40
306 #define KEY_PCIID_SHFT 32
307 #define KEY_HUBWID_SHFT 24
308 #define KEY_HSTNASID_SHFT 8
310 #define MK_SN0_KEY(nasid, widid, pciid) \
311 ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
312 ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
313 ((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
315 #define ADD_HUBWID_KEY(key,hubwid)\
316 (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
318 #define ADD_HSTNASID_KEY(key,hstnasid)\
319 (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
321 #define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT))
322 #define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT))
323 #define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT))
324 #define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT))
325 #define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT))
327 #define PCI_64_TARGID_SHFT 60
329 #define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
330 GET_WIDID_FROM_KEY(key))\
331 | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
333 #define GET_PCICFGBASE_FROM_KEY(key) \
334 (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
335 GET_WIDID_FROM_KEY(key))\
336 | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
338 #define GET_WIDBASE_FROM_KEY(key) \
339 (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
340 GET_WIDID_FROM_KEY(key)))
342 #define PUT_INSTALL_STATUS(c,s) c->Revision = s
343 #define GET_INSTALL_STATUS(c) c->Revision
345 #endif /* !__ASSEMBLY__ */
347 #endif /* _STANDALONE */
349 #if defined (HUB_ERR_STS_WAR)
351 #define ERR_STS_WAR_REGISTER IIO_IIBUSERR
352 #define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR)
353 #define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
354 /* Used to match addr in error reg. */
355 #define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
357 #endif /* HUB_ERR_STS_WAR */
359 #endif /* _ASM_SN_SN0_ADDRS_H */