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   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/highmem.h>
  14 #include <linux/pci.h>
  15 #include <linux/dma-mapping.h>
  16
  17 #include <linux/mmc/host.h>
  18
  19 #include <asm/scatterlist.h>
  20
  21 #include "sdhci.h"
  22
  23 #define DRIVER_NAME "sdhci"
  24
  25 #define DBG(f, x...) \
  26         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  27
  28 static unsigned int debug_nodma = 0;
  29 static unsigned int debug_forcedma = 0;
  30 static unsigned int debug_quirks = 0;
  31
  32 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
  33 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
  34 /* Controller doesn't like some resets when there is no card inserted. */
  35 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
  36 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
  37 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
  38
  39 static const struct pci_device_id pci_ids[] __devinitdata = {
  40         {
  41                 .vendor         = PCI_VENDOR_ID_RICOH,
  42                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  43                 .subvendor      = PCI_VENDOR_ID_IBM,
  44                 .subdevice      = PCI_ANY_ID,
  45                 .driver_data    = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  46                                   SDHCI_QUIRK_FORCE_DMA,
  47         },
  48
  49         {
  50                 .vendor         = PCI_VENDOR_ID_RICOH,
  51                 .device         = PCI_DEVICE_ID_RICOH_R5C822,
  52                 .subvendor      = PCI_ANY_ID,
  53                 .subdevice      = PCI_ANY_ID,
  54                 .driver_data    = SDHCI_QUIRK_FORCE_DMA |
  55                                   SDHCI_QUIRK_NO_CARD_NO_RESET,
  56         },
  57
  58         {
  59                 .vendor         = PCI_VENDOR_ID_TI,
  60                 .device         = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  61                 .subvendor      = PCI_ANY_ID,
  62                 .subdevice      = PCI_ANY_ID,
  63                 .driver_data    = SDHCI_QUIRK_FORCE_DMA,
  64         },
  65
  66         {
  67                 .vendor         = PCI_VENDOR_ID_ENE,
  68                 .device         = PCI_DEVICE_ID_ENE_CB712_SD,
  69                 .subvendor      = PCI_ANY_ID,
  70                 .subdevice      = PCI_ANY_ID,
  71                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE,
  72         },
  73
  74         {
  75                 .vendor         = PCI_VENDOR_ID_ENE,
  76                 .device         = PCI_DEVICE_ID_ENE_CB712_SD_2,
  77                 .subvendor      = PCI_ANY_ID,
  78                 .subdevice      = PCI_ANY_ID,
  79                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE,
  80         },
  81
  82         {
  83                 .vendor         = PCI_VENDOR_ID_ENE,
  84                 .device         = PCI_DEVICE_ID_ENE_CB714_SD,
  85                 .subvendor      = PCI_ANY_ID,
  86                 .subdevice      = PCI_ANY_ID,
  87                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  88                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
  89         },
  90
  91         {
  92                 .vendor         = PCI_VENDOR_ID_ENE,
  93                 .device         = PCI_DEVICE_ID_ENE_CB714_SD_2,
  94                 .subvendor      = PCI_ANY_ID,
  95                 .subdevice      = PCI_ANY_ID,
  96                 .driver_data    = SDHCI_QUIRK_SINGLE_POWER_WRITE |
  97                                   SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
  98         },
  99
 100         {       /* Generic SD host controller */
 101                 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
 102         },
 103
 104         { /* end: all zeroes */ },
 105 };
 106
 107 MODULE_DEVICE_TABLE(pci, pci_ids);
 108
 109 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
 110 static void sdhci_finish_data(struct sdhci_host *);
 111
 112 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
 113 static void sdhci_finish_command(struct sdhci_host *);
 114
 115 static void sdhci_dumpregs(struct sdhci_host *host)
 116 {
 117         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
 118
 119         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
 120                 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 121                 readw(host->ioaddr + SDHCI_HOST_VERSION));
 122         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
 123                 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
 124                 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
 125         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
 126                 readl(host->ioaddr + SDHCI_ARGUMENT),
 127                 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
 128         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
 129                 readl(host->ioaddr + SDHCI_PRESENT_STATE),
 130                 readb(host->ioaddr + SDHCI_HOST_CONTROL));
 131         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 132                 readb(host->ioaddr + SDHCI_POWER_CONTROL),
 133                 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
 134         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 135                 readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
 136                 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
 137         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 138                 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
 139                 readl(host->ioaddr + SDHCI_INT_STATUS));
 140         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 141                 readl(host->ioaddr + SDHCI_INT_ENABLE),
 142                 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
 143         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 144                 readw(host->ioaddr + SDHCI_ACMD12_ERR),
 145                 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
 146         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
 147                 readl(host->ioaddr + SDHCI_CAPABILITIES),
 148                 readl(host->ioaddr + SDHCI_MAX_CURRENT));
 149
 150         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
 151 }
 152
 153 /*****************************************************************************\
 154  *                                                                           *
 155  * Low level functions                                                       *
 156  *                                                                           *
 157 \*****************************************************************************/
 158
 159 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 160 {
 161         unsigned long timeout;
 162
 163         if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 164                 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 165                         SDHCI_CARD_PRESENT))
 166                         return;
 167         }
 168
 169         writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
 170
 171         if (mask & SDHCI_RESET_ALL)
 172                 host->clock = 0;
 173
 174         /* Wait max 100 ms */
 175         timeout = 100;
 176
 177         /* hw clears the bit when it's done */
 178         while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
 179                 if (timeout == 0) {
 180                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 181                                 mmc_hostname(host->mmc), (int)mask);
 182                         sdhci_dumpregs(host);
 183                         return;
 184                 }
 185                 timeout--;
 186                 mdelay(1);
 187         }
 188 }
 189
 190 static void sdhci_init(struct sdhci_host *host)
 191 {
 192         u32 intmask;
 193
 194         sdhci_reset(host, SDHCI_RESET_ALL);
 195
 196         intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 197                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 198                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 199                 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
 200                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
 201                 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
 202
 203         writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
 204         writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 205 }
 206
 207 static void sdhci_activate_led(struct sdhci_host *host)
 208 {
 209         u8 ctrl;
 210
 211         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 212         ctrl |= SDHCI_CTRL_LED;
 213         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 214 }
 215
 216 static void sdhci_deactivate_led(struct sdhci_host *host)
 217 {
 218         u8 ctrl;
 219
 220         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 221         ctrl &= ~SDHCI_CTRL_LED;
 222         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 223 }
 224
 225 /*****************************************************************************\
 226  *                                                                           *
 227  * Core functions                                                            *
 228  *                                                                           *
 229 \*****************************************************************************/
 230
 231 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
 232 {
 233         return page_address(host->cur_sg->page) + host->cur_sg->offset;
 234 }
 235
 236 static inline int sdhci_next_sg(struct sdhci_host* host)
 237 {
 238         /*
 239          * Skip to next SG entry.
 240          */
 241         host->cur_sg++;
 242         host->num_sg--;
 243
 244         /*
 245          * Any entries left?
 246          */
 247         if (host->num_sg > 0) {
 248                 host->offset = 0;
 249                 host->remain = host->cur_sg->length;
 250         }
 251
 252         return host->num_sg;
 253 }
 254
 255 static void sdhci_read_block_pio(struct sdhci_host *host)
 256 {
 257         int blksize, chunk_remain;
 258         u32 data;
 259         char *buffer;
 260         int size;
 261
 262         DBG("PIO reading\n");
 263
 264         blksize = host->data->blksz;
 265         chunk_remain = 0;
 266         data = 0;
 267
 268         buffer = sdhci_sg_to_buffer(host) + host->offset;
 269
 270         while (blksize) {
 271                 if (chunk_remain == 0) {
 272                         data = readl(host->ioaddr + SDHCI_BUFFER);
 273                         chunk_remain = min(blksize, 4);
 274                 }
 275
 276                 size = min(host->remain, chunk_remain);
 277
 278                 chunk_remain -= size;
 279                 blksize -= size;
 280                 host->offset += size;
 281                 host->remain -= size;
 282
 283                 while (size) {
 284                         *buffer = data & 0xFF;
 285                         buffer++;
 286                         data >>= 8;
 287                         size--;
 288                 }
 289
 290                 if (host->remain == 0) {
 291                         if (sdhci_next_sg(host) == 0) {
 292                                 BUG_ON(blksize != 0);
 293                                 return;
 294                         }
 295                         buffer = sdhci_sg_to_buffer(host);
 296                 }
 297         }
 298 }
 299
 300 static void sdhci_write_block_pio(struct sdhci_host *host)
 301 {
 302         int blksize, chunk_remain;
 303         u32 data;
 304         char *buffer;
 305         int bytes, size;
 306
 307         DBG("PIO writing\n");
 308
 309         blksize = host->data->blksz;
 310         chunk_remain = 4;
 311         data = 0;
 312
 313         bytes = 0;
 314         buffer = sdhci_sg_to_buffer(host) + host->offset;
 315
 316         while (blksize) {
 317                 size = min(host->remain, chunk_remain);
 318
 319                 chunk_remain -= size;
 320                 blksize -= size;
 321                 host->offset += size;
 322                 host->remain -= size;
 323
 324                 while (size) {
 325                         data >>= 8;
 326                         data |= (u32)*buffer << 24;
 327                         buffer++;
 328                         size--;
 329                 }
 330
 331                 if (chunk_remain == 0) {
 332                         writel(data, host->ioaddr + SDHCI_BUFFER);
 333                         chunk_remain = min(blksize, 4);
 334                 }
 335
 336                 if (host->remain == 0) {
 337                         if (sdhci_next_sg(host) == 0) {
 338                                 BUG_ON(blksize != 0);
 339                                 return;
 340                         }
 341                         buffer = sdhci_sg_to_buffer(host);
 342                 }
 343         }
 344 }
 345
 346 static void sdhci_transfer_pio(struct sdhci_host *host)
 347 {
 348         u32 mask;
 349
 350         BUG_ON(!host->data);
 351
 352         if (host->num_sg == 0)
 353                 return;
 354
 355         if (host->data->flags & MMC_DATA_READ)
 356                 mask = SDHCI_DATA_AVAILABLE;
 357         else
 358                 mask = SDHCI_SPACE_AVAILABLE;
 359
 360         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 361                 if (host->data->flags & MMC_DATA_READ)
 362                         sdhci_read_block_pio(host);
 363                 else
 364                         sdhci_write_block_pio(host);
 365
 366                 if (host->num_sg == 0)
 367                         break;
 368         }
 369
 370         DBG("PIO transfer complete.\n");
 371 }
 372
 373 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 374 {
 375         u8 count;
 376         unsigned target_timeout, current_timeout;
 377
 378         WARN_ON(host->data);
 379
 380         if (data == NULL)
 381                 return;
 382
 383         /* Sanity checks */
 384         BUG_ON(data->blksz * data->blocks > 524288);
 385         BUG_ON(data->blksz > host->mmc->max_blk_size);
 386         BUG_ON(data->blocks > 65535);
 387
 388         /* timeout in us */
 389         target_timeout = data->timeout_ns / 1000 +
 390                 data->timeout_clks / host->clock;
 391
 392         /*
 393          * Figure out needed cycles.
 394          * We do this in steps in order to fit inside a 32 bit int.
 395          * The first step is the minimum timeout, which will have a
 396          * minimum resolution of 6 bits:
 397          * (1) 2^13*1000 > 2^22,
 398          * (2) host->timeout_clk < 2^16
 399          *     =>
 400          *     (1) / (2) > 2^6
 401          */
 402         count = 0;
 403         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 404         while (current_timeout < target_timeout) {
 405                 count++;
 406                 current_timeout <<= 1;
 407                 if (count >= 0xF)
 408                         break;
 409         }
 410
 411         if (count >= 0xF) {
 412                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 413                         mmc_hostname(host->mmc));
 414                 count = 0xE;
 415         }
 416
 417         writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
 418
 419         if (host->flags & SDHCI_USE_DMA) {
 420                 int count;
 421
 422                 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
 423                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 424                 BUG_ON(count != 1);
 425
 426                 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
 427         } else {
 428                 host->cur_sg = data->sg;
 429                 host->num_sg = data->sg_len;
 430
 431                 host->offset = 0;
 432                 host->remain = host->cur_sg->length;
 433         }
 434
 435         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 436         writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
 437                 host->ioaddr + SDHCI_BLOCK_SIZE);
 438         writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
 439 }
 440
 441 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 442         struct mmc_data *data)
 443 {
 444         u16 mode;
 445
 446         WARN_ON(host->data);
 447
 448         if (data == NULL)
 449                 return;
 450
 451         mode = SDHCI_TRNS_BLK_CNT_EN;
 452         if (data->blocks > 1)
 453                 mode |= SDHCI_TRNS_MULTI;
 454         if (data->flags & MMC_DATA_READ)
 455                 mode |= SDHCI_TRNS_READ;
 456         if (host->flags & SDHCI_USE_DMA)
 457                 mode |= SDHCI_TRNS_DMA;
 458
 459         writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
 460 }
 461
 462 static void sdhci_finish_data(struct sdhci_host *host)
 463 {
 464         struct mmc_data *data;
 465         u16 blocks;
 466
 467         BUG_ON(!host->data);
 468
 469         data = host->data;
 470         host->data = NULL;
 471
 472         if (host->flags & SDHCI_USE_DMA) {
 473                 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
 474                         (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
 475         }
 476
 477         /*
 478          * Controller doesn't count down when in single block mode.
 479          */
 480         if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
 481                 blocks = 0;
 482         else
 483                 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
 484         data->bytes_xfered = data->blksz * (data->blocks - blocks);
 485
 486         if ((data->error == MMC_ERR_NONE) && blocks) {
 487                 printk(KERN_ERR "%s: Controller signalled completion even "
 488                         "though there were blocks left.\n",
 489                         mmc_hostname(host->mmc));
 490                 data->error = MMC_ERR_FAILED;
 491         }
 492
 493         if (data->stop) {
 494                 /*
 495                  * The controller needs a reset of internal state machines
 496                  * upon error conditions.
 497                  */
 498                 if (data->error != MMC_ERR_NONE) {
 499                         sdhci_reset(host, SDHCI_RESET_CMD);
 500                         sdhci_reset(host, SDHCI_RESET_DATA);
 501                 }
 502
 503                 sdhci_send_command(host, data->stop);
 504         } else
 505                 tasklet_schedule(&host->finish_tasklet);
 506 }
 507
 508 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 509 {
 510         int flags;
 511         u32 mask;
 512         unsigned long timeout;
 513
 514         WARN_ON(host->cmd);
 515
 516         /* Wait max 10 ms */
 517         timeout = 10;
 518
 519         mask = SDHCI_CMD_INHIBIT;
 520         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 521                 mask |= SDHCI_DATA_INHIBIT;
 522
 523         /* We shouldn't wait for data inihibit for stop commands, even
 524            though they might use busy signaling */
 525         if (host->mrq->data && (cmd == host->mrq->data->stop))
 526                 mask &= ~SDHCI_DATA_INHIBIT;
 527
 528         while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
 529                 if (timeout == 0) {
 530                         printk(KERN_ERR "%s: Controller never released "
 531                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 532                         sdhci_dumpregs(host);
 533                         cmd->error = MMC_ERR_FAILED;
 534                         tasklet_schedule(&host->finish_tasklet);
 535                         return;
 536                 }
 537                 timeout--;
 538                 mdelay(1);
 539         }
 540
 541         mod_timer(&host->timer, jiffies + 10 * HZ);
 542
 543         host->cmd = cmd;
 544
 545         sdhci_prepare_data(host, cmd->data);
 546
 547         writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
 548
 549         sdhci_set_transfer_mode(host, cmd->data);
 550
 551         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 552                 printk(KERN_ERR "%s: Unsupported response type!\n",
 553                         mmc_hostname(host->mmc));
 554                 cmd->error = MMC_ERR_INVALID;
 555                 tasklet_schedule(&host->finish_tasklet);
 556                 return;
 557         }
 558
 559         if (!(cmd->flags & MMC_RSP_PRESENT))
 560                 flags = SDHCI_CMD_RESP_NONE;
 561         else if (cmd->flags & MMC_RSP_136)
 562                 flags = SDHCI_CMD_RESP_LONG;
 563         else if (cmd->flags & MMC_RSP_BUSY)
 564                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 565         else
 566                 flags = SDHCI_CMD_RESP_SHORT;
 567
 568         if (cmd->flags & MMC_RSP_CRC)
 569                 flags |= SDHCI_CMD_CRC;
 570         if (cmd->flags & MMC_RSP_OPCODE)
 571                 flags |= SDHCI_CMD_INDEX;
 572         if (cmd->data)
 573                 flags |= SDHCI_CMD_DATA;
 574
 575         writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
 576                 host->ioaddr + SDHCI_COMMAND);
 577 }
 578
 579 static void sdhci_finish_command(struct sdhci_host *host)
 580 {
 581         int i;
 582
 583         BUG_ON(host->cmd == NULL);
 584
 585         if (host->cmd->flags & MMC_RSP_PRESENT) {
 586                 if (host->cmd->flags & MMC_RSP_136) {
 587                         /* CRC is stripped so we need to do some shifting. */
 588                         for (i = 0;i < 4;i++) {
 589                                 host->cmd->resp[i] = readl(host->ioaddr +
 590                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 591                                 if (i != 3)
 592                                         host->cmd->resp[i] |=
 593                                                 readb(host->ioaddr +
 594                                                 SDHCI_RESPONSE + (3-i)*4-1);
 595                         }
 596                 } else {
 597                         host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
 598                 }
 599         }
 600
 601         host->cmd->error = MMC_ERR_NONE;
 602
 603         if (host->cmd->data)
 604                 host->data = host->cmd->data;
 605         else
 606                 tasklet_schedule(&host->finish_tasklet);
 607
 608         host->cmd = NULL;
 609 }
 610
 611 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 612 {
 613         int div;
 614         u16 clk;
 615         unsigned long timeout;
 616
 617         if (clock == host->clock)
 618                 return;
 619
 620         writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
 621
 622         if (clock == 0)
 623                 goto out;
 624
 625         for (div = 1;div < 256;div *= 2) {
 626                 if ((host->max_clk / div) <= clock)
 627                         break;
 628         }
 629         div >>= 1;
 630
 631         clk = div << SDHCI_DIVIDER_SHIFT;
 632         clk |= SDHCI_CLOCK_INT_EN;
 633         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 634
 635         /* Wait max 10 ms */
 636         timeout = 10;
 637         while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
 638                 & SDHCI_CLOCK_INT_STABLE)) {
 639                 if (timeout == 0) {
 640                         printk(KERN_ERR "%s: Internal clock never "
 641                                 "stabilised.\n", mmc_hostname(host->mmc));
 642                         sdhci_dumpregs(host);
 643                         return;
 644                 }
 645                 timeout--;
 646                 mdelay(1);
 647         }
 648
 649         clk |= SDHCI_CLOCK_CARD_EN;
 650         writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
 651
 652 out:
 653         host->clock = clock;
 654 }
 655
 656 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 657 {
 658         u8 pwr;
 659
 660         if (host->power == power)
 661                 return;
 662
 663         if (power == (unsigned short)-1) {
 664                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 665                 goto out;
 666         }
 667
 668         /*
 669          * Spec says that we should clear the power reg before setting
 670          * a new value. Some controllers don't seem to like this though.
 671          */
 672         if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
 673                 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
 674
 675         pwr = SDHCI_POWER_ON;
 676
 677         switch (1 << power) {
 678         case MMC_VDD_165_195:
 679                 pwr |= SDHCI_POWER_180;
 680                 break;
 681         case MMC_VDD_29_30:
 682         case MMC_VDD_30_31:
 683                 pwr |= SDHCI_POWER_300;
 684                 break;
 685         case MMC_VDD_32_33:
 686         case MMC_VDD_33_34:
 687                 pwr |= SDHCI_POWER_330;
 688                 break;
 689         default:
 690                 BUG();
 691         }
 692
 693         writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
 694
 695 out:
 696         host->power = power;
 697 }
 698
 699 /*****************************************************************************\
 700  *                                                                           *
 701  * MMC callbacks                                                             *
 702  *                                                                           *
 703 \*****************************************************************************/
 704
 705 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 706 {
 707         struct sdhci_host *host;
 708         unsigned long flags;
 709
 710         host = mmc_priv(mmc);
 711
 712         spin_lock_irqsave(&host->lock, flags);
 713
 714         WARN_ON(host->mrq != NULL);
 715
 716         sdhci_activate_led(host);
 717
 718         host->mrq = mrq;
 719
 720         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 721                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
 722                 tasklet_schedule(&host->finish_tasklet);
 723         } else
 724                 sdhci_send_command(host, mrq->cmd);
 725
 726         mmiowb();
 727         spin_unlock_irqrestore(&host->lock, flags);
 728 }
 729
 730 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 731 {
 732         struct sdhci_host *host;
 733         unsigned long flags;
 734         u8 ctrl;
 735
 736         host = mmc_priv(mmc);
 737
 738         spin_lock_irqsave(&host->lock, flags);
 739
 740         /*
 741          * Reset the chip on each power off.
 742          * Should clear out any weird states.
 743          */
 744         if (ios->power_mode == MMC_POWER_OFF) {
 745                 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
 746                 sdhci_init(host);
 747         }
 748
 749         sdhci_set_clock(host, ios->clock);
 750
 751         if (ios->power_mode == MMC_POWER_OFF)
 752                 sdhci_set_power(host, -1);
 753         else
 754                 sdhci_set_power(host, ios->vdd);
 755
 756         ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
 757
 758         if (ios->bus_width == MMC_BUS_WIDTH_4)
 759                 ctrl |= SDHCI_CTRL_4BITBUS;
 760         else
 761                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 762
 763         if (ios->timing == MMC_TIMING_SD_HS)
 764                 ctrl |= SDHCI_CTRL_HISPD;
 765         else
 766                 ctrl &= ~SDHCI_CTRL_HISPD;
 767
 768         writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
 769
 770         /*
 771          * Some (ENE) controllers go apeshit on some ios operation,
 772          * signalling timeout and CRC errors even on CMD0. Resetting
 773          * it on each ios seems to solve the problem.
 774          */
 775         if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
 776                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
 777
 778         mmiowb();
 779         spin_unlock_irqrestore(&host->lock, flags);
 780 }
 781
 782 static int sdhci_get_ro(struct mmc_host *mmc)
 783 {
 784         struct sdhci_host *host;
 785         unsigned long flags;
 786         int present;
 787
 788         host = mmc_priv(mmc);
 789
 790         spin_lock_irqsave(&host->lock, flags);
 791
 792         present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
 793
 794         spin_unlock_irqrestore(&host->lock, flags);
 795
 796         return !(present & SDHCI_WRITE_PROTECT);
 797 }
 798
 799 static const struct mmc_host_ops sdhci_ops = {
 800         .request        = sdhci_request,
 801         .set_ios        = sdhci_set_ios,
 802         .get_ro         = sdhci_get_ro,
 803 };
 804
 805 /*****************************************************************************\
 806  *                                                                           *
 807  * Tasklets                                                                  *
 808  *                                                                           *
 809 \*****************************************************************************/
 810
 811 static void sdhci_tasklet_card(unsigned long param)
 812 {
 813         struct sdhci_host *host;
 814         unsigned long flags;
 815
 816         host = (struct sdhci_host*)param;
 817
 818         spin_lock_irqsave(&host->lock, flags);
 819
 820         if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
 821                 if (host->mrq) {
 822                         printk(KERN_ERR "%s: Card removed during transfer!\n",
 823                                 mmc_hostname(host->mmc));
 824                         printk(KERN_ERR "%s: Resetting controller.\n",
 825                                 mmc_hostname(host->mmc));
 826
 827                         sdhci_reset(host, SDHCI_RESET_CMD);
 828                         sdhci_reset(host, SDHCI_RESET_DATA);
 829
 830                         host->mrq->cmd->error = MMC_ERR_FAILED;
 831                         tasklet_schedule(&host->finish_tasklet);
 832                 }
 833         }
 834
 835         spin_unlock_irqrestore(&host->lock, flags);
 836
 837         mmc_detect_change(host->mmc, msecs_to_jiffies(500));
 838 }
 839
 840 static void sdhci_tasklet_finish(unsigned long param)
 841 {
 842         struct sdhci_host *host;
 843         unsigned long flags;
 844         struct mmc_request *mrq;
 845
 846         host = (struct sdhci_host*)param;
 847
 848         spin_lock_irqsave(&host->lock, flags);
 849
 850         del_timer(&host->timer);
 851
 852         mrq = host->mrq;
 853
 854         /*
 855          * The controller needs a reset of internal state machines
 856          * upon error conditions.
 857          */
 858         if ((mrq->cmd->error != MMC_ERR_NONE) ||
 859                 (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
 860                 (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
 861
 862                 /* Some controllers need this kick or reset won't work here */
 863                 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
 864                         unsigned int clock;
 865
 866                         /* This is to force an update */
 867                         clock = host->clock;
 868                         host->clock = 0;
 869                         sdhci_set_clock(host, clock);
 870                 }
 871
 872                 /* Spec says we should do both at the same time, but Ricoh
 873                    controllers do not like that. */
 874                 sdhci_reset(host, SDHCI_RESET_CMD);
 875                 sdhci_reset(host, SDHCI_RESET_DATA);
 876         }
 877
 878         host->mrq = NULL;
 879         host->cmd = NULL;
 880         host->data = NULL;
 881
 882         sdhci_deactivate_led(host);
 883
 884         mmiowb();
 885         spin_unlock_irqrestore(&host->lock, flags);
 886
 887         mmc_request_done(host->mmc, mrq);
 888 }
 889
 890 static void sdhci_timeout_timer(unsigned long data)
 891 {
 892         struct sdhci_host *host;
 893         unsigned long flags;
 894
 895         host = (struct sdhci_host*)data;
 896
 897         spin_lock_irqsave(&host->lock, flags);
 898
 899         if (host->mrq) {
 900                 printk(KERN_ERR "%s: Timeout waiting for hardware "
 901                         "interrupt.\n", mmc_hostname(host->mmc));
 902                 sdhci_dumpregs(host);
 903
 904                 if (host->data) {
 905                         host->data->error = MMC_ERR_TIMEOUT;
 906                         sdhci_finish_data(host);
 907                 } else {
 908                         if (host->cmd)
 909                                 host->cmd->error = MMC_ERR_TIMEOUT;
 910                         else
 911                                 host->mrq->cmd->error = MMC_ERR_TIMEOUT;
 912
 913                         tasklet_schedule(&host->finish_tasklet);
 914                 }
 915         }
 916
 917         mmiowb();
 918         spin_unlock_irqrestore(&host->lock, flags);
 919 }
 920
 921 /*****************************************************************************\
 922  *                                                                           *
 923  * Interrupt handling                                                        *
 924  *                                                                           *
 925 \*****************************************************************************/
 926
 927 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
 928 {
 929         BUG_ON(intmask == 0);
 930
 931         if (!host->cmd) {
 932                 printk(KERN_ERR "%s: Got command interrupt even though no "
 933                         "command operation was in progress.\n",
 934                         mmc_hostname(host->mmc));
 935                 sdhci_dumpregs(host);
 936                 return;
 937         }
 938
 939         if (intmask & SDHCI_INT_TIMEOUT)
 940                 host->cmd->error = MMC_ERR_TIMEOUT;
 941         else if (intmask & SDHCI_INT_CRC)
 942                 host->cmd->error = MMC_ERR_BADCRC;
 943         else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
 944                 host->cmd->error = MMC_ERR_FAILED;
 945
 946         if (host->cmd->error != MMC_ERR_NONE)
 947                 tasklet_schedule(&host->finish_tasklet);
 948         else if (intmask & SDHCI_INT_RESPONSE)
 949                 sdhci_finish_command(host);
 950 }
 951
 952 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
 953 {
 954         BUG_ON(intmask == 0);
 955
 956         if (!host->data) {
 957                 /*
 958                  * A data end interrupt is sent together with the response
 959                  * for the stop command.
 960                  */
 961                 if (intmask & SDHCI_INT_DATA_END)
 962                         return;
 963
 964                 printk(KERN_ERR "%s: Got data interrupt even though no "
 965                         "data operation was in progress.\n",
 966                         mmc_hostname(host->mmc));
 967                 sdhci_dumpregs(host);
 968
 969                 return;
 970         }
 971
 972         if (intmask & SDHCI_INT_DATA_TIMEOUT)
 973                 host->data->error = MMC_ERR_TIMEOUT;
 974         else if (intmask & SDHCI_INT_DATA_CRC)
 975                 host->data->error = MMC_ERR_BADCRC;
 976         else if (intmask & SDHCI_INT_DATA_END_BIT)
 977                 host->data->error = MMC_ERR_FAILED;
 978
 979         if (host->data->error != MMC_ERR_NONE)
 980                 sdhci_finish_data(host);
 981         else {
 982                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
 983                         sdhci_transfer_pio(host);
 984
 985                 /*
 986                  * We currently don't do anything fancy with DMA
 987                  * boundaries, but as we can't disable the feature
 988                  * we need to at least restart the transfer.
 989                  */
 990                 if (intmask & SDHCI_INT_DMA_END)
 991                         writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
 992                                 host->ioaddr + SDHCI_DMA_ADDRESS);
 993
 994                 if (intmask & SDHCI_INT_DATA_END)
 995                         sdhci_finish_data(host);
 996         }
 997 }
 998
 999 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1000 {
1001         irqreturn_t result;
1002         struct sdhci_host* host = dev_id;
1003         u32 intmask;
1004
1005         spin_lock(&host->lock);
1006
1007         intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1008
1009         if (!intmask || intmask == 0xffffffff) {
1010                 result = IRQ_NONE;
1011                 goto out;
1012         }
1013
1014         DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
1015
1016         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1017                 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1018                         host->ioaddr + SDHCI_INT_STATUS);
1019                 tasklet_schedule(&host->card_tasklet);
1020         }
1021
1022         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1023
1024         if (intmask & SDHCI_INT_CMD_MASK) {
1025                 writel(intmask & SDHCI_INT_CMD_MASK,
1026                         host->ioaddr + SDHCI_INT_STATUS);
1027                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1028         }
1029
1030         if (intmask & SDHCI_INT_DATA_MASK) {
1031                 writel(intmask & SDHCI_INT_DATA_MASK,
1032                         host->ioaddr + SDHCI_INT_STATUS);
1033                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1034         }
1035
1036         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1037
1038         intmask &= ~SDHCI_INT_ERROR;
1039
1040         if (intmask & SDHCI_INT_BUS_POWER) {
1041                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1042                         mmc_hostname(host->mmc));
1043                 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1044         }
1045
1046         intmask &= ~SDHCI_INT_BUS_POWER;
1047
1048         if (intmask) {
1049                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1050                         mmc_hostname(host->mmc), intmask);
1051                 sdhci_dumpregs(host);
1052
1053                 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1054         }
1055
1056         result = IRQ_HANDLED;
1057
1058         mmiowb();
1059 out:
1060         spin_unlock(&host->lock);
1061
1062         return result;
1063 }
1064
1065 /*****************************************************************************\
1066  *                                                                           *
1067  * Suspend/resume                                                            *
1068  *                                                                           *
1069 \*****************************************************************************/
1070
1071 #ifdef CONFIG_PM
1072
1073 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1074 {
1075         struct sdhci_chip *chip;
1076         int i, ret;
1077
1078         chip = pci_get_drvdata(pdev);
1079         if (!chip)
1080                 return 0;
1081
1082         DBG("Suspending...\n");
1083
1084         for (i = 0;i < chip->num_slots;i++) {
1085                 if (!chip->hosts[i])
1086                         continue;
1087                 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1088                 if (ret) {
1089                         for (i--;i >= 0;i--)
1090                                 mmc_resume_host(chip->hosts[i]->mmc);
1091                         return ret;
1092                 }
1093         }
1094
1095         pci_save_state(pdev);
1096         pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1097
1098         for (i = 0;i < chip->num_slots;i++) {
1099                 if (!chip->hosts[i])
1100                         continue;
1101                 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1102         }
1103
1104         pci_disable_device(pdev);
1105         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1106
1107         return 0;
1108 }
1109
1110 static int sdhci_resume (struct pci_dev *pdev)
1111 {
1112         struct sdhci_chip *chip;
1113         int i, ret;
1114
1115         chip = pci_get_drvdata(pdev);
1116         if (!chip)
1117                 return 0;
1118
1119         DBG("Resuming...\n");
1120
1121         pci_set_power_state(pdev, PCI_D0);
1122         pci_restore_state(pdev);
1123         ret = pci_enable_device(pdev);
1124         if (ret)
1125                 return ret;
1126
1127         for (i = 0;i < chip->num_slots;i++) {
1128                 if (!chip->hosts[i])
1129                         continue;
1130                 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1131                         pci_set_master(pdev);
1132                 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1133                         IRQF_SHARED, chip->hosts[i]->slot_descr,
1134                         chip->hosts[i]);
1135                 if (ret)
1136                         return ret;
1137                 sdhci_init(chip->hosts[i]);
1138                 mmiowb();
1139                 ret = mmc_resume_host(chip->hosts[i]->mmc);
1140                 if (ret)
1141                         return ret;
1142         }
1143
1144         return 0;
1145 }
1146
1147 #else /* CONFIG_PM */
1148
1149 #define sdhci_suspend NULL
1150 #define sdhci_resume NULL
1151
1152 #endif /* CONFIG_PM */
1153
1154 /*****************************************************************************\
1155  *                                                                           *
1156  * Device probing/removal                                                    *
1157  *                                                                           *
1158 \*****************************************************************************/
1159
1160 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1161 {
1162         int ret;
1163         unsigned int version;
1164         struct sdhci_chip *chip;
1165         struct mmc_host *mmc;
1166         struct sdhci_host *host;
1167
1168         u8 first_bar;
1169         unsigned int caps;
1170
1171         chip = pci_get_drvdata(pdev);
1172         BUG_ON(!chip);
1173
1174         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1175         if (ret)
1176                 return ret;
1177
1178         first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1179
1180         if (first_bar > 5) {
1181                 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1182                 return -ENODEV;
1183         }
1184
1185         if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1186                 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1187                 return -ENODEV;
1188         }
1189
1190         if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1191                 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1192                         "You may experience problems.\n");
1193         }
1194
1195         if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1196                 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1197                 return -ENODEV;
1198         }
1199
1200         if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1201                 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1202                 return -ENODEV;
1203         }
1204
1205         mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1206         if (!mmc)
1207                 return -ENOMEM;
1208
1209         host = mmc_priv(mmc);
1210         host->mmc = mmc;
1211
1212         host->chip = chip;
1213         chip->hosts[slot] = host;
1214
1215         host->bar = first_bar + slot;
1216
1217         host->addr = pci_resource_start(pdev, host->bar);
1218         host->irq = pdev->irq;
1219
1220         DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1221
1222         snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
1223
1224         ret = pci_request_region(pdev, host->bar, host->slot_descr);
1225         if (ret)
1226                 goto free;
1227
1228         host->ioaddr = ioremap_nocache(host->addr,
1229                 pci_resource_len(pdev, host->bar));
1230         if (!host->ioaddr) {
1231                 ret = -ENOMEM;
1232                 goto release;
1233         }
1234
1235         sdhci_reset(host, SDHCI_RESET_ALL);
1236
1237         version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1238         version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1239         if (version != 0) {
1240                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1241                         "You may experience problems.\n", host->slot_descr,
1242                         version);
1243         }
1244
1245         caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1246
1247         if (debug_nodma)
1248                 DBG("DMA forced off\n");
1249         else if (debug_forcedma) {
1250                 DBG("DMA forced on\n");
1251                 host->flags |= SDHCI_USE_DMA;
1252         } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1253                 host->flags |= SDHCI_USE_DMA;
1254         else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
1255                 DBG("Controller doesn't have DMA interface\n");
1256         else if (!(caps & SDHCI_CAN_DO_DMA))
1257                 DBG("Controller doesn't have DMA capability\n");
1258         else
1259                 host->flags |= SDHCI_USE_DMA;
1260
1261         if (host->flags & SDHCI_USE_DMA) {
1262                 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1263                         printk(KERN_WARNING "%s: No suitable DMA available. "
1264                                 "Falling back to PIO.\n", host->slot_descr);
1265                         host->flags &= ~SDHCI_USE_DMA;
1266                 }
1267         }
1268
1269         if (host->flags & SDHCI_USE_DMA)
1270                 pci_set_master(pdev);
1271         else /* XXX: Hack to get MMC layer to avoid highmem */
1272                 pdev->dma_mask = 0;
1273
1274         host->max_clk =
1275                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1276         if (host->max_clk == 0) {
1277                 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1278                         "frequency.\n", host->slot_descr);
1279                 ret = -ENODEV;
1280                 goto unmap;
1281         }
1282         host->max_clk *= 1000000;
1283
1284         host->timeout_clk =
1285                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1286         if (host->timeout_clk == 0) {
1287                 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1288                         "frequency.\n", host->slot_descr);
1289                 ret = -ENODEV;
1290                 goto unmap;
1291         }
1292         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1293                 host->timeout_clk *= 1000;
1294
1295         /*
1296          * Set host parameters.
1297          */
1298         mmc->ops = &sdhci_ops;
1299         mmc->f_min = host->max_clk / 256;
1300         mmc->f_max = host->max_clk;
1301         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
1302
1303         if (caps & SDHCI_CAN_DO_HISPD)
1304                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1305
1306         mmc->ocr_avail = 0;
1307         if (caps & SDHCI_CAN_VDD_330)
1308                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1309         if (caps & SDHCI_CAN_VDD_300)
1310                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1311         if (caps & SDHCI_CAN_VDD_180)
1312                 mmc->ocr_avail |= MMC_VDD_165_195;
1313
1314         if (mmc->ocr_avail == 0) {
1315                 printk(KERN_ERR "%s: Hardware doesn't report any "
1316                         "support voltages.\n", host->slot_descr);
1317                 ret = -ENODEV;
1318                 goto unmap;
1319         }
1320
1321         spin_lock_init(&host->lock);
1322
1323         /*
1324          * Maximum number of segments. Hardware cannot do scatter lists.
1325          */
1326         if (host->flags & SDHCI_USE_DMA)
1327                 mmc->max_hw_segs = 1;
1328         else
1329                 mmc->max_hw_segs = 16;
1330         mmc->max_phys_segs = 16;
1331
1332         /*
1333          * Maximum number of sectors in one transfer. Limited by DMA boundary
1334          * size (512KiB).
1335          */
1336         mmc->max_req_size = 524288;
1337
1338         /*
1339          * Maximum segment size. Could be one segment with the maximum number
1340          * of bytes.
1341          */
1342         mmc->max_seg_size = mmc->max_req_size;
1343
1344         /*
1345          * Maximum block size. This varies from controller to controller and
1346          * is specified in the capabilities register.
1347          */
1348         mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1349         if (mmc->max_blk_size >= 3) {
1350                 printk(KERN_ERR "%s: Invalid maximum block size.\n",
1351                         host->slot_descr);
1352                 ret = -ENODEV;
1353                 goto unmap;
1354         }
1355         mmc->max_blk_size = 512 << mmc->max_blk_size;
1356
1357         /*
1358          * Maximum block count.
1359          */
1360         mmc->max_blk_count = 65535;
1361
1362         /*
1363          * Init tasklets.
1364          */
1365         tasklet_init(&host->card_tasklet,
1366                 sdhci_tasklet_card, (unsigned long)host);
1367         tasklet_init(&host->finish_tasklet,
1368                 sdhci_tasklet_finish, (unsigned long)host);
1369
1370         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1371
1372         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1373                 host->slot_descr, host);
1374         if (ret)
1375                 goto untasklet;
1376
1377         sdhci_init(host);
1378
1379 #ifdef CONFIG_MMC_DEBUG
1380         sdhci_dumpregs(host);
1381 #endif
1382
1383         mmiowb();
1384
1385         mmc_add_host(mmc);
1386
1387         printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
1388                 host->addr, host->irq,
1389                 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1390
1391         return 0;
1392
1393 untasklet:
1394         tasklet_kill(&host->card_tasklet);
1395         tasklet_kill(&host->finish_tasklet);
1396 unmap:
1397         iounmap(host->ioaddr);
1398 release:
1399         pci_release_region(pdev, host->bar);
1400 free:
1401         mmc_free_host(mmc);
1402
1403         return ret;
1404 }
1405
1406 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1407 {
1408         struct sdhci_chip *chip;
1409         struct mmc_host *mmc;
1410         struct sdhci_host *host;
1411
1412         chip = pci_get_drvdata(pdev);
1413         host = chip->hosts[slot];
1414         mmc = host->mmc;
1415
1416         chip->hosts[slot] = NULL;
1417
1418         mmc_remove_host(mmc);
1419
1420         sdhci_reset(host, SDHCI_RESET_ALL);
1421
1422         free_irq(host->irq, host);
1423
1424         del_timer_sync(&host->timer);
1425
1426         tasklet_kill(&host->card_tasklet);
1427         tasklet_kill(&host->finish_tasklet);
1428
1429         iounmap(host->ioaddr);
1430
1431         pci_release_region(pdev, host->bar);
1432
1433         mmc_free_host(mmc);
1434 }
1435
1436 static int __devinit sdhci_probe(struct pci_dev *pdev,
1437         const struct pci_device_id *ent)
1438 {
1439         int ret, i;
1440         u8 slots, rev;
1441         struct sdhci_chip *chip;
1442
1443         BUG_ON(pdev == NULL);
1444         BUG_ON(ent == NULL);
1445
1446         pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1447
1448         printk(KERN_INFO DRIVER_NAME
1449                 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1450                 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1451                 (int)rev);
1452
1453         ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1454         if (ret)
1455                 return ret;
1456
1457         slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1458         DBG("found %d slot(s)\n", slots);
1459         if (slots == 0)
1460                 return -ENODEV;
1461
1462         ret = pci_enable_device(pdev);
1463         if (ret)
1464                 return ret;
1465
1466         chip = kzalloc(sizeof(struct sdhci_chip) +
1467                 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1468         if (!chip) {
1469                 ret = -ENOMEM;
1470                 goto err;
1471         }
1472
1473         chip->pdev = pdev;
1474         chip->quirks = ent->driver_data;
1475
1476         if (debug_quirks)
1477                 chip->quirks = debug_quirks;
1478
1479         chip->num_slots = slots;
1480         pci_set_drvdata(pdev, chip);
1481
1482         for (i = 0;i < slots;i++) {
1483                 ret = sdhci_probe_slot(pdev, i);
1484                 if (ret) {
1485                         for (i--;i >= 0;i--)
1486                                 sdhci_remove_slot(pdev, i);
1487                         goto free;
1488                 }
1489         }
1490
1491         return 0;
1492
1493 free:
1494         pci_set_drvdata(pdev, NULL);
1495         kfree(chip);
1496
1497 err:
1498         pci_disable_device(pdev);
1499         return ret;
1500 }
1501
1502 static void __devexit sdhci_remove(struct pci_dev *pdev)
1503 {
1504         int i;
1505         struct sdhci_chip *chip;
1506
1507         chip = pci_get_drvdata(pdev);
1508
1509         if (chip) {
1510                 for (i = 0;i < chip->num_slots;i++)
1511                         sdhci_remove_slot(pdev, i);
1512
1513                 pci_set_drvdata(pdev, NULL);
1514
1515                 kfree(chip);
1516         }
1517
1518         pci_disable_device(pdev);
1519 }
1520
1521 static struct pci_driver sdhci_driver = {
1522         .name =         DRIVER_NAME,
1523         .id_table =     pci_ids,
1524         .probe =        sdhci_probe,
1525         .remove =       __devexit_p(sdhci_remove),
1526         .suspend =      sdhci_suspend,
1527         .resume =       sdhci_resume,
1528 };
1529
1530 /*****************************************************************************\
1531  *                                                                           *
1532  * Driver init/exit                                                          *
1533  *                                                                           *
1534 \*****************************************************************************/
1535
1536 static int __init sdhci_drv_init(void)
1537 {
1538         printk(KERN_INFO DRIVER_NAME
1539                 ": Secure Digital Host Controller Interface driver\n");
1540         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1541
1542         return pci_register_driver(&sdhci_driver);
1543 }
1544
1545 static void __exit sdhci_drv_exit(void)
1546 {
1547         DBG("Exiting\n");
1548
1549         pci_unregister_driver(&sdhci_driver);
1550 }
1551
1552 module_init(sdhci_drv_init);
1553 module_exit(sdhci_drv_exit);
1554
1555 module_param(debug_nodma, uint, 0444);
1556 module_param(debug_forcedma, uint, 0444);
1557 module_param(debug_quirks, uint, 0444);
1558
1559 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1560 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1561 MODULE_LICENSE("GPL");
1562
1563 MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
1564 MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
1565 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");