2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/mii.h>
45 #define DRV_NAME "skge"
46 #define DRV_VERSION "1.3"
47 #define PFX DRV_NAME " "
49 #define DEFAULT_TX_RING_SIZE 128
50 #define DEFAULT_RX_RING_SIZE 512
51 #define MAX_TX_RING_SIZE 1024
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
61 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
62 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
63 MODULE_LICENSE("GPL");
64 MODULE_VERSION(DRV_VERSION);
66 static const u32 default_msg
67 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
68 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70 static int debug = -1; /* defaults above */
71 module_param(debug, int, 0);
72 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74 static const struct pci_device_id skge_id_table[] = {
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
82 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
84 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
87 MODULE_DEVICE_TABLE(pci, skge_id_table);
89 static int skge_up(struct net_device *dev);
90 static int skge_down(struct net_device *dev);
91 static void skge_phy_reset(struct skge_port *skge);
92 static void skge_tx_clean(struct skge_port *skge);
93 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
94 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
95 static void genesis_get_stats(struct skge_port *skge, u64 *data);
96 static void yukon_get_stats(struct skge_port *skge, u64 *data);
97 static void yukon_init(struct skge_hw *hw, int port);
98 static void genesis_mac_init(struct skge_hw *hw, int port);
99 static void genesis_link_up(struct skge_port *skge);
101 /* Avoid conditionals by using array */
102 static const int txqaddr[] = { Q_XA1, Q_XA2 };
103 static const int rxqaddr[] = { Q_R1, Q_R2 };
104 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
106 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
108 static int skge_get_regs_len(struct net_device *dev)
114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
118 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 const struct skge_port *skge = netdev_priv(dev);
122 const void __iomem *io = skge->hw->regs;
125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
132 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
133 static int wol_supported(const struct skge_hw *hw)
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
139 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
141 struct skge_port *skge = netdev_priv(dev);
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
147 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
158 skge->wol = wol->wolopts == WAKE_MAGIC;
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
172 /* Determine supported/advertised modes based on hardware.
173 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 static u32 skge_supported_modes(const struct skge_hw *hw)
180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
203 static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
209 ecmd->transceiver = XCVR_INTERNAL;
210 ecmd->supported = skge_supported_modes(hw);
213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
216 ecmd->port = PORT_FIBRE;
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
225 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
229 u32 supported = skge_supported_modes(hw);
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
232 ecmd->advertising = supported;
238 switch (ecmd->speed) {
240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
268 if ((setting & supported) == 0)
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
275 skge->autoneg = ecmd->autoneg;
276 skge->advertising = ecmd->advertising;
278 if (netif_running(dev))
279 skge_phy_reset(skge);
284 static void skge_get_drvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
287 struct skge_port *skge = netdev_priv(dev);
289 strcpy(info->driver, DRV_NAME);
290 strcpy(info->version, DRV_VERSION);
291 strcpy(info->fw_version, "N/A");
292 strcpy(info->bus_info, pci_name(skge->hw->pdev));
295 static const struct skge_stat {
296 char name[ETH_GSTRING_LEN];
300 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
301 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
304 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
305 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
306 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
307 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
308 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
309 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
310 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
313 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
314 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
315 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
316 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
317 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
320 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
321 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
322 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
326 static int skge_get_stats_count(struct net_device *dev)
328 return ARRAY_SIZE(skge_stats);
331 static void skge_get_ethtool_stats(struct net_device *dev,
332 struct ethtool_stats *stats, u64 *data)
334 struct skge_port *skge = netdev_priv(dev);
336 if (skge->hw->chip_id == CHIP_ID_GENESIS)
337 genesis_get_stats(skge, data);
339 yukon_get_stats(skge, data);
342 /* Use hardware MIB variables for critical path statistics and
343 * transmit feedback not reported at interrupt.
344 * Other errors are accounted for in interrupt handler.
346 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 struct skge_port *skge = netdev_priv(dev);
349 u64 data[ARRAY_SIZE(skge_stats)];
351 if (skge->hw->chip_id == CHIP_ID_GENESIS)
352 genesis_get_stats(skge, data);
354 yukon_get_stats(skge, data);
356 skge->net_stats.tx_bytes = data[0];
357 skge->net_stats.rx_bytes = data[1];
358 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
359 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
360 skge->net_stats.multicast = data[5] + data[7];
361 skge->net_stats.collisions = data[10];
362 skge->net_stats.tx_aborted_errors = data[12];
364 return &skge->net_stats;
367 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
373 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
374 memcpy(data + i * ETH_GSTRING_LEN,
375 skge_stats[i].name, ETH_GSTRING_LEN);
380 static void skge_get_ring_param(struct net_device *dev,
381 struct ethtool_ringparam *p)
383 struct skge_port *skge = netdev_priv(dev);
385 p->rx_max_pending = MAX_RX_RING_SIZE;
386 p->tx_max_pending = MAX_TX_RING_SIZE;
387 p->rx_mini_max_pending = 0;
388 p->rx_jumbo_max_pending = 0;
390 p->rx_pending = skge->rx_ring.count;
391 p->tx_pending = skge->tx_ring.count;
392 p->rx_mini_pending = 0;
393 p->rx_jumbo_pending = 0;
396 static int skge_set_ring_param(struct net_device *dev,
397 struct ethtool_ringparam *p)
399 struct skge_port *skge = netdev_priv(dev);
402 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
403 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
406 skge->rx_ring.count = p->rx_pending;
407 skge->tx_ring.count = p->tx_pending;
409 if (netif_running(dev)) {
419 static u32 skge_get_msglevel(struct net_device *netdev)
421 struct skge_port *skge = netdev_priv(netdev);
422 return skge->msg_enable;
425 static void skge_set_msglevel(struct net_device *netdev, u32 value)
427 struct skge_port *skge = netdev_priv(netdev);
428 skge->msg_enable = value;
431 static int skge_nway_reset(struct net_device *dev)
433 struct skge_port *skge = netdev_priv(dev);
435 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
438 skge_phy_reset(skge);
442 static int skge_set_sg(struct net_device *dev, u32 data)
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
447 if (hw->chip_id == CHIP_ID_GENESIS && data)
449 return ethtool_op_set_sg(dev, data);
452 static int skge_set_tx_csum(struct net_device *dev, u32 data)
454 struct skge_port *skge = netdev_priv(dev);
455 struct skge_hw *hw = skge->hw;
457 if (hw->chip_id == CHIP_ID_GENESIS && data)
460 return ethtool_op_set_tx_csum(dev, data);
463 static u32 skge_get_rx_csum(struct net_device *dev)
465 struct skge_port *skge = netdev_priv(dev);
467 return skge->rx_csum;
470 /* Only Yukon supports checksum offload. */
471 static int skge_set_rx_csum(struct net_device *dev, u32 data)
473 struct skge_port *skge = netdev_priv(dev);
475 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
478 skge->rx_csum = data;
482 static void skge_get_pauseparam(struct net_device *dev,
483 struct ethtool_pauseparam *ecmd)
485 struct skge_port *skge = netdev_priv(dev);
487 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
488 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
489 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
490 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492 ecmd->autoneg = skge->autoneg;
495 static int skge_set_pauseparam(struct net_device *dev,
496 struct ethtool_pauseparam *ecmd)
498 struct skge_port *skge = netdev_priv(dev);
500 skge->autoneg = ecmd->autoneg;
501 if (ecmd->rx_pause && ecmd->tx_pause)
502 skge->flow_control = FLOW_MODE_SYMMETRIC;
503 else if (ecmd->rx_pause && !ecmd->tx_pause)
504 skge->flow_control = FLOW_MODE_REM_SEND;
505 else if (!ecmd->rx_pause && ecmd->tx_pause)
506 skge->flow_control = FLOW_MODE_LOC_SEND;
508 skge->flow_control = FLOW_MODE_NONE;
510 if (netif_running(dev))
511 skge_phy_reset(skge);
515 /* Chip internal frequency for clock calculations */
516 static inline u32 hwkhz(const struct skge_hw *hw)
518 if (hw->chip_id == CHIP_ID_GENESIS)
519 return 53215; /* or: 53.125 MHz */
521 return 78215; /* or: 78.125 MHz */
524 /* Chip HZ to microseconds */
525 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
527 return (ticks * 1000) / hwkhz(hw);
530 /* Microseconds to chip HZ */
531 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
533 return hwkhz(hw) * usec / 1000;
536 static int skge_get_coalesce(struct net_device *dev,
537 struct ethtool_coalesce *ecmd)
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
541 int port = skge->port;
543 ecmd->rx_coalesce_usecs = 0;
544 ecmd->tx_coalesce_usecs = 0;
546 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
547 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
548 u32 msk = skge_read32(hw, B2_IRQM_MSK);
550 if (msk & rxirqmask[port])
551 ecmd->rx_coalesce_usecs = delay;
552 if (msk & txirqmask[port])
553 ecmd->tx_coalesce_usecs = delay;
559 /* Note: interrupt timer is per board, but can turn on/off per port */
560 static int skge_set_coalesce(struct net_device *dev,
561 struct ethtool_coalesce *ecmd)
563 struct skge_port *skge = netdev_priv(dev);
564 struct skge_hw *hw = skge->hw;
565 int port = skge->port;
566 u32 msk = skge_read32(hw, B2_IRQM_MSK);
569 if (ecmd->rx_coalesce_usecs == 0)
570 msk &= ~rxirqmask[port];
571 else if (ecmd->rx_coalesce_usecs < 25 ||
572 ecmd->rx_coalesce_usecs > 33333)
575 msk |= rxirqmask[port];
576 delay = ecmd->rx_coalesce_usecs;
579 if (ecmd->tx_coalesce_usecs == 0)
580 msk &= ~txirqmask[port];
581 else if (ecmd->tx_coalesce_usecs < 25 ||
582 ecmd->tx_coalesce_usecs > 33333)
585 msk |= txirqmask[port];
586 delay = min(delay, ecmd->rx_coalesce_usecs);
589 skge_write32(hw, B2_IRQM_MSK, msk);
591 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
593 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
594 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
599 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
600 static void skge_led(struct skge_port *skge, enum led_mode mode)
602 struct skge_hw *hw = skge->hw;
603 int port = skge->port;
605 spin_lock_bh(&hw->phy_lock);
606 if (hw->chip_id == CHIP_ID_GENESIS) {
609 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
610 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
611 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
612 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
616 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
617 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
619 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
620 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
625 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
626 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
627 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
629 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
635 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
636 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
637 PHY_M_LED_MO_DUP(MO_LED_OFF) |
638 PHY_M_LED_MO_10(MO_LED_OFF) |
639 PHY_M_LED_MO_100(MO_LED_OFF) |
640 PHY_M_LED_MO_1000(MO_LED_OFF) |
641 PHY_M_LED_MO_RX(MO_LED_OFF));
644 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
645 PHY_M_LED_PULS_DUR(PULS_170MS) |
646 PHY_M_LED_BLINK_RT(BLINK_84MS) |
650 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
651 PHY_M_LED_MO_RX(MO_LED_OFF) |
652 (skge->speed == SPEED_100 ?
653 PHY_M_LED_MO_100(MO_LED_ON) : 0));
656 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
657 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
658 PHY_M_LED_MO_DUP(MO_LED_ON) |
659 PHY_M_LED_MO_10(MO_LED_ON) |
660 PHY_M_LED_MO_100(MO_LED_ON) |
661 PHY_M_LED_MO_1000(MO_LED_ON) |
662 PHY_M_LED_MO_RX(MO_LED_ON));
665 spin_unlock_bh(&hw->phy_lock);
668 /* blink LED's for finding board */
669 static int skge_phys_id(struct net_device *dev, u32 data)
671 struct skge_port *skge = netdev_priv(dev);
673 enum led_mode mode = LED_MODE_TST;
675 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
676 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
681 skge_led(skge, mode);
682 mode ^= LED_MODE_TST;
684 if (msleep_interruptible(BLINK_MS))
689 /* back to regular LED state */
690 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
695 static struct ethtool_ops skge_ethtool_ops = {
696 .get_settings = skge_get_settings,
697 .set_settings = skge_set_settings,
698 .get_drvinfo = skge_get_drvinfo,
699 .get_regs_len = skge_get_regs_len,
700 .get_regs = skge_get_regs,
701 .get_wol = skge_get_wol,
702 .set_wol = skge_set_wol,
703 .get_msglevel = skge_get_msglevel,
704 .set_msglevel = skge_set_msglevel,
705 .nway_reset = skge_nway_reset,
706 .get_link = ethtool_op_get_link,
707 .get_ringparam = skge_get_ring_param,
708 .set_ringparam = skge_set_ring_param,
709 .get_pauseparam = skge_get_pauseparam,
710 .set_pauseparam = skge_set_pauseparam,
711 .get_coalesce = skge_get_coalesce,
712 .set_coalesce = skge_set_coalesce,
713 .get_sg = ethtool_op_get_sg,
714 .set_sg = skge_set_sg,
715 .get_tx_csum = ethtool_op_get_tx_csum,
716 .set_tx_csum = skge_set_tx_csum,
717 .get_rx_csum = skge_get_rx_csum,
718 .set_rx_csum = skge_set_rx_csum,
719 .get_strings = skge_get_strings,
720 .phys_id = skge_phys_id,
721 .get_stats_count = skge_get_stats_count,
722 .get_ethtool_stats = skge_get_ethtool_stats,
723 .get_perm_addr = ethtool_op_get_perm_addr,
727 * Allocate ring elements and chain them together
728 * One-to-one association of board descriptors with ring elements
730 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
732 struct skge_tx_desc *d;
733 struct skge_element *e;
736 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
740 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
743 if (i == ring->count - 1) {
744 e->next = ring->start;
745 d->next_offset = base;
748 d->next_offset = base + (i+1) * sizeof(*d);
751 ring->to_use = ring->to_clean = ring->start;
756 /* Allocate and setup a new buffer for receiving */
757 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
758 struct sk_buff *skb, unsigned int bufsize)
760 struct skge_rx_desc *rd = e->desc;
763 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
767 rd->dma_hi = map >> 32;
769 rd->csum1_start = ETH_HLEN;
770 rd->csum2_start = ETH_HLEN;
776 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
777 pci_unmap_addr_set(e, mapaddr, map);
778 pci_unmap_len_set(e, maplen, bufsize);
781 /* Resume receiving using existing skb,
782 * Note: DMA address is not changed by chip.
783 * MTU not changed while receiver active.
785 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
787 struct skge_rx_desc *rd = e->desc;
790 rd->csum2_start = ETH_HLEN;
794 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
798 /* Free all buffers in receive ring, assumes receiver stopped */
799 static void skge_rx_clean(struct skge_port *skge)
801 struct skge_hw *hw = skge->hw;
802 struct skge_ring *ring = &skge->rx_ring;
803 struct skge_element *e;
807 struct skge_rx_desc *rd = e->desc;
810 pci_unmap_single(hw->pdev,
811 pci_unmap_addr(e, mapaddr),
812 pci_unmap_len(e, maplen),
814 dev_kfree_skb(e->skb);
817 } while ((e = e->next) != ring->start);
821 /* Allocate buffers for receive ring
822 * For receive: to_clean is next received frame.
824 static int skge_rx_fill(struct skge_port *skge)
826 struct skge_ring *ring = &skge->rx_ring;
827 struct skge_element *e;
833 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
837 skb_reserve(skb, NET_IP_ALIGN);
838 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
839 } while ( (e = e->next) != ring->start);
841 ring->to_clean = ring->start;
845 static void skge_link_up(struct skge_port *skge)
847 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
848 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
850 netif_carrier_on(skge->netdev);
851 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
852 netif_wake_queue(skge->netdev);
854 if (netif_msg_link(skge))
856 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
857 skge->netdev->name, skge->speed,
858 skge->duplex == DUPLEX_FULL ? "full" : "half",
859 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
860 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
861 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
862 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
866 static void skge_link_down(struct skge_port *skge)
868 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
869 netif_carrier_off(skge->netdev);
870 netif_stop_queue(skge->netdev);
872 if (netif_msg_link(skge))
873 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
876 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
880 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
881 xm_read16(hw, port, XM_PHY_DATA);
883 /* Need to wait for external PHY */
884 for (i = 0; i < PHY_RETRIES; i++) {
886 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
892 *val = xm_read16(hw, port, XM_PHY_DATA);
897 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
900 if (__xm_phy_read(hw, port, reg, &v))
901 printk(KERN_WARNING PFX "%s: phy read timed out\n",
902 hw->dev[port]->name);
906 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
910 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
911 for (i = 0; i < PHY_RETRIES; i++) {
912 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
919 xm_write16(hw, port, XM_PHY_DATA, val);
923 static void genesis_init(struct skge_hw *hw)
925 /* set blink source counter */
926 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
927 skge_write8(hw, B2_BSC_CTRL, BSC_START);
929 /* configure mac arbiter */
930 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
932 /* configure mac arbiter timeout values */
933 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
934 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
935 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
936 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_RCINI_RX1, 0);
939 skge_write8(hw, B3_MA_RCINI_RX2, 0);
940 skge_write8(hw, B3_MA_RCINI_TX1, 0);
941 skge_write8(hw, B3_MA_RCINI_TX2, 0);
943 /* configure packet arbiter timeout */
944 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
945 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
946 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
947 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
948 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
951 static void genesis_reset(struct skge_hw *hw, int port)
953 const u8 zero[8] = { 0 };
955 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
957 /* reset the statistics module */
958 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
959 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
960 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
961 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
962 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
964 /* disable Broadcom PHY IRQ */
965 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
967 xm_outhash(hw, port, XM_HSM, zero);
971 /* Convert mode to MII values */
972 static const u16 phy_pause_map[] = {
973 [FLOW_MODE_NONE] = 0,
974 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
975 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
976 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
980 /* Check status of Broadcom phy link */
981 static void bcom_check_link(struct skge_hw *hw, int port)
983 struct net_device *dev = hw->dev[port];
984 struct skge_port *skge = netdev_priv(dev);
987 /* read twice because of latch */
988 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
989 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
991 if ((status & PHY_ST_LSYNC) == 0) {
992 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
993 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
994 xm_write16(hw, port, XM_MMU_CMD, cmd);
995 /* dummy read to ensure writing */
996 (void) xm_read16(hw, port, XM_MMU_CMD);
998 if (netif_carrier_ok(dev))
999 skge_link_down(skge);
1001 if (skge->autoneg == AUTONEG_ENABLE &&
1002 (status & PHY_ST_AN_OVER)) {
1003 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1004 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1006 if (lpa & PHY_B_AN_RF) {
1007 printk(KERN_NOTICE PFX "%s: remote fault\n",
1012 /* Check Duplex mismatch */
1013 switch (aux & PHY_B_AS_AN_RES_MSK) {
1014 case PHY_B_RES_1000FD:
1015 skge->duplex = DUPLEX_FULL;
1017 case PHY_B_RES_1000HD:
1018 skge->duplex = DUPLEX_HALF;
1021 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1027 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1028 switch (aux & PHY_B_AS_PAUSE_MSK) {
1029 case PHY_B_AS_PAUSE_MSK:
1030 skge->flow_control = FLOW_MODE_SYMMETRIC;
1033 skge->flow_control = FLOW_MODE_REM_SEND;
1036 skge->flow_control = FLOW_MODE_LOC_SEND;
1039 skge->flow_control = FLOW_MODE_NONE;
1042 skge->speed = SPEED_1000;
1045 if (!netif_carrier_ok(dev))
1046 genesis_link_up(skge);
1050 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1051 * Phy on for 100 or 10Mbit operation
1053 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1055 struct skge_hw *hw = skge->hw;
1056 int port = skge->port;
1058 u16 id1, r, ext, ctl;
1060 /* magic workaround patterns for Broadcom */
1061 static const struct {
1065 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1066 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1067 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1068 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1070 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1071 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1074 /* read Id from external PHY (all have the same address) */
1075 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1077 /* Optimize MDIO transfer by suppressing preamble. */
1078 r = xm_read16(hw, port, XM_MMU_CMD);
1080 xm_write16(hw, port, XM_MMU_CMD,r);
1083 case PHY_BCOM_ID1_C0:
1085 * Workaround BCOM Errata for the C0 type.
1086 * Write magic patterns to reserved registers.
1088 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1089 xm_phy_write(hw, port,
1090 C0hack[i].reg, C0hack[i].val);
1093 case PHY_BCOM_ID1_A1:
1095 * Workaround BCOM Errata for the A1 type.
1096 * Write magic patterns to reserved registers.
1098 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1099 xm_phy_write(hw, port,
1100 A1hack[i].reg, A1hack[i].val);
1105 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1106 * Disable Power Management after reset.
1108 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1109 r |= PHY_B_AC_DIS_PM;
1110 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1113 xm_read16(hw, port, XM_ISRC);
1115 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1116 ctl = PHY_CT_SP1000; /* always 1000mbit */
1118 if (skge->autoneg == AUTONEG_ENABLE) {
1120 * Workaround BCOM Errata #1 for the C5 type.
1121 * 1000Base-T Link Acquisition Failure in Slave Mode
1122 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1124 u16 adv = PHY_B_1000C_RD;
1125 if (skge->advertising & ADVERTISED_1000baseT_Half)
1126 adv |= PHY_B_1000C_AHD;
1127 if (skge->advertising & ADVERTISED_1000baseT_Full)
1128 adv |= PHY_B_1000C_AFD;
1129 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1131 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1133 if (skge->duplex == DUPLEX_FULL)
1134 ctl |= PHY_CT_DUP_MD;
1135 /* Force to slave */
1136 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1139 /* Set autonegotiation pause parameters */
1140 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1141 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1143 /* Handle Jumbo frames */
1145 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1146 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1148 ext |= PHY_B_PEC_HIGH_LA;
1152 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1153 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1155 /* Use link status change interrupt */
1156 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1158 bcom_check_link(hw, port);
1161 static void genesis_mac_init(struct skge_hw *hw, int port)
1163 struct net_device *dev = hw->dev[port];
1164 struct skge_port *skge = netdev_priv(dev);
1165 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1168 const u8 zero[6] = { 0 };
1170 /* Clear MIB counters */
1171 xm_write16(hw, port, XM_STAT_CMD,
1172 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1173 /* Clear two times according to Errata #3 */
1174 xm_write16(hw, port, XM_STAT_CMD,
1175 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1177 /* Unreset the XMAC. */
1178 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1181 * Perform additional initialization for external PHYs,
1182 * namely for the 1000baseTX cards that use the XMAC's
1185 /* Take external Phy out of reset */
1186 r = skge_read32(hw, B2_GP_IO);
1188 r |= GP_DIR_0|GP_IO_0;
1190 r |= GP_DIR_2|GP_IO_2;
1192 skge_write32(hw, B2_GP_IO, r);
1193 skge_read32(hw, B2_GP_IO);
1195 /* Enable GMII interface */
1196 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1198 bcom_phy_init(skge, jumbo);
1200 /* Set Station Address */
1201 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1203 /* We don't use match addresses so clear */
1204 for (i = 1; i < 16; i++)
1205 xm_outaddr(hw, port, XM_EXM(i), zero);
1207 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1208 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1210 /* We don't need the FCS appended to the packet. */
1211 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1213 r |= XM_RX_BIG_PK_OK;
1215 if (skge->duplex == DUPLEX_HALF) {
1217 * If in manual half duplex mode the other side might be in
1218 * full duplex mode, so ignore if a carrier extension is not seen
1219 * on frames received
1221 r |= XM_RX_DIS_CEXT;
1223 xm_write16(hw, port, XM_RX_CMD, r);
1226 /* We want short frames padded to 60 bytes. */
1227 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1230 * Bump up the transmit threshold. This helps hold off transmit
1231 * underruns when we're blasting traffic from both ports at once.
1233 xm_write16(hw, port, XM_TX_THR, 512);
1236 * Enable the reception of all error frames. This is is
1237 * a necessary evil due to the design of the XMAC. The
1238 * XMAC's receive FIFO is only 8K in size, however jumbo
1239 * frames can be up to 9000 bytes in length. When bad
1240 * frame filtering is enabled, the XMAC's RX FIFO operates
1241 * in 'store and forward' mode. For this to work, the
1242 * entire frame has to fit into the FIFO, but that means
1243 * that jumbo frames larger than 8192 bytes will be
1244 * truncated. Disabling all bad frame filtering causes
1245 * the RX FIFO to operate in streaming mode, in which
1246 * case the XMAC will start transferring frames out of the
1247 * RX FIFO as soon as the FIFO threshold is reached.
1249 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1253 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1254 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1255 * and 'Octets Rx OK Hi Cnt Ov'.
1257 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1260 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1261 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1262 * and 'Octets Tx OK Hi Cnt Ov'.
1264 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1266 /* Configure MAC arbiter */
1267 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1269 /* configure timeout values */
1270 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1271 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1272 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1273 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1275 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1276 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1277 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1278 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1280 /* Configure Rx MAC FIFO */
1281 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1282 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1283 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1285 /* Configure Tx MAC FIFO */
1286 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1287 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1288 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1291 /* Enable frame flushing if jumbo frames used */
1292 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1294 /* enable timeout timers if normal frames */
1295 skge_write16(hw, B3_PA_CTRL,
1296 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1300 static void genesis_stop(struct skge_port *skge)
1302 struct skge_hw *hw = skge->hw;
1303 int port = skge->port;
1306 genesis_reset(hw, port);
1308 /* Clear Tx packet arbiter timeout IRQ */
1309 skge_write16(hw, B3_PA_CTRL,
1310 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1313 * If the transfer sticks at the MAC the STOP command will not
1314 * terminate if we don't flush the XMAC's transmit FIFO !
1316 xm_write32(hw, port, XM_MODE,
1317 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1321 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1323 /* For external PHYs there must be special handling */
1324 reg = skge_read32(hw, B2_GP_IO);
1332 skge_write32(hw, B2_GP_IO, reg);
1333 skge_read32(hw, B2_GP_IO);
1335 xm_write16(hw, port, XM_MMU_CMD,
1336 xm_read16(hw, port, XM_MMU_CMD)
1337 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1339 xm_read16(hw, port, XM_MMU_CMD);
1343 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1345 struct skge_hw *hw = skge->hw;
1346 int port = skge->port;
1348 unsigned long timeout = jiffies + HZ;
1350 xm_write16(hw, port,
1351 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1353 /* wait for update to complete */
1354 while (xm_read16(hw, port, XM_STAT_CMD)
1355 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1356 if (time_after(jiffies, timeout))
1361 /* special case for 64 bit octet counter */
1362 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1363 | xm_read32(hw, port, XM_TXO_OK_LO);
1364 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1365 | xm_read32(hw, port, XM_RXO_OK_LO);
1367 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1368 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1371 static void genesis_mac_intr(struct skge_hw *hw, int port)
1373 struct skge_port *skge = netdev_priv(hw->dev[port]);
1374 u16 status = xm_read16(hw, port, XM_ISRC);
1376 if (netif_msg_intr(skge))
1377 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1378 skge->netdev->name, status);
1380 if (status & XM_IS_TXF_UR) {
1381 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1382 ++skge->net_stats.tx_fifo_errors;
1384 if (status & XM_IS_RXF_OV) {
1385 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1386 ++skge->net_stats.rx_fifo_errors;
1390 static void genesis_link_up(struct skge_port *skge)
1392 struct skge_hw *hw = skge->hw;
1393 int port = skge->port;
1397 cmd = xm_read16(hw, port, XM_MMU_CMD);
1400 * enabling pause frame reception is required for 1000BT
1401 * because the XMAC is not reset if the link is going down
1403 if (skge->flow_control == FLOW_MODE_NONE ||
1404 skge->flow_control == FLOW_MODE_LOC_SEND)
1405 /* Disable Pause Frame Reception */
1406 cmd |= XM_MMU_IGN_PF;
1408 /* Enable Pause Frame Reception */
1409 cmd &= ~XM_MMU_IGN_PF;
1411 xm_write16(hw, port, XM_MMU_CMD, cmd);
1413 mode = xm_read32(hw, port, XM_MODE);
1414 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1415 skge->flow_control == FLOW_MODE_LOC_SEND) {
1417 * Configure Pause Frame Generation
1418 * Use internal and external Pause Frame Generation.
1419 * Sending pause frames is edge triggered.
1420 * Send a Pause frame with the maximum pause time if
1421 * internal oder external FIFO full condition occurs.
1422 * Send a zero pause time frame to re-start transmission.
1424 /* XM_PAUSE_DA = '010000C28001' (default) */
1425 /* XM_MAC_PTIME = 0xffff (maximum) */
1426 /* remember this value is defined in big endian (!) */
1427 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1429 mode |= XM_PAUSE_MODE;
1430 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1433 * disable pause frame generation is required for 1000BT
1434 * because the XMAC is not reset if the link is going down
1436 /* Disable Pause Mode in Mode Register */
1437 mode &= ~XM_PAUSE_MODE;
1439 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1442 xm_write32(hw, port, XM_MODE, mode);
1445 /* disable GP0 interrupt bit for external Phy */
1446 msk |= XM_IS_INP_ASS;
1448 xm_write16(hw, port, XM_IMSK, msk);
1449 xm_read16(hw, port, XM_ISRC);
1451 /* get MMU Command Reg. */
1452 cmd = xm_read16(hw, port, XM_MMU_CMD);
1453 if (skge->duplex == DUPLEX_FULL)
1454 cmd |= XM_MMU_GMII_FD;
1457 * Workaround BCOM Errata (#10523) for all BCom Phys
1458 * Enable Power Management after link up
1460 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1461 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1462 & ~PHY_B_AC_DIS_PM);
1463 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1466 xm_write16(hw, port, XM_MMU_CMD,
1467 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1472 static inline void bcom_phy_intr(struct skge_port *skge)
1474 struct skge_hw *hw = skge->hw;
1475 int port = skge->port;
1478 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1479 if (netif_msg_intr(skge))
1480 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1481 skge->netdev->name, isrc);
1483 if (isrc & PHY_B_IS_PSE)
1484 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1485 hw->dev[port]->name);
1487 /* Workaround BCom Errata:
1488 * enable and disable loopback mode if "NO HCD" occurs.
1490 if (isrc & PHY_B_IS_NO_HDCL) {
1491 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1492 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1493 ctrl | PHY_CT_LOOP);
1494 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1495 ctrl & ~PHY_CT_LOOP);
1498 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1499 bcom_check_link(hw, port);
1503 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1507 gma_write16(hw, port, GM_SMI_DATA, val);
1508 gma_write16(hw, port, GM_SMI_CTRL,
1509 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1510 for (i = 0; i < PHY_RETRIES; i++) {
1513 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1517 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1518 hw->dev[port]->name);
1522 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1526 gma_write16(hw, port, GM_SMI_CTRL,
1527 GM_SMI_CT_PHY_AD(hw->phy_addr)
1528 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1530 for (i = 0; i < PHY_RETRIES; i++) {
1532 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1538 *val = gma_read16(hw, port, GM_SMI_DATA);
1542 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1545 if (__gm_phy_read(hw, port, reg, &v))
1546 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1547 hw->dev[port]->name);
1551 /* Marvell Phy Initialization */
1552 static void yukon_init(struct skge_hw *hw, int port)
1554 struct skge_port *skge = netdev_priv(hw->dev[port]);
1555 u16 ctrl, ct1000, adv;
1557 if (skge->autoneg == AUTONEG_ENABLE) {
1558 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1560 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1561 PHY_M_EC_MAC_S_MSK);
1562 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1564 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1566 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1569 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1570 if (skge->autoneg == AUTONEG_DISABLE)
1571 ctrl &= ~PHY_CT_ANE;
1573 ctrl |= PHY_CT_RESET;
1574 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1580 if (skge->autoneg == AUTONEG_ENABLE) {
1582 if (skge->advertising & ADVERTISED_1000baseT_Full)
1583 ct1000 |= PHY_M_1000C_AFD;
1584 if (skge->advertising & ADVERTISED_1000baseT_Half)
1585 ct1000 |= PHY_M_1000C_AHD;
1586 if (skge->advertising & ADVERTISED_100baseT_Full)
1587 adv |= PHY_M_AN_100_FD;
1588 if (skge->advertising & ADVERTISED_100baseT_Half)
1589 adv |= PHY_M_AN_100_HD;
1590 if (skge->advertising & ADVERTISED_10baseT_Full)
1591 adv |= PHY_M_AN_10_FD;
1592 if (skge->advertising & ADVERTISED_10baseT_Half)
1593 adv |= PHY_M_AN_10_HD;
1594 } else /* special defines for FIBER (88E1011S only) */
1595 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1597 /* Set Flow-control capabilities */
1598 adv |= phy_pause_map[skge->flow_control];
1600 /* Restart Auto-negotiation */
1601 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1603 /* forced speed/duplex settings */
1604 ct1000 = PHY_M_1000C_MSE;
1606 if (skge->duplex == DUPLEX_FULL)
1607 ctrl |= PHY_CT_DUP_MD;
1609 switch (skge->speed) {
1611 ctrl |= PHY_CT_SP1000;
1614 ctrl |= PHY_CT_SP100;
1618 ctrl |= PHY_CT_RESET;
1621 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1623 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1624 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1626 /* Enable phy interrupt on autonegotiation complete (or link up) */
1627 if (skge->autoneg == AUTONEG_ENABLE)
1628 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1630 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1633 static void yukon_reset(struct skge_hw *hw, int port)
1635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1636 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1637 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1638 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1639 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1641 gma_write16(hw, port, GM_RX_CTRL,
1642 gma_read16(hw, port, GM_RX_CTRL)
1643 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1646 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1647 static int is_yukon_lite_a0(struct skge_hw *hw)
1652 if (hw->chip_id != CHIP_ID_YUKON)
1655 reg = skge_read32(hw, B2_FAR);
1656 skge_write8(hw, B2_FAR + 3, 0xff);
1657 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1658 skge_write32(hw, B2_FAR, reg);
1662 static void yukon_mac_init(struct skge_hw *hw, int port)
1664 struct skge_port *skge = netdev_priv(hw->dev[port]);
1667 const u8 *addr = hw->dev[port]->dev_addr;
1669 /* WA code for COMA mode -- set PHY reset */
1670 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1671 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1672 reg = skge_read32(hw, B2_GP_IO);
1673 reg |= GP_DIR_9 | GP_IO_9;
1674 skge_write32(hw, B2_GP_IO, reg);
1678 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1679 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1681 /* WA code for COMA mode -- clear PHY reset */
1682 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1683 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1684 reg = skge_read32(hw, B2_GP_IO);
1687 skge_write32(hw, B2_GP_IO, reg);
1690 /* Set hardware config mode */
1691 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1692 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1693 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1695 /* Clear GMC reset */
1696 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1697 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1698 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1699 if (skge->autoneg == AUTONEG_DISABLE) {
1700 reg = GM_GPCR_AU_ALL_DIS;
1701 gma_write16(hw, port, GM_GP_CTRL,
1702 gma_read16(hw, port, GM_GP_CTRL) | reg);
1704 switch (skge->speed) {
1706 reg |= GM_GPCR_SPEED_1000;
1709 reg |= GM_GPCR_SPEED_100;
1712 if (skge->duplex == DUPLEX_FULL)
1713 reg |= GM_GPCR_DUP_FULL;
1715 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1716 switch (skge->flow_control) {
1717 case FLOW_MODE_NONE:
1718 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1719 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1721 case FLOW_MODE_LOC_SEND:
1722 /* disable Rx flow-control */
1723 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1726 gma_write16(hw, port, GM_GP_CTRL, reg);
1727 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1729 yukon_init(hw, port);
1732 reg = gma_read16(hw, port, GM_PHY_ADDR);
1733 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1735 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1736 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1737 gma_write16(hw, port, GM_PHY_ADDR, reg);
1739 /* transmit control */
1740 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1742 /* receive control reg: unicast + multicast + no FCS */
1743 gma_write16(hw, port, GM_RX_CTRL,
1744 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1746 /* transmit flow control */
1747 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1749 /* transmit parameter */
1750 gma_write16(hw, port, GM_TX_PARAM,
1751 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1752 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1753 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1755 /* serial mode register */
1756 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1757 if (hw->dev[port]->mtu > 1500)
1758 reg |= GM_SMOD_JUMBO_ENA;
1760 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1762 /* physical address: used for pause frames */
1763 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1764 /* virtual address for data */
1765 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1767 /* enable interrupt mask for counter overflows */
1768 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1769 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1770 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1772 /* Initialize Mac Fifo */
1774 /* Configure Rx MAC FIFO */
1775 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1776 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1778 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1779 if (is_yukon_lite_a0(hw))
1780 reg &= ~GMF_RX_F_FL_ON;
1782 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1783 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1785 * because Pause Packet Truncation in GMAC is not working
1786 * we have to increase the Flush Threshold to 64 bytes
1787 * in order to flush pause packets in Rx FIFO on Yukon-1
1789 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1791 /* Configure Tx MAC FIFO */
1792 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1793 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1796 /* Go into power down mode */
1797 static void yukon_suspend(struct skge_hw *hw, int port)
1801 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1802 ctrl |= PHY_M_PC_POL_R_DIS;
1803 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1805 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1806 ctrl |= PHY_CT_RESET;
1807 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1809 /* switch IEEE compatible power down mode on */
1810 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1811 ctrl |= PHY_CT_PDOWN;
1812 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1815 static void yukon_stop(struct skge_port *skge)
1817 struct skge_hw *hw = skge->hw;
1818 int port = skge->port;
1820 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1821 yukon_reset(hw, port);
1823 gma_write16(hw, port, GM_GP_CTRL,
1824 gma_read16(hw, port, GM_GP_CTRL)
1825 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1826 gma_read16(hw, port, GM_GP_CTRL);
1828 yukon_suspend(hw, port);
1830 /* set GPHY Control reset */
1831 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1832 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1835 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1837 struct skge_hw *hw = skge->hw;
1838 int port = skge->port;
1841 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1842 | gma_read32(hw, port, GM_TXO_OK_LO);
1843 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1844 | gma_read32(hw, port, GM_RXO_OK_LO);
1846 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1847 data[i] = gma_read32(hw, port,
1848 skge_stats[i].gma_offset);
1851 static void yukon_mac_intr(struct skge_hw *hw, int port)
1853 struct net_device *dev = hw->dev[port];
1854 struct skge_port *skge = netdev_priv(dev);
1855 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1857 if (netif_msg_intr(skge))
1858 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1861 if (status & GM_IS_RX_FF_OR) {
1862 ++skge->net_stats.rx_fifo_errors;
1863 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1866 if (status & GM_IS_TX_FF_UR) {
1867 ++skge->net_stats.tx_fifo_errors;
1868 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1873 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1875 switch (aux & PHY_M_PS_SPEED_MSK) {
1876 case PHY_M_PS_SPEED_1000:
1878 case PHY_M_PS_SPEED_100:
1885 static void yukon_link_up(struct skge_port *skge)
1887 struct skge_hw *hw = skge->hw;
1888 int port = skge->port;
1891 /* Enable Transmit FIFO Underrun */
1892 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1894 reg = gma_read16(hw, port, GM_GP_CTRL);
1895 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1896 reg |= GM_GPCR_DUP_FULL;
1899 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1900 gma_write16(hw, port, GM_GP_CTRL, reg);
1902 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1906 static void yukon_link_down(struct skge_port *skge)
1908 struct skge_hw *hw = skge->hw;
1909 int port = skge->port;
1912 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1914 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1915 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1916 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1918 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1919 /* restore Asymmetric Pause bit */
1920 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1921 gm_phy_read(hw, port,
1927 yukon_reset(hw, port);
1928 skge_link_down(skge);
1930 yukon_init(hw, port);
1933 static void yukon_phy_intr(struct skge_port *skge)
1935 struct skge_hw *hw = skge->hw;
1936 int port = skge->port;
1937 const char *reason = NULL;
1938 u16 istatus, phystat;
1940 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1941 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1943 if (netif_msg_intr(skge))
1944 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1945 skge->netdev->name, istatus, phystat);
1947 if (istatus & PHY_M_IS_AN_COMPL) {
1948 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1950 reason = "remote fault";
1954 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1955 reason = "master/slave fault";
1959 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1960 reason = "speed/duplex";
1964 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1965 ? DUPLEX_FULL : DUPLEX_HALF;
1966 skge->speed = yukon_speed(hw, phystat);
1968 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1969 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1970 case PHY_M_PS_PAUSE_MSK:
1971 skge->flow_control = FLOW_MODE_SYMMETRIC;
1973 case PHY_M_PS_RX_P_EN:
1974 skge->flow_control = FLOW_MODE_REM_SEND;
1976 case PHY_M_PS_TX_P_EN:
1977 skge->flow_control = FLOW_MODE_LOC_SEND;
1980 skge->flow_control = FLOW_MODE_NONE;
1983 if (skge->flow_control == FLOW_MODE_NONE ||
1984 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1985 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1987 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1988 yukon_link_up(skge);
1992 if (istatus & PHY_M_IS_LSP_CHANGE)
1993 skge->speed = yukon_speed(hw, phystat);
1995 if (istatus & PHY_M_IS_DUP_CHANGE)
1996 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1997 if (istatus & PHY_M_IS_LST_CHANGE) {
1998 if (phystat & PHY_M_PS_LINK_UP)
1999 yukon_link_up(skge);
2001 yukon_link_down(skge);
2005 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2006 skge->netdev->name, reason);
2008 /* XXX restart autonegotiation? */
2011 static void skge_phy_reset(struct skge_port *skge)
2013 struct skge_hw *hw = skge->hw;
2014 int port = skge->port;
2016 netif_stop_queue(skge->netdev);
2017 netif_carrier_off(skge->netdev);
2019 spin_lock_bh(&hw->phy_lock);
2020 if (hw->chip_id == CHIP_ID_GENESIS) {
2021 genesis_reset(hw, port);
2022 genesis_mac_init(hw, port);
2024 yukon_reset(hw, port);
2025 yukon_init(hw, port);
2027 spin_unlock_bh(&hw->phy_lock);
2030 /* Basic MII support */
2031 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2033 struct mii_ioctl_data *data = if_mii(ifr);
2034 struct skge_port *skge = netdev_priv(dev);
2035 struct skge_hw *hw = skge->hw;
2036 int err = -EOPNOTSUPP;
2038 if (!netif_running(dev))
2039 return -ENODEV; /* Phy still in reset */
2043 data->phy_id = hw->phy_addr;
2048 spin_lock_bh(&hw->phy_lock);
2049 if (hw->chip_id == CHIP_ID_GENESIS)
2050 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2052 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2053 spin_unlock_bh(&hw->phy_lock);
2054 data->val_out = val;
2059 if (!capable(CAP_NET_ADMIN))
2062 spin_lock_bh(&hw->phy_lock);
2063 if (hw->chip_id == CHIP_ID_GENESIS)
2064 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2067 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2069 spin_unlock_bh(&hw->phy_lock);
2075 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2081 end = start + len - 1;
2083 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2084 skge_write32(hw, RB_ADDR(q, RB_START), start);
2085 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2086 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2087 skge_write32(hw, RB_ADDR(q, RB_END), end);
2089 if (q == Q_R1 || q == Q_R2) {
2090 /* Set thresholds on receive queue's */
2091 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2093 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2096 /* Enable store & forward on Tx queue's because
2097 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2099 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2102 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2105 /* Setup Bus Memory Interface */
2106 static void skge_qset(struct skge_port *skge, u16 q,
2107 const struct skge_element *e)
2109 struct skge_hw *hw = skge->hw;
2110 u32 watermark = 0x600;
2111 u64 base = skge->dma + (e->desc - skge->mem);
2113 /* optimization to reduce window on 32bit/33mhz */
2114 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2117 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2118 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2119 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2120 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2123 static int skge_up(struct net_device *dev)
2125 struct skge_port *skge = netdev_priv(dev);
2126 struct skge_hw *hw = skge->hw;
2127 int port = skge->port;
2128 u32 chunk, ram_addr;
2129 size_t rx_size, tx_size;
2132 if (netif_msg_ifup(skge))
2133 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2135 if (dev->mtu > RX_BUF_SIZE)
2136 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2138 skge->rx_buf_size = RX_BUF_SIZE;
2141 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2142 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2143 skge->mem_size = tx_size + rx_size;
2144 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2148 memset(skge->mem, 0, skge->mem_size);
2150 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2153 err = skge_rx_fill(skge);
2157 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2158 skge->dma + rx_size)))
2161 skge->tx_avail = skge->tx_ring.count - 1;
2163 /* Enable IRQ from port */
2164 hw->intr_mask |= portirqmask[port];
2165 skge_write32(hw, B0_IMSK, hw->intr_mask);
2167 /* Initialize MAC */
2168 spin_lock_bh(&hw->phy_lock);
2169 if (hw->chip_id == CHIP_ID_GENESIS)
2170 genesis_mac_init(hw, port);
2172 yukon_mac_init(hw, port);
2173 spin_unlock_bh(&hw->phy_lock);
2175 /* Configure RAMbuffers */
2176 chunk = hw->ram_size / ((hw->ports + 1)*2);
2177 ram_addr = hw->ram_offset + 2 * chunk * port;
2179 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2180 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2182 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2183 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2184 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2186 /* Start receiver BMU */
2188 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2189 skge_led(skge, LED_MODE_ON);
2194 skge_rx_clean(skge);
2195 kfree(skge->rx_ring.start);
2197 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2203 static int skge_down(struct net_device *dev)
2205 struct skge_port *skge = netdev_priv(dev);
2206 struct skge_hw *hw = skge->hw;
2207 int port = skge->port;
2209 if (skge->mem == NULL)
2212 if (netif_msg_ifdown(skge))
2213 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2215 netif_stop_queue(dev);
2217 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2218 if (hw->chip_id == CHIP_ID_GENESIS)
2223 hw->intr_mask &= ~portirqmask[skge->port];
2224 skge_write32(hw, B0_IMSK, hw->intr_mask);
2226 /* Stop transmitter */
2227 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2228 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2229 RB_RST_SET|RB_DIS_OP_MD);
2232 /* Disable Force Sync bit and Enable Alloc bit */
2233 skge_write8(hw, SK_REG(port, TXA_CTRL),
2234 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2236 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2237 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2238 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2240 /* Reset PCI FIFO */
2241 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2242 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2244 /* Reset the RAM Buffer async Tx queue */
2245 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2247 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2248 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2249 RB_RST_SET|RB_DIS_OP_MD);
2250 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2252 if (hw->chip_id == CHIP_ID_GENESIS) {
2253 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2254 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2256 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2257 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2260 skge_led(skge, LED_MODE_OFF);
2262 skge_tx_clean(skge);
2263 skge_rx_clean(skge);
2265 kfree(skge->rx_ring.start);
2266 kfree(skge->tx_ring.start);
2267 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2272 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2274 struct skge_port *skge = netdev_priv(dev);
2275 struct skge_hw *hw = skge->hw;
2276 struct skge_ring *ring = &skge->tx_ring;
2277 struct skge_element *e;
2278 struct skge_tx_desc *td;
2282 unsigned long flags;
2284 skb = skb_padto(skb, ETH_ZLEN);
2286 return NETDEV_TX_OK;
2288 local_irq_save(flags);
2289 if (!spin_trylock(&skge->tx_lock)) {
2290 /* Collision - tell upper layer to requeue */
2291 local_irq_restore(flags);
2292 return NETDEV_TX_LOCKED;
2295 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2296 if (!netif_queue_stopped(dev)) {
2297 netif_stop_queue(dev);
2299 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2302 spin_unlock_irqrestore(&skge->tx_lock, flags);
2303 return NETDEV_TX_BUSY;
2309 len = skb_headlen(skb);
2310 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2311 pci_unmap_addr_set(e, mapaddr, map);
2312 pci_unmap_len_set(e, maplen, len);
2315 td->dma_hi = map >> 32;
2317 if (skb->ip_summed == CHECKSUM_HW) {
2318 int offset = skb->h.raw - skb->data;
2320 /* This seems backwards, but it is what the sk98lin
2321 * does. Looks like hardware is wrong?
2323 if (skb->h.ipiph->protocol == IPPROTO_UDP
2324 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2325 control = BMU_TCP_CHECK;
2327 control = BMU_UDP_CHECK;
2330 td->csum_start = offset;
2331 td->csum_write = offset + skb->csum;
2333 control = BMU_CHECK;
2335 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2336 control |= BMU_EOF| BMU_IRQ_EOF;
2338 struct skge_tx_desc *tf = td;
2340 control |= BMU_STFWD;
2341 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2342 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2344 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2345 frag->size, PCI_DMA_TODEVICE);
2351 tf->dma_hi = (u64) map >> 32;
2352 pci_unmap_addr_set(e, mapaddr, map);
2353 pci_unmap_len_set(e, maplen, frag->size);
2355 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2357 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2359 /* Make sure all the descriptors written */
2361 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2364 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2366 if (netif_msg_tx_queued(skge))
2367 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2368 dev->name, e - ring->start, skb->len);
2370 ring->to_use = e->next;
2371 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2372 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2373 pr_debug("%s: transmit queue full\n", dev->name);
2374 netif_stop_queue(dev);
2377 dev->trans_start = jiffies;
2378 spin_unlock_irqrestore(&skge->tx_lock, flags);
2380 return NETDEV_TX_OK;
2383 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2385 /* This ring element can be skb or fragment */
2387 pci_unmap_single(hw->pdev,
2388 pci_unmap_addr(e, mapaddr),
2389 pci_unmap_len(e, maplen),
2391 dev_kfree_skb_any(e->skb);
2394 pci_unmap_page(hw->pdev,
2395 pci_unmap_addr(e, mapaddr),
2396 pci_unmap_len(e, maplen),
2401 static void skge_tx_clean(struct skge_port *skge)
2403 struct skge_ring *ring = &skge->tx_ring;
2404 struct skge_element *e;
2405 unsigned long flags;
2407 spin_lock_irqsave(&skge->tx_lock, flags);
2408 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2410 skge_tx_free(skge->hw, e);
2413 spin_unlock_irqrestore(&skge->tx_lock, flags);
2416 static void skge_tx_timeout(struct net_device *dev)
2418 struct skge_port *skge = netdev_priv(dev);
2420 if (netif_msg_timer(skge))
2421 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2423 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2424 skge_tx_clean(skge);
2427 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2431 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2434 if (!netif_running(dev)) {
2450 static void genesis_set_multicast(struct net_device *dev)
2452 struct skge_port *skge = netdev_priv(dev);
2453 struct skge_hw *hw = skge->hw;
2454 int port = skge->port;
2455 int i, count = dev->mc_count;
2456 struct dev_mc_list *list = dev->mc_list;
2460 mode = xm_read32(hw, port, XM_MODE);
2461 mode |= XM_MD_ENA_HASH;
2462 if (dev->flags & IFF_PROMISC)
2463 mode |= XM_MD_ENA_PROM;
2465 mode &= ~XM_MD_ENA_PROM;
2467 if (dev->flags & IFF_ALLMULTI)
2468 memset(filter, 0xff, sizeof(filter));
2470 memset(filter, 0, sizeof(filter));
2471 for (i = 0; list && i < count; i++, list = list->next) {
2473 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2475 filter[bit/8] |= 1 << (bit%8);
2479 xm_write32(hw, port, XM_MODE, mode);
2480 xm_outhash(hw, port, XM_HSM, filter);
2483 static void yukon_set_multicast(struct net_device *dev)
2485 struct skge_port *skge = netdev_priv(dev);
2486 struct skge_hw *hw = skge->hw;
2487 int port = skge->port;
2488 struct dev_mc_list *list = dev->mc_list;
2492 memset(filter, 0, sizeof(filter));
2494 reg = gma_read16(hw, port, GM_RX_CTRL);
2495 reg |= GM_RXCR_UCF_ENA;
2497 if (dev->flags & IFF_PROMISC) /* promiscuous */
2498 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2499 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2500 memset(filter, 0xff, sizeof(filter));
2501 else if (dev->mc_count == 0) /* no multicast */
2502 reg &= ~GM_RXCR_MCF_ENA;
2505 reg |= GM_RXCR_MCF_ENA;
2507 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2508 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2509 filter[bit/8] |= 1 << (bit%8);
2514 gma_write16(hw, port, GM_MC_ADDR_H1,
2515 (u16)filter[0] | ((u16)filter[1] << 8));
2516 gma_write16(hw, port, GM_MC_ADDR_H2,
2517 (u16)filter[2] | ((u16)filter[3] << 8));
2518 gma_write16(hw, port, GM_MC_ADDR_H3,
2519 (u16)filter[4] | ((u16)filter[5] << 8));
2520 gma_write16(hw, port, GM_MC_ADDR_H4,
2521 (u16)filter[6] | ((u16)filter[7] << 8));
2523 gma_write16(hw, port, GM_RX_CTRL, reg);
2526 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2528 if (hw->chip_id == CHIP_ID_GENESIS)
2529 return status >> XMR_FS_LEN_SHIFT;
2531 return status >> GMR_FS_LEN_SHIFT;
2534 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2536 if (hw->chip_id == CHIP_ID_GENESIS)
2537 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2539 return (status & GMR_FS_ANY_ERR) ||
2540 (status & GMR_FS_RX_OK) == 0;
2544 /* Get receive buffer from descriptor.
2545 * Handles copy of small buffers and reallocation failures
2547 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2548 struct skge_element *e,
2549 u32 control, u32 status, u16 csum)
2551 struct sk_buff *skb;
2552 u16 len = control & BMU_BBC;
2554 if (unlikely(netif_msg_rx_status(skge)))
2555 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2556 skge->netdev->name, e - skge->rx_ring.start,
2559 if (len > skge->rx_buf_size)
2562 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2565 if (bad_phy_status(skge->hw, status))
2568 if (phy_length(skge->hw, status) != len)
2571 if (len < RX_COPY_THRESHOLD) {
2572 skb = dev_alloc_skb(len + 2);
2576 skb_reserve(skb, 2);
2577 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2578 pci_unmap_addr(e, mapaddr),
2579 len, PCI_DMA_FROMDEVICE);
2580 memcpy(skb->data, e->skb->data, len);
2581 pci_dma_sync_single_for_device(skge->hw->pdev,
2582 pci_unmap_addr(e, mapaddr),
2583 len, PCI_DMA_FROMDEVICE);
2584 skge_rx_reuse(e, skge->rx_buf_size);
2586 struct sk_buff *nskb;
2587 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2591 pci_unmap_single(skge->hw->pdev,
2592 pci_unmap_addr(e, mapaddr),
2593 pci_unmap_len(e, maplen),
2594 PCI_DMA_FROMDEVICE);
2596 prefetch(skb->data);
2597 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2601 skb->dev = skge->netdev;
2602 if (skge->rx_csum) {
2604 skb->ip_summed = CHECKSUM_HW;
2607 skb->protocol = eth_type_trans(skb, skge->netdev);
2612 if (netif_msg_rx_err(skge))
2613 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2614 skge->netdev->name, e - skge->rx_ring.start,
2617 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2618 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2619 skge->net_stats.rx_length_errors++;
2620 if (status & XMR_FS_FRA_ERR)
2621 skge->net_stats.rx_frame_errors++;
2622 if (status & XMR_FS_FCS_ERR)
2623 skge->net_stats.rx_crc_errors++;
2625 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2626 skge->net_stats.rx_length_errors++;
2627 if (status & GMR_FS_FRAGMENT)
2628 skge->net_stats.rx_frame_errors++;
2629 if (status & GMR_FS_CRC_ERR)
2630 skge->net_stats.rx_crc_errors++;
2634 skge_rx_reuse(e, skge->rx_buf_size);
2639 static int skge_poll(struct net_device *dev, int *budget)
2641 struct skge_port *skge = netdev_priv(dev);
2642 struct skge_hw *hw = skge->hw;
2643 struct skge_ring *ring = &skge->rx_ring;
2644 struct skge_element *e;
2645 unsigned int to_do = min(dev->quota, *budget);
2646 unsigned int work_done = 0;
2648 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
2649 struct skge_rx_desc *rd = e->desc;
2650 struct sk_buff *skb;
2654 control = rd->control;
2655 if (control & BMU_OWN)
2658 skb = skge_rx_get(skge, e, control, rd->status,
2659 le16_to_cpu(rd->csum2));
2661 dev->last_rx = jiffies;
2662 netif_receive_skb(skb);
2666 skge_rx_reuse(e, skge->rx_buf_size);
2670 /* restart receiver */
2672 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2673 CSR_START | CSR_IRQ_CL_F);
2675 *budget -= work_done;
2676 dev->quota -= work_done;
2678 if (work_done >= to_do)
2679 return 1; /* not done */
2681 netif_rx_complete(dev);
2682 hw->intr_mask |= portirqmask[skge->port];
2683 skge_write32(hw, B0_IMSK, hw->intr_mask);
2684 skge_read32(hw, B0_IMSK);
2689 static inline void skge_tx_intr(struct net_device *dev)
2691 struct skge_port *skge = netdev_priv(dev);
2692 struct skge_hw *hw = skge->hw;
2693 struct skge_ring *ring = &skge->tx_ring;
2694 struct skge_element *e;
2696 spin_lock(&skge->tx_lock);
2697 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
2698 struct skge_tx_desc *td = e->desc;
2702 control = td->control;
2703 if (control & BMU_OWN)
2706 if (unlikely(netif_msg_tx_done(skge)))
2707 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2708 dev->name, e - ring->start, td->status);
2710 skge_tx_free(hw, e);
2715 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2717 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2718 netif_wake_queue(dev);
2720 spin_unlock(&skge->tx_lock);
2723 /* Parity errors seem to happen when Genesis is connected to a switch
2724 * with no other ports present. Heartbeat error??
2726 static void skge_mac_parity(struct skge_hw *hw, int port)
2728 struct net_device *dev = hw->dev[port];
2731 struct skge_port *skge = netdev_priv(dev);
2732 ++skge->net_stats.tx_heartbeat_errors;
2735 if (hw->chip_id == CHIP_ID_GENESIS)
2736 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2739 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2740 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2741 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2742 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2745 static void skge_pci_clear(struct skge_hw *hw)
2749 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2750 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2751 pci_write_config_word(hw->pdev, PCI_STATUS,
2752 status | PCI_STATUS_ERROR_BITS);
2753 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2756 static void skge_mac_intr(struct skge_hw *hw, int port)
2758 if (hw->chip_id == CHIP_ID_GENESIS)
2759 genesis_mac_intr(hw, port);
2761 yukon_mac_intr(hw, port);
2764 /* Handle device specific framing and timeout interrupts */
2765 static void skge_error_irq(struct skge_hw *hw)
2767 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2769 if (hw->chip_id == CHIP_ID_GENESIS) {
2770 /* clear xmac errors */
2771 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2772 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2773 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2774 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2776 /* Timestamp (unused) overflow */
2777 if (hwstatus & IS_IRQ_TIST_OV)
2778 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2781 if (hwstatus & IS_RAM_RD_PAR) {
2782 printk(KERN_ERR PFX "Ram read data parity error\n");
2783 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2786 if (hwstatus & IS_RAM_WR_PAR) {
2787 printk(KERN_ERR PFX "Ram write data parity error\n");
2788 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2791 if (hwstatus & IS_M1_PAR_ERR)
2792 skge_mac_parity(hw, 0);
2794 if (hwstatus & IS_M2_PAR_ERR)
2795 skge_mac_parity(hw, 1);
2797 if (hwstatus & IS_R1_PAR_ERR)
2798 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2800 if (hwstatus & IS_R2_PAR_ERR)
2801 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2803 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2804 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2809 /* if error still set then just ignore it */
2810 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2811 if (hwstatus & IS_IRQ_STAT) {
2812 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2814 hw->intr_mask &= ~IS_HW_ERR;
2820 * Interrupt from PHY are handled in tasklet (soft irq)
2821 * because accessing phy registers requires spin wait which might
2822 * cause excess interrupt latency.
2824 static void skge_extirq(unsigned long data)
2826 struct skge_hw *hw = (struct skge_hw *) data;
2829 spin_lock(&hw->phy_lock);
2830 for (port = 0; port < 2; port++) {
2831 struct net_device *dev = hw->dev[port];
2833 if (dev && netif_running(dev)) {
2834 struct skge_port *skge = netdev_priv(dev);
2836 if (hw->chip_id != CHIP_ID_GENESIS)
2837 yukon_phy_intr(skge);
2839 bcom_phy_intr(skge);
2842 spin_unlock(&hw->phy_lock);
2844 local_irq_disable();
2845 hw->intr_mask |= IS_EXT_REG;
2846 skge_write32(hw, B0_IMSK, hw->intr_mask);
2850 static inline void skge_wakeup(struct net_device *dev)
2852 struct skge_port *skge = netdev_priv(dev);
2854 prefetch(skge->rx_ring.to_clean);
2855 netif_rx_schedule(dev);
2858 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2860 struct skge_hw *hw = dev_id;
2861 u32 status = skge_read32(hw, B0_SP_ISRC);
2863 if (status == 0 || status == ~0) /* hotplug or shared irq */
2866 status &= hw->intr_mask;
2867 if (status & IS_R1_F) {
2868 hw->intr_mask &= ~IS_R1_F;
2869 skge_wakeup(hw->dev[0]);
2872 if (status & IS_R2_F) {
2873 hw->intr_mask &= ~IS_R2_F;
2874 skge_wakeup(hw->dev[1]);
2877 if (status & IS_XA1_F)
2878 skge_tx_intr(hw->dev[0]);
2880 if (status & IS_XA2_F)
2881 skge_tx_intr(hw->dev[1]);
2883 if (status & IS_PA_TO_RX1) {
2884 struct skge_port *skge = netdev_priv(hw->dev[0]);
2885 ++skge->net_stats.rx_over_errors;
2886 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2889 if (status & IS_PA_TO_RX2) {
2890 struct skge_port *skge = netdev_priv(hw->dev[1]);
2891 ++skge->net_stats.rx_over_errors;
2892 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2895 if (status & IS_PA_TO_TX1)
2896 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2898 if (status & IS_PA_TO_TX2)
2899 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2901 if (status & IS_MAC1)
2902 skge_mac_intr(hw, 0);
2904 if (status & IS_MAC2)
2905 skge_mac_intr(hw, 1);
2907 if (status & IS_HW_ERR)
2910 if (status & IS_EXT_REG) {
2911 hw->intr_mask &= ~IS_EXT_REG;
2912 tasklet_schedule(&hw->ext_tasklet);
2915 skge_write32(hw, B0_IMSK, hw->intr_mask);
2920 #ifdef CONFIG_NET_POLL_CONTROLLER
2921 static void skge_netpoll(struct net_device *dev)
2923 struct skge_port *skge = netdev_priv(dev);
2925 disable_irq(dev->irq);
2926 skge_intr(dev->irq, skge->hw, NULL);
2927 enable_irq(dev->irq);
2931 static int skge_set_mac_address(struct net_device *dev, void *p)
2933 struct skge_port *skge = netdev_priv(dev);
2934 struct skge_hw *hw = skge->hw;
2935 unsigned port = skge->port;
2936 const struct sockaddr *addr = p;
2938 if (!is_valid_ether_addr(addr->sa_data))
2939 return -EADDRNOTAVAIL;
2941 spin_lock_bh(&hw->phy_lock);
2942 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2943 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2944 dev->dev_addr, ETH_ALEN);
2945 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2946 dev->dev_addr, ETH_ALEN);
2948 if (hw->chip_id == CHIP_ID_GENESIS)
2949 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2951 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2952 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2954 spin_unlock_bh(&hw->phy_lock);
2959 static const struct {
2963 { CHIP_ID_GENESIS, "Genesis" },
2964 { CHIP_ID_YUKON, "Yukon" },
2965 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2966 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2969 static const char *skge_board_name(const struct skge_hw *hw)
2972 static char buf[16];
2974 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2975 if (skge_chips[i].id == hw->chip_id)
2976 return skge_chips[i].name;
2978 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2984 * Setup the board data structure, but don't bring up
2987 static int skge_reset(struct skge_hw *hw)
2991 u8 t8, mac_cfg, pmd_type, phy_type;
2994 ctst = skge_read16(hw, B0_CTST);
2997 skge_write8(hw, B0_CTST, CS_RST_SET);
2998 skge_write8(hw, B0_CTST, CS_RST_CLR);
3000 /* clear PCI errors, if any */
3003 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3005 /* restore CLK_RUN bits (for Yukon-Lite) */
3006 skge_write16(hw, B0_CTST,
3007 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3009 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3010 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3011 pmd_type = skge_read8(hw, B2_PMD_TYP);
3012 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3014 switch (hw->chip_id) {
3015 case CHIP_ID_GENESIS:
3018 hw->phy_addr = PHY_ADDR_BCOM;
3021 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
3022 pci_name(hw->pdev), phy_type);
3028 case CHIP_ID_YUKON_LITE:
3029 case CHIP_ID_YUKON_LP:
3030 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3033 hw->phy_addr = PHY_ADDR_MARV;
3037 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3038 pci_name(hw->pdev), hw->chip_id);
3042 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3043 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3044 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3046 /* read the adapters RAM size */
3047 t8 = skge_read8(hw, B2_E_0);
3048 if (hw->chip_id == CHIP_ID_GENESIS) {
3050 /* special case: 4 x 64k x 36, offset = 0x80000 */
3051 hw->ram_size = 0x100000;
3052 hw->ram_offset = 0x80000;
3054 hw->ram_size = t8 * 512;
3057 hw->ram_size = 0x20000;
3059 hw->ram_size = t8 * 4096;
3061 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
3062 if (hw->chip_id == CHIP_ID_GENESIS)
3065 /* switch power to VCC (WA for VAUX problem) */
3066 skge_write8(hw, B0_POWER_CTRL,
3067 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3069 /* avoid boards with stuck Hardware error bits */
3070 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3071 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3072 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3073 hw->intr_mask &= ~IS_HW_ERR;
3076 /* Clear PHY COMA */
3077 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3078 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3079 reg &= ~PCI_PHY_COMA;
3080 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3081 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3084 for (i = 0; i < hw->ports; i++) {
3085 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3086 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3090 /* turn off hardware timer (unused) */
3091 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3092 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3093 skge_write8(hw, B0_LED, LED_STAT_ON);
3095 /* enable the Tx Arbiters */
3096 for (i = 0; i < hw->ports; i++)
3097 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3099 /* Initialize ram interface */
3100 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3102 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3103 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3104 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3105 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3106 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3107 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3108 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3109 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3110 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3111 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3112 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3113 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3115 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3117 /* Set interrupt moderation for Transmit only
3118 * Receive interrupts avoided by NAPI
3120 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3121 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3122 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3124 skge_write32(hw, B0_IMSK, hw->intr_mask);
3126 spin_lock_bh(&hw->phy_lock);
3127 for (i = 0; i < hw->ports; i++) {
3128 if (hw->chip_id == CHIP_ID_GENESIS)
3129 genesis_reset(hw, i);
3133 spin_unlock_bh(&hw->phy_lock);
3138 /* Initialize network device */
3139 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3142 struct skge_port *skge;
3143 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3146 printk(KERN_ERR "skge etherdev alloc failed");
3150 SET_MODULE_OWNER(dev);
3151 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3152 dev->open = skge_up;
3153 dev->stop = skge_down;
3154 dev->do_ioctl = skge_ioctl;
3155 dev->hard_start_xmit = skge_xmit_frame;
3156 dev->get_stats = skge_get_stats;
3157 if (hw->chip_id == CHIP_ID_GENESIS)
3158 dev->set_multicast_list = genesis_set_multicast;
3160 dev->set_multicast_list = yukon_set_multicast;
3162 dev->set_mac_address = skge_set_mac_address;
3163 dev->change_mtu = skge_change_mtu;
3164 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3165 dev->tx_timeout = skge_tx_timeout;
3166 dev->watchdog_timeo = TX_WATCHDOG;
3167 dev->poll = skge_poll;
3168 dev->weight = NAPI_WEIGHT;
3169 #ifdef CONFIG_NET_POLL_CONTROLLER
3170 dev->poll_controller = skge_netpoll;
3172 dev->irq = hw->pdev->irq;
3173 dev->features = NETIF_F_LLTX;
3175 dev->features |= NETIF_F_HIGHDMA;
3177 skge = netdev_priv(dev);
3180 skge->msg_enable = netif_msg_init(debug, default_msg);
3181 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3182 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3184 /* Auto speed and flow control */
3185 skge->autoneg = AUTONEG_ENABLE;
3186 skge->flow_control = FLOW_MODE_SYMMETRIC;
3189 skge->advertising = skge_supported_modes(hw);
3191 hw->dev[port] = dev;
3195 spin_lock_init(&skge->tx_lock);
3197 if (hw->chip_id != CHIP_ID_GENESIS) {
3198 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3202 /* read the mac address */
3203 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3204 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3206 /* device is off until link detection */
3207 netif_carrier_off(dev);
3208 netif_stop_queue(dev);
3213 static void __devinit skge_show_addr(struct net_device *dev)
3215 const struct skge_port *skge = netdev_priv(dev);
3217 if (netif_msg_probe(skge))
3218 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3220 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3221 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3224 static int __devinit skge_probe(struct pci_dev *pdev,
3225 const struct pci_device_id *ent)
3227 struct net_device *dev, *dev1;
3229 int err, using_dac = 0;
3231 if ((err = pci_enable_device(pdev))) {
3232 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3237 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3238 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3240 goto err_out_disable_pdev;
3243 pci_set_master(pdev);
3245 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3247 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3248 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3250 goto err_out_free_regions;
3254 /* byte swap descriptors in hardware */
3258 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3259 reg |= PCI_REV_DESC;
3260 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3265 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3267 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3269 goto err_out_free_regions;
3273 spin_lock_init(&hw->phy_lock);
3274 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3276 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3278 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3280 goto err_out_free_hw;
3283 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3284 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3285 pci_name(pdev), pdev->irq);
3286 goto err_out_iounmap;
3288 pci_set_drvdata(pdev, hw);
3290 err = skge_reset(hw);
3292 goto err_out_free_irq;
3294 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
3295 pci_resource_start(pdev, 0), pdev->irq,
3296 skge_board_name(hw), hw->chip_rev);
3298 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3299 goto err_out_led_off;
3301 if ((err = register_netdev(dev))) {
3302 printk(KERN_ERR PFX "%s: cannot register net device\n",
3304 goto err_out_free_netdev;
3307 skge_show_addr(dev);
3309 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3310 if (register_netdev(dev1) == 0)
3311 skge_show_addr(dev1);
3313 /* Failure to register second port need not be fatal */
3314 printk(KERN_WARNING PFX "register of second port failed\n");
3322 err_out_free_netdev:
3325 skge_write16(hw, B0_LED, LED_STAT_OFF);
3327 free_irq(pdev->irq, hw);
3332 err_out_free_regions:
3333 pci_release_regions(pdev);
3334 err_out_disable_pdev:
3335 pci_disable_device(pdev);
3336 pci_set_drvdata(pdev, NULL);
3341 static void __devexit skge_remove(struct pci_dev *pdev)
3343 struct skge_hw *hw = pci_get_drvdata(pdev);
3344 struct net_device *dev0, *dev1;
3349 if ((dev1 = hw->dev[1]))
3350 unregister_netdev(dev1);
3352 unregister_netdev(dev0);
3354 skge_write32(hw, B0_IMSK, 0);
3355 skge_write16(hw, B0_LED, LED_STAT_OFF);
3357 skge_write8(hw, B0_CTST, CS_RST_SET);
3359 tasklet_kill(&hw->ext_tasklet);
3361 free_irq(pdev->irq, hw);
3362 pci_release_regions(pdev);
3363 pci_disable_device(pdev);
3370 pci_set_drvdata(pdev, NULL);
3374 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3376 struct skge_hw *hw = pci_get_drvdata(pdev);
3379 for (i = 0; i < 2; i++) {
3380 struct net_device *dev = hw->dev[i];
3383 struct skge_port *skge = netdev_priv(dev);
3384 if (netif_running(dev)) {
3385 netif_carrier_off(dev);
3387 netif_stop_queue(dev);
3391 netif_device_detach(dev);
3396 pci_save_state(pdev);
3397 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3398 pci_disable_device(pdev);
3399 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3404 static int skge_resume(struct pci_dev *pdev)
3406 struct skge_hw *hw = pci_get_drvdata(pdev);
3409 pci_set_power_state(pdev, PCI_D0);
3410 pci_restore_state(pdev);
3411 pci_enable_wake(pdev, PCI_D0, 0);
3415 for (i = 0; i < 2; i++) {
3416 struct net_device *dev = hw->dev[i];
3418 netif_device_attach(dev);
3419 if (netif_running(dev) && skge_up(dev))
3427 static struct pci_driver skge_driver = {
3429 .id_table = skge_id_table,
3430 .probe = skge_probe,
3431 .remove = __devexit_p(skge_remove),
3433 .suspend = skge_suspend,
3434 .resume = skge_resume,
3438 static int __init skge_init_module(void)
3440 return pci_module_init(&skge_driver);
3443 static void __exit skge_cleanup_module(void)
3445 pci_unregister_driver(&skge_driver);
3448 module_init(skge_init_module);
3449 module_exit(skge_cleanup_module);