2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
27 #include <linux/list.h>
28 #include <linux/syscalls.h>
29 #include <linux/irq.h>
30 #include <linux/vmalloc.h>
32 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
37 #include <asm/machdep.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/firmware.h>
42 static DEFINE_SPINLOCK(hose_spinlock);
44 /* XXX kill that some day ... */
45 static int global_phb_number; /* Global phb counter */
47 /* ISA Memory physical address */
48 resource_size_t isa_mem_base;
50 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
51 unsigned int ppc_pci_flags = 0;
54 static struct dma_mapping_ops *pci_dma_ops;
56 void set_pci_dma_ops(struct dma_mapping_ops *dma_ops)
58 pci_dma_ops = dma_ops;
61 struct dma_mapping_ops *get_pci_dma_ops(void)
65 EXPORT_SYMBOL(get_pci_dma_ops);
67 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
69 return dma_set_mask(&dev->dev, mask);
72 int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
76 rc = dma_set_mask(&dev->dev, mask);
77 dev->dev.coherent_dma_mask = dev->dma_mask;
82 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
84 struct pci_controller *phb;
86 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
89 spin_lock(&hose_spinlock);
90 phb->global_number = global_phb_number++;
91 list_add_tail(&phb->list_node, &hose_list);
92 spin_unlock(&hose_spinlock);
94 phb->is_dynamic = mem_init_done;
97 int nid = of_node_to_nid(dev);
99 if (nid < 0 || !node_online(nid))
102 PHB_SET_NODE(phb, nid);
108 void pcibios_free_controller(struct pci_controller *phb)
110 spin_lock(&hose_spinlock);
111 list_del(&phb->list_node);
112 spin_unlock(&hose_spinlock);
118 int pcibios_vaddr_is_ioport(void __iomem *address)
121 struct pci_controller *hose;
124 spin_lock(&hose_spinlock);
125 list_for_each_entry(hose, &hose_list, list_node) {
127 size = hose->pci_io_size;
129 size = hose->io_resource.end - hose->io_resource.start + 1;
131 if (address >= hose->io_base_virt &&
132 address < (hose->io_base_virt + size)) {
137 spin_unlock(&hose_spinlock);
142 * Return the domain number for this bus.
144 int pci_domain_nr(struct pci_bus *bus)
146 struct pci_controller *hose = pci_bus_to_host(bus);
148 return hose->global_number;
150 EXPORT_SYMBOL(pci_domain_nr);
154 /* This routine is meant to be used early during boot, when the
155 * PCI bus numbers have not yet been assigned, and you need to
156 * issue PCI config cycles to an OF device.
157 * It could also be used to "fix" RTAS config cycles if you want
158 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
161 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
164 struct pci_controller *hose, *tmp;
165 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
166 if (hose->dn == node)
173 static ssize_t pci_show_devspec(struct device *dev,
174 struct device_attribute *attr, char *buf)
176 struct pci_dev *pdev;
177 struct device_node *np;
179 pdev = to_pci_dev (dev);
180 np = pci_device_to_OF_node(pdev);
181 if (np == NULL || np->full_name == NULL)
183 return sprintf(buf, "%s", np->full_name);
185 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
186 #endif /* CONFIG_PPC_OF */
188 /* Add sysfs properties */
189 int pcibios_add_platform_entries(struct pci_dev *pdev)
192 return device_create_file(&pdev->dev, &dev_attr_devspec);
195 #endif /* CONFIG_PPC_OF */
199 char __devinit *pcibios_setup(char *str)
205 * Reads the interrupt pin to determine if interrupt is use by card.
206 * If the interrupt is used, then gets the interrupt line from the
207 * openfirmware and sets it in the pci_dev and pci_config line.
209 int pci_read_irq_line(struct pci_dev *pci_dev)
214 /* The current device-tree that iSeries generates from the HV
215 * PCI informations doesn't contain proper interrupt routing,
216 * and all the fallback would do is print out crap, so we
217 * don't attempt to resolve the interrupts here at all, some
218 * iSeries specific fixup does it.
220 * In the long run, we will hopefully fix the generated device-tree
223 #ifdef CONFIG_PPC_ISERIES
224 if (firmware_has_feature(FW_FEATURE_ISERIES))
228 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
231 memset(&oirq, 0xff, sizeof(oirq));
233 /* Try to get a mapping from the device-tree */
234 if (of_irq_map_pci(pci_dev, &oirq)) {
237 /* If that fails, lets fallback to what is in the config
238 * space and map that through the default controller. We
239 * also set the type to level low since that's what PCI
240 * interrupts are. If your platform does differently, then
241 * either provide a proper interrupt tree or don't use this
244 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
248 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
249 line == 0xff || line == 0) {
252 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
255 virq = irq_create_mapping(NULL, line);
257 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
259 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
260 oirq.size, oirq.specifier[0], oirq.specifier[1],
261 oirq.controller->full_name);
263 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
267 pr_debug(" Failed to map !\n");
271 pr_debug(" Mapped to linux irq %d\n", virq);
277 EXPORT_SYMBOL(pci_read_irq_line);
280 * Platform support for /proc/bus/pci/X/Y mmap()s,
281 * modelled on the sparc64 implementation by Dave Miller.
286 * Adjust vm_pgoff of VMA such that it is the physical page offset
287 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
289 * Basically, the user finds the base address for his device which he wishes
290 * to mmap. They read the 32-bit value from the config space base register,
291 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
292 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
294 * Returns negative error code on failure, zero on success.
296 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
297 resource_size_t *offset,
298 enum pci_mmap_state mmap_state)
300 struct pci_controller *hose = pci_bus_to_host(dev->bus);
301 unsigned long io_offset = 0;
305 return NULL; /* should never happen */
307 /* If memory, add on the PCI bridge address offset */
308 if (mmap_state == pci_mmap_mem) {
309 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
310 *offset += hose->pci_mem_offset;
312 res_bit = IORESOURCE_MEM;
314 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
315 *offset += io_offset;
316 res_bit = IORESOURCE_IO;
320 * Check that the offset requested corresponds to one of the
321 * resources of the device.
323 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
324 struct resource *rp = &dev->resource[i];
325 int flags = rp->flags;
327 /* treat ROM as memory (should be already) */
328 if (i == PCI_ROM_RESOURCE)
329 flags |= IORESOURCE_MEM;
331 /* Active and same type? */
332 if ((flags & res_bit) == 0)
335 /* In the range of this resource? */
336 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
339 /* found it! construct the final physical address */
340 if (mmap_state == pci_mmap_io)
341 *offset += hose->io_base_phys - io_offset;
349 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
352 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
354 enum pci_mmap_state mmap_state,
357 unsigned long prot = pgprot_val(protection);
359 /* Write combine is always 0 on non-memory space mappings. On
360 * memory space, if the user didn't pass 1, we check for a
361 * "prefetchable" resource. This is a bit hackish, but we use
362 * this to workaround the inability of /sysfs to provide a write
365 if (mmap_state != pci_mmap_mem)
367 else if (write_combine == 0) {
368 if (rp->flags & IORESOURCE_PREFETCH)
372 /* XXX would be nice to have a way to ask for write-through */
373 prot |= _PAGE_NO_CACHE;
375 prot &= ~_PAGE_GUARDED;
377 prot |= _PAGE_GUARDED;
379 return __pgprot(prot);
383 * This one is used by /dev/mem and fbdev who have no clue about the
384 * PCI device, it tries to find the PCI device first and calls the
387 pgprot_t pci_phys_mem_access_prot(struct file *file,
392 struct pci_dev *pdev = NULL;
393 struct resource *found = NULL;
394 unsigned long prot = pgprot_val(protection);
395 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
398 if (page_is_ram(pfn))
399 return __pgprot(prot);
401 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
403 for_each_pci_dev(pdev) {
404 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
405 struct resource *rp = &pdev->resource[i];
406 int flags = rp->flags;
408 /* Active and same type? */
409 if ((flags & IORESOURCE_MEM) == 0)
411 /* In the range of this resource? */
412 if (offset < (rp->start & PAGE_MASK) ||
422 if (found->flags & IORESOURCE_PREFETCH)
423 prot &= ~_PAGE_GUARDED;
427 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
428 (unsigned long long)offset, prot);
430 return __pgprot(prot);
435 * Perform the actual remap of the pages for a PCI device mapping, as
436 * appropriate for this architecture. The region in the process to map
437 * is described by vm_start and vm_end members of VMA, the base physical
438 * address is found in vm_pgoff.
439 * The pci device structure is provided so that architectures may make mapping
440 * decisions on a per-device or per-bus basis.
442 * Returns a negative error code on failure, zero on success.
444 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
445 enum pci_mmap_state mmap_state, int write_combine)
447 resource_size_t offset =
448 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
452 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
456 vma->vm_pgoff = offset >> PAGE_SHIFT;
457 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
459 mmap_state, write_combine);
461 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
462 vma->vm_end - vma->vm_start, vma->vm_page_prot);
467 /* This provides legacy IO read access on a bus */
468 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
470 unsigned long offset;
471 struct pci_controller *hose = pci_bus_to_host(bus);
472 struct resource *rp = &hose->io_resource;
475 /* Check if port can be supported by that bus. We only check
476 * the ranges of the PHB though, not the bus itself as the rules
477 * for forwarding legacy cycles down bridges are not our problem
478 * here. So if the host bridge supports it, we do it.
480 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
483 if (!(rp->flags & IORESOURCE_IO))
485 if (offset < rp->start || (offset + size) > rp->end)
487 addr = hose->io_base_virt + port;
491 *((u8 *)val) = in_8(addr);
496 *((u16 *)val) = in_le16(addr);
501 *((u32 *)val) = in_le32(addr);
507 /* This provides legacy IO write access on a bus */
508 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
510 unsigned long offset;
511 struct pci_controller *hose = pci_bus_to_host(bus);
512 struct resource *rp = &hose->io_resource;
515 /* Check if port can be supported by that bus. We only check
516 * the ranges of the PHB though, not the bus itself as the rules
517 * for forwarding legacy cycles down bridges are not our problem
518 * here. So if the host bridge supports it, we do it.
520 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
523 if (!(rp->flags & IORESOURCE_IO))
525 if (offset < rp->start || (offset + size) > rp->end)
527 addr = hose->io_base_virt + port;
529 /* WARNING: The generic code is idiotic. It gets passed a pointer
530 * to what can be a 1, 2 or 4 byte quantity and always reads that
531 * as a u32, which means that we have to correct the location of
532 * the data read within those 32 bits for size 1 and 2
536 out_8(addr, val >> 24);
541 out_le16(addr, val >> 16);
552 /* This provides legacy IO or memory mmap access on a bus */
553 int pci_mmap_legacy_page_range(struct pci_bus *bus,
554 struct vm_area_struct *vma,
555 enum pci_mmap_state mmap_state)
557 struct pci_controller *hose = pci_bus_to_host(bus);
558 resource_size_t offset =
559 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
560 resource_size_t size = vma->vm_end - vma->vm_start;
563 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
564 pci_domain_nr(bus), bus->number,
565 mmap_state == pci_mmap_mem ? "MEM" : "IO",
566 (unsigned long long)offset,
567 (unsigned long long)(offset + size - 1));
569 if (mmap_state == pci_mmap_mem) {
570 if ((offset + size) > hose->isa_mem_size)
572 offset += hose->isa_mem_phys;
574 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
575 unsigned long roffset = offset + io_offset;
576 rp = &hose->io_resource;
577 if (!(rp->flags & IORESOURCE_IO))
579 if (roffset < rp->start || (roffset + size) > rp->end)
581 offset += hose->io_base_phys;
583 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
585 vma->vm_pgoff = offset >> PAGE_SHIFT;
586 vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot)
587 | _PAGE_NO_CACHE | _PAGE_GUARDED);
588 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
589 vma->vm_end - vma->vm_start,
593 void pci_resource_to_user(const struct pci_dev *dev, int bar,
594 const struct resource *rsrc,
595 resource_size_t *start, resource_size_t *end)
597 struct pci_controller *hose = pci_bus_to_host(dev->bus);
598 resource_size_t offset = 0;
603 if (rsrc->flags & IORESOURCE_IO)
604 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
606 /* We pass a fully fixed up address to userland for MMIO instead of
607 * a BAR value because X is lame and expects to be able to use that
608 * to pass to /dev/mem !
610 * That means that we'll have potentially 64 bits values where some
611 * userland apps only expect 32 (like X itself since it thinks only
612 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
615 * Hopefully, the sysfs insterface is immune to that gunk. Once X
616 * has been fixed (and the fix spread enough), we can re-enable the
617 * 2 lines below and pass down a BAR value to userland. In that case
618 * we'll also have to re-enable the matching code in
619 * __pci_mmap_make_offset().
624 else if (rsrc->flags & IORESOURCE_MEM)
625 offset = hose->pci_mem_offset;
628 *start = rsrc->start - offset;
629 *end = rsrc->end - offset;
633 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
634 * @hose: newly allocated pci_controller to be setup
635 * @dev: device node of the host bridge
636 * @primary: set if primary bus (32 bits only, soon to be deprecated)
638 * This function will parse the "ranges" property of a PCI host bridge device
639 * node and setup the resource mapping of a pci controller based on its
642 * Life would be boring if it wasn't for a few issues that we have to deal
645 * - We can only cope with one IO space range and up to 3 Memory space
646 * ranges. However, some machines (thanks Apple !) tend to split their
647 * space into lots of small contiguous ranges. So we have to coalesce.
649 * - We can only cope with all memory ranges having the same offset
650 * between CPU addresses and PCI addresses. Unfortunately, some bridges
651 * are setup for a large 1:1 mapping along with a small "window" which
652 * maps PCI address 0 to some arbitrary high address of the CPU space in
653 * order to give access to the ISA memory hole.
654 * The way out of here that I've chosen for now is to always set the
655 * offset based on the first resource found, then override it if we
656 * have a different offset and the previous was set by an ISA hole.
658 * - Some busses have IO space not starting at 0, which causes trouble with
659 * the way we do our IO resource renumbering. The code somewhat deals with
660 * it for 64 bits but I would expect problems on 32 bits.
662 * - Some 32 bits platforms such as 4xx can have physical space larger than
663 * 32 bits so we need to use 64 bits values for the parsing
665 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
666 struct device_node *dev,
671 int pna = of_n_addr_cells(dev);
673 int memno = 0, isa_hole = -1;
675 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
676 unsigned long long isa_mb = 0;
677 struct resource *res;
679 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
680 dev->full_name, primary ? "(primary)" : "");
682 /* Get ranges property */
683 ranges = of_get_property(dev, "ranges", &rlen);
688 while ((rlen -= np * 4) >= 0) {
689 /* Read next ranges element */
690 pci_space = ranges[0];
691 pci_addr = of_read_number(ranges + 1, 2);
692 cpu_addr = of_translate_address(dev, ranges + 3);
693 size = of_read_number(ranges + pna + 3, 2);
696 /* If we failed translation or got a zero-sized region
697 * (some FW try to feed us with non sensical zero sized regions
698 * such as power3 which look like some kind of attempt at exposing
699 * the VGA memory hole)
701 if (cpu_addr == OF_BAD_ADDR || size == 0)
704 /* Now consume following elements while they are contiguous */
705 for (; rlen >= np * sizeof(u32);
706 ranges += np, rlen -= np * 4) {
707 if (ranges[0] != pci_space)
709 pci_next = of_read_number(ranges + 1, 2);
710 cpu_next = of_translate_address(dev, ranges + 3);
711 if (pci_next != pci_addr + size ||
712 cpu_next != cpu_addr + size)
714 size += of_read_number(ranges + pna + 3, 2);
717 /* Act based on address space type */
719 switch ((pci_space >> 24) & 0x3) {
720 case 1: /* PCI IO space */
722 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
723 cpu_addr, cpu_addr + size - 1, pci_addr);
725 /* We support only one IO range */
726 if (hose->pci_io_size) {
728 " \\--> Skipped (too many) !\n");
732 /* On 32 bits, limit I/O space to 16MB */
733 if (size > 0x01000000)
736 /* 32 bits needs to map IOs here */
737 hose->io_base_virt = ioremap(cpu_addr, size);
739 /* Expect trouble if pci_addr is not 0 */
742 (unsigned long)hose->io_base_virt;
743 #endif /* CONFIG_PPC32 */
744 /* pci_io_size and io_base_phys always represent IO
745 * space starting at 0 so we factor in pci_addr
747 hose->pci_io_size = pci_addr + size;
748 hose->io_base_phys = cpu_addr - pci_addr;
751 res = &hose->io_resource;
752 res->flags = IORESOURCE_IO;
753 res->start = pci_addr;
755 case 2: /* PCI Memory space */
756 case 3: /* PCI 64 bits Memory space */
758 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
759 cpu_addr, cpu_addr + size - 1, pci_addr,
760 (pci_space & 0x40000000) ? "Prefetch" : "");
762 /* We support only 3 memory ranges */
765 " \\--> Skipped (too many) !\n");
768 /* Handles ISA memory hole space here */
772 if (primary || isa_mem_base == 0)
773 isa_mem_base = cpu_addr;
774 hose->isa_mem_phys = cpu_addr;
775 hose->isa_mem_size = size;
778 /* We get the PCI/Mem offset from the first range or
779 * the, current one if the offset came from an ISA
780 * hole. If they don't match, bugger.
783 (isa_hole >= 0 && pci_addr != 0 &&
784 hose->pci_mem_offset == isa_mb))
785 hose->pci_mem_offset = cpu_addr - pci_addr;
786 else if (pci_addr != 0 &&
787 hose->pci_mem_offset != cpu_addr - pci_addr) {
789 " \\--> Skipped (offset mismatch) !\n");
794 res = &hose->mem_resources[memno++];
795 res->flags = IORESOURCE_MEM;
796 if (pci_space & 0x40000000)
797 res->flags |= IORESOURCE_PREFETCH;
798 res->start = cpu_addr;
802 res->name = dev->full_name;
803 res->end = res->start + size - 1;
810 /* If there's an ISA hole and the pci_mem_offset is -not- matching
811 * the ISA hole offset, then we need to remove the ISA hole from
812 * the resource list for that brige
814 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
815 unsigned int next = isa_hole + 1;
816 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
818 memmove(&hose->mem_resources[isa_hole],
819 &hose->mem_resources[next],
820 sizeof(struct resource) * (memno - next));
821 hose->mem_resources[--memno].flags = 0;
825 /* Decide whether to display the domain number in /proc */
826 int pci_proc_domain(struct pci_bus *bus)
828 struct pci_controller *hose = pci_bus_to_host(bus);
830 if (!(ppc_pci_flags & PPC_PCI_ENABLE_PROC_DOMAINS))
832 if (ppc_pci_flags & PPC_PCI_COMPAT_DOMAIN_0)
833 return hose->global_number != 0;
837 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
838 struct resource *res)
840 resource_size_t offset = 0, mask = (resource_size_t)-1;
841 struct pci_controller *hose = pci_bus_to_host(dev->bus);
845 if (res->flags & IORESOURCE_IO) {
846 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
848 } else if (res->flags & IORESOURCE_MEM)
849 offset = hose->pci_mem_offset;
851 region->start = (res->start - offset) & mask;
852 region->end = (res->end - offset) & mask;
854 EXPORT_SYMBOL(pcibios_resource_to_bus);
856 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
857 struct pci_bus_region *region)
859 resource_size_t offset = 0, mask = (resource_size_t)-1;
860 struct pci_controller *hose = pci_bus_to_host(dev->bus);
864 if (res->flags & IORESOURCE_IO) {
865 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
867 } else if (res->flags & IORESOURCE_MEM)
868 offset = hose->pci_mem_offset;
869 res->start = (region->start + offset) & mask;
870 res->end = (region->end + offset) & mask;
872 EXPORT_SYMBOL(pcibios_bus_to_resource);
874 /* Fixup a bus resource into a linux resource */
875 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
877 struct pci_controller *hose = pci_bus_to_host(dev->bus);
878 resource_size_t offset = 0, mask = (resource_size_t)-1;
880 if (res->flags & IORESOURCE_IO) {
881 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
883 } else if (res->flags & IORESOURCE_MEM)
884 offset = hose->pci_mem_offset;
886 res->start = (res->start + offset) & mask;
887 res->end = (res->end + offset) & mask;
891 /* This header fixup will do the resource fixup for all devices as they are
892 * probed, but not for bridge ranges
894 static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
896 struct pci_controller *hose = pci_bus_to_host(dev->bus);
900 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
904 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
905 struct resource *res = dev->resource + i;
908 /* On platforms that have PPC_PCI_PROBE_ONLY set, we don't
909 * consider 0 as an unassigned BAR value. It's technically
910 * a valid value, but linux doesn't like it... so when we can
911 * re-assign things, we do so, but if we can't, we keep it
912 * around and hope for the best...
914 if (res->start == 0 && !(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
915 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] is unassigned\n",
917 (unsigned long long)res->start,
918 (unsigned long long)res->end,
919 (unsigned int)res->flags);
920 res->end -= res->start;
922 res->flags |= IORESOURCE_UNSET;
926 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
928 (unsigned long long)res->start,\
929 (unsigned long long)res->end,
930 (unsigned int)res->flags);
932 fixup_resource(res, dev);
934 pr_debug("PCI:%s %016llx-%016llx\n",
936 (unsigned long long)res->start,
937 (unsigned long long)res->end);
940 /* Call machine specific resource fixup */
941 if (ppc_md.pcibios_fixup_resources)
942 ppc_md.pcibios_fixup_resources(dev);
944 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
946 /* This function tries to figure out if a bridge resource has been initialized
947 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
948 * things go more smoothly when it gets it right. It should covers cases such
949 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
951 static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
952 struct resource *res)
954 struct pci_controller *hose = pci_bus_to_host(bus);
955 struct pci_dev *dev = bus->self;
956 resource_size_t offset;
960 /* We don't do anything if PCI_PROBE_ONLY is set */
961 if (ppc_pci_flags & PPC_PCI_PROBE_ONLY)
964 /* Job is a bit different between memory and IO */
965 if (res->flags & IORESOURCE_MEM) {
966 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
967 * initialized by somebody
969 if (res->start != hose->pci_mem_offset)
972 /* The BAR is 0, let's check if memory decoding is enabled on
973 * the bridge. If not, we consider it unassigned
975 pci_read_config_word(dev, PCI_COMMAND, &command);
976 if ((command & PCI_COMMAND_MEMORY) == 0)
979 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
980 * resources covers that starting address (0 then it's good enough for
983 for (i = 0; i < 3; i++) {
984 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
985 hose->mem_resources[i].start == hose->pci_mem_offset)
989 /* Well, it starts at 0 and we know it will collide so we may as
990 * well consider it as unassigned. That covers the Apple case.
994 /* If the BAR is non-0, then we consider it assigned */
995 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
996 if (((res->start - offset) & 0xfffffffful) != 0)
999 /* Here, we are a bit different than memory as typically IO space
1000 * starting at low addresses -is- valid. What we do instead if that
1001 * we consider as unassigned anything that doesn't have IO enabled
1002 * in the PCI command register, and that's it.
1004 pci_read_config_word(dev, PCI_COMMAND, &command);
1005 if (command & PCI_COMMAND_IO)
1008 /* It's starting at 0 and IO is disabled in the bridge, consider
1015 /* Fixup resources of a PCI<->PCI bridge */
1016 static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
1018 struct resource *res;
1021 struct pci_dev *dev = bus->self;
1023 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1024 if ((res = bus->resource[i]) == NULL)
1028 if (i >= 3 && bus->self->transparent)
1031 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1033 (unsigned long long)res->start,\
1034 (unsigned long long)res->end,
1035 (unsigned int)res->flags);
1038 fixup_resource(res, dev);
1040 /* Try to detect uninitialized P2P bridge resources,
1041 * and clear them out so they get re-assigned later
1043 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1045 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1048 pr_debug("PCI:%s %016llx-%016llx\n",
1050 (unsigned long long)res->start,
1051 (unsigned long long)res->end);
1056 void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1058 /* Fix up the bus resources for P2P bridges */
1059 if (bus->self != NULL)
1060 pcibios_fixup_bridge(bus);
1062 /* Platform specific bus fixups. This is currently only used
1063 * by fsl_pci and I'm hoping to get rid of it at some point
1065 if (ppc_md.pcibios_fixup_bus)
1066 ppc_md.pcibios_fixup_bus(bus);
1068 /* Setup bus DMA mappings */
1069 if (ppc_md.pci_dma_bus_setup)
1070 ppc_md.pci_dma_bus_setup(bus);
1073 void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1075 struct pci_dev *dev;
1077 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1078 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1080 list_for_each_entry(dev, &bus->devices, bus_list) {
1081 struct dev_archdata *sd = &dev->dev.archdata;
1083 /* Setup OF node pointer in archdata */
1084 sd->of_node = pci_device_to_OF_node(dev);
1086 /* Fixup NUMA node as it may not be setup yet by the generic
1087 * code and is needed by the DMA init
1089 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1091 /* Hook up default DMA ops */
1092 sd->dma_ops = pci_dma_ops;
1093 sd->dma_data = (void *)PCI_DRAM_OFFSET;
1095 /* Additional platform DMA/iommu setup */
1096 if (ppc_md.pci_dma_dev_setup)
1097 ppc_md.pci_dma_dev_setup(dev);
1099 /* Read default IRQs and fixup if necessary */
1100 pci_read_irq_line(dev);
1101 if (ppc_md.pci_irq_fixup)
1102 ppc_md.pci_irq_fixup(dev);
1106 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1108 /* When called from the generic PCI probe, read PCI<->PCI bridge
1109 * bases. This is -not- called when generating the PCI tree from
1110 * the OF device-tree.
1112 if (bus->self != NULL)
1113 pci_read_bridge_bases(bus);
1115 /* Now fixup the bus bus */
1116 pcibios_setup_bus_self(bus);
1118 /* Now fixup devices on that bus */
1119 pcibios_setup_bus_devices(bus);
1121 EXPORT_SYMBOL(pcibios_fixup_bus);
1123 static int skip_isa_ioresource_align(struct pci_dev *dev)
1125 if ((ppc_pci_flags & PPC_PCI_CAN_SKIP_ISA_ALIGN) &&
1126 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1132 * We need to avoid collisions with `mirrored' VGA ports
1133 * and other strange ISA hardware, so we always want the
1134 * addresses to be allocated in the 0x000-0x0ff region
1137 * Why? Because some silly external IO cards only decode
1138 * the low 10 bits of the IO address. The 0x00-0xff region
1139 * is reserved for motherboard devices that decode all 16
1140 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1141 * but we want to try to avoid allocating at 0x2900-0x2bff
1142 * which might have be mirrored at 0x0100-0x03ff..
1144 void pcibios_align_resource(void *data, struct resource *res,
1145 resource_size_t size, resource_size_t align)
1147 struct pci_dev *dev = data;
1149 if (res->flags & IORESOURCE_IO) {
1150 resource_size_t start = res->start;
1152 if (skip_isa_ioresource_align(dev))
1154 if (start & 0x300) {
1155 start = (start + 0x3ff) & ~0x3ff;
1160 EXPORT_SYMBOL(pcibios_align_resource);
1163 * Reparent resource children of pr that conflict with res
1164 * under res, and make res replace those children.
1166 static int __init reparent_resources(struct resource *parent,
1167 struct resource *res)
1169 struct resource *p, **pp;
1170 struct resource **firstpp = NULL;
1172 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1173 if (p->end < res->start)
1175 if (res->end < p->start)
1177 if (p->start < res->start || p->end > res->end)
1178 return -1; /* not completely contained */
1179 if (firstpp == NULL)
1182 if (firstpp == NULL)
1183 return -1; /* didn't find any conflicting entries? */
1184 res->parent = parent;
1185 res->child = *firstpp;
1189 for (p = res->child; p != NULL; p = p->sibling) {
1191 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1193 (unsigned long long)p->start,
1194 (unsigned long long)p->end, res->name);
1200 * Handle resources of PCI devices. If the world were perfect, we could
1201 * just allocate all the resource regions and do nothing more. It isn't.
1202 * On the other hand, we cannot just re-allocate all devices, as it would
1203 * require us to know lots of host bridge internals. So we attempt to
1204 * keep as much of the original configuration as possible, but tweak it
1205 * when it's found to be wrong.
1207 * Known BIOS problems we have to work around:
1208 * - I/O or memory regions not configured
1209 * - regions configured, but not enabled in the command register
1210 * - bogus I/O addresses above 64K used
1211 * - expansion ROMs left enabled (this may sound harmless, but given
1212 * the fact the PCI specs explicitly allow address decoders to be
1213 * shared between expansion ROMs and other resource regions, it's
1214 * at least dangerous)
1217 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1218 * This gives us fixed barriers on where we can allocate.
1219 * (2) Allocate resources for all enabled devices. If there is
1220 * a collision, just mark the resource as unallocated. Also
1221 * disable expansion ROMs during this step.
1222 * (3) Try to allocate resources for disabled devices. If the
1223 * resources were assigned correctly, everything goes well,
1224 * if they weren't, they won't disturb allocation of other
1226 * (4) Assign new addresses to resources which were either
1227 * not configured at all or misconfigured. If explicitly
1228 * requested by the user, configure expansion ROM address
1232 void pcibios_allocate_bus_resources(struct pci_bus *bus)
1236 struct resource *res, *pr;
1238 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1239 pci_domain_nr(bus), bus->number);
1241 for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
1242 if ((res = bus->resource[i]) == NULL || !res->flags
1243 || res->start > res->end || res->parent)
1245 if (bus->parent == NULL)
1246 pr = (res->flags & IORESOURCE_IO) ?
1247 &ioport_resource : &iomem_resource;
1249 /* Don't bother with non-root busses when
1250 * re-assigning all resources. We clear the
1251 * resource flags as if they were colliding
1252 * and as such ensure proper re-allocation
1255 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)
1256 goto clear_resource;
1257 pr = pci_find_parent_resource(bus->self, res);
1259 /* this happens when the generic PCI
1260 * code (wrongly) decides that this
1261 * bridge is transparent -- paulus
1267 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1268 "[0x%x], parent %p (%s)\n",
1269 bus->self ? pci_name(bus->self) : "PHB",
1271 (unsigned long long)res->start,
1272 (unsigned long long)res->end,
1273 (unsigned int)res->flags,
1274 pr, (pr && pr->name) ? pr->name : "nil");
1276 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1277 if (request_resource(pr, res) == 0)
1280 * Must be a conflict with an existing entry.
1281 * Move that entry (or entries) under the
1282 * bridge resource and try again.
1284 if (reparent_resources(pr, res) == 0)
1287 printk(KERN_WARNING "PCI: Cannot allocate resource region "
1288 "%d of PCI bridge %d, will remap\n", i, bus->number);
1293 list_for_each_entry(b, &bus->children, node)
1294 pcibios_allocate_bus_resources(b);
1297 static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
1299 struct resource *pr, *r = &dev->resource[idx];
1301 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1303 (unsigned long long)r->start,
1304 (unsigned long long)r->end,
1305 (unsigned int)r->flags);
1307 pr = pci_find_parent_resource(dev, r);
1308 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1309 request_resource(pr, r) < 0) {
1310 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1311 " of device %s, will remap\n", idx, pci_name(dev));
1313 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1315 (unsigned long long)pr->start,
1316 (unsigned long long)pr->end,
1317 (unsigned int)pr->flags);
1318 /* We'll assign a new address later */
1319 r->flags |= IORESOURCE_UNSET;
1325 static void __init pcibios_allocate_resources(int pass)
1327 struct pci_dev *dev = NULL;
1332 for_each_pci_dev(dev) {
1333 pci_read_config_word(dev, PCI_COMMAND, &command);
1334 for (idx = 0; idx < 6; idx++) {
1335 r = &dev->resource[idx];
1336 if (r->parent) /* Already allocated */
1338 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1339 continue; /* Not assigned at all */
1340 if (r->flags & IORESOURCE_IO)
1341 disabled = !(command & PCI_COMMAND_IO);
1343 disabled = !(command & PCI_COMMAND_MEMORY);
1344 if (pass == disabled)
1345 alloc_resource(dev, idx);
1349 r = &dev->resource[PCI_ROM_RESOURCE];
1350 if (r->flags & IORESOURCE_ROM_ENABLE) {
1351 /* Turn the ROM off, leave the resource region,
1352 * but keep it unregistered.
1355 pr_debug("PCI: Switching off ROM of %s\n",
1357 r->flags &= ~IORESOURCE_ROM_ENABLE;
1358 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1359 pci_write_config_dword(dev, dev->rom_base_reg,
1360 reg & ~PCI_ROM_ADDRESS_ENABLE);
1365 void __init pcibios_resource_survey(void)
1369 /* Allocate and assign resources. If we re-assign everything, then
1370 * we skip the allocate phase
1372 list_for_each_entry(b, &pci_root_buses, node)
1373 pcibios_allocate_bus_resources(b);
1375 if (!(ppc_pci_flags & PPC_PCI_REASSIGN_ALL_RSRC)) {
1376 pcibios_allocate_resources(0);
1377 pcibios_allocate_resources(1);
1380 if (!(ppc_pci_flags & PPC_PCI_PROBE_ONLY)) {
1381 pr_debug("PCI: Assigning unassigned resouces...\n");
1382 pci_assign_unassigned_resources();
1385 /* Call machine dependent fixup */
1386 if (ppc_md.pcibios_fixup)
1387 ppc_md.pcibios_fixup();
1390 #ifdef CONFIG_HOTPLUG
1392 /* This is used by the PCI hotplug driver to allocate resource
1393 * of newly plugged busses. We can try to consolidate with the
1394 * rest of the code later, for now, keep it as-is as our main
1395 * resource allocation function doesn't deal with sub-trees yet.
1397 void __devinit pcibios_claim_one_bus(struct pci_bus *bus)
1399 struct pci_dev *dev;
1400 struct pci_bus *child_bus;
1402 list_for_each_entry(dev, &bus->devices, bus_list) {
1405 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1406 struct resource *r = &dev->resource[i];
1408 if (r->parent || !r->start || !r->flags)
1411 pr_debug("PCI: Claiming %s: "
1412 "Resource %d: %016llx..%016llx [%x]\n",
1414 (unsigned long long)r->start,
1415 (unsigned long long)r->end,
1416 (unsigned int)r->flags);
1418 pci_claim_resource(dev, i);
1422 list_for_each_entry(child_bus, &bus->children, node)
1423 pcibios_claim_one_bus(child_bus);
1425 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1428 /* pcibios_finish_adding_to_bus
1430 * This is to be called by the hotplug code after devices have been
1431 * added to a bus, this include calling it for a PHB that is just
1434 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1436 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1437 pci_domain_nr(bus), bus->number);
1439 /* Allocate bus and devices resources */
1440 pcibios_allocate_bus_resources(bus);
1441 pcibios_claim_one_bus(bus);
1443 /* Add new devices to global lists. Register in proc, sysfs. */
1444 pci_bus_add_devices(bus);
1447 eeh_add_device_tree_late(bus);
1449 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1451 #endif /* CONFIG_HOTPLUG */
1453 int pcibios_enable_device(struct pci_dev *dev, int mask)
1455 if (ppc_md.pcibios_enable_device_hook)
1456 if (ppc_md.pcibios_enable_device_hook(dev))
1459 return pci_enable_resources(dev, mask);
1462 void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
1464 struct pci_bus *bus = hose->bus;
1465 struct resource *res;
1468 /* Hookup PHB IO resource */
1469 bus->resource[0] = res = &hose->io_resource;
1472 printk(KERN_WARNING "PCI: I/O resource not set for host"
1473 " bridge %s (domain %d)\n",
1474 hose->dn->full_name, hose->global_number);
1476 /* Workaround for lack of IO resource only on 32-bit */
1477 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1478 res->end = res->start + IO_SPACE_LIMIT;
1479 res->flags = IORESOURCE_IO;
1480 #endif /* CONFIG_PPC32 */
1483 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1484 (unsigned long long)res->start,
1485 (unsigned long long)res->end,
1486 (unsigned long)res->flags);
1488 /* Hookup PHB Memory resources */
1489 for (i = 0; i < 3; ++i) {
1490 res = &hose->mem_resources[i];
1494 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1495 "host bridge %s (domain %d)\n",
1496 hose->dn->full_name, hose->global_number);
1498 /* Workaround for lack of MEM resource only on 32-bit */
1499 res->start = hose->pci_mem_offset;
1500 res->end = (resource_size_t)-1LL;
1501 res->flags = IORESOURCE_MEM;
1502 #endif /* CONFIG_PPC32 */
1504 bus->resource[i+1] = res;
1506 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1507 (unsigned long long)res->start,
1508 (unsigned long long)res->end,
1509 (unsigned long)res->flags);
1512 pr_debug("PCI: PHB MEM offset = %016llx\n",
1513 (unsigned long long)hose->pci_mem_offset);
1514 pr_debug("PCI: PHB IO offset = %08lx\n",
1515 (unsigned long)hose->io_base_virt - _IO_BASE);