git.oblomov.eu Git - linux-2.6/blob - drivers/net/typhoon.c

   1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
   2 /*
   3         Written 2002-2004 by David Dillow <dave@thedillows.org>
   4         Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
   5         Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
   6
   7         This software may be used and distributed according to the terms of
   8         the GNU General Public License (GPL), incorporated herein by reference.
   9         Drivers based on or derived from this code fall under the GPL and must
  10         retain the authorship, copyright and license notice.  This file is not
  11         a complete program and may only be used when the entire operating
  12         system is licensed under the GPL.
  13
  14         This software is available on a public web site. It may enable
  15         cryptographic capabilities of the 3Com hardware, and may be
  16         exported from the United States under License Exception "TSU"
  17         pursuant to 15 C.F.R. Section 740.13(e).
  18
  19         This work was funded by the National Library of Medicine under
  20         the Department of Energy project number 0274DD06D1 and NLM project
  21         number Y1-LM-2015-01.
  22
  23         This driver is designed for the 3Com 3CR990 Family of cards with the
  24         3XP Processor. It has been tested on x86 and sparc64.
  25
  26         KNOWN ISSUES:
  27         *) The current firmware always strips the VLAN tag off, even if
  28                 we tell it not to. You should filter VLANs at the switch
  29                 as a workaround (good practice in any event) until we can
  30                 get this fixed.
  31         *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  32                 issue. Hopefully 3Com will fix it.
  33         *) Waiting for a command response takes 8ms due to non-preemptable
  34                 polling. Only significant for getting stats and creating
  35                 SAs, but an ugly wart never the less.
  36
  37         TODO:
  38         *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  39         *) Add more support for ethtool (especially for NIC stats)
  40         *) Allow disabling of RX checksum offloading
  41         *) Fix MAC changing to work while the interface is up
  42                 (Need to put commands on the TX ring, which changes
  43                 the locking)
  44         *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  45                 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  46 */
  47
  48 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  49  * Setting to > 1518 effectively disables this feature.
  50  */
  51 static int rx_copybreak = 200;
  52
  53 /* Should we use MMIO or Port IO?
  54  * 0: Port IO
  55  * 1: MMIO
  56  * 2: Try MMIO, fallback to Port IO
  57  */
  58 static unsigned int use_mmio = 2;
  59
  60 /* end user-configurable values */
  61
  62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  63  */
  64 static const int multicast_filter_limit = 32;
  65
  66 /* Operational parameters that are set at compile time. */
  67
  68 /* Keep the ring sizes a power of two for compile efficiency.
  69  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  70  * Making the Tx ring too large decreases the effectiveness of channel
  71  * bonding and packet priority.
  72  * There are no ill effects from too-large receive rings.
  73  *
  74  * We don't currently use the Hi Tx ring so, don't make it very big.
  75  *
  76  * Beware that if we start using the Hi Tx ring, we will need to change
  77  * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  78  */
  79 #define TXHI_ENTRIES            2
  80 #define TXLO_ENTRIES            128
  81 #define RX_ENTRIES              32
  82 #define COMMAND_ENTRIES         16
  83 #define RESPONSE_ENTRIES        32
  84
  85 #define COMMAND_RING_SIZE       (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  86 #define RESPONSE_RING_SIZE      (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  87
  88 /* The 3XP will preload and remove 64 entries from the free buffer
  89  * list, and we need one entry to keep the ring from wrapping, so
  90  * to keep this a power of two, we use 128 entries.
  91  */
  92 #define RXFREE_ENTRIES          128
  93 #define RXENT_ENTRIES           (RXFREE_ENTRIES - 1)
  94
  95 /* Operational parameters that usually are not changed. */
  96
  97 /* Time in jiffies before concluding the transmitter is hung. */
  98 #define TX_TIMEOUT  (2*HZ)
  99
 100 #define PKT_BUF_SZ              1536
 101
 102 #define DRV_MODULE_NAME         "typhoon"
 103 #define DRV_MODULE_VERSION      "1.5.8"
 104 #define DRV_MODULE_RELDATE      "06/11/09"
 105 #define PFX                     DRV_MODULE_NAME ": "
 106 #define ERR_PFX                 KERN_ERR PFX
 107
 108 #include <linux/module.h>
 109 #include <linux/kernel.h>
 110 #include <linux/string.h>
 111 #include <linux/timer.h>
 112 #include <linux/errno.h>
 113 #include <linux/ioport.h>
 114 #include <linux/slab.h>
 115 #include <linux/interrupt.h>
 116 #include <linux/pci.h>
 117 #include <linux/netdevice.h>
 118 #include <linux/etherdevice.h>
 119 #include <linux/skbuff.h>
 120 #include <linux/mm.h>
 121 #include <linux/init.h>
 122 #include <linux/delay.h>
 123 #include <linux/ethtool.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/crc32.h>
 126 #include <linux/bitops.h>
 127 #include <asm/processor.h>
 128 #include <asm/io.h>
 129 #include <asm/uaccess.h>
 130 #include <linux/in6.h>
 131 #include <linux/version.h>
 132 #include <linux/dma-mapping.h>
 133
 134 #include "typhoon.h"
 135 #include "typhoon-firmware.h"
 136
 137 static const char version[] __devinitdata =
 138     "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 139
 140 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142 MODULE_LICENSE("GPL");
 143 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
 144 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
 145                                "the buffer given back to the NIC. Default "
 146                                "is 200.");
 147 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
 148                            "Default is to try MMIO and fallback to PIO.");
 149 module_param(rx_copybreak, int, 0);
 150 module_param(use_mmio, int, 0);
 151
 152 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
 153 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
 154 #undef NETIF_F_TSO
 155 #endif
 156
 157 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
 158 #error TX ring too small!
 159 #endif
 160
 161 struct typhoon_card_info {
 162         char *name;
 163         int capabilities;
 164 };
 165
 166 #define TYPHOON_CRYPTO_NONE             0x00
 167 #define TYPHOON_CRYPTO_DES              0x01
 168 #define TYPHOON_CRYPTO_3DES             0x02
 169 #define TYPHOON_CRYPTO_VARIABLE         0x04
 170 #define TYPHOON_FIBER                   0x08
 171 #define TYPHOON_WAKEUP_NEEDS_RESET      0x10
 172
 173 enum typhoon_cards {
 174         TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
 175         TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
 176         TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
 177         TYPHOON_FXM,
 178 };
 179
 180 /* directly indexed by enum typhoon_cards, above */
 181 static const struct typhoon_card_info typhoon_card_info[] __devinitdata = {
 182         { "3Com Typhoon (3C990-TX)",
 183                 TYPHOON_CRYPTO_NONE},
 184         { "3Com Typhoon (3CR990-TX-95)",
 185                 TYPHOON_CRYPTO_DES},
 186         { "3Com Typhoon (3CR990-TX-97)",
 187                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 188         { "3Com Typhoon (3C990SVR)",
 189                 TYPHOON_CRYPTO_NONE},
 190         { "3Com Typhoon (3CR990SVR95)",
 191                 TYPHOON_CRYPTO_DES},
 192         { "3Com Typhoon (3CR990SVR97)",
 193                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 194         { "3Com Typhoon2 (3C990B-TX-M)",
 195                 TYPHOON_CRYPTO_VARIABLE},
 196         { "3Com Typhoon2 (3C990BSVR)",
 197                 TYPHOON_CRYPTO_VARIABLE},
 198         { "3Com Typhoon (3CR990-FX-95)",
 199                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 200         { "3Com Typhoon (3CR990-FX-97)",
 201                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 202         { "3Com Typhoon (3CR990-FX-95 Server)",
 203                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 204         { "3Com Typhoon (3CR990-FX-97 Server)",
 205                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 206         { "3Com Typhoon2 (3C990B-FX-97)",
 207                 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
 208 };
 209
 210 /* Notes on the new subsystem numbering scheme:
 211  * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
 212  * bit 4 indicates if this card has secured firmware (we don't support it)
 213  * bit 8 indicates if this is a (0) copper or (1) fiber card
 214  * bits 12-16 indicate card type: (0) client and (1) server
 215  */
 216 static struct pci_device_id typhoon_pci_tbl[] = {
 217         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
 218           PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
 219         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
 220           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
 221         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
 223         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 224           PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
 225         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 226           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
 227         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 228           PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
 229         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 230           PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
 231         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 232           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
 233         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 234           PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
 235         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 236           PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
 237         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
 238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
 239         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
 240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
 241         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
 242           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
 243         { 0, }
 244 };
 245 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
 246
 247 /* Define the shared memory area
 248  * Align everything the 3XP will normally be using.
 249  * We'll need to move/align txHi if we start using that ring.
 250  */
 251 #define __3xp_aligned   ____cacheline_aligned
 252 struct typhoon_shared {
 253         struct typhoon_interface        iface;
 254         struct typhoon_indexes          indexes                 __3xp_aligned;
 255         struct tx_desc                  txLo[TXLO_ENTRIES]      __3xp_aligned;
 256         struct rx_desc                  rxLo[RX_ENTRIES]        __3xp_aligned;
 257         struct rx_desc                  rxHi[RX_ENTRIES]        __3xp_aligned;
 258         struct cmd_desc                 cmd[COMMAND_ENTRIES]    __3xp_aligned;
 259         struct resp_desc                resp[RESPONSE_ENTRIES]  __3xp_aligned;
 260         struct rx_free                  rxBuff[RXFREE_ENTRIES]  __3xp_aligned;
 261         u32                             zeroWord;
 262         struct tx_desc                  txHi[TXHI_ENTRIES];
 263 } __attribute__ ((packed));
 264
 265 struct rxbuff_ent {
 266         struct sk_buff *skb;
 267         dma_addr_t      dma_addr;
 268 };
 269
 270 struct typhoon {
 271         /* Tx cache line section */
 272         struct transmit_ring    txLoRing        ____cacheline_aligned;
 273         struct pci_dev *        tx_pdev;
 274         void __iomem            *tx_ioaddr;
 275         u32                     txlo_dma_addr;
 276
 277         /* Irq/Rx cache line section */
 278         void __iomem            *ioaddr         ____cacheline_aligned;
 279         struct typhoon_indexes *indexes;
 280         u8                      awaiting_resp;
 281         u8                      duplex;
 282         u8                      speed;
 283         u8                      card_state;
 284         struct basic_ring       rxLoRing;
 285         struct pci_dev *        pdev;
 286         struct net_device *     dev;
 287         spinlock_t              state_lock;
 288         struct vlan_group *     vlgrp;
 289         struct basic_ring       rxHiRing;
 290         struct basic_ring       rxBuffRing;
 291         struct rxbuff_ent       rxbuffers[RXENT_ENTRIES];
 292
 293         /* general section */
 294         spinlock_t              command_lock    ____cacheline_aligned;
 295         struct basic_ring       cmdRing;
 296         struct basic_ring       respRing;
 297         struct net_device_stats stats;
 298         struct net_device_stats stats_saved;
 299         const char *            name;
 300         struct typhoon_shared * shared;
 301         dma_addr_t              shared_dma;
 302         u16                     xcvr_select;
 303         u16                     wol_events;
 304         u32                     offload;
 305
 306         /* unused stuff (future use) */
 307         int                     capabilities;
 308         struct transmit_ring    txHiRing;
 309 };
 310
 311 enum completion_wait_values {
 312         NoWait = 0, WaitNoSleep, WaitSleep,
 313 };
 314
 315 /* These are the values for the typhoon.card_state variable.
 316  * These determine where the statistics will come from in get_stats().
 317  * The sleep image does not support the statistics we need.
 318  */
 319 enum state_values {
 320         Sleeping = 0, Running,
 321 };
 322
 323 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
 324  * cannot pass a read, so this forces current writes to post.
 325  */
 326 #define typhoon_post_pci_writes(x) \
 327         do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
 328
 329 /* We'll wait up to six seconds for a reset, and half a second normally.
 330  */
 331 #define TYPHOON_UDELAY                  50
 332 #define TYPHOON_RESET_TIMEOUT_SLEEP     (6 * HZ)
 333 #define TYPHOON_RESET_TIMEOUT_NOSLEEP   ((6 * 1000000) / TYPHOON_UDELAY)
 334 #define TYPHOON_WAIT_TIMEOUT            ((1000000 / 2) / TYPHOON_UDELAY)
 335
 336 #define typhoon_synchronize_irq(x) synchronize_irq(x)
 337
 338 #if defined(NETIF_F_TSO)
 339 #define skb_tso_size(x)         (skb_shinfo(x)->gso_size)
 340 #define TSO_NUM_DESCRIPTORS     2
 341 #define TSO_OFFLOAD_ON          TYPHOON_OFFLOAD_TCP_SEGMENT
 342 #else
 343 #define NETIF_F_TSO             0
 344 #define skb_tso_size(x)         0
 345 #define TSO_NUM_DESCRIPTORS     0
 346 #define TSO_OFFLOAD_ON          0
 347 #endif
 348
 349 static inline void
 350 typhoon_inc_index(u32 *index, const int count, const int num_entries)
 351 {
 352         /* Increment a ring index -- we can use this for all rings execept
 353          * the Rx rings, as they use different size descriptors
 354          * otherwise, everything is the same size as a cmd_desc
 355          */
 356         *index += count * sizeof(struct cmd_desc);
 357         *index %= num_entries * sizeof(struct cmd_desc);
 358 }
 359
 360 static inline void
 361 typhoon_inc_cmd_index(u32 *index, const int count)
 362 {
 363         typhoon_inc_index(index, count, COMMAND_ENTRIES);
 364 }
 365
 366 static inline void
 367 typhoon_inc_resp_index(u32 *index, const int count)
 368 {
 369         typhoon_inc_index(index, count, RESPONSE_ENTRIES);
 370 }
 371
 372 static inline void
 373 typhoon_inc_rxfree_index(u32 *index, const int count)
 374 {
 375         typhoon_inc_index(index, count, RXFREE_ENTRIES);
 376 }
 377
 378 static inline void
 379 typhoon_inc_tx_index(u32 *index, const int count)
 380 {
 381         /* if we start using the Hi Tx ring, this needs updateing */
 382         typhoon_inc_index(index, count, TXLO_ENTRIES);
 383 }
 384
 385 static inline void
 386 typhoon_inc_rx_index(u32 *index, const int count)
 387 {
 388         /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
 389         *index += count * sizeof(struct rx_desc);
 390         *index %= RX_ENTRIES * sizeof(struct rx_desc);
 391 }
 392
 393 static int
 394 typhoon_reset(void __iomem *ioaddr, int wait_type)
 395 {
 396         int i, err = 0;
 397         int timeout;
 398
 399         if(wait_type == WaitNoSleep)
 400                 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
 401         else
 402                 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
 403
 404         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 405         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 406
 407         iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
 408         typhoon_post_pci_writes(ioaddr);
 409         udelay(1);
 410         iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
 411
 412         if(wait_type != NoWait) {
 413                 for(i = 0; i < timeout; i++) {
 414                         if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
 415                            TYPHOON_STATUS_WAITING_FOR_HOST)
 416                                 goto out;
 417
 418                         if(wait_type == WaitSleep)
 419                                 schedule_timeout_uninterruptible(1);
 420                         else
 421                                 udelay(TYPHOON_UDELAY);
 422                 }
 423
 424                 err = -ETIMEDOUT;
 425         }
 426
 427 out:
 428         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 429         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 430
 431         /* The 3XP seems to need a little extra time to complete the load
 432          * of the sleep image before we can reliably boot it. Failure to
 433          * do this occasionally results in a hung adapter after boot in
 434          * typhoon_init_one() while trying to read the MAC address or
 435          * putting the card to sleep. 3Com's driver waits 5ms, but
 436          * that seems to be overkill. However, if we can sleep, we might
 437          * as well give it that much time. Otherwise, we'll give it 500us,
 438          * which should be enough (I've see it work well at 100us, but still
 439          * saw occasional problems.)
 440          */
 441         if(wait_type == WaitSleep)
 442                 msleep(5);
 443         else
 444                 udelay(500);
 445         return err;
 446 }
 447
 448 static int
 449 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
 450 {
 451         int i, err = 0;
 452
 453         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
 454                 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
 455                         goto out;
 456                 udelay(TYPHOON_UDELAY);
 457         }
 458
 459         err = -ETIMEDOUT;
 460
 461 out:
 462         return err;
 463 }
 464
 465 static inline void
 466 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
 467 {
 468         if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
 469                 netif_carrier_off(dev);
 470         else
 471                 netif_carrier_on(dev);
 472 }
 473
 474 static inline void
 475 typhoon_hello(struct typhoon *tp)
 476 {
 477         struct basic_ring *ring = &tp->cmdRing;
 478         struct cmd_desc *cmd;
 479
 480         /* We only get a hello request if we've not sent anything to the
 481          * card in a long while. If the lock is held, then we're in the
 482          * process of issuing a command, so we don't need to respond.
 483          */
 484         if(spin_trylock(&tp->command_lock)) {
 485                 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
 486                 typhoon_inc_cmd_index(&ring->lastWrite, 1);
 487
 488                 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
 489                 smp_wmb();
 490                 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 491                 spin_unlock(&tp->command_lock);
 492         }
 493 }
 494
 495 static int
 496 typhoon_process_response(struct typhoon *tp, int resp_size,
 497                                 struct resp_desc *resp_save)
 498 {
 499         struct typhoon_indexes *indexes = tp->indexes;
 500         struct resp_desc *resp;
 501         u8 *base = tp->respRing.ringBase;
 502         int count, len, wrap_len;
 503         u32 cleared;
 504         u32 ready;
 505
 506         cleared = le32_to_cpu(indexes->respCleared);
 507         ready = le32_to_cpu(indexes->respReady);
 508         while(cleared != ready) {
 509                 resp = (struct resp_desc *)(base + cleared);
 510                 count = resp->numDesc + 1;
 511                 if(resp_save && resp->seqNo) {
 512                         if(count > resp_size) {
 513                                 resp_save->flags = TYPHOON_RESP_ERROR;
 514                                 goto cleanup;
 515                         }
 516
 517                         wrap_len = 0;
 518                         len = count * sizeof(*resp);
 519                         if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
 520                                 wrap_len = cleared + len - RESPONSE_RING_SIZE;
 521                                 len = RESPONSE_RING_SIZE - cleared;
 522                         }
 523
 524                         memcpy(resp_save, resp, len);
 525                         if(unlikely(wrap_len)) {
 526                                 resp_save += len / sizeof(*resp);
 527                                 memcpy(resp_save, base, wrap_len);
 528                         }
 529
 530                         resp_save = NULL;
 531                 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
 532                         typhoon_media_status(tp->dev, resp);
 533                 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
 534                         typhoon_hello(tp);
 535                 } else {
 536                         printk(KERN_ERR "%s: dumping unexpected response "
 537                                "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
 538                                tp->name, le16_to_cpu(resp->cmd),
 539                                resp->numDesc, resp->flags,
 540                                le16_to_cpu(resp->parm1),
 541                                le32_to_cpu(resp->parm2),
 542                                le32_to_cpu(resp->parm3));
 543                 }
 544
 545 cleanup:
 546                 typhoon_inc_resp_index(&cleared, count);
 547         }
 548
 549         indexes->respCleared = cpu_to_le32(cleared);
 550         wmb();
 551         return (resp_save == NULL);
 552 }
 553
 554 static inline int
 555 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
 556 {
 557         /* this works for all descriptors but rx_desc, as they are a
 558          * different size than the cmd_desc -- everyone else is the same
 559          */
 560         lastWrite /= sizeof(struct cmd_desc);
 561         lastRead /= sizeof(struct cmd_desc);
 562         return (ringSize + lastRead - lastWrite - 1) % ringSize;
 563 }
 564
 565 static inline int
 566 typhoon_num_free_cmd(struct typhoon *tp)
 567 {
 568         int lastWrite = tp->cmdRing.lastWrite;
 569         int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
 570
 571         return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
 572 }
 573
 574 static inline int
 575 typhoon_num_free_resp(struct typhoon *tp)
 576 {
 577         int respReady = le32_to_cpu(tp->indexes->respReady);
 578         int respCleared = le32_to_cpu(tp->indexes->respCleared);
 579
 580         return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
 581 }
 582
 583 static inline int
 584 typhoon_num_free_tx(struct transmit_ring *ring)
 585 {
 586         /* if we start using the Hi Tx ring, this needs updating */
 587         return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
 588 }
 589
 590 static int
 591 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
 592                       int num_resp, struct resp_desc *resp)
 593 {
 594         struct typhoon_indexes *indexes = tp->indexes;
 595         struct basic_ring *ring = &tp->cmdRing;
 596         struct resp_desc local_resp;
 597         int i, err = 0;
 598         int got_resp;
 599         int freeCmd, freeResp;
 600         int len, wrap_len;
 601
 602         spin_lock(&tp->command_lock);
 603
 604         freeCmd = typhoon_num_free_cmd(tp);
 605         freeResp = typhoon_num_free_resp(tp);
 606
 607         if(freeCmd < num_cmd || freeResp < num_resp) {
 608                 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
 609                         "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
 610                         freeResp, num_resp);
 611                 err = -ENOMEM;
 612                 goto out;
 613         }
 614
 615         if(cmd->flags & TYPHOON_CMD_RESPOND) {
 616                 /* If we're expecting a response, but the caller hasn't given
 617                  * us a place to put it, we'll provide one.
 618                  */
 619                 tp->awaiting_resp = 1;
 620                 if(resp == NULL) {
 621                         resp = &local_resp;
 622                         num_resp = 1;
 623                 }
 624         }
 625
 626         wrap_len = 0;
 627         len = num_cmd * sizeof(*cmd);
 628         if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
 629                 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
 630                 len = COMMAND_RING_SIZE - ring->lastWrite;
 631         }
 632
 633         memcpy(ring->ringBase + ring->lastWrite, cmd, len);
 634         if(unlikely(wrap_len)) {
 635                 struct cmd_desc *wrap_ptr = cmd;
 636                 wrap_ptr += len / sizeof(*cmd);
 637                 memcpy(ring->ringBase, wrap_ptr, wrap_len);
 638         }
 639
 640         typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
 641
 642         /* "I feel a presence... another warrior is on the mesa."
 643          */
 644         wmb();
 645         iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 646         typhoon_post_pci_writes(tp->ioaddr);
 647
 648         if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
 649                 goto out;
 650
 651         /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
 652          * preempt or do anything other than take interrupts. So, don't
 653          * wait for a response unless you have to.
 654          *
 655          * I've thought about trying to sleep here, but we're called
 656          * from many contexts that don't allow that. Also, given the way
 657          * 3Com has implemented irq coalescing, we would likely timeout --
 658          * this has been observed in real life!
 659          *
 660          * The big killer is we have to wait to get stats from the card,
 661          * though we could go to a periodic refresh of those if we don't
 662          * mind them getting somewhat stale. The rest of the waiting
 663          * commands occur during open/close/suspend/resume, so they aren't
 664          * time critical. Creating SAs in the future will also have to
 665          * wait here.
 666          */
 667         got_resp = 0;
 668         for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
 669                 if(indexes->respCleared != indexes->respReady)
 670                         got_resp = typhoon_process_response(tp, num_resp,
 671                                                                 resp);
 672                 udelay(TYPHOON_UDELAY);
 673         }
 674
 675         if(!got_resp) {
 676                 err = -ETIMEDOUT;
 677                 goto out;
 678         }
 679
 680         /* Collect the error response even if we don't care about the
 681          * rest of the response
 682          */
 683         if(resp->flags & TYPHOON_RESP_ERROR)
 684                 err = -EIO;
 685
 686 out:
 687         if(tp->awaiting_resp) {
 688                 tp->awaiting_resp = 0;
 689                 smp_wmb();
 690
 691                 /* Ugh. If a response was added to the ring between
 692                  * the call to typhoon_process_response() and the clearing
 693                  * of tp->awaiting_resp, we could have missed the interrupt
 694                  * and it could hang in the ring an indeterminate amount of
 695                  * time. So, check for it, and interrupt ourselves if this
 696                  * is the case.
 697                  */
 698                 if(indexes->respCleared != indexes->respReady)
 699                         iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
 700         }
 701
 702         spin_unlock(&tp->command_lock);
 703         return err;
 704 }
 705
 706 static void
 707 typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 708 {
 709         struct typhoon *tp = netdev_priv(dev);
 710         struct cmd_desc xp_cmd;
 711         int err;
 712
 713         spin_lock_bh(&tp->state_lock);
 714         if(!tp->vlgrp != !grp) {
 715                 /* We've either been turned on for the first time, or we've
 716                  * been turned off. Update the 3XP.
 717                  */
 718                 if(grp)
 719                         tp->offload |= TYPHOON_OFFLOAD_VLAN;
 720                 else
 721                         tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
 722
 723                 /* If the interface is up, the runtime is running -- and we
 724                  * must be up for the vlan core to call us.
 725                  *
 726                  * Do the command outside of the spin lock, as it is slow.
 727                  */
 728                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
 729                                         TYPHOON_CMD_SET_OFFLOAD_TASKS);
 730                 xp_cmd.parm2 = tp->offload;
 731                 xp_cmd.parm3 = tp->offload;
 732                 spin_unlock_bh(&tp->state_lock);
 733                 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 734                 if(err < 0)
 735                         printk("%s: vlan offload error %d\n", tp->name, -err);
 736                 spin_lock_bh(&tp->state_lock);
 737         }
 738
 739         /* now make the change visible */
 740         tp->vlgrp = grp;
 741         spin_unlock_bh(&tp->state_lock);
 742 }
 743
 744 static inline void
 745 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
 746                         u32 ring_dma)
 747 {
 748         struct tcpopt_desc *tcpd;
 749         u32 tcpd_offset = ring_dma;
 750
 751         tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
 752         tcpd_offset += txRing->lastWrite;
 753         tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
 754         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 755
 756         tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
 757         tcpd->numDesc = 1;
 758         tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
 759         tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
 760         tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
 761         tcpd->bytesTx = cpu_to_le32(skb->len);
 762         tcpd->status = 0;
 763 }
 764
 765 static int
 766 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
 767 {
 768         struct typhoon *tp = netdev_priv(dev);
 769         struct transmit_ring *txRing;
 770         struct tx_desc *txd, *first_txd;
 771         dma_addr_t skb_dma;
 772         int numDesc;
 773
 774         /* we have two rings to choose from, but we only use txLo for now
 775          * If we start using the Hi ring as well, we'll need to update
 776          * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
 777          * and TXHI_ENTRIES to match, as well as update the TSO code below
 778          * to get the right DMA address
 779          */
 780         txRing = &tp->txLoRing;
 781
 782         /* We need one descriptor for each fragment of the sk_buff, plus the
 783          * one for the ->data area of it.
 784          *
 785          * The docs say a maximum of 16 fragment descriptors per TCP option
 786          * descriptor, then make a new packet descriptor and option descriptor
 787          * for the next 16 fragments. The engineers say just an option
 788          * descriptor is needed. I've tested up to 26 fragments with a single
 789          * packet descriptor/option descriptor combo, so I use that for now.
 790          *
 791          * If problems develop with TSO, check this first.
 792          */
 793         numDesc = skb_shinfo(skb)->nr_frags + 1;
 794         if (skb_is_gso(skb))
 795                 numDesc++;
 796
 797         /* When checking for free space in the ring, we need to also
 798          * account for the initial Tx descriptor, and we always must leave
 799          * at least one descriptor unused in the ring so that it doesn't
 800          * wrap and look empty.
 801          *
 802          * The only time we should loop here is when we hit the race
 803          * between marking the queue awake and updating the cleared index.
 804          * Just loop and it will appear. This comes from the acenic driver.
 805          */
 806         while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
 807                 smp_rmb();
 808
 809         first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 810         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 811
 812         first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
 813         first_txd->numDesc = 0;
 814         first_txd->len = 0;
 815         first_txd->addr = (u64)((unsigned long) skb) & 0xffffffff;
 816         first_txd->addrHi = (u64)((unsigned long) skb) >> 32;
 817         first_txd->processFlags = 0;
 818
 819         if(skb->ip_summed == CHECKSUM_PARTIAL) {
 820                 /* The 3XP will figure out if this is UDP/TCP */
 821                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
 822                 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
 823                 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
 824         }
 825
 826         if(vlan_tx_tag_present(skb)) {
 827                 first_txd->processFlags |=
 828                     TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
 829                 first_txd->processFlags |=
 830                     cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
 831                                 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
 832         }
 833
 834         if (skb_is_gso(skb)) {
 835                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
 836                 first_txd->numDesc++;
 837
 838                 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
 839         }
 840
 841         txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 842         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 843
 844         /* No need to worry about padding packet -- the firmware pads
 845          * it with zeros to ETH_ZLEN for us.
 846          */
 847         if(skb_shinfo(skb)->nr_frags == 0) {
 848                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
 849                                        PCI_DMA_TODEVICE);
 850                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 851                 txd->len = cpu_to_le16(skb->len);
 852                 txd->addr = cpu_to_le32(skb_dma);
 853                 txd->addrHi = 0;
 854                 first_txd->numDesc++;
 855         } else {
 856                 int i, len;
 857
 858                 len = skb_headlen(skb);
 859                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
 860                                          PCI_DMA_TODEVICE);
 861                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 862                 txd->len = cpu_to_le16(len);
 863                 txd->addr = cpu_to_le32(skb_dma);
 864                 txd->addrHi = 0;
 865                 first_txd->numDesc++;
 866
 867                 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 868                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 869                         void *frag_addr;
 870
 871                         txd = (struct tx_desc *) (txRing->ringBase +
 872                                                 txRing->lastWrite);
 873                         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 874
 875                         len = frag->size;
 876                         frag_addr = (void *) page_address(frag->page) +
 877                                                 frag->page_offset;
 878                         skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
 879                                          PCI_DMA_TODEVICE);
 880                         txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 881                         txd->len = cpu_to_le16(len);
 882                         txd->addr = cpu_to_le32(skb_dma);
 883                         txd->addrHi = 0;
 884                         first_txd->numDesc++;
 885                 }
 886         }
 887
 888         /* Kick the 3XP
 889          */
 890         wmb();
 891         iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
 892
 893         dev->trans_start = jiffies;
 894
 895         /* If we don't have room to put the worst case packet on the
 896          * queue, then we must stop the queue. We need 2 extra
 897          * descriptors -- one to prevent ring wrap, and one for the
 898          * Tx header.
 899          */
 900         numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
 901
 902         if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
 903                 netif_stop_queue(dev);
 904
 905                 /* A Tx complete IRQ could have gotten inbetween, making
 906                  * the ring free again. Only need to recheck here, since
 907                  * Tx is serialized.
 908                  */
 909                 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
 910                         netif_wake_queue(dev);
 911         }
 912
 913         return 0;
 914 }
 915
 916 static void
 917 typhoon_set_rx_mode(struct net_device *dev)
 918 {
 919         struct typhoon *tp = netdev_priv(dev);
 920         struct cmd_desc xp_cmd;
 921         u32 mc_filter[2];
 922         u16 filter;
 923
 924         filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
 925         if(dev->flags & IFF_PROMISC) {
 926                 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
 927         } else if((dev->mc_count > multicast_filter_limit) ||
 928                   (dev->flags & IFF_ALLMULTI)) {
 929                 /* Too many to match, or accept all multicasts. */
 930                 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
 931         } else if(dev->mc_count) {
 932                 struct dev_mc_list *mclist;
 933                 int i;
 934
 935                 memset(mc_filter, 0, sizeof(mc_filter));
 936                 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
 937                     i++, mclist = mclist->next) {
 938                         int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
 939                         mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
 940                 }
 941
 942                 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
 943                                          TYPHOON_CMD_SET_MULTICAST_HASH);
 944                 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
 945                 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
 946                 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
 947                 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 948
 949                 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
 950         }
 951
 952         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
 953         xp_cmd.parm1 = filter;
 954         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 955 }
 956
 957 static int
 958 typhoon_do_get_stats(struct typhoon *tp)
 959 {
 960         struct net_device_stats *stats = &tp->stats;
 961         struct net_device_stats *saved = &tp->stats_saved;
 962         struct cmd_desc xp_cmd;
 963         struct resp_desc xp_resp[7];
 964         struct stats_resp *s = (struct stats_resp *) xp_resp;
 965         int err;
 966
 967         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
 968         err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
 969         if(err < 0)
 970                 return err;
 971
 972         /* 3Com's Linux driver uses txMultipleCollisions as it's
 973          * collisions value, but there is some other collision info as well...
 974          *
 975          * The extra status reported would be a good candidate for
 976          * ethtool_ops->get_{strings,stats}()
 977          */
 978         stats->tx_packets = le32_to_cpu(s->txPackets);
 979         stats->tx_bytes = le32_to_cpu(s->txBytes);
 980         stats->tx_errors = le32_to_cpu(s->txCarrierLost);
 981         stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
 982         stats->collisions = le32_to_cpu(s->txMultipleCollisions);
 983         stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
 984         stats->rx_bytes = le32_to_cpu(s->rxBytesGood);
 985         stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
 986         stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
 987                         le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
 988         stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
 989         stats->rx_length_errors = le32_to_cpu(s->rxOversized);
 990         tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
 991                         SPEED_100 : SPEED_10;
 992         tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
 993                         DUPLEX_FULL : DUPLEX_HALF;
 994
 995         /* add in the saved statistics
 996          */
 997         stats->tx_packets += saved->tx_packets;
 998         stats->tx_bytes += saved->tx_bytes;
 999         stats->tx_errors += saved->tx_errors;
1000         stats->collisions += saved->collisions;
1001         stats->rx_packets += saved->rx_packets;
1002         stats->rx_bytes += saved->rx_bytes;
1003         stats->rx_fifo_errors += saved->rx_fifo_errors;
1004         stats->rx_errors += saved->rx_errors;
1005         stats->rx_crc_errors += saved->rx_crc_errors;
1006         stats->rx_length_errors += saved->rx_length_errors;
1007
1008         return 0;
1009 }
1010
1011 static struct net_device_stats *
1012 typhoon_get_stats(struct net_device *dev)
1013 {
1014         struct typhoon *tp = netdev_priv(dev);
1015         struct net_device_stats *stats = &tp->stats;
1016         struct net_device_stats *saved = &tp->stats_saved;
1017
1018         smp_rmb();
1019         if(tp->card_state == Sleeping)
1020                 return saved;
1021
1022         if(typhoon_do_get_stats(tp) < 0) {
1023                 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1024                 return saved;
1025         }
1026
1027         return stats;
1028 }
1029
1030 static int
1031 typhoon_set_mac_address(struct net_device *dev, void *addr)
1032 {
1033         struct sockaddr *saddr = (struct sockaddr *) addr;
1034
1035         if(netif_running(dev))
1036                 return -EBUSY;
1037
1038         memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1039         return 0;
1040 }
1041
1042 static void
1043 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1044 {
1045         struct typhoon *tp = netdev_priv(dev);
1046         struct pci_dev *pci_dev = tp->pdev;
1047         struct cmd_desc xp_cmd;
1048         struct resp_desc xp_resp[3];
1049
1050         smp_rmb();
1051         if(tp->card_state == Sleeping) {
1052                 strcpy(info->fw_version, "Sleep image");
1053         } else {
1054                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1055                 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1056                         strcpy(info->fw_version, "Unknown runtime");
1057                 } else {
1058                         u32 sleep_ver = xp_resp[0].parm2;
1059                         snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1060                                  sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1061                                  sleep_ver & 0xfff);
1062                 }
1063         }
1064
1065         strcpy(info->driver, DRV_MODULE_NAME);
1066         strcpy(info->version, DRV_MODULE_VERSION);
1067         strcpy(info->bus_info, pci_name(pci_dev));
1068 }
1069
1070 static int
1071 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1072 {
1073         struct typhoon *tp = netdev_priv(dev);
1074
1075         cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1076                                 SUPPORTED_Autoneg;
1077
1078         switch (tp->xcvr_select) {
1079         case TYPHOON_XCVR_10HALF:
1080                 cmd->advertising = ADVERTISED_10baseT_Half;
1081                 break;
1082         case TYPHOON_XCVR_10FULL:
1083                 cmd->advertising = ADVERTISED_10baseT_Full;
1084                 break;
1085         case TYPHOON_XCVR_100HALF:
1086                 cmd->advertising = ADVERTISED_100baseT_Half;
1087                 break;
1088         case TYPHOON_XCVR_100FULL:
1089                 cmd->advertising = ADVERTISED_100baseT_Full;
1090                 break;
1091         case TYPHOON_XCVR_AUTONEG:
1092                 cmd->advertising = ADVERTISED_10baseT_Half |
1093                                             ADVERTISED_10baseT_Full |
1094                                             ADVERTISED_100baseT_Half |
1095                                             ADVERTISED_100baseT_Full |
1096                                             ADVERTISED_Autoneg;
1097                 break;
1098         }
1099
1100         if(tp->capabilities & TYPHOON_FIBER) {
1101                 cmd->supported |= SUPPORTED_FIBRE;
1102                 cmd->advertising |= ADVERTISED_FIBRE;
1103                 cmd->port = PORT_FIBRE;
1104         } else {
1105                 cmd->supported |= SUPPORTED_10baseT_Half |
1106                                         SUPPORTED_10baseT_Full |
1107                                         SUPPORTED_TP;
1108                 cmd->advertising |= ADVERTISED_TP;
1109                 cmd->port = PORT_TP;
1110         }
1111
1112         /* need to get stats to make these link speed/duplex valid */
1113         typhoon_do_get_stats(tp);
1114         cmd->speed = tp->speed;
1115         cmd->duplex = tp->duplex;
1116         cmd->phy_address = 0;
1117         cmd->transceiver = XCVR_INTERNAL;
1118         if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1119                 cmd->autoneg = AUTONEG_ENABLE;
1120         else
1121                 cmd->autoneg = AUTONEG_DISABLE;
1122         cmd->maxtxpkt = 1;
1123         cmd->maxrxpkt = 1;
1124
1125         return 0;
1126 }
1127
1128 static int
1129 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1130 {
1131         struct typhoon *tp = netdev_priv(dev);
1132         struct cmd_desc xp_cmd;
1133         int xcvr;
1134         int err;
1135
1136         err = -EINVAL;
1137         if(cmd->autoneg == AUTONEG_ENABLE) {
1138                 xcvr = TYPHOON_XCVR_AUTONEG;
1139         } else {
1140                 if(cmd->duplex == DUPLEX_HALF) {
1141                         if(cmd->speed == SPEED_10)
1142                                 xcvr = TYPHOON_XCVR_10HALF;
1143                         else if(cmd->speed == SPEED_100)
1144                                 xcvr = TYPHOON_XCVR_100HALF;
1145                         else
1146                                 goto out;
1147                 } else if(cmd->duplex == DUPLEX_FULL) {
1148                         if(cmd->speed == SPEED_10)
1149                                 xcvr = TYPHOON_XCVR_10FULL;
1150                         else if(cmd->speed == SPEED_100)
1151                                 xcvr = TYPHOON_XCVR_100FULL;
1152                         else
1153                                 goto out;
1154                 } else
1155                         goto out;
1156         }
1157
1158         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1159         xp_cmd.parm1 = cpu_to_le16(xcvr);
1160         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1161         if(err < 0)
1162                 goto out;
1163
1164         tp->xcvr_select = xcvr;
1165         if(cmd->autoneg == AUTONEG_ENABLE) {
1166                 tp->speed = 0xff;       /* invalid */
1167                 tp->duplex = 0xff;      /* invalid */
1168         } else {
1169                 tp->speed = cmd->speed;
1170                 tp->duplex = cmd->duplex;
1171         }
1172
1173 out:
1174         return err;
1175 }
1176
1177 static void
1178 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1179 {
1180         struct typhoon *tp = netdev_priv(dev);
1181
1182         wol->supported = WAKE_PHY | WAKE_MAGIC;
1183         wol->wolopts = 0;
1184         if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1185                 wol->wolopts |= WAKE_PHY;
1186         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1187                 wol->wolopts |= WAKE_MAGIC;
1188         memset(&wol->sopass, 0, sizeof(wol->sopass));
1189 }
1190
1191 static int
1192 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1193 {
1194         struct typhoon *tp = netdev_priv(dev);
1195
1196         if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1197                 return -EINVAL;
1198
1199         tp->wol_events = 0;
1200         if(wol->wolopts & WAKE_PHY)
1201                 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1202         if(wol->wolopts & WAKE_MAGIC)
1203                 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1204
1205         return 0;
1206 }
1207
1208 static u32
1209 typhoon_get_rx_csum(struct net_device *dev)
1210 {
1211         /* For now, we don't allow turning off RX checksums.
1212          */
1213         return 1;
1214 }
1215
1216 static void
1217 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1218 {
1219         ering->rx_max_pending = RXENT_ENTRIES;
1220         ering->rx_mini_max_pending = 0;
1221         ering->rx_jumbo_max_pending = 0;
1222         ering->tx_max_pending = TXLO_ENTRIES - 1;
1223
1224         ering->rx_pending = RXENT_ENTRIES;
1225         ering->rx_mini_pending = 0;
1226         ering->rx_jumbo_pending = 0;
1227         ering->tx_pending = TXLO_ENTRIES - 1;
1228 }
1229
1230 static const struct ethtool_ops typhoon_ethtool_ops = {
1231         .get_settings           = typhoon_get_settings,
1232         .set_settings           = typhoon_set_settings,
1233         .get_drvinfo            = typhoon_get_drvinfo,
1234         .get_wol                = typhoon_get_wol,
1235         .set_wol                = typhoon_set_wol,
1236         .get_link               = ethtool_op_get_link,
1237         .get_rx_csum            = typhoon_get_rx_csum,
1238         .get_tx_csum            = ethtool_op_get_tx_csum,
1239         .set_tx_csum            = ethtool_op_set_tx_csum,
1240         .get_sg                 = ethtool_op_get_sg,
1241         .set_sg                 = ethtool_op_set_sg,
1242         .get_tso                = ethtool_op_get_tso,
1243         .set_tso                = ethtool_op_set_tso,
1244         .get_ringparam          = typhoon_get_ringparam,
1245 };
1246
1247 static int
1248 typhoon_wait_interrupt(void __iomem *ioaddr)
1249 {
1250         int i, err = 0;
1251
1252         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1253                 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1254                    TYPHOON_INTR_BOOTCMD)
1255                         goto out;
1256                 udelay(TYPHOON_UDELAY);
1257         }
1258
1259         err = -ETIMEDOUT;
1260
1261 out:
1262         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1263         return err;
1264 }
1265
1266 #define shared_offset(x)        offsetof(struct typhoon_shared, x)
1267
1268 static void
1269 typhoon_init_interface(struct typhoon *tp)
1270 {
1271         struct typhoon_interface *iface = &tp->shared->iface;
1272         dma_addr_t shared_dma;
1273
1274         memset(tp->shared, 0, sizeof(struct typhoon_shared));
1275
1276         /* The *Hi members of iface are all init'd to zero by the memset().
1277          */
1278         shared_dma = tp->shared_dma + shared_offset(indexes);
1279         iface->ringIndex = cpu_to_le32(shared_dma);
1280
1281         shared_dma = tp->shared_dma + shared_offset(txLo);
1282         iface->txLoAddr = cpu_to_le32(shared_dma);
1283         iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1284
1285         shared_dma = tp->shared_dma + shared_offset(txHi);
1286         iface->txHiAddr = cpu_to_le32(shared_dma);
1287         iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1288
1289         shared_dma = tp->shared_dma + shared_offset(rxBuff);
1290         iface->rxBuffAddr = cpu_to_le32(shared_dma);
1291         iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1292                                         sizeof(struct rx_free));
1293
1294         shared_dma = tp->shared_dma + shared_offset(rxLo);
1295         iface->rxLoAddr = cpu_to_le32(shared_dma);
1296         iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1297
1298         shared_dma = tp->shared_dma + shared_offset(rxHi);
1299         iface->rxHiAddr = cpu_to_le32(shared_dma);
1300         iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1301
1302         shared_dma = tp->shared_dma + shared_offset(cmd);
1303         iface->cmdAddr = cpu_to_le32(shared_dma);
1304         iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1305
1306         shared_dma = tp->shared_dma + shared_offset(resp);
1307         iface->respAddr = cpu_to_le32(shared_dma);
1308         iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1309
1310         shared_dma = tp->shared_dma + shared_offset(zeroWord);
1311         iface->zeroAddr = cpu_to_le32(shared_dma);
1312
1313         tp->indexes = &tp->shared->indexes;
1314         tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1315         tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1316         tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1317         tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1318         tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1319         tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1320         tp->respRing.ringBase = (u8 *) tp->shared->resp;
1321
1322         tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1323         tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1324
1325         tp->txlo_dma_addr = iface->txLoAddr;
1326         tp->card_state = Sleeping;
1327         smp_wmb();
1328
1329         tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1330         tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1331
1332         spin_lock_init(&tp->command_lock);
1333         spin_lock_init(&tp->state_lock);
1334 }
1335
1336 static void
1337 typhoon_init_rings(struct typhoon *tp)
1338 {
1339         memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1340
1341         tp->txLoRing.lastWrite = 0;
1342         tp->txHiRing.lastWrite = 0;
1343         tp->rxLoRing.lastWrite = 0;
1344         tp->rxHiRing.lastWrite = 0;
1345         tp->rxBuffRing.lastWrite = 0;
1346         tp->cmdRing.lastWrite = 0;
1347         tp->cmdRing.lastWrite = 0;
1348
1349         tp->txLoRing.lastRead = 0;
1350         tp->txHiRing.lastRead = 0;
1351 }
1352
1353 static int
1354 typhoon_download_firmware(struct typhoon *tp)
1355 {
1356         void __iomem *ioaddr = tp->ioaddr;
1357         struct pci_dev *pdev = tp->pdev;
1358         struct typhoon_file_header *fHdr;
1359         struct typhoon_section_header *sHdr;
1360         u8 *image_data;
1361         void *dpage;
1362         dma_addr_t dpage_dma;
1363         unsigned int csum;
1364         u32 irqEnabled;
1365         u32 irqMasked;
1366         u32 numSections;
1367         u32 section_len;
1368         u32 len;
1369         u32 load_addr;
1370         u32 hmac;
1371         int i;
1372         int err;
1373
1374         err = -EINVAL;
1375         fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
1376         image_data = (u8 *) fHdr;
1377
1378         if(memcmp(fHdr->tag, "TYPHOON", 8)) {
1379                 printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
1380                 goto err_out;
1381         }
1382
1383         /* Cannot just map the firmware image using pci_map_single() as
1384          * the firmware is part of the kernel/module image, so we allocate
1385          * some consistent memory to copy the sections into, as it is simpler,
1386          * and short-lived. If we ever split out and require a userland
1387          * firmware loader, then we can revisit this.
1388          */
1389         err = -ENOMEM;
1390         dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1391         if(!dpage) {
1392                 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1393                 goto err_out;
1394         }
1395
1396         irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1397         iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1398                ioaddr + TYPHOON_REG_INTR_ENABLE);
1399         irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1400         iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1401                ioaddr + TYPHOON_REG_INTR_MASK);
1402
1403         err = -ETIMEDOUT;
1404         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1405                 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1406                 goto err_out_irq;
1407         }
1408
1409         numSections = le32_to_cpu(fHdr->numSections);
1410         load_addr = le32_to_cpu(fHdr->startAddr);
1411
1412         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1413         iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1414         hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1415         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1416         hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1417         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1418         hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1419         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1420         hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1421         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1422         hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1423         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1424         typhoon_post_pci_writes(ioaddr);
1425         iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1426
1427         image_data += sizeof(struct typhoon_file_header);
1428
1429         /* The ioread32() in typhoon_wait_interrupt() will force the
1430          * last write to the command register to post, so
1431          * we don't need a typhoon_post_pci_writes() after it.
1432          */
1433         for(i = 0; i < numSections; i++) {
1434                 sHdr = (struct typhoon_section_header *) image_data;
1435                 image_data += sizeof(struct typhoon_section_header);
1436                 load_addr = le32_to_cpu(sHdr->startAddr);
1437                 section_len = le32_to_cpu(sHdr->len);
1438
1439                 while(section_len) {
1440                         len = min_t(u32, section_len, PAGE_SIZE);
1441
1442                         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1443                            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1444                            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1445                                 printk(KERN_ERR "%s: segment ready timeout\n",
1446                                        tp->name);
1447                                 goto err_out_irq;
1448                         }
1449
1450                         /* Do an pseudo IPv4 checksum on the data -- first
1451                          * need to convert each u16 to cpu order before
1452                          * summing. Fortunately, due to the properties of
1453                          * the checksum, we can do this once, at the end.
1454                          */
1455                         csum = csum_partial_copy_nocheck(image_data, dpage,
1456                                                          len, 0);
1457                         csum = csum_fold(csum);
1458                         csum = le16_to_cpu(csum);
1459
1460                         iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1461                         iowrite32(csum, ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1462                         iowrite32(load_addr,
1463                                         ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1464                         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1465                         iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1466                         typhoon_post_pci_writes(ioaddr);
1467                         iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1468                                ioaddr + TYPHOON_REG_COMMAND);
1469
1470                         image_data += len;
1471                         load_addr += len;
1472                         section_len -= len;
1473                 }
1474         }
1475
1476         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1477            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1478            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1479                 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1480                 goto err_out_irq;
1481         }
1482
1483         iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1484
1485         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1486                 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1487                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1488                 goto err_out_irq;
1489         }
1490
1491         err = 0;
1492
1493 err_out_irq:
1494         iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1495         iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1496
1497         pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1498
1499 err_out:
1500         return err;
1501 }
1502
1503 static int
1504 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1505 {
1506         void __iomem *ioaddr = tp->ioaddr;
1507
1508         if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1509                 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1510                 goto out_timeout;
1511         }
1512
1513         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1514         iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1515         typhoon_post_pci_writes(ioaddr);
1516         iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1517                                 ioaddr + TYPHOON_REG_COMMAND);
1518
1519         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1520                 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1521                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1522                 goto out_timeout;
1523         }
1524
1525         /* Clear the Transmit and Command ready registers
1526          */
1527         iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1528         iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1529         iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1530         typhoon_post_pci_writes(ioaddr);
1531         iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1532
1533         return 0;
1534
1535 out_timeout:
1536         return -ETIMEDOUT;
1537 }
1538
1539 static u32
1540 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1541                         volatile u32 * index)
1542 {
1543         u32 lastRead = txRing->lastRead;
1544         struct tx_desc *tx;
1545         dma_addr_t skb_dma;
1546         int dma_len;
1547         int type;
1548
1549         while(lastRead != le32_to_cpu(*index)) {
1550                 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1551                 type = tx->flags & TYPHOON_TYPE_MASK;
1552
1553                 if(type == TYPHOON_TX_DESC) {
1554                         /* This tx_desc describes a packet.
1555                          */
1556                         unsigned long ptr = tx->addr | ((u64)tx->addrHi << 32);
1557                         struct sk_buff *skb = (struct sk_buff *) ptr;
1558                         dev_kfree_skb_irq(skb);
1559                 } else if(type == TYPHOON_FRAG_DESC) {
1560                         /* This tx_desc describes a memory mapping. Free it.
1561                          */
1562                         skb_dma = (dma_addr_t) le32_to_cpu(tx->addr);
1563                         dma_len = le16_to_cpu(tx->len);
1564                         pci_unmap_single(tp->pdev, skb_dma, dma_len,
1565                                        PCI_DMA_TODEVICE);
1566                 }
1567
1568                 tx->flags = 0;
1569                 typhoon_inc_tx_index(&lastRead, 1);
1570         }
1571
1572         return lastRead;
1573 }
1574
1575 static void
1576 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1577                         volatile u32 * index)
1578 {
1579         u32 lastRead;
1580         int numDesc = MAX_SKB_FRAGS + 1;
1581
1582         /* This will need changing if we start to use the Hi Tx ring. */
1583         lastRead = typhoon_clean_tx(tp, txRing, index);
1584         if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1585                                 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1586                 netif_wake_queue(tp->dev);
1587
1588         txRing->lastRead = lastRead;
1589         smp_wmb();
1590 }
1591
1592 static void
1593 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1594 {
1595         struct typhoon_indexes *indexes = tp->indexes;
1596         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1597         struct basic_ring *ring = &tp->rxBuffRing;
1598         struct rx_free *r;
1599
1600         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1601                                 indexes->rxBuffCleared) {
1602                 /* no room in ring, just drop the skb
1603                  */
1604                 dev_kfree_skb_any(rxb->skb);
1605                 rxb->skb = NULL;
1606                 return;
1607         }
1608
1609         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1610         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1611         r->virtAddr = idx;
1612         r->physAddr = cpu_to_le32(rxb->dma_addr);
1613
1614         /* Tell the card about it */
1615         wmb();
1616         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1617 }
1618
1619 static int
1620 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1621 {
1622         struct typhoon_indexes *indexes = tp->indexes;
1623         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1624         struct basic_ring *ring = &tp->rxBuffRing;
1625         struct rx_free *r;
1626         struct sk_buff *skb;
1627         dma_addr_t dma_addr;
1628
1629         rxb->skb = NULL;
1630
1631         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1632                                 indexes->rxBuffCleared)
1633                 return -ENOMEM;
1634
1635         skb = dev_alloc_skb(PKT_BUF_SZ);
1636         if(!skb)
1637                 return -ENOMEM;
1638
1639 #if 0
1640         /* Please, 3com, fix the firmware to allow DMA to a unaligned
1641          * address! Pretty please?
1642          */
1643         skb_reserve(skb, 2);
1644 #endif
1645
1646         skb->dev = tp->dev;
1647         dma_addr = pci_map_single(tp->pdev, skb->data,
1648                                   PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1649
1650         /* Since no card does 64 bit DAC, the high bits will never
1651          * change from zero.
1652          */
1653         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1654         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1655         r->virtAddr = idx;
1656         r->physAddr = cpu_to_le32(dma_addr);
1657         rxb->skb = skb;
1658         rxb->dma_addr = dma_addr;
1659
1660         /* Tell the card about it */
1661         wmb();
1662         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1663         return 0;
1664 }
1665
1666 static int
1667 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready,
1668            volatile u32 * cleared, int budget)
1669 {
1670         struct rx_desc *rx;
1671         struct sk_buff *skb, *new_skb;
1672         struct rxbuff_ent *rxb;
1673         dma_addr_t dma_addr;
1674         u32 local_ready;
1675         u32 rxaddr;
1676         int pkt_len;
1677         u32 idx;
1678         u32 csum_bits;
1679         int received;
1680
1681         received = 0;
1682         local_ready = le32_to_cpu(*ready);
1683         rxaddr = le32_to_cpu(*cleared);
1684         while(rxaddr != local_ready && budget > 0) {
1685                 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1686                 idx = rx->addr;
1687                 rxb = &tp->rxbuffers[idx];
1688                 skb = rxb->skb;
1689                 dma_addr = rxb->dma_addr;
1690
1691                 typhoon_inc_rx_index(&rxaddr, 1);
1692
1693                 if(rx->flags & TYPHOON_RX_ERROR) {
1694                         typhoon_recycle_rx_skb(tp, idx);
1695                         continue;
1696                 }
1697
1698                 pkt_len = le16_to_cpu(rx->frameLen);
1699
1700                 if(pkt_len < rx_copybreak &&
1701                    (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1702                         skb_reserve(new_skb, 2);
1703                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1704                                                     PKT_BUF_SZ,
1705                                                     PCI_DMA_FROMDEVICE);
1706                         skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1707                         pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1708                                                        PKT_BUF_SZ,
1709                                                        PCI_DMA_FROMDEVICE);
1710                         skb_put(new_skb, pkt_len);
1711                         typhoon_recycle_rx_skb(tp, idx);
1712                 } else {
1713                         new_skb = skb;
1714                         skb_put(new_skb, pkt_len);
1715                         pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1716                                        PCI_DMA_FROMDEVICE);
1717                         typhoon_alloc_rx_skb(tp, idx);
1718                 }
1719                 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1720                 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1721                         TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1722                 if(csum_bits ==
1723                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1724                    || csum_bits ==
1725                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1726                         new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1727                 } else
1728                         new_skb->ip_summed = CHECKSUM_NONE;
1729
1730                 spin_lock(&tp->state_lock);
1731                 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1732                         vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1733                                                  ntohl(rx->vlanTag) & 0xffff);
1734                 else
1735                         netif_receive_skb(new_skb);
1736                 spin_unlock(&tp->state_lock);
1737
1738                 tp->dev->last_rx = jiffies;
1739                 received++;
1740                 budget--;
1741         }
1742         *cleared = cpu_to_le32(rxaddr);
1743
1744         return received;
1745 }
1746
1747 static void
1748 typhoon_fill_free_ring(struct typhoon *tp)
1749 {
1750         u32 i;
1751
1752         for(i = 0; i < RXENT_ENTRIES; i++) {
1753                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1754                 if(rxb->skb)
1755                         continue;
1756                 if(typhoon_alloc_rx_skb(tp, i) < 0)
1757                         break;
1758         }
1759 }
1760
1761 static int
1762 typhoon_poll(struct net_device *dev, int *total_budget)
1763 {
1764         struct typhoon *tp = netdev_priv(dev);
1765         struct typhoon_indexes *indexes = tp->indexes;
1766         int orig_budget = *total_budget;
1767         int budget, work_done, done;
1768
1769         rmb();
1770         if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1771                         typhoon_process_response(tp, 0, NULL);
1772
1773         if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1774                 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1775
1776         if(orig_budget > dev->quota)
1777                 orig_budget = dev->quota;
1778
1779         budget = orig_budget;
1780         work_done = 0;
1781         done = 1;
1782
1783         if(indexes->rxHiCleared != indexes->rxHiReady) {
1784                 work_done = typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1785                                         &indexes->rxHiCleared, budget);
1786                 budget -= work_done;
1787         }
1788
1789         if(indexes->rxLoCleared != indexes->rxLoReady) {
1790                 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1791                                         &indexes->rxLoCleared, budget);
1792         }
1793
1794         if(work_done) {
1795                 *total_budget -= work_done;
1796                 dev->quota -= work_done;
1797
1798                 if(work_done >= orig_budget)
1799                         done = 0;
1800         }
1801
1802         if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1803                 /* rxBuff ring is empty, try to fill it. */
1804                 typhoon_fill_free_ring(tp);
1805         }
1806
1807         if(done) {
1808                 netif_rx_complete(dev);
1809                 iowrite32(TYPHOON_INTR_NONE,
1810                                 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1811                 typhoon_post_pci_writes(tp->ioaddr);
1812         }
1813
1814         return (done ? 0 : 1);
1815 }
1816
1817 static irqreturn_t
1818 typhoon_interrupt(int irq, void *dev_instance)
1819 {
1820         struct net_device *dev = (struct net_device *) dev_instance;
1821         struct typhoon *tp = dev->priv;
1822         void __iomem *ioaddr = tp->ioaddr;
1823         u32 intr_status;
1824
1825         intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1826         if(!(intr_status & TYPHOON_INTR_HOST_INT))
1827                 return IRQ_NONE;
1828
1829         iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1830
1831         if(netif_rx_schedule_prep(dev)) {
1832                 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1833                 typhoon_post_pci_writes(ioaddr);
1834                 __netif_rx_schedule(dev);
1835         } else {
1836                 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1837                        dev->name);
1838         }
1839         return IRQ_HANDLED;
1840 }
1841
1842 static void
1843 typhoon_free_rx_rings(struct typhoon *tp)
1844 {
1845         u32 i;
1846
1847         for(i = 0; i < RXENT_ENTRIES; i++) {
1848                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1849                 if(rxb->skb) {
1850                         pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1851                                        PCI_DMA_FROMDEVICE);
1852                         dev_kfree_skb(rxb->skb);
1853                         rxb->skb = NULL;
1854                 }
1855         }
1856 }
1857
1858 static int
1859 typhoon_sleep(struct typhoon *tp, pci_power_t state, u16 events)
1860 {
1861         struct pci_dev *pdev = tp->pdev;
1862         void __iomem *ioaddr = tp->ioaddr;
1863         struct cmd_desc xp_cmd;
1864         int err;
1865
1866         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1867         xp_cmd.parm1 = events;
1868         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1869         if(err < 0) {
1870                 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1871                                 tp->name, err);
1872                 return err;
1873         }
1874
1875         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1876         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1877         if(err < 0) {
1878                 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1879                                 tp->name, err);
1880                 return err;
1881         }
1882
1883         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1884                 return -ETIMEDOUT;
1885
1886         /* Since we cannot monitor the status of the link while sleeping,
1887          * tell the world it went away.
1888          */
1889         netif_carrier_off(tp->dev);
1890
1891         pci_enable_wake(tp->pdev, state, 1);
1892         pci_disable_device(pdev);
1893         return pci_set_power_state(pdev, state);
1894 }
1895
1896 static int
1897 typhoon_wakeup(struct typhoon *tp, int wait_type)
1898 {
1899         struct pci_dev *pdev = tp->pdev;
1900         void __iomem *ioaddr = tp->ioaddr;
1901
1902         pci_set_power_state(pdev, PCI_D0);
1903         pci_restore_state(pdev);
1904
1905         /* Post 2.x.x versions of the Sleep Image require a reset before
1906          * we can download the Runtime Image. But let's not make users of
1907          * the old firmware pay for the reset.
1908          */
1909         iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1910         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1911                         (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1912                 return typhoon_reset(ioaddr, wait_type);
1913
1914         return 0;
1915 }
1916
1917 static int
1918 typhoon_start_runtime(struct typhoon *tp)
1919 {
1920         struct net_device *dev = tp->dev;
1921         void __iomem *ioaddr = tp->ioaddr;
1922         struct cmd_desc xp_cmd;
1923         int err;
1924
1925         typhoon_init_rings(tp);
1926         typhoon_fill_free_ring(tp);
1927
1928         err = typhoon_download_firmware(tp);
1929         if(err < 0) {
1930                 printk("%s: cannot load runtime on 3XP\n", tp->name);
1931                 goto error_out;
1932         }
1933
1934         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1935                 printk("%s: cannot boot 3XP\n", tp->name);
1936                 err = -EIO;
1937                 goto error_out;
1938         }
1939
1940         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1941         xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1942         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1943         if(err < 0)
1944                 goto error_out;
1945
1946         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1947         xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
1948         xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
1949         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1950         if(err < 0)
1951                 goto error_out;
1952
1953         /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1954          * us some more information on how to control it.
1955          */
1956         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1957         xp_cmd.parm1 = 0;
1958         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1959         if(err < 0)
1960                 goto error_out;
1961
1962         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1963         xp_cmd.parm1 = tp->xcvr_select;
1964         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1965         if(err < 0)
1966                 goto error_out;
1967
1968         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1969         xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
1970         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1971         if(err < 0)
1972                 goto error_out;
1973
1974         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1975         spin_lock_bh(&tp->state_lock);
1976         xp_cmd.parm2 = tp->offload;
1977         xp_cmd.parm3 = tp->offload;
1978         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1979         spin_unlock_bh(&tp->state_lock);
1980         if(err < 0)
1981                 goto error_out;
1982
1983         typhoon_set_rx_mode(dev);
1984
1985         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1986         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1987         if(err < 0)
1988                 goto error_out;
1989
1990         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1991         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1992         if(err < 0)
1993                 goto error_out;
1994
1995         tp->card_state = Running;
1996         smp_wmb();
1997
1998         iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1999         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
2000         typhoon_post_pci_writes(ioaddr);
2001
2002         return 0;
2003
2004 error_out:
2005         typhoon_reset(ioaddr, WaitNoSleep);
2006         typhoon_free_rx_rings(tp);
2007         typhoon_init_rings(tp);
2008         return err;
2009 }
2010
2011 static int
2012 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
2013 {
2014         struct typhoon_indexes *indexes = tp->indexes;
2015         struct transmit_ring *txLo = &tp->txLoRing;
2016         void __iomem *ioaddr = tp->ioaddr;
2017         struct cmd_desc xp_cmd;
2018         int i;
2019
2020         /* Disable interrupts early, since we can't schedule a poll
2021          * when called with !netif_running(). This will be posted
2022          * when we force the posting of the command.
2023          */
2024         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2025
2026         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2027         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2028
2029         /* Wait 1/2 sec for any outstanding transmits to occur
2030          * We'll cleanup after the reset if this times out.
2031          */
2032         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2033                 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2034                         break;
2035                 udelay(TYPHOON_UDELAY);
2036         }
2037
2038         if(i == TYPHOON_WAIT_TIMEOUT)
2039                 printk(KERN_ERR
2040                        "%s: halt timed out waiting for Tx to complete\n",
2041                        tp->name);
2042
2043         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2044         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2045
2046         /* save the statistics so when we bring the interface up again,
2047          * the values reported to userspace are correct.
2048          */
2049         tp->card_state = Sleeping;
2050         smp_wmb();
2051         typhoon_do_get_stats(tp);
2052         memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2053
2054         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2055         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2056
2057         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2058                 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2059                        tp->name);
2060
2061         if(typhoon_reset(ioaddr, wait_type) < 0) {
2062                 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2063                 return -ETIMEDOUT;
2064         }
2065
2066         /* cleanup any outstanding Tx packets */
2067         if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2068                 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2069                 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2070         }
2071
2072         return 0;
2073 }
2074
2075 static void
2076 typhoon_tx_timeout(struct net_device *dev)
2077 {
2078         struct typhoon *tp = netdev_priv(dev);
2079
2080         if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2081                 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2082                                         dev->name);
2083                 goto truely_dead;
2084         }
2085
2086         /* If we ever start using the Hi ring, it will need cleaning too */
2087         typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2088         typhoon_free_rx_rings(tp);
2089
2090         if(typhoon_start_runtime(tp) < 0) {
2091                 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2092                                         dev->name);
2093                 goto truely_dead;
2094         }
2095
2096         netif_wake_queue(dev);
2097         return;
2098
2099 truely_dead:
2100         /* Reset the hardware, and turn off carrier to avoid more timeouts */
2101         typhoon_reset(tp->ioaddr, NoWait);
2102         netif_carrier_off(dev);
2103 }
2104
2105 static int
2106 typhoon_open(struct net_device *dev)
2107 {
2108         struct typhoon *tp = netdev_priv(dev);
2109         int err;
2110
2111         err = typhoon_wakeup(tp, WaitSleep);
2112         if(err < 0) {
2113                 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2114                 goto out_sleep;
2115         }
2116
2117         err = request_irq(dev->irq, &typhoon_interrupt, IRQF_SHARED,
2118                                 dev->name, dev);
2119         if(err < 0)
2120                 goto out_sleep;
2121
2122         err = typhoon_start_runtime(tp);
2123         if(err < 0)
2124                 goto out_irq;
2125
2126         netif_start_queue(dev);
2127         return 0;
2128
2129 out_irq:
2130         free_irq(dev->irq, dev);
2131
2132 out_sleep:
2133         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2134                 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2135                                 dev->name);
2136                 typhoon_reset(tp->ioaddr, NoWait);
2137                 goto out;
2138         }
2139
2140         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2141                 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2142
2143 out:
2144         return err;
2145 }
2146
2147 static int
2148 typhoon_close(struct net_device *dev)
2149 {
2150         struct typhoon *tp = netdev_priv(dev);
2151
2152         netif_stop_queue(dev);
2153
2154         if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2155                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2156
2157         /* Make sure there is no irq handler running on a different CPU. */
2158         typhoon_synchronize_irq(dev->irq);
2159         free_irq(dev->irq, dev);
2160
2161         typhoon_free_rx_rings(tp);
2162         typhoon_init_rings(tp);
2163
2164         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2165                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2166
2167         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2168                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2169
2170         return 0;
2171 }
2172
2173 #ifdef CONFIG_PM
2174 static int
2175 typhoon_resume(struct pci_dev *pdev)
2176 {
2177         struct net_device *dev = pci_get_drvdata(pdev);
2178         struct typhoon *tp = netdev_priv(dev);
2179
2180         /* If we're down, resume when we are upped.
2181          */
2182         if(!netif_running(dev))
2183                 return 0;
2184
2185         if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2186                 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2187                                 dev->name);
2188                 goto reset;
2189         }
2190
2191         if(typhoon_start_runtime(tp) < 0) {
2192                 printk(KERN_ERR "%s: critical: could not start runtime in "
2193                                 "resume\n", dev->name);
2194                 goto reset;
2195         }
2196
2197         netif_device_attach(dev);
2198         netif_start_queue(dev);
2199         return 0;
2200
2201 reset:
2202         typhoon_reset(tp->ioaddr, NoWait);
2203         return -EBUSY;
2204 }
2205
2206 static int
2207 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2208 {
2209         struct net_device *dev = pci_get_drvdata(pdev);
2210         struct typhoon *tp = netdev_priv(dev);
2211         struct cmd_desc xp_cmd;
2212
2213         /* If we're down, we're already suspended.
2214          */
2215         if(!netif_running(dev))
2216                 return 0;
2217
2218         spin_lock_bh(&tp->state_lock);
2219         if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2220                 spin_unlock_bh(&tp->state_lock);
2221                 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2222                                 dev->name);
2223                 return -EBUSY;
2224         }
2225         spin_unlock_bh(&tp->state_lock);
2226
2227         netif_device_detach(dev);
2228
2229         if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2230                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2231                 goto need_resume;
2232         }
2233
2234         typhoon_free_rx_rings(tp);
2235         typhoon_init_rings(tp);
2236
2237         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2238                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2239                 goto need_resume;
2240         }
2241
2242         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2243         xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
2244         xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
2245         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2246                 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2247                                 dev->name);
2248                 goto need_resume;
2249         }
2250
2251         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2252         xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2253         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2254                 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2255                                 dev->name);
2256                 goto need_resume;
2257         }
2258
2259         if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2260                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2261                 goto need_resume;
2262         }
2263
2264         return 0;
2265
2266 need_resume:
2267         typhoon_resume(pdev);
2268         return -EBUSY;
2269 }
2270 #endif
2271
2272 static int __devinit
2273 typhoon_test_mmio(struct pci_dev *pdev)
2274 {
2275         void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2276         int mode = 0;
2277         u32 val;
2278
2279         if(!ioaddr)
2280                 goto out;
2281
2282         if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2283                                 TYPHOON_STATUS_WAITING_FOR_HOST)
2284                 goto out_unmap;
2285
2286         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2287         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2288         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2289
2290         /* Ok, see if we can change our interrupt status register by
2291          * sending ourselves an interrupt. If so, then MMIO works.
2292          * The 50usec delay is arbitrary -- it could probably be smaller.
2293          */
2294         val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2295         if((val & TYPHOON_INTR_SELF) == 0) {
2296                 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2297                 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2298                 udelay(50);
2299                 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2300                 if(val & TYPHOON_INTR_SELF)
2301                         mode = 1;
2302         }
2303
2304         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2305         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2306         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2307         ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2308
2309 out_unmap:
2310         pci_iounmap(pdev, ioaddr);
2311
2312 out:
2313         if(!mode)
2314                 printk(KERN_INFO PFX "falling back to port IO\n");
2315         return mode;
2316 }
2317
2318 static int __devinit
2319 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2320 {
2321         static int did_version = 0;
2322         struct net_device *dev;
2323         struct typhoon *tp;
2324         int card_id = (int) ent->driver_data;
2325         void __iomem *ioaddr;
2326         void *shared;
2327         dma_addr_t shared_dma;
2328         struct cmd_desc xp_cmd;
2329         struct resp_desc xp_resp[3];
2330         int i;
2331         int err = 0;
2332
2333         if(!did_version++)
2334                 printk(KERN_INFO "%s", version);
2335
2336         dev = alloc_etherdev(sizeof(*tp));
2337         if(dev == NULL) {
2338                 printk(ERR_PFX "%s: unable to alloc new net device\n",
2339                        pci_name(pdev));
2340                 err = -ENOMEM;
2341                 goto error_out;
2342         }
2343         SET_MODULE_OWNER(dev);
2344         SET_NETDEV_DEV(dev, &pdev->dev);
2345
2346         err = pci_enable_device(pdev);
2347         if(err < 0) {
2348                 printk(ERR_PFX "%s: unable to enable device\n",
2349                        pci_name(pdev));
2350                 goto error_out_dev;
2351         }
2352
2353         err = pci_set_mwi(pdev);
2354         if(err < 0) {
2355                 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2356                 goto error_out_disable;
2357         }
2358
2359         err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2360         if(err < 0) {
2361                 printk(ERR_PFX "%s: No usable DMA configuration\n",
2362                        pci_name(pdev));
2363                 goto error_out_mwi;
2364         }
2365
2366         /* sanity checks on IO and MMIO BARs
2367          */
2368         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2369                 printk(ERR_PFX
2370                        "%s: region #1 not a PCI IO resource, aborting\n",
2371                        pci_name(pdev));
2372                 err = -ENODEV;
2373                 goto error_out_mwi;
2374         }
2375         if(pci_resource_len(pdev, 0) < 128) {
2376                 printk(ERR_PFX "%s: Invalid PCI IO region size, aborting\n",
2377                        pci_name(pdev));
2378                 err = -ENODEV;
2379                 goto error_out_mwi;
2380         }
2381         if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2382                 printk(ERR_PFX
2383                        "%s: region #1 not a PCI MMIO resource, aborting\n",
2384                        pci_name(pdev));
2385                 err = -ENODEV;
2386                 goto error_out_mwi;
2387         }
2388         if(pci_resource_len(pdev, 1) < 128) {
2389                 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2390                        pci_name(pdev));
2391                 err = -ENODEV;
2392                 goto error_out_mwi;
2393         }
2394
2395         err = pci_request_regions(pdev, "typhoon");
2396         if(err < 0) {
2397                 printk(ERR_PFX "%s: could not request regions\n",
2398                        pci_name(pdev));
2399                 goto error_out_mwi;
2400         }
2401
2402         /* map our registers
2403          */
2404         if(use_mmio != 0 && use_mmio != 1)
2405                 use_mmio = typhoon_test_mmio(pdev);
2406
2407         ioaddr = pci_iomap(pdev, use_mmio, 128);
2408         if (!ioaddr) {
2409                 printk(ERR_PFX "%s: cannot remap registers, aborting\n",
2410                        pci_name(pdev));
2411                 err = -EIO;
2412                 goto error_out_regions;
2413         }
2414
2415         /* allocate pci dma space for rx and tx descriptor rings
2416          */
2417         shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2418                                       &shared_dma);
2419         if(!shared) {
2420                 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2421                        pci_name(pdev));
2422                 err = -ENOMEM;
2423                 goto error_out_remap;
2424         }
2425
2426         dev->irq = pdev->irq;
2427         tp = netdev_priv(dev);
2428         tp->shared = (struct typhoon_shared *) shared;
2429         tp->shared_dma = shared_dma;
2430         tp->pdev = pdev;
2431         tp->tx_pdev = pdev;
2432         tp->ioaddr = ioaddr;
2433         tp->tx_ioaddr = ioaddr;
2434         tp->dev = dev;
2435
2436         /* Init sequence:
2437          * 1) Reset the adapter to clear any bad juju
2438          * 2) Reload the sleep image
2439          * 3) Boot the sleep image
2440          * 4) Get the hardware address.
2441          * 5) Put the card to sleep.
2442          */
2443         if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2444                 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2445                 err = -EIO;
2446                 goto error_out_dma;
2447         }
2448
2449         /* Now that we've reset the 3XP and are sure it's not going to
2450          * write all over memory, enable bus mastering, and save our
2451          * state for resuming after a suspend.
2452          */
2453         pci_set_master(pdev);
2454         pci_save_state(pdev);
2455
2456         /* dev->name is not valid until we register, but we need to
2457          * use some common routines to initialize the card. So that those
2458          * routines print the right name, we keep our oun pointer to the name
2459          */
2460         tp->name = pci_name(pdev);
2461
2462         typhoon_init_interface(tp);
2463         typhoon_init_rings(tp);
2464
2465         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2466                 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2467                        pci_name(pdev));
2468                 err = -EIO;
2469                 goto error_out_reset;
2470         }
2471
2472         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2473         if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2474                 printk(ERR_PFX "%s: cannot read MAC address\n",
2475                        pci_name(pdev));
2476                 err = -EIO;
2477                 goto error_out_reset;
2478         }
2479
2480         *(u16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2481         *(u32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2482
2483         if(!is_valid_ether_addr(dev->dev_addr)) {
2484                 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2485                        "aborting\n", pci_name(pdev));
2486                 goto error_out_reset;
2487         }
2488
2489         /* Read the Sleep Image version last, so the response is valid
2490          * later when we print out the version reported.
2491          */
2492         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2493         if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2494                 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2495                         pci_name(pdev));
2496                 goto error_out_reset;
2497         }
2498
2499         tp->capabilities = typhoon_card_info[card_id].capabilities;
2500         tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2501
2502         /* Typhoon 1.0 Sleep Images return one response descriptor to the
2503          * READ_VERSIONS command. Those versions are OK after waking up
2504          * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2505          * seem to need a little extra help to get started. Since we don't
2506          * know how to nudge it along, just kick it.
2507          */
2508         if(xp_resp[0].numDesc != 0)
2509                 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2510
2511         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2512                 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2513                        pci_name(pdev));
2514                 err = -EIO;
2515                 goto error_out_reset;
2516         }
2517
2518         /* The chip-specific entries in the device structure. */
2519         dev->open               = typhoon_open;
2520         dev->hard_start_xmit    = typhoon_start_tx;
2521         dev->stop               = typhoon_close;
2522         dev->set_multicast_list = typhoon_set_rx_mode;
2523         dev->tx_timeout         = typhoon_tx_timeout;
2524         dev->poll               = typhoon_poll;
2525         dev->weight             = 16;
2526         dev->watchdog_timeo     = TX_TIMEOUT;
2527         dev->get_stats          = typhoon_get_stats;
2528         dev->set_mac_address    = typhoon_set_mac_address;
2529         dev->vlan_rx_register   = typhoon_vlan_rx_register;
2530
2531         SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2532
2533         /* We can handle scatter gather, up to 16 entries, and
2534          * we can do IP checksumming (only version 4, doh...)
2535          */
2536         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2537         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2538         dev->features |= NETIF_F_TSO;
2539
2540         if(register_netdev(dev) < 0)
2541                 goto error_out_reset;
2542
2543         /* fixup our local name */
2544         tp->name = dev->name;
2545
2546         pci_set_drvdata(pdev, dev);
2547
2548         printk(KERN_INFO "%s: %s at %s 0x%llx, ",
2549                dev->name, typhoon_card_info[card_id].name,
2550                use_mmio ? "MMIO" : "IO",
2551                (unsigned long long)pci_resource_start(pdev, use_mmio));
2552         for(i = 0; i < 5; i++)
2553                 printk("%2.2x:", dev->dev_addr[i]);
2554         printk("%2.2x\n", dev->dev_addr[i]);
2555
2556         /* xp_resp still contains the response to the READ_VERSIONS command.
2557          * For debugging, let the user know what version he has.
2558          */
2559         if(xp_resp[0].numDesc == 0) {
2560                 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2561                  * of version is Month/Day of build.
2562                  */
2563                 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2564                 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2565                         "%02u/%02u/2000\n", dev->name, monthday >> 8,
2566                         monthday & 0xff);
2567         } else if(xp_resp[0].numDesc == 2) {
2568                 /* This is the Typhoon 1.1+ type Sleep Image
2569                  */
2570                 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2571                 u8 *ver_string = (u8 *) &xp_resp[1];
2572                 ver_string[25] = 0;
2573                 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2574                         "%02x.%03x.%03x %s\n", dev->name, sleep_ver >> 24,
2575                         (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff,
2576                         ver_string);
2577         } else {
2578                 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2579                         "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2580                         le32_to_cpu(xp_resp[0].parm2));
2581         }
2582
2583         return 0;
2584
2585 error_out_reset:
2586         typhoon_reset(ioaddr, NoWait);
2587
2588 error_out_dma:
2589         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2590                             shared, shared_dma);
2591 error_out_remap:
2592         pci_iounmap(pdev, ioaddr);
2593 error_out_regions:
2594         pci_release_regions(pdev);
2595 error_out_mwi:
2596         pci_clear_mwi(pdev);
2597 error_out_disable:
2598         pci_disable_device(pdev);
2599 error_out_dev:
2600         free_netdev(dev);
2601 error_out:
2602         return err;
2603 }
2604
2605 static void __devexit
2606 typhoon_remove_one(struct pci_dev *pdev)
2607 {
2608         struct net_device *dev = pci_get_drvdata(pdev);
2609         struct typhoon *tp = netdev_priv(dev);
2610
2611         unregister_netdev(dev);
2612         pci_set_power_state(pdev, PCI_D0);
2613         pci_restore_state(pdev);
2614         typhoon_reset(tp->ioaddr, NoWait);
2615         pci_iounmap(pdev, tp->ioaddr);
2616         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2617                             tp->shared, tp->shared_dma);
2618         pci_release_regions(pdev);
2619         pci_clear_mwi(pdev);
2620         pci_disable_device(pdev);
2621         pci_set_drvdata(pdev, NULL);
2622         free_netdev(dev);
2623 }
2624
2625 static struct pci_driver typhoon_driver = {
2626         .name           = DRV_MODULE_NAME,
2627         .id_table       = typhoon_pci_tbl,
2628         .probe          = typhoon_init_one,
2629         .remove         = __devexit_p(typhoon_remove_one),
2630 #ifdef CONFIG_PM
2631         .suspend        = typhoon_suspend,
2632         .resume         = typhoon_resume,
2633 #endif
2634 };
2635
2636 static int __init
2637 typhoon_init(void)
2638 {
2639         return pci_register_driver(&typhoon_driver);
2640 }
2641
2642 static void __exit
2643 typhoon_cleanup(void)
2644 {
2645         pci_unregister_driver(&typhoon_driver);
2646 }
2647
2648 module_init(typhoon_init);
2649 module_exit(typhoon_cleanup);