Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-2.6] / drivers / ide / pci / hpt34x.c
1 /*
2  * linux/drivers/ide/pci/hpt34x.c               Version 0.40    Sept 10, 2002
3  *
4  * Copyright (C) 1998-2000      Andre Hedrick <andre@linux-ide.org>
5  * May be copied or modified under the terms of the GNU General Public License
6  *
7  *
8  * 00:12.0 Unknown mass storage controller:
9  * Triones Technologies, Inc.
10  * Unknown device 0003 (rev 01)
11  *
12  * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13  * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14  * hde: DMA 2  (0x0000 0x0002) (0x0000 0x0010)
15  * hdf: DMA 2  (0x0002 0x0012) (0x0010 0x0030)
16  * hdg: DMA 1  (0x0012 0x0052) (0x0030 0x0070)
17  * hdh: DMA 1  (0x0052 0x0252) (0x0070 0x00f0)
18  *
19  * ide-pci.c reference
20  *
21  * Since there are two cards that report almost identically,
22  * the only discernable difference is the values reported in pcicmd.
23  * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24  * Non-bootable card or HPT343 :: pcicmd == 0x05
25  */
26
27 #include <linux/module.h>
28 #include <linux/types.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/timer.h>
32 #include <linux/mm.h>
33 #include <linux/ioport.h>
34 #include <linux/blkdev.h>
35 #include <linux/hdreg.h>
36 #include <linux/interrupt.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/ide.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43
44 #define HPT343_DEBUG_DRIVE_INFO         0
45
46 static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
47 {
48         struct pci_dev *dev     = HWIF(drive)->pci_dev;
49         u8 speed = ide_rate_filter(drive, xferspeed);
50         u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
51         u8                      hi_speed, lo_speed;
52
53         hi_speed = speed >> 4;
54         lo_speed = speed & 0x0f;
55
56         if (hi_speed & 7) {
57                 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
58         } else {
59                 lo_speed <<= 5;
60                 lo_speed >>= 5;
61         }
62
63         pci_read_config_dword(dev, 0x44, &reg1);
64         pci_read_config_dword(dev, 0x48, &reg2);
65         tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
66         tmp2 = ((hi_speed << drive->dn) | (reg2 & ~(0x11 << drive->dn)));
67         pci_write_config_dword(dev, 0x44, tmp1);
68         pci_write_config_dword(dev, 0x48, tmp2);
69
70 #if HPT343_DEBUG_DRIVE_INFO
71         printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
72                 " (0x%02x 0x%02x)\n",
73                 drive->name, ide_xfer_verbose(speed),
74                 drive->dn, reg1, tmp1, reg2, tmp2,
75                 hi_speed, lo_speed);
76 #endif /* HPT343_DEBUG_DRIVE_INFO */
77
78         return(ide_config_drive_speed(drive, speed));
79 }
80
81 static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
82 {
83         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
84         (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
85 }
86
87 static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
88 {
89         drive->init_speed = 0;
90
91         if (ide_tune_dma(drive))
92 #ifndef CONFIG_HPT34X_AUTODMA
93                 return -1;
94 #else
95                 return 0;
96 #endif
97
98         if (ide_use_fast_pio(drive))
99                 hpt34x_tune_drive(drive, 255);
100
101         return -1;
102 }
103
104 /*
105  * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
106  */
107 #define HPT34X_PCI_INIT_REG             0x80
108
109 static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
110 {
111         int i = 0;
112         unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
113         unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
114         unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
115         u16 cmd;
116         unsigned long flags;
117
118         local_irq_save(flags);
119
120         pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
121         pci_read_config_word(dev, PCI_COMMAND, &cmd);
122
123         if (cmd & PCI_COMMAND_MEMORY) {
124                 if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
125                         pci_write_config_dword(dev, PCI_ROM_ADDRESS,
126                                 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
127                         printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
128                                 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
129                 }
130                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
131         } else {
132                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
133         }
134
135         /*
136          * Since 20-23 can be assigned and are R/W, we correct them.
137          */
138         pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
139         for(i=0; i<4; i++) {
140                 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
141                 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
142                 dev->resource[i].flags = IORESOURCE_IO;
143                 pci_write_config_dword(dev,
144                                 (PCI_BASE_ADDRESS_0 + (i * 4)),
145                                 dev->resource[i].start);
146         }
147         pci_write_config_word(dev, PCI_COMMAND, cmd);
148
149         local_irq_restore(flags);
150
151         return dev->irq;
152 }
153
154 static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
155 {
156         u16 pcicmd = 0;
157
158         hwif->autodma = 0;
159
160         hwif->tuneproc = &hpt34x_tune_drive;
161         hwif->speedproc = &hpt34x_tune_chipset;
162         hwif->drives[0].autotune = 1;
163         hwif->drives[1].autotune = 1;
164
165         pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
166
167         if (!hwif->dma_base)
168                 return;
169
170         hwif->ultra_mask = 0x07;
171         hwif->mwdma_mask = 0x07;
172         hwif->swdma_mask = 0x07;
173
174         hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
175         if (!noautodma)
176                 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
177         hwif->drives[0].autodma = hwif->autodma;
178         hwif->drives[1].autodma = hwif->autodma;
179 }
180
181 static ide_pci_device_t hpt34x_chipset __devinitdata = {
182         .name           = "HPT34X",
183         .init_chipset   = init_chipset_hpt34x,
184         .init_hwif      = init_hwif_hpt34x,
185         .channels       = 2,
186         .autodma        = NOAUTODMA,
187         .bootable       = NEVER_BOARD,
188         .extra          = 16
189 };
190
191 static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
192 {
193         ide_pci_device_t *d = &hpt34x_chipset;
194         static char *chipset_names[] = {"HPT343", "HPT345"};
195         u16 pcicmd = 0;
196
197         pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
198
199         d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
200         d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
201
202         return ide_setup_pci_device(dev, d);
203 }
204
205 static struct pci_device_id hpt34x_pci_tbl[] = {
206         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
207         { 0, },
208 };
209 MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
210
211 static struct pci_driver driver = {
212         .name           = "HPT34x_IDE",
213         .id_table       = hpt34x_pci_tbl,
214         .probe          = hpt34x_init_one,
215 };
216
217 static int __init hpt34x_ide_init(void)
218 {
219         return ide_pci_register_driver(&driver);
220 }
221
222 module_init(hpt34x_ide_init);
223
224 MODULE_AUTHOR("Andre Hedrick");
225 MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
226 MODULE_LICENSE("GPL");